1 /* 2 * Copyright © 2012-2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * Daniel Vetter <daniel.vetter@ffwll.ch> 26 * 27 */ 28 29 #include "i915_drv.h" 30 #include "intel_drv.h" 31 32 /** 33 * DOC: runtime pm 34 * 35 * The i915 driver supports dynamic enabling and disabling of entire hardware 36 * blocks at runtime. This is especially important on the display side where 37 * software is supposed to control many power gates manually on recent hardware, 38 * since on the GT side a lot of the power management is done by the hardware. 39 * But even there some manual control at the device level is required. 40 * 41 * Since i915 supports a diverse set of platforms with a unified codebase and 42 * hardware engineers just love to shuffle functionality around between power 43 * domains there's a sizeable amount of indirection required. This file provides 44 * generic functions to the driver for grabbing and releasing references for 45 * abstract power domains. It then maps those to the actual power wells 46 * present for a given platform. 47 */ 48 49 #define for_each_power_well(i, power_well, domain_mask, power_domains) \ 50 for (i = 0; \ 51 i < (power_domains)->power_well_count && \ 52 ((power_well) = &(power_domains)->power_wells[i]); \ 53 i++) \ 54 for_each_if ((power_well)->domains & (domain_mask)) 55 56 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ 57 for (i = (power_domains)->power_well_count - 1; \ 58 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ 59 i--) \ 60 for_each_if ((power_well)->domains & (domain_mask)) 61 62 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 63 int power_well_id); 64 65 const char * 66 intel_display_power_domain_str(enum intel_display_power_domain domain) 67 { 68 switch (domain) { 69 case POWER_DOMAIN_PIPE_A: 70 return "PIPE_A"; 71 case POWER_DOMAIN_PIPE_B: 72 return "PIPE_B"; 73 case POWER_DOMAIN_PIPE_C: 74 return "PIPE_C"; 75 case POWER_DOMAIN_PIPE_A_PANEL_FITTER: 76 return "PIPE_A_PANEL_FITTER"; 77 case POWER_DOMAIN_PIPE_B_PANEL_FITTER: 78 return "PIPE_B_PANEL_FITTER"; 79 case POWER_DOMAIN_PIPE_C_PANEL_FITTER: 80 return "PIPE_C_PANEL_FITTER"; 81 case POWER_DOMAIN_TRANSCODER_A: 82 return "TRANSCODER_A"; 83 case POWER_DOMAIN_TRANSCODER_B: 84 return "TRANSCODER_B"; 85 case POWER_DOMAIN_TRANSCODER_C: 86 return "TRANSCODER_C"; 87 case POWER_DOMAIN_TRANSCODER_EDP: 88 return "TRANSCODER_EDP"; 89 case POWER_DOMAIN_PORT_DDI_A_LANES: 90 return "PORT_DDI_A_LANES"; 91 case POWER_DOMAIN_PORT_DDI_B_LANES: 92 return "PORT_DDI_B_LANES"; 93 case POWER_DOMAIN_PORT_DDI_C_LANES: 94 return "PORT_DDI_C_LANES"; 95 case POWER_DOMAIN_PORT_DDI_D_LANES: 96 return "PORT_DDI_D_LANES"; 97 case POWER_DOMAIN_PORT_DDI_E_LANES: 98 return "PORT_DDI_E_LANES"; 99 case POWER_DOMAIN_PORT_DSI: 100 return "PORT_DSI"; 101 case POWER_DOMAIN_PORT_CRT: 102 return "PORT_CRT"; 103 case POWER_DOMAIN_PORT_OTHER: 104 return "PORT_OTHER"; 105 case POWER_DOMAIN_VGA: 106 return "VGA"; 107 case POWER_DOMAIN_AUDIO: 108 return "AUDIO"; 109 case POWER_DOMAIN_PLLS: 110 return "PLLS"; 111 case POWER_DOMAIN_AUX_A: 112 return "AUX_A"; 113 case POWER_DOMAIN_AUX_B: 114 return "AUX_B"; 115 case POWER_DOMAIN_AUX_C: 116 return "AUX_C"; 117 case POWER_DOMAIN_AUX_D: 118 return "AUX_D"; 119 case POWER_DOMAIN_GMBUS: 120 return "GMBUS"; 121 case POWER_DOMAIN_INIT: 122 return "INIT"; 123 case POWER_DOMAIN_MODESET: 124 return "MODESET"; 125 default: 126 MISSING_CASE(domain); 127 return "?"; 128 } 129 } 130 131 static void intel_power_well_enable(struct drm_i915_private *dev_priv, 132 struct i915_power_well *power_well) 133 { 134 DRM_DEBUG_KMS("enabling %s\n", power_well->name); 135 power_well->ops->enable(dev_priv, power_well); 136 power_well->hw_enabled = true; 137 } 138 139 static void intel_power_well_disable(struct drm_i915_private *dev_priv, 140 struct i915_power_well *power_well) 141 { 142 DRM_DEBUG_KMS("disabling %s\n", power_well->name); 143 power_well->hw_enabled = false; 144 power_well->ops->disable(dev_priv, power_well); 145 } 146 147 /* 148 * We should only use the power well if we explicitly asked the hardware to 149 * enable it, so check if it's enabled and also check if we've requested it to 150 * be enabled. 151 */ 152 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, 153 struct i915_power_well *power_well) 154 { 155 return I915_READ(HSW_PWR_WELL_DRIVER) == 156 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 157 } 158 159 /** 160 * __intel_display_power_is_enabled - unlocked check for a power domain 161 * @dev_priv: i915 device instance 162 * @domain: power domain to check 163 * 164 * This is the unlocked version of intel_display_power_is_enabled() and should 165 * only be used from error capture and recovery code where deadlocks are 166 * possible. 167 * 168 * Returns: 169 * True when the power domain is enabled, false otherwise. 170 */ 171 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 172 enum intel_display_power_domain domain) 173 { 174 struct i915_power_domains *power_domains; 175 struct i915_power_well *power_well; 176 bool is_enabled; 177 int i; 178 179 if (dev_priv->pm.suspended) 180 return false; 181 182 power_domains = &dev_priv->power_domains; 183 184 is_enabled = true; 185 186 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 187 if (power_well->always_on) 188 continue; 189 190 if (!power_well->hw_enabled) { 191 is_enabled = false; 192 break; 193 } 194 } 195 196 return is_enabled; 197 } 198 199 /** 200 * intel_display_power_is_enabled - check for a power domain 201 * @dev_priv: i915 device instance 202 * @domain: power domain to check 203 * 204 * This function can be used to check the hw power domain state. It is mostly 205 * used in hardware state readout functions. Everywhere else code should rely 206 * upon explicit power domain reference counting to ensure that the hardware 207 * block is powered up before accessing it. 208 * 209 * Callers must hold the relevant modesetting locks to ensure that concurrent 210 * threads can't disable the power well while the caller tries to read a few 211 * registers. 212 * 213 * Returns: 214 * True when the power domain is enabled, false otherwise. 215 */ 216 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 217 enum intel_display_power_domain domain) 218 { 219 struct i915_power_domains *power_domains; 220 bool ret; 221 222 power_domains = &dev_priv->power_domains; 223 224 mutex_lock(&power_domains->lock); 225 ret = __intel_display_power_is_enabled(dev_priv, domain); 226 mutex_unlock(&power_domains->lock); 227 228 return ret; 229 } 230 231 /** 232 * intel_display_set_init_power - set the initial power domain state 233 * @dev_priv: i915 device instance 234 * @enable: whether to enable or disable the initial power domain state 235 * 236 * For simplicity our driver load/unload and system suspend/resume code assumes 237 * that all power domains are always enabled. This functions controls the state 238 * of this little hack. While the initial power domain state is enabled runtime 239 * pm is effectively disabled. 240 */ 241 void intel_display_set_init_power(struct drm_i915_private *dev_priv, 242 bool enable) 243 { 244 if (dev_priv->power_domains.init_power_on == enable) 245 return; 246 247 if (enable) 248 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 249 else 250 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 251 252 dev_priv->power_domains.init_power_on = enable; 253 } 254 255 /* 256 * Starting with Haswell, we have a "Power Down Well" that can be turned off 257 * when not needed anymore. We have 4 registers that can request the power well 258 * to be enabled, and it will only be disabled if none of the registers is 259 * requesting it to be enabled. 260 */ 261 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) 262 { 263 struct drm_device *dev = dev_priv->dev; 264 265 /* 266 * After we re-enable the power well, if we touch VGA register 0x3d5 267 * we'll get unclaimed register interrupts. This stops after we write 268 * anything to the VGA MSR register. The vgacon module uses this 269 * register all the time, so if we unbind our driver and, as a 270 * consequence, bind vgacon, we'll get stuck in an infinite loop at 271 * console_unlock(). So make here we touch the VGA MSR register, making 272 * sure vgacon can keep working normally without triggering interrupts 273 * and error messages. 274 */ 275 #if 0 276 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 277 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 278 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 279 #endif 280 281 if (IS_BROADWELL(dev)) 282 gen8_irq_power_well_post_enable(dev_priv, 283 1 << PIPE_C | 1 << PIPE_B); 284 } 285 286 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) 287 { 288 if (IS_BROADWELL(dev_priv)) 289 gen8_irq_power_well_pre_disable(dev_priv, 290 1 << PIPE_C | 1 << PIPE_B); 291 } 292 293 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, 294 struct i915_power_well *power_well) 295 { 296 #if 0 297 struct drm_device *dev = dev_priv->dev; 298 #endif 299 300 /* 301 * After we re-enable the power well, if we touch VGA register 0x3d5 302 * we'll get unclaimed register interrupts. This stops after we write 303 * anything to the VGA MSR register. The vgacon module uses this 304 * register all the time, so if we unbind our driver and, as a 305 * consequence, bind vgacon, we'll get stuck in an infinite loop at 306 * console_unlock(). So make here we touch the VGA MSR register, making 307 * sure vgacon can keep working normally without triggering interrupts 308 * and error messages. 309 */ 310 if (power_well->data == SKL_DISP_PW_2) { 311 #if 0 312 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 313 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); 314 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 315 #endif 316 317 gen8_irq_power_well_post_enable(dev_priv, 318 1 << PIPE_C | 1 << PIPE_B); 319 } 320 } 321 322 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, 323 struct i915_power_well *power_well) 324 { 325 if (power_well->data == SKL_DISP_PW_2) 326 gen8_irq_power_well_pre_disable(dev_priv, 327 1 << PIPE_C | 1 << PIPE_B); 328 } 329 330 static void hsw_set_power_well(struct drm_i915_private *dev_priv, 331 struct i915_power_well *power_well, bool enable) 332 { 333 bool is_enabled, enable_requested; 334 uint32_t tmp; 335 336 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 337 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; 338 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; 339 340 if (enable) { 341 if (!enable_requested) 342 I915_WRITE(HSW_PWR_WELL_DRIVER, 343 HSW_PWR_WELL_ENABLE_REQUEST); 344 345 if (!is_enabled) { 346 DRM_DEBUG_KMS("Enabling power well\n"); 347 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 348 HSW_PWR_WELL_STATE_ENABLED), 20)) 349 DRM_ERROR("Timeout enabling power well\n"); 350 hsw_power_well_post_enable(dev_priv); 351 } 352 353 } else { 354 if (enable_requested) { 355 hsw_power_well_pre_disable(dev_priv); 356 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 357 POSTING_READ(HSW_PWR_WELL_DRIVER); 358 DRM_DEBUG_KMS("Requesting to disable the power well\n"); 359 } 360 } 361 } 362 363 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 364 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 365 BIT(POWER_DOMAIN_PIPE_B) | \ 366 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 367 BIT(POWER_DOMAIN_PIPE_C) | \ 368 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 369 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 370 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 371 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 372 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 373 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 374 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 375 BIT(POWER_DOMAIN_AUX_B) | \ 376 BIT(POWER_DOMAIN_AUX_C) | \ 377 BIT(POWER_DOMAIN_AUX_D) | \ 378 BIT(POWER_DOMAIN_AUDIO) | \ 379 BIT(POWER_DOMAIN_VGA) | \ 380 BIT(POWER_DOMAIN_INIT)) 381 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ 382 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 383 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ 384 BIT(POWER_DOMAIN_INIT)) 385 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ 386 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 387 BIT(POWER_DOMAIN_INIT)) 388 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ 389 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 390 BIT(POWER_DOMAIN_INIT)) 391 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ 392 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 393 BIT(POWER_DOMAIN_INIT)) 394 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 395 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 396 BIT(POWER_DOMAIN_MODESET) | \ 397 BIT(POWER_DOMAIN_AUX_A) | \ 398 BIT(POWER_DOMAIN_INIT)) 399 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 400 (POWER_DOMAIN_MASK & ~( \ 401 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 402 SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \ 403 BIT(POWER_DOMAIN_INIT)) 404 405 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ 406 BIT(POWER_DOMAIN_TRANSCODER_A) | \ 407 BIT(POWER_DOMAIN_PIPE_B) | \ 408 BIT(POWER_DOMAIN_TRANSCODER_B) | \ 409 BIT(POWER_DOMAIN_PIPE_C) | \ 410 BIT(POWER_DOMAIN_TRANSCODER_C) | \ 411 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ 412 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ 413 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 414 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 415 BIT(POWER_DOMAIN_AUX_B) | \ 416 BIT(POWER_DOMAIN_AUX_C) | \ 417 BIT(POWER_DOMAIN_AUDIO) | \ 418 BIT(POWER_DOMAIN_VGA) | \ 419 BIT(POWER_DOMAIN_GMBUS) | \ 420 BIT(POWER_DOMAIN_INIT)) 421 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ 422 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 423 BIT(POWER_DOMAIN_PIPE_A) | \ 424 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 425 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ 426 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 427 BIT(POWER_DOMAIN_AUX_A) | \ 428 BIT(POWER_DOMAIN_PLLS) | \ 429 BIT(POWER_DOMAIN_INIT)) 430 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ 431 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ 432 BIT(POWER_DOMAIN_MODESET) | \ 433 BIT(POWER_DOMAIN_AUX_A) | \ 434 BIT(POWER_DOMAIN_INIT)) 435 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ 436 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ 437 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ 438 BIT(POWER_DOMAIN_INIT)) 439 440 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) 441 { 442 struct drm_device *dev = dev_priv->dev; 443 444 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); 445 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 446 "DC9 already programmed to be enabled.\n"); 447 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 448 "DC5 still not disabled to enable DC9.\n"); 449 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); 450 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 451 452 /* 453 * TODO: check for the following to verify the conditions to enter DC9 454 * state are satisfied: 455 * 1] Check relevant display engine registers to verify if mode set 456 * disable sequence was followed. 457 * 2] Check if display uninitialize sequence is initialized. 458 */ 459 } 460 461 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) 462 { 463 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); 464 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), 465 "DC9 already programmed to be disabled.\n"); 466 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, 467 "DC5 still not disabled.\n"); 468 469 /* 470 * TODO: check for the following to verify DC9 state was indeed 471 * entered before programming to disable it: 472 * 1] Check relevant display engine registers to verify if mode 473 * set disable sequence was followed. 474 * 2] Check if display uninitialize sequence is initialized. 475 */ 476 } 477 478 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 479 { 480 uint32_t val, mask; 481 482 mask = DC_STATE_DEBUG_MASK_MEMORY_UP; 483 484 if (IS_BROXTON(dev_priv)) 485 mask |= DC_STATE_DEBUG_MASK_CORES; 486 487 /* The below bit doesn't need to be cleared ever afterwards */ 488 val = I915_READ(DC_STATE_DEBUG); 489 if ((val & mask) != mask) { 490 val |= mask; 491 I915_WRITE(DC_STATE_DEBUG, val); 492 POSTING_READ(DC_STATE_DEBUG); 493 } 494 } 495 496 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, 497 u32 state) 498 { 499 int rewrites = 0; 500 int rereads = 0; 501 u32 v; 502 503 I915_WRITE(DC_STATE_EN, state); 504 505 /* It has been observed that disabling the dc6 state sometimes 506 * doesn't stick and dmc keeps returning old value. Make sure 507 * the write really sticks enough times and also force rewrite until 508 * we are confident that state is exactly what we want. 509 */ 510 do { 511 v = I915_READ(DC_STATE_EN); 512 513 if (v != state) { 514 I915_WRITE(DC_STATE_EN, state); 515 rewrites++; 516 rereads = 0; 517 } else if (rereads++ > 5) { 518 break; 519 } 520 521 } while (rewrites < 100); 522 523 if (v != state) 524 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", 525 state, v); 526 527 /* Most of the times we need one retry, avoid spam */ 528 if (rewrites > 1) 529 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", 530 state, rewrites); 531 } 532 533 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) 534 { 535 uint32_t val; 536 uint32_t mask; 537 538 mask = DC_STATE_EN_UPTO_DC5; 539 if (IS_BROXTON(dev_priv)) 540 mask |= DC_STATE_EN_DC9; 541 else 542 mask |= DC_STATE_EN_UPTO_DC6; 543 544 WARN_ON_ONCE(state & ~mask); 545 546 if (i915.enable_dc == 0) 547 state = DC_STATE_DISABLE; 548 else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5) 549 state = DC_STATE_EN_UPTO_DC5; 550 551 val = I915_READ(DC_STATE_EN); 552 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", 553 val & mask, state); 554 555 /* Check if DMC is ignoring our DC state requests */ 556 if ((val & mask) != dev_priv->csr.dc_state) 557 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", 558 dev_priv->csr.dc_state, val & mask); 559 560 val &= ~mask; 561 val |= state; 562 563 gen9_write_dc_state(dev_priv, val); 564 565 dev_priv->csr.dc_state = val & mask; 566 } 567 568 void bxt_enable_dc9(struct drm_i915_private *dev_priv) 569 { 570 assert_can_enable_dc9(dev_priv); 571 572 DRM_DEBUG_KMS("Enabling DC9\n"); 573 574 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); 575 } 576 577 void bxt_disable_dc9(struct drm_i915_private *dev_priv) 578 { 579 assert_can_disable_dc9(dev_priv); 580 581 DRM_DEBUG_KMS("Disabling DC9\n"); 582 583 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 584 } 585 586 static void assert_csr_loaded(struct drm_i915_private *dev_priv) 587 { 588 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), 589 "CSR program storage start is NULL\n"); 590 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); 591 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); 592 } 593 594 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) 595 { 596 struct drm_device *dev = dev_priv->dev; 597 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, 598 SKL_DISP_PW_2); 599 600 WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev), 601 "Platform doesn't support DC5.\n"); 602 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 603 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); 604 605 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), 606 "DC5 already programmed to be enabled.\n"); 607 assert_rpm_wakelock_held(dev_priv); 608 609 assert_csr_loaded(dev_priv); 610 } 611 612 static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) 613 { 614 /* 615 * During initialization, the firmware may not be loaded yet. 616 * We still want to make sure that the DC enabling flag is cleared. 617 */ 618 if (dev_priv->power_domains.initializing) 619 return; 620 621 assert_rpm_wakelock_held(dev_priv); 622 } 623 624 static void gen9_enable_dc5(struct drm_i915_private *dev_priv) 625 { 626 assert_can_enable_dc5(dev_priv); 627 628 DRM_DEBUG_KMS("Enabling DC5\n"); 629 630 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 631 } 632 633 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) 634 { 635 struct drm_device *dev = dev_priv->dev; 636 637 WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev), 638 "Platform doesn't support DC6.\n"); 639 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); 640 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, 641 "Backlight is not disabled.\n"); 642 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 643 "DC6 already programmed to be enabled.\n"); 644 645 assert_csr_loaded(dev_priv); 646 } 647 648 static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) 649 { 650 /* 651 * During initialization, the firmware may not be loaded yet. 652 * We still want to make sure that the DC enabling flag is cleared. 653 */ 654 if (dev_priv->power_domains.initializing) 655 return; 656 657 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), 658 "DC6 already programmed to be disabled.\n"); 659 } 660 661 static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv) 662 { 663 assert_can_disable_dc5(dev_priv); 664 665 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 666 i915.enable_dc != 0 && i915.enable_dc != 1) 667 assert_can_disable_dc6(dev_priv); 668 669 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 670 } 671 672 void skl_enable_dc6(struct drm_i915_private *dev_priv) 673 { 674 assert_can_enable_dc6(dev_priv); 675 676 DRM_DEBUG_KMS("Enabling DC6\n"); 677 678 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 679 680 } 681 682 void skl_disable_dc6(struct drm_i915_private *dev_priv) 683 { 684 assert_can_disable_dc6(dev_priv); 685 686 DRM_DEBUG_KMS("Disabling DC6\n"); 687 688 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 689 } 690 691 static void skl_set_power_well(struct drm_i915_private *dev_priv, 692 struct i915_power_well *power_well, bool enable) 693 { 694 uint32_t tmp, fuse_status; 695 uint32_t req_mask, state_mask; 696 bool is_enabled, enable_requested, check_fuse_status = false; 697 698 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 699 fuse_status = I915_READ(SKL_FUSE_STATUS); 700 701 switch (power_well->data) { 702 case SKL_DISP_PW_1: 703 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 704 SKL_FUSE_PG0_DIST_STATUS), 1)) { 705 DRM_ERROR("PG0 not enabled\n"); 706 return; 707 } 708 break; 709 case SKL_DISP_PW_2: 710 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { 711 DRM_ERROR("PG1 in disabled state\n"); 712 return; 713 } 714 break; 715 case SKL_DISP_PW_DDI_A_E: 716 case SKL_DISP_PW_DDI_B: 717 case SKL_DISP_PW_DDI_C: 718 case SKL_DISP_PW_DDI_D: 719 case SKL_DISP_PW_MISC_IO: 720 break; 721 default: 722 WARN(1, "Unknown power well %lu\n", power_well->data); 723 return; 724 } 725 726 req_mask = SKL_POWER_WELL_REQ(power_well->data); 727 enable_requested = tmp & req_mask; 728 state_mask = SKL_POWER_WELL_STATE(power_well->data); 729 is_enabled = tmp & state_mask; 730 731 if (!enable && enable_requested) 732 skl_power_well_pre_disable(dev_priv, power_well); 733 734 if (enable) { 735 if (!enable_requested) { 736 WARN((tmp & state_mask) && 737 !I915_READ(HSW_PWR_WELL_BIOS), 738 "Invalid for power well status to be enabled, unless done by the BIOS, \ 739 when request is to disable!\n"); 740 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); 741 } 742 743 if (!is_enabled) { 744 DRM_DEBUG_KMS("Enabling %s\n", power_well->name); 745 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & 746 state_mask), 1)) 747 DRM_ERROR("%s enable timeout\n", 748 power_well->name); 749 check_fuse_status = true; 750 } 751 } else { 752 if (enable_requested) { 753 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); 754 POSTING_READ(HSW_PWR_WELL_DRIVER); 755 DRM_DEBUG_KMS("Disabling %s\n", power_well->name); 756 } 757 } 758 759 if (check_fuse_status) { 760 if (power_well->data == SKL_DISP_PW_1) { 761 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 762 SKL_FUSE_PG1_DIST_STATUS), 1)) 763 DRM_ERROR("PG1 distributing status timeout\n"); 764 } else if (power_well->data == SKL_DISP_PW_2) { 765 if (wait_for((I915_READ(SKL_FUSE_STATUS) & 766 SKL_FUSE_PG2_DIST_STATUS), 1)) 767 DRM_ERROR("PG2 distributing status timeout\n"); 768 } 769 } 770 771 if (enable && !is_enabled) 772 skl_power_well_post_enable(dev_priv, power_well); 773 } 774 775 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, 776 struct i915_power_well *power_well) 777 { 778 hsw_set_power_well(dev_priv, power_well, power_well->count > 0); 779 780 /* 781 * We're taking over the BIOS, so clear any requests made by it since 782 * the driver is in charge now. 783 */ 784 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 785 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 786 } 787 788 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, 789 struct i915_power_well *power_well) 790 { 791 hsw_set_power_well(dev_priv, power_well, true); 792 } 793 794 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, 795 struct i915_power_well *power_well) 796 { 797 hsw_set_power_well(dev_priv, power_well, false); 798 } 799 800 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, 801 struct i915_power_well *power_well) 802 { 803 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | 804 SKL_POWER_WELL_STATE(power_well->data); 805 806 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; 807 } 808 809 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, 810 struct i915_power_well *power_well) 811 { 812 skl_set_power_well(dev_priv, power_well, power_well->count > 0); 813 814 /* Clear any request made by BIOS as driver is taking over */ 815 I915_WRITE(HSW_PWR_WELL_BIOS, 0); 816 } 817 818 static void skl_power_well_enable(struct drm_i915_private *dev_priv, 819 struct i915_power_well *power_well) 820 { 821 skl_set_power_well(dev_priv, power_well, true); 822 } 823 824 static void skl_power_well_disable(struct drm_i915_private *dev_priv, 825 struct i915_power_well *power_well) 826 { 827 skl_set_power_well(dev_priv, power_well, false); 828 } 829 830 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, 831 struct i915_power_well *power_well) 832 { 833 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; 834 } 835 836 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, 837 struct i915_power_well *power_well) 838 { 839 gen9_disable_dc5_dc6(dev_priv); 840 } 841 842 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, 843 struct i915_power_well *power_well) 844 { 845 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 846 i915.enable_dc != 0 && i915.enable_dc != 1) 847 skl_enable_dc6(dev_priv); 848 else 849 gen9_enable_dc5(dev_priv); 850 } 851 852 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, 853 struct i915_power_well *power_well) 854 { 855 if (power_well->count > 0) { 856 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 857 } else { 858 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && 859 i915.enable_dc != 0 && 860 i915.enable_dc != 1) 861 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); 862 else 863 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); 864 } 865 } 866 867 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, 868 struct i915_power_well *power_well) 869 { 870 } 871 872 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, 873 struct i915_power_well *power_well) 874 { 875 return true; 876 } 877 878 static void vlv_set_power_well(struct drm_i915_private *dev_priv, 879 struct i915_power_well *power_well, bool enable) 880 { 881 enum punit_power_well power_well_id = power_well->data; 882 u32 mask; 883 u32 state; 884 u32 ctrl; 885 886 mask = PUNIT_PWRGT_MASK(power_well_id); 887 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : 888 PUNIT_PWRGT_PWR_GATE(power_well_id); 889 890 mutex_lock(&dev_priv->rps.hw_lock); 891 892 #define COND \ 893 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) 894 895 if (COND) 896 goto out; 897 898 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); 899 ctrl &= ~mask; 900 ctrl |= state; 901 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); 902 903 if (wait_for(COND, 100)) 904 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 905 state, 906 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); 907 908 #undef COND 909 910 out: 911 mutex_unlock(&dev_priv->rps.hw_lock); 912 } 913 914 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, 915 struct i915_power_well *power_well) 916 { 917 vlv_set_power_well(dev_priv, power_well, power_well->count > 0); 918 } 919 920 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, 921 struct i915_power_well *power_well) 922 { 923 vlv_set_power_well(dev_priv, power_well, true); 924 } 925 926 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, 927 struct i915_power_well *power_well) 928 { 929 vlv_set_power_well(dev_priv, power_well, false); 930 } 931 932 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, 933 struct i915_power_well *power_well) 934 { 935 int power_well_id = power_well->data; 936 bool enabled = false; 937 u32 mask; 938 u32 state; 939 u32 ctrl; 940 941 mask = PUNIT_PWRGT_MASK(power_well_id); 942 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); 943 944 mutex_lock(&dev_priv->rps.hw_lock); 945 946 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; 947 /* 948 * We only ever set the power-on and power-gate states, anything 949 * else is unexpected. 950 */ 951 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && 952 state != PUNIT_PWRGT_PWR_GATE(power_well_id)); 953 if (state == ctrl) 954 enabled = true; 955 956 /* 957 * A transient state at this point would mean some unexpected party 958 * is poking at the power controls too. 959 */ 960 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; 961 WARN_ON(ctrl != state); 962 963 mutex_unlock(&dev_priv->rps.hw_lock); 964 965 return enabled; 966 } 967 968 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) 969 { 970 enum i915_pipe pipe; 971 972 /* 973 * Enable the CRI clock source so we can get at the 974 * display and the reference clock for VGA 975 * hotplug / manual detection. Supposedly DSI also 976 * needs the ref clock up and running. 977 * 978 * CHV DPLL B/C have some issues if VGA mode is enabled. 979 */ 980 for_each_pipe(dev_priv->dev, pipe) { 981 u32 val = I915_READ(DPLL(pipe)); 982 983 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 984 if (pipe != PIPE_A) 985 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 986 987 I915_WRITE(DPLL(pipe), val); 988 } 989 990 spin_lock_irq(&dev_priv->irq_lock); 991 valleyview_enable_display_irqs(dev_priv); 992 spin_unlock_irq(&dev_priv->irq_lock); 993 994 /* 995 * During driver initialization/resume we can avoid restoring the 996 * part of the HW/SW state that will be inited anyway explicitly. 997 */ 998 if (dev_priv->power_domains.initializing) 999 return; 1000 1001 intel_hpd_init(dev_priv); 1002 1003 i915_redisable_vga_power_on(dev_priv->dev); 1004 } 1005 1006 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) 1007 { 1008 spin_lock_irq(&dev_priv->irq_lock); 1009 valleyview_disable_display_irqs(dev_priv); 1010 spin_unlock_irq(&dev_priv->irq_lock); 1011 1012 /* make sure we're done processing display irqs */ 1013 #if 0 1014 synchronize_irq(dev_priv->dev->irq); 1015 #endif 1016 1017 vlv_power_sequencer_reset(dev_priv); 1018 } 1019 1020 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, 1021 struct i915_power_well *power_well) 1022 { 1023 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1024 1025 vlv_set_power_well(dev_priv, power_well, true); 1026 1027 vlv_display_power_well_init(dev_priv); 1028 } 1029 1030 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, 1031 struct i915_power_well *power_well) 1032 { 1033 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); 1034 1035 vlv_display_power_well_deinit(dev_priv); 1036 1037 vlv_set_power_well(dev_priv, power_well, false); 1038 } 1039 1040 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1041 struct i915_power_well *power_well) 1042 { 1043 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1044 1045 /* since ref/cri clock was enabled */ 1046 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1047 1048 vlv_set_power_well(dev_priv, power_well, true); 1049 1050 /* 1051 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1052 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1053 * a. GUnit 0x2110 bit[0] set to 1 (def 0) 1054 * b. The other bits such as sfr settings / modesel may all 1055 * be set to 0. 1056 * 1057 * This should only be done on init and resume from S3 with 1058 * both PLLs disabled, or we risk losing DPIO and PLL 1059 * synchronization. 1060 */ 1061 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); 1062 } 1063 1064 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1065 struct i915_power_well *power_well) 1066 { 1067 enum i915_pipe pipe; 1068 1069 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); 1070 1071 for_each_pipe(dev_priv, pipe) 1072 assert_pll_disabled(dev_priv, pipe); 1073 1074 /* Assert common reset */ 1075 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); 1076 1077 vlv_set_power_well(dev_priv, power_well, false); 1078 } 1079 1080 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) 1081 1082 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, 1083 int power_well_id) 1084 { 1085 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1086 int i; 1087 1088 for (i = 0; i < power_domains->power_well_count; i++) { 1089 struct i915_power_well *power_well; 1090 1091 power_well = &power_domains->power_wells[i]; 1092 if (power_well->data == power_well_id) 1093 return power_well; 1094 } 1095 1096 return NULL; 1097 } 1098 1099 #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) 1100 1101 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) 1102 { 1103 struct i915_power_well *cmn_bc = 1104 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 1105 struct i915_power_well *cmn_d = 1106 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 1107 u32 phy_control = dev_priv->chv_phy_control; 1108 u32 phy_status = 0; 1109 u32 phy_status_mask = 0xffffffff; 1110 u32 tmp; 1111 1112 /* 1113 * The BIOS can leave the PHY is some weird state 1114 * where it doesn't fully power down some parts. 1115 * Disable the asserts until the PHY has been fully 1116 * reset (ie. the power well has been disabled at 1117 * least once). 1118 */ 1119 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) 1120 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | 1121 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | 1122 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | 1123 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | 1124 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | 1125 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); 1126 1127 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) 1128 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | 1129 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | 1130 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); 1131 1132 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 1133 phy_status |= PHY_POWERGOOD(DPIO_PHY0); 1134 1135 /* this assumes override is only used to enable lanes */ 1136 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) 1137 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); 1138 1139 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) 1140 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); 1141 1142 /* CL1 is on whenever anything is on in either channel */ 1143 if (BITS_SET(phy_control, 1144 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | 1145 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) 1146 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); 1147 1148 /* 1149 * The DPLLB check accounts for the pipe B + port A usage 1150 * with CL2 powered up but all the lanes in the second channel 1151 * powered down. 1152 */ 1153 if (BITS_SET(phy_control, 1154 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && 1155 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) 1156 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); 1157 1158 if (BITS_SET(phy_control, 1159 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) 1160 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); 1161 if (BITS_SET(phy_control, 1162 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) 1163 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); 1164 1165 if (BITS_SET(phy_control, 1166 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) 1167 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); 1168 if (BITS_SET(phy_control, 1169 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) 1170 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); 1171 } 1172 1173 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 1174 phy_status |= PHY_POWERGOOD(DPIO_PHY1); 1175 1176 /* this assumes override is only used to enable lanes */ 1177 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) 1178 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); 1179 1180 if (BITS_SET(phy_control, 1181 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) 1182 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); 1183 1184 if (BITS_SET(phy_control, 1185 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) 1186 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); 1187 if (BITS_SET(phy_control, 1188 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) 1189 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); 1190 } 1191 1192 phy_status &= phy_status_mask; 1193 1194 /* 1195 * The PHY may be busy with some initial calibration and whatnot, 1196 * so the power state can take a while to actually change. 1197 */ 1198 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) 1199 WARN(phy_status != tmp, 1200 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", 1201 tmp, phy_status, dev_priv->chv_phy_control); 1202 } 1203 1204 #undef BITS_SET 1205 1206 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, 1207 struct i915_power_well *power_well) 1208 { 1209 enum dpio_phy phy; 1210 enum i915_pipe pipe; 1211 uint32_t tmp; 1212 1213 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1214 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1215 1216 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1217 pipe = PIPE_A; 1218 phy = DPIO_PHY0; 1219 } else { 1220 pipe = PIPE_C; 1221 phy = DPIO_PHY1; 1222 } 1223 1224 /* since ref/cri clock was enabled */ 1225 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ 1226 vlv_set_power_well(dev_priv, power_well, true); 1227 1228 /* Poll for phypwrgood signal */ 1229 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) 1230 DRM_ERROR("Display PHY %d is not power up\n", phy); 1231 1232 mutex_lock(&dev_priv->sb_lock); 1233 1234 /* Enable dynamic power down */ 1235 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); 1236 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | 1237 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; 1238 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); 1239 1240 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1241 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); 1242 tmp |= DPIO_DYNPWRDOWNEN_CH1; 1243 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); 1244 } else { 1245 /* 1246 * Force the non-existing CL2 off. BXT does this 1247 * too, so maybe it saves some power even though 1248 * CL2 doesn't exist? 1249 */ 1250 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); 1251 tmp |= DPIO_CL2_LDOFUSE_PWRENB; 1252 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); 1253 } 1254 1255 mutex_unlock(&dev_priv->sb_lock); 1256 1257 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); 1258 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1259 1260 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1261 phy, dev_priv->chv_phy_control); 1262 1263 assert_chv_phy_status(dev_priv); 1264 } 1265 1266 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, 1267 struct i915_power_well *power_well) 1268 { 1269 enum dpio_phy phy; 1270 1271 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && 1272 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); 1273 1274 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { 1275 phy = DPIO_PHY0; 1276 assert_pll_disabled(dev_priv, PIPE_A); 1277 assert_pll_disabled(dev_priv, PIPE_B); 1278 } else { 1279 phy = DPIO_PHY1; 1280 assert_pll_disabled(dev_priv, PIPE_C); 1281 } 1282 1283 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); 1284 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1285 1286 vlv_set_power_well(dev_priv, power_well, false); 1287 1288 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", 1289 phy, dev_priv->chv_phy_control); 1290 1291 /* PHY is fully reset now, so we can enable the PHY state asserts */ 1292 dev_priv->chv_phy_assert[phy] = true; 1293 1294 assert_chv_phy_status(dev_priv); 1295 } 1296 1297 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1298 enum dpio_channel ch, bool override, unsigned int mask) 1299 { 1300 enum i915_pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; 1301 u32 reg, val, expected, actual; 1302 1303 /* 1304 * The BIOS can leave the PHY is some weird state 1305 * where it doesn't fully power down some parts. 1306 * Disable the asserts until the PHY has been fully 1307 * reset (ie. the power well has been disabled at 1308 * least once). 1309 */ 1310 if (!dev_priv->chv_phy_assert[phy]) 1311 return; 1312 1313 if (ch == DPIO_CH0) 1314 reg = _CHV_CMN_DW0_CH0; 1315 else 1316 reg = _CHV_CMN_DW6_CH1; 1317 1318 mutex_lock(&dev_priv->sb_lock); 1319 val = vlv_dpio_read(dev_priv, pipe, reg); 1320 mutex_unlock(&dev_priv->sb_lock); 1321 1322 /* 1323 * This assumes !override is only used when the port is disabled. 1324 * All lanes should power down even without the override when 1325 * the port is disabled. 1326 */ 1327 if (!override || mask == 0xf) { 1328 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1329 /* 1330 * If CH1 common lane is not active anymore 1331 * (eg. for pipe B DPLL) the entire channel will 1332 * shut down, which causes the common lane registers 1333 * to read as 0. That means we can't actually check 1334 * the lane power down status bits, but as the entire 1335 * register reads as 0 it's a good indication that the 1336 * channel is indeed entirely powered down. 1337 */ 1338 if (ch == DPIO_CH1 && val == 0) 1339 expected = 0; 1340 } else if (mask != 0x0) { 1341 expected = DPIO_ANYDL_POWERDOWN; 1342 } else { 1343 expected = 0; 1344 } 1345 1346 if (ch == DPIO_CH0) 1347 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; 1348 else 1349 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; 1350 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; 1351 1352 WARN(actual != expected, 1353 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", 1354 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), 1355 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), 1356 reg, val); 1357 } 1358 1359 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, 1360 enum dpio_channel ch, bool override) 1361 { 1362 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1363 bool was_override; 1364 1365 mutex_lock(&power_domains->lock); 1366 1367 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1368 1369 if (override == was_override) 1370 goto out; 1371 1372 if (override) 1373 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1374 else 1375 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1376 1377 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1378 1379 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", 1380 phy, ch, dev_priv->chv_phy_control); 1381 1382 assert_chv_phy_status(dev_priv); 1383 1384 out: 1385 mutex_unlock(&power_domains->lock); 1386 1387 return was_override; 1388 } 1389 1390 void chv_phy_powergate_lanes(struct intel_encoder *encoder, 1391 bool override, unsigned int mask) 1392 { 1393 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1394 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1395 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); 1396 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); 1397 1398 mutex_lock(&power_domains->lock); 1399 1400 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); 1401 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); 1402 1403 if (override) 1404 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1405 else 1406 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); 1407 1408 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 1409 1410 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", 1411 phy, ch, mask, dev_priv->chv_phy_control); 1412 1413 assert_chv_phy_status(dev_priv); 1414 1415 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); 1416 1417 mutex_unlock(&power_domains->lock); 1418 } 1419 1420 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, 1421 struct i915_power_well *power_well) 1422 { 1423 enum i915_pipe pipe = power_well->data; 1424 bool enabled; 1425 u32 state, ctrl; 1426 1427 mutex_lock(&dev_priv->rps.hw_lock); 1428 1429 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); 1430 /* 1431 * We only ever set the power-on and power-gate states, anything 1432 * else is unexpected. 1433 */ 1434 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); 1435 enabled = state == DP_SSS_PWR_ON(pipe); 1436 1437 /* 1438 * A transient state at this point would mean some unexpected party 1439 * is poking at the power controls too. 1440 */ 1441 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); 1442 WARN_ON(ctrl << 16 != state); 1443 1444 mutex_unlock(&dev_priv->rps.hw_lock); 1445 1446 return enabled; 1447 } 1448 1449 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, 1450 struct i915_power_well *power_well, 1451 bool enable) 1452 { 1453 enum i915_pipe pipe = power_well->data; 1454 u32 state; 1455 u32 ctrl; 1456 1457 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); 1458 1459 mutex_lock(&dev_priv->rps.hw_lock); 1460 1461 #define COND \ 1462 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) 1463 1464 if (COND) 1465 goto out; 1466 1467 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 1468 ctrl &= ~DP_SSC_MASK(pipe); 1469 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); 1470 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); 1471 1472 if (wait_for(COND, 100)) 1473 DRM_ERROR("timeout setting power well state %08x (%08x)\n", 1474 state, 1475 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); 1476 1477 #undef COND 1478 1479 out: 1480 mutex_unlock(&dev_priv->rps.hw_lock); 1481 } 1482 1483 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, 1484 struct i915_power_well *power_well) 1485 { 1486 WARN_ON_ONCE(power_well->data != PIPE_A); 1487 1488 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); 1489 } 1490 1491 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, 1492 struct i915_power_well *power_well) 1493 { 1494 WARN_ON_ONCE(power_well->data != PIPE_A); 1495 1496 chv_set_pipe_power_well(dev_priv, power_well, true); 1497 1498 vlv_display_power_well_init(dev_priv); 1499 } 1500 1501 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, 1502 struct i915_power_well *power_well) 1503 { 1504 WARN_ON_ONCE(power_well->data != PIPE_A); 1505 1506 vlv_display_power_well_deinit(dev_priv); 1507 1508 chv_set_pipe_power_well(dev_priv, power_well, false); 1509 } 1510 1511 static void 1512 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, 1513 enum intel_display_power_domain domain) 1514 { 1515 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1516 struct i915_power_well *power_well; 1517 int i; 1518 1519 for_each_power_well(i, power_well, BIT(domain), power_domains) { 1520 if (!power_well->count++) 1521 intel_power_well_enable(dev_priv, power_well); 1522 } 1523 1524 power_domains->domain_use_count[domain]++; 1525 } 1526 1527 /** 1528 * intel_display_power_get - grab a power domain reference 1529 * @dev_priv: i915 device instance 1530 * @domain: power domain to reference 1531 * 1532 * This function grabs a power domain reference for @domain and ensures that the 1533 * power domain and all its parents are powered up. Therefore users should only 1534 * grab a reference to the innermost power domain they need. 1535 * 1536 * Any power domain reference obtained by this function must have a symmetric 1537 * call to intel_display_power_put() to release the reference again. 1538 */ 1539 void intel_display_power_get(struct drm_i915_private *dev_priv, 1540 enum intel_display_power_domain domain) 1541 { 1542 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1543 1544 intel_runtime_pm_get(dev_priv); 1545 1546 mutex_lock(&power_domains->lock); 1547 1548 __intel_display_power_get_domain(dev_priv, domain); 1549 1550 mutex_unlock(&power_domains->lock); 1551 } 1552 1553 /** 1554 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain 1555 * @dev_priv: i915 device instance 1556 * @domain: power domain to reference 1557 * 1558 * This function grabs a power domain reference for @domain and ensures that the 1559 * power domain and all its parents are powered up. Therefore users should only 1560 * grab a reference to the innermost power domain they need. 1561 * 1562 * Any power domain reference obtained by this function must have a symmetric 1563 * call to intel_display_power_put() to release the reference again. 1564 */ 1565 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, 1566 enum intel_display_power_domain domain) 1567 { 1568 struct i915_power_domains *power_domains = &dev_priv->power_domains; 1569 bool is_enabled; 1570 1571 if (!intel_runtime_pm_get_if_in_use(dev_priv)) 1572 return false; 1573 1574 mutex_lock(&power_domains->lock); 1575 1576 if (__intel_display_power_is_enabled(dev_priv, domain)) { 1577 __intel_display_power_get_domain(dev_priv, domain); 1578 is_enabled = true; 1579 } else { 1580 is_enabled = false; 1581 } 1582 1583 mutex_unlock(&power_domains->lock); 1584 1585 if (!is_enabled) 1586 intel_runtime_pm_put(dev_priv); 1587 1588 return is_enabled; 1589 } 1590 1591 /** 1592 * intel_display_power_put - release a power domain reference 1593 * @dev_priv: i915 device instance 1594 * @domain: power domain to reference 1595 * 1596 * This function drops the power domain reference obtained by 1597 * intel_display_power_get() and might power down the corresponding hardware 1598 * block right away if this is the last reference. 1599 */ 1600 void intel_display_power_put(struct drm_i915_private *dev_priv, 1601 enum intel_display_power_domain domain) 1602 { 1603 struct i915_power_domains *power_domains; 1604 struct i915_power_well *power_well; 1605 int i; 1606 1607 power_domains = &dev_priv->power_domains; 1608 1609 mutex_lock(&power_domains->lock); 1610 1611 WARN(!power_domains->domain_use_count[domain], 1612 "Use count on domain %s is already zero\n", 1613 intel_display_power_domain_str(domain)); 1614 power_domains->domain_use_count[domain]--; 1615 1616 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { 1617 WARN(!power_well->count, 1618 "Use count on power well %s is already zero", 1619 power_well->name); 1620 1621 if (!--power_well->count) 1622 intel_power_well_disable(dev_priv, power_well); 1623 } 1624 1625 mutex_unlock(&power_domains->lock); 1626 1627 intel_runtime_pm_put(dev_priv); 1628 } 1629 1630 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ 1631 BIT(POWER_DOMAIN_PIPE_A) | \ 1632 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ 1633 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ 1634 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1635 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1636 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1637 BIT(POWER_DOMAIN_PORT_CRT) | \ 1638 BIT(POWER_DOMAIN_PLLS) | \ 1639 BIT(POWER_DOMAIN_AUX_A) | \ 1640 BIT(POWER_DOMAIN_AUX_B) | \ 1641 BIT(POWER_DOMAIN_AUX_C) | \ 1642 BIT(POWER_DOMAIN_AUX_D) | \ 1643 BIT(POWER_DOMAIN_GMBUS) | \ 1644 BIT(POWER_DOMAIN_INIT)) 1645 #define HSW_DISPLAY_POWER_DOMAINS ( \ 1646 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ 1647 BIT(POWER_DOMAIN_INIT)) 1648 1649 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ 1650 HSW_ALWAYS_ON_POWER_DOMAINS | \ 1651 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) 1652 #define BDW_DISPLAY_POWER_DOMAINS ( \ 1653 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ 1654 BIT(POWER_DOMAIN_INIT)) 1655 1656 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) 1657 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK 1658 1659 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1660 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1661 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1662 BIT(POWER_DOMAIN_PORT_CRT) | \ 1663 BIT(POWER_DOMAIN_AUX_B) | \ 1664 BIT(POWER_DOMAIN_AUX_C) | \ 1665 BIT(POWER_DOMAIN_INIT)) 1666 1667 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ 1668 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1669 BIT(POWER_DOMAIN_AUX_B) | \ 1670 BIT(POWER_DOMAIN_INIT)) 1671 1672 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ 1673 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1674 BIT(POWER_DOMAIN_AUX_B) | \ 1675 BIT(POWER_DOMAIN_INIT)) 1676 1677 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ 1678 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1679 BIT(POWER_DOMAIN_AUX_C) | \ 1680 BIT(POWER_DOMAIN_INIT)) 1681 1682 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ 1683 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1684 BIT(POWER_DOMAIN_AUX_C) | \ 1685 BIT(POWER_DOMAIN_INIT)) 1686 1687 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ 1688 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ 1689 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ 1690 BIT(POWER_DOMAIN_AUX_B) | \ 1691 BIT(POWER_DOMAIN_AUX_C) | \ 1692 BIT(POWER_DOMAIN_INIT)) 1693 1694 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ 1695 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ 1696 BIT(POWER_DOMAIN_AUX_D) | \ 1697 BIT(POWER_DOMAIN_INIT)) 1698 1699 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { 1700 .sync_hw = i9xx_always_on_power_well_noop, 1701 .enable = i9xx_always_on_power_well_noop, 1702 .disable = i9xx_always_on_power_well_noop, 1703 .is_enabled = i9xx_always_on_power_well_enabled, 1704 }; 1705 1706 static const struct i915_power_well_ops chv_pipe_power_well_ops = { 1707 .sync_hw = chv_pipe_power_well_sync_hw, 1708 .enable = chv_pipe_power_well_enable, 1709 .disable = chv_pipe_power_well_disable, 1710 .is_enabled = chv_pipe_power_well_enabled, 1711 }; 1712 1713 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { 1714 .sync_hw = vlv_power_well_sync_hw, 1715 .enable = chv_dpio_cmn_power_well_enable, 1716 .disable = chv_dpio_cmn_power_well_disable, 1717 .is_enabled = vlv_power_well_enabled, 1718 }; 1719 1720 static struct i915_power_well i9xx_always_on_power_well[] = { 1721 { 1722 .name = "always-on", 1723 .always_on = 1, 1724 .domains = POWER_DOMAIN_MASK, 1725 .ops = &i9xx_always_on_power_well_ops, 1726 }, 1727 }; 1728 1729 static const struct i915_power_well_ops hsw_power_well_ops = { 1730 .sync_hw = hsw_power_well_sync_hw, 1731 .enable = hsw_power_well_enable, 1732 .disable = hsw_power_well_disable, 1733 .is_enabled = hsw_power_well_enabled, 1734 }; 1735 1736 static const struct i915_power_well_ops skl_power_well_ops = { 1737 .sync_hw = skl_power_well_sync_hw, 1738 .enable = skl_power_well_enable, 1739 .disable = skl_power_well_disable, 1740 .is_enabled = skl_power_well_enabled, 1741 }; 1742 1743 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { 1744 .sync_hw = gen9_dc_off_power_well_sync_hw, 1745 .enable = gen9_dc_off_power_well_enable, 1746 .disable = gen9_dc_off_power_well_disable, 1747 .is_enabled = gen9_dc_off_power_well_enabled, 1748 }; 1749 1750 static struct i915_power_well hsw_power_wells[] = { 1751 { 1752 .name = "always-on", 1753 .always_on = 1, 1754 .domains = HSW_ALWAYS_ON_POWER_DOMAINS, 1755 .ops = &i9xx_always_on_power_well_ops, 1756 }, 1757 { 1758 .name = "display", 1759 .domains = HSW_DISPLAY_POWER_DOMAINS, 1760 .ops = &hsw_power_well_ops, 1761 }, 1762 }; 1763 1764 static struct i915_power_well bdw_power_wells[] = { 1765 { 1766 .name = "always-on", 1767 .always_on = 1, 1768 .domains = BDW_ALWAYS_ON_POWER_DOMAINS, 1769 .ops = &i9xx_always_on_power_well_ops, 1770 }, 1771 { 1772 .name = "display", 1773 .domains = BDW_DISPLAY_POWER_DOMAINS, 1774 .ops = &hsw_power_well_ops, 1775 }, 1776 }; 1777 1778 static const struct i915_power_well_ops vlv_display_power_well_ops = { 1779 .sync_hw = vlv_power_well_sync_hw, 1780 .enable = vlv_display_power_well_enable, 1781 .disable = vlv_display_power_well_disable, 1782 .is_enabled = vlv_power_well_enabled, 1783 }; 1784 1785 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { 1786 .sync_hw = vlv_power_well_sync_hw, 1787 .enable = vlv_dpio_cmn_power_well_enable, 1788 .disable = vlv_dpio_cmn_power_well_disable, 1789 .is_enabled = vlv_power_well_enabled, 1790 }; 1791 1792 static const struct i915_power_well_ops vlv_dpio_power_well_ops = { 1793 .sync_hw = vlv_power_well_sync_hw, 1794 .enable = vlv_power_well_enable, 1795 .disable = vlv_power_well_disable, 1796 .is_enabled = vlv_power_well_enabled, 1797 }; 1798 1799 static struct i915_power_well vlv_power_wells[] = { 1800 { 1801 .name = "always-on", 1802 .always_on = 1, 1803 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1804 .ops = &i9xx_always_on_power_well_ops, 1805 .data = PUNIT_POWER_WELL_ALWAYS_ON, 1806 }, 1807 { 1808 .name = "display", 1809 .domains = VLV_DISPLAY_POWER_DOMAINS, 1810 .data = PUNIT_POWER_WELL_DISP2D, 1811 .ops = &vlv_display_power_well_ops, 1812 }, 1813 { 1814 .name = "dpio-tx-b-01", 1815 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1816 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1817 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1818 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1819 .ops = &vlv_dpio_power_well_ops, 1820 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, 1821 }, 1822 { 1823 .name = "dpio-tx-b-23", 1824 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1825 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1826 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1827 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1828 .ops = &vlv_dpio_power_well_ops, 1829 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, 1830 }, 1831 { 1832 .name = "dpio-tx-c-01", 1833 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1834 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1835 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1836 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1837 .ops = &vlv_dpio_power_well_ops, 1838 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, 1839 }, 1840 { 1841 .name = "dpio-tx-c-23", 1842 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | 1843 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | 1844 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | 1845 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, 1846 .ops = &vlv_dpio_power_well_ops, 1847 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, 1848 }, 1849 { 1850 .name = "dpio-common", 1851 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, 1852 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1853 .ops = &vlv_dpio_cmn_power_well_ops, 1854 }, 1855 }; 1856 1857 static struct i915_power_well chv_power_wells[] = { 1858 { 1859 .name = "always-on", 1860 .always_on = 1, 1861 .domains = VLV_ALWAYS_ON_POWER_DOMAINS, 1862 .ops = &i9xx_always_on_power_well_ops, 1863 }, 1864 { 1865 .name = "display", 1866 /* 1867 * Pipe A power well is the new disp2d well. Pipe B and C 1868 * power wells don't actually exist. Pipe A power well is 1869 * required for any pipe to work. 1870 */ 1871 .domains = VLV_DISPLAY_POWER_DOMAINS, 1872 .data = PIPE_A, 1873 .ops = &chv_pipe_power_well_ops, 1874 }, 1875 { 1876 .name = "dpio-common-bc", 1877 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, 1878 .data = PUNIT_POWER_WELL_DPIO_CMN_BC, 1879 .ops = &chv_dpio_cmn_power_well_ops, 1880 }, 1881 { 1882 .name = "dpio-common-d", 1883 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, 1884 .data = PUNIT_POWER_WELL_DPIO_CMN_D, 1885 .ops = &chv_dpio_cmn_power_well_ops, 1886 }, 1887 }; 1888 1889 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, 1890 int power_well_id) 1891 { 1892 struct i915_power_well *power_well; 1893 bool ret; 1894 1895 power_well = lookup_power_well(dev_priv, power_well_id); 1896 ret = power_well->ops->is_enabled(dev_priv, power_well); 1897 1898 return ret; 1899 } 1900 1901 static struct i915_power_well skl_power_wells[] = { 1902 { 1903 .name = "always-on", 1904 .always_on = 1, 1905 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1906 .ops = &i9xx_always_on_power_well_ops, 1907 .data = SKL_DISP_PW_ALWAYS_ON, 1908 }, 1909 { 1910 .name = "power well 1", 1911 /* Handled by the DMC firmware */ 1912 .domains = 0, 1913 .ops = &skl_power_well_ops, 1914 .data = SKL_DISP_PW_1, 1915 }, 1916 { 1917 .name = "MISC IO power well", 1918 /* Handled by the DMC firmware */ 1919 .domains = 0, 1920 .ops = &skl_power_well_ops, 1921 .data = SKL_DISP_PW_MISC_IO, 1922 }, 1923 { 1924 .name = "DC off", 1925 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, 1926 .ops = &gen9_dc_off_power_well_ops, 1927 .data = SKL_DISP_PW_DC_OFF, 1928 }, 1929 { 1930 .name = "power well 2", 1931 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, 1932 .ops = &skl_power_well_ops, 1933 .data = SKL_DISP_PW_2, 1934 }, 1935 { 1936 .name = "DDI A/E power well", 1937 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, 1938 .ops = &skl_power_well_ops, 1939 .data = SKL_DISP_PW_DDI_A_E, 1940 }, 1941 { 1942 .name = "DDI B power well", 1943 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, 1944 .ops = &skl_power_well_ops, 1945 .data = SKL_DISP_PW_DDI_B, 1946 }, 1947 { 1948 .name = "DDI C power well", 1949 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, 1950 .ops = &skl_power_well_ops, 1951 .data = SKL_DISP_PW_DDI_C, 1952 }, 1953 { 1954 .name = "DDI D power well", 1955 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, 1956 .ops = &skl_power_well_ops, 1957 .data = SKL_DISP_PW_DDI_D, 1958 }, 1959 }; 1960 1961 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv) 1962 { 1963 struct i915_power_well *well; 1964 1965 if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) 1966 return; 1967 1968 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1969 intel_power_well_enable(dev_priv, well); 1970 1971 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1972 intel_power_well_enable(dev_priv, well); 1973 } 1974 1975 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv) 1976 { 1977 struct i915_power_well *well; 1978 1979 if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))) 1980 return; 1981 1982 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); 1983 intel_power_well_disable(dev_priv, well); 1984 1985 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); 1986 intel_power_well_disable(dev_priv, well); 1987 } 1988 1989 static struct i915_power_well bxt_power_wells[] = { 1990 { 1991 .name = "always-on", 1992 .always_on = 1, 1993 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, 1994 .ops = &i9xx_always_on_power_well_ops, 1995 }, 1996 { 1997 .name = "power well 1", 1998 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, 1999 .ops = &skl_power_well_ops, 2000 .data = SKL_DISP_PW_1, 2001 }, 2002 { 2003 .name = "DC off", 2004 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, 2005 .ops = &gen9_dc_off_power_well_ops, 2006 .data = SKL_DISP_PW_DC_OFF, 2007 }, 2008 { 2009 .name = "power well 2", 2010 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, 2011 .ops = &skl_power_well_ops, 2012 .data = SKL_DISP_PW_2, 2013 }, 2014 }; 2015 2016 static int 2017 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, 2018 int disable_power_well) 2019 { 2020 if (disable_power_well >= 0) 2021 return !!disable_power_well; 2022 2023 if (IS_BROXTON(dev_priv)) { 2024 DRM_DEBUG_KMS("Disabling display power well support\n"); 2025 return 0; 2026 } 2027 2028 return 1; 2029 } 2030 2031 #define set_power_wells(power_domains, __power_wells) ({ \ 2032 (power_domains)->power_wells = (__power_wells); \ 2033 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ 2034 }) 2035 2036 /** 2037 * intel_power_domains_init - initializes the power domain structures 2038 * @dev_priv: i915 device instance 2039 * 2040 * Initializes the power domain structures for @dev_priv depending upon the 2041 * supported platform. 2042 */ 2043 int intel_power_domains_init(struct drm_i915_private *dev_priv) 2044 { 2045 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2046 2047 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, 2048 i915.disable_power_well); 2049 2050 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); 2051 2052 lockinit(&power_domains->lock, "i915pl", 0, LK_CANRECURSE); 2053 2054 /* 2055 * The enabling order will be from lower to higher indexed wells, 2056 * the disabling order is reversed. 2057 */ 2058 if (IS_HASWELL(dev_priv->dev)) { 2059 set_power_wells(power_domains, hsw_power_wells); 2060 } else if (IS_BROADWELL(dev_priv->dev)) { 2061 set_power_wells(power_domains, bdw_power_wells); 2062 } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { 2063 set_power_wells(power_domains, skl_power_wells); 2064 } else if (IS_BROXTON(dev_priv->dev)) { 2065 set_power_wells(power_domains, bxt_power_wells); 2066 } else if (IS_CHERRYVIEW(dev_priv->dev)) { 2067 set_power_wells(power_domains, chv_power_wells); 2068 } else if (IS_VALLEYVIEW(dev_priv->dev)) { 2069 set_power_wells(power_domains, vlv_power_wells); 2070 } else { 2071 set_power_wells(power_domains, i9xx_always_on_power_well); 2072 } 2073 2074 return 0; 2075 } 2076 2077 /** 2078 * intel_power_domains_fini - finalizes the power domain structures 2079 * @dev_priv: i915 device instance 2080 * 2081 * Finalizes the power domain structures for @dev_priv depending upon the 2082 * supported platform. This function also disables runtime pm and ensures that 2083 * the device stays powered up so that the driver can be reloaded. 2084 */ 2085 void intel_power_domains_fini(struct drm_i915_private *dev_priv) 2086 { 2087 #if 0 2088 struct device *device = &dev_priv->dev->pdev->dev; 2089 #endif 2090 2091 /* 2092 * The i915.ko module is still not prepared to be loaded when 2093 * the power well is not enabled, so just enable it in case 2094 * we're going to unload/reload. 2095 * The following also reacquires the RPM reference the core passed 2096 * to the driver during loading, which is dropped in 2097 * intel_runtime_pm_enable(). We have to hand back the control of the 2098 * device to the core with this reference held. 2099 */ 2100 intel_display_set_init_power(dev_priv, true); 2101 2102 /* Remove the refcount we took to keep power well support disabled. */ 2103 if (!i915.disable_power_well) 2104 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2105 2106 /* 2107 * Remove the refcount we took in intel_runtime_pm_enable() in case 2108 * the platform doesn't support runtime PM. 2109 */ 2110 #if 0 2111 if (!HAS_RUNTIME_PM(dev_priv)) 2112 pm_runtime_put(device); 2113 #endif 2114 } 2115 2116 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) 2117 { 2118 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2119 struct i915_power_well *power_well; 2120 int i; 2121 2122 mutex_lock(&power_domains->lock); 2123 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { 2124 power_well->ops->sync_hw(dev_priv, power_well); 2125 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, 2126 power_well); 2127 } 2128 mutex_unlock(&power_domains->lock); 2129 } 2130 2131 static void skl_display_core_init(struct drm_i915_private *dev_priv, 2132 bool resume) 2133 { 2134 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2135 uint32_t val; 2136 2137 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2138 2139 /* enable PCH reset handshake */ 2140 val = I915_READ(HSW_NDE_RSTWRN_OPT); 2141 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); 2142 2143 /* enable PG1 and Misc I/O */ 2144 mutex_lock(&power_domains->lock); 2145 skl_pw1_misc_io_init(dev_priv); 2146 mutex_unlock(&power_domains->lock); 2147 2148 if (!resume) 2149 return; 2150 2151 skl_init_cdclk(dev_priv); 2152 2153 if (dev_priv->csr.dmc_payload && intel_csr_load_program(dev_priv)) 2154 gen9_set_dc_state_debugmask(dev_priv); 2155 } 2156 2157 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) 2158 { 2159 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2160 2161 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); 2162 2163 skl_uninit_cdclk(dev_priv); 2164 2165 /* The spec doesn't call for removing the reset handshake flag */ 2166 /* disable PG1 and Misc I/O */ 2167 mutex_lock(&power_domains->lock); 2168 skl_pw1_misc_io_fini(dev_priv); 2169 mutex_unlock(&power_domains->lock); 2170 } 2171 2172 static void chv_phy_control_init(struct drm_i915_private *dev_priv) 2173 { 2174 struct i915_power_well *cmn_bc = 2175 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2176 struct i915_power_well *cmn_d = 2177 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); 2178 2179 /* 2180 * DISPLAY_PHY_CONTROL can get corrupted if read. As a 2181 * workaround never ever read DISPLAY_PHY_CONTROL, and 2182 * instead maintain a shadow copy ourselves. Use the actual 2183 * power well state and lane status to reconstruct the 2184 * expected initial value. 2185 */ 2186 dev_priv->chv_phy_control = 2187 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | 2188 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | 2189 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | 2190 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | 2191 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); 2192 2193 /* 2194 * If all lanes are disabled we leave the override disabled 2195 * with all power down bits cleared to match the state we 2196 * would use after disabling the port. Otherwise enable the 2197 * override and set the lane powerdown bits accding to the 2198 * current lane status. 2199 */ 2200 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { 2201 uint32_t status = I915_READ(DPLL(PIPE_A)); 2202 unsigned int mask; 2203 2204 mask = status & DPLL_PORTB_READY_MASK; 2205 if (mask == 0xf) 2206 mask = 0x0; 2207 else 2208 dev_priv->chv_phy_control |= 2209 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); 2210 2211 dev_priv->chv_phy_control |= 2212 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); 2213 2214 mask = (status & DPLL_PORTC_READY_MASK) >> 4; 2215 if (mask == 0xf) 2216 mask = 0x0; 2217 else 2218 dev_priv->chv_phy_control |= 2219 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); 2220 2221 dev_priv->chv_phy_control |= 2222 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); 2223 2224 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); 2225 2226 dev_priv->chv_phy_assert[DPIO_PHY0] = false; 2227 } else { 2228 dev_priv->chv_phy_assert[DPIO_PHY0] = true; 2229 } 2230 2231 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { 2232 uint32_t status = I915_READ(DPIO_PHY_STATUS); 2233 unsigned int mask; 2234 2235 mask = status & DPLL_PORTD_READY_MASK; 2236 2237 if (mask == 0xf) 2238 mask = 0x0; 2239 else 2240 dev_priv->chv_phy_control |= 2241 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); 2242 2243 dev_priv->chv_phy_control |= 2244 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); 2245 2246 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); 2247 2248 dev_priv->chv_phy_assert[DPIO_PHY1] = false; 2249 } else { 2250 dev_priv->chv_phy_assert[DPIO_PHY1] = true; 2251 } 2252 2253 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); 2254 2255 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", 2256 dev_priv->chv_phy_control); 2257 } 2258 2259 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) 2260 { 2261 struct i915_power_well *cmn = 2262 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); 2263 struct i915_power_well *disp2d = 2264 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); 2265 2266 /* If the display might be already active skip this */ 2267 if (cmn->ops->is_enabled(dev_priv, cmn) && 2268 disp2d->ops->is_enabled(dev_priv, disp2d) && 2269 I915_READ(DPIO_CTL) & DPIO_CMNRST) 2270 return; 2271 2272 DRM_DEBUG_KMS("toggling display PHY side reset\n"); 2273 2274 /* cmnlane needs DPLL registers */ 2275 disp2d->ops->enable(dev_priv, disp2d); 2276 2277 /* 2278 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: 2279 * Need to assert and de-assert PHY SB reset by gating the 2280 * common lane power, then un-gating it. 2281 * Simply ungating isn't enough to reset the PHY enough to get 2282 * ports and lanes running. 2283 */ 2284 cmn->ops->disable(dev_priv, cmn); 2285 } 2286 2287 /** 2288 * intel_power_domains_init_hw - initialize hardware power domain state 2289 * @dev_priv: i915 device instance 2290 * 2291 * This function initializes the hardware power domain state and enables all 2292 * power domains using intel_display_set_init_power(). 2293 */ 2294 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) 2295 { 2296 struct drm_device *dev = dev_priv->dev; 2297 struct i915_power_domains *power_domains = &dev_priv->power_domains; 2298 2299 power_domains->initializing = true; 2300 2301 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 2302 skl_display_core_init(dev_priv, resume); 2303 } else if (IS_CHERRYVIEW(dev)) { 2304 mutex_lock(&power_domains->lock); 2305 chv_phy_control_init(dev_priv); 2306 mutex_unlock(&power_domains->lock); 2307 } else if (IS_VALLEYVIEW(dev)) { 2308 mutex_lock(&power_domains->lock); 2309 vlv_cmnlane_wa(dev_priv); 2310 mutex_unlock(&power_domains->lock); 2311 } 2312 2313 /* For now, we need the power well to be always enabled. */ 2314 intel_display_set_init_power(dev_priv, true); 2315 /* Disable power support if the user asked so. */ 2316 if (!i915.disable_power_well) 2317 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 2318 intel_power_domains_sync_hw(dev_priv); 2319 power_domains->initializing = false; 2320 } 2321 2322 /** 2323 * intel_power_domains_suspend - suspend power domain state 2324 * @dev_priv: i915 device instance 2325 * 2326 * This function prepares the hardware power domain state before entering 2327 * system suspend. It must be paired with intel_power_domains_init_hw(). 2328 */ 2329 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) 2330 { 2331 /* 2332 * Even if power well support was disabled we still want to disable 2333 * power wells while we are system suspended. 2334 */ 2335 if (!i915.disable_power_well) 2336 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 2337 2338 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) 2339 skl_display_core_uninit(dev_priv); 2340 } 2341 2342 /** 2343 * intel_runtime_pm_get - grab a runtime pm reference 2344 * @dev_priv: i915 device instance 2345 * 2346 * This function grabs a device-level runtime pm reference (mostly used for GEM 2347 * code to ensure the GTT or GT is on) and ensures that it is powered up. 2348 * 2349 * Any runtime pm reference obtained by this function must have a symmetric 2350 * call to intel_runtime_pm_put() to release the reference again. 2351 */ 2352 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) 2353 { 2354 #if 0 2355 struct drm_device *dev = dev_priv->dev; 2356 struct device *device = &dev->pdev->dev; 2357 2358 pm_runtime_get_sync(device); 2359 #endif 2360 2361 atomic_inc(&dev_priv->pm.wakeref_count); 2362 assert_rpm_wakelock_held(dev_priv); 2363 } 2364 2365 /** 2366 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use 2367 * @dev_priv: i915 device instance 2368 * 2369 * This function grabs a device-level runtime pm reference if the device is 2370 * already in use and ensures that it is powered up. 2371 * 2372 * Any runtime pm reference obtained by this function must have a symmetric 2373 * call to intel_runtime_pm_put() to release the reference again. 2374 */ 2375 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) 2376 { 2377 #ifndef __DragonFly__ 2378 struct drm_device *dev = dev_priv->dev; 2379 struct device *device = &dev->pdev->dev; 2380 2381 if (IS_ENABLED(CONFIG_PM)) { 2382 int ret = pm_runtime_get_if_in_use(device); 2383 2384 /* 2385 * In cases runtime PM is disabled by the RPM core and we get 2386 * an -EINVAL return value we are not supposed to call this 2387 * function, since the power state is undefined. This applies 2388 * atm to the late/early system suspend/resume handlers. 2389 */ 2390 WARN_ON_ONCE(ret < 0); 2391 if (ret <= 0) 2392 return false; 2393 } 2394 2395 atomic_inc(&dev_priv->pm.wakeref_count); 2396 assert_rpm_wakelock_held(dev_priv); 2397 #endif 2398 2399 return true; 2400 } 2401 2402 /** 2403 * intel_runtime_pm_get_noresume - grab a runtime pm reference 2404 * @dev_priv: i915 device instance 2405 * 2406 * This function grabs a device-level runtime pm reference (mostly used for GEM 2407 * code to ensure the GTT or GT is on). 2408 * 2409 * It will _not_ power up the device but instead only check that it's powered 2410 * on. Therefore it is only valid to call this functions from contexts where 2411 * the device is known to be powered up and where trying to power it up would 2412 * result in hilarity and deadlocks. That pretty much means only the system 2413 * suspend/resume code where this is used to grab runtime pm references for 2414 * delayed setup down in work items. 2415 * 2416 * Any runtime pm reference obtained by this function must have a symmetric 2417 * call to intel_runtime_pm_put() to release the reference again. 2418 */ 2419 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) 2420 { 2421 #if 0 2422 struct drm_device *dev = dev_priv->dev; 2423 struct device *device = &dev->pdev->dev; 2424 #endif 2425 2426 assert_rpm_wakelock_held(dev_priv); 2427 #if 0 2428 pm_runtime_get_noresume(device); 2429 #endif 2430 2431 atomic_inc(&dev_priv->pm.wakeref_count); 2432 } 2433 2434 /** 2435 * intel_runtime_pm_put - release a runtime pm reference 2436 * @dev_priv: i915 device instance 2437 * 2438 * This function drops the device-level runtime pm reference obtained by 2439 * intel_runtime_pm_get() and might power down the corresponding 2440 * hardware block right away if this is the last reference. 2441 */ 2442 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) 2443 { 2444 #if 0 2445 struct drm_device *dev = dev_priv->dev; 2446 struct device *device = &dev->pdev->dev; 2447 2448 assert_rpm_wakelock_held(dev_priv); 2449 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count)) 2450 atomic_inc(&dev_priv->pm.atomic_seq); 2451 2452 pm_runtime_mark_last_busy(device); 2453 pm_runtime_put_autosuspend(device); 2454 #endif 2455 } 2456 2457 /** 2458 * intel_runtime_pm_enable - enable runtime pm 2459 * @dev_priv: i915 device instance 2460 * 2461 * This function enables runtime pm at the end of the driver load sequence. 2462 * 2463 * Note that this function does currently not enable runtime pm for the 2464 * subordinate display power domains. That is only done on the first modeset 2465 * using intel_display_set_init_power(). 2466 */ 2467 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) 2468 { 2469 #if 0 2470 struct drm_device *dev = dev_priv->dev; 2471 struct device *device = &dev->pdev->dev; 2472 2473 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ 2474 pm_runtime_mark_last_busy(device); 2475 2476 /* 2477 * Take a permanent reference to disable the RPM functionality and drop 2478 * it only when unloading the driver. Use the low level get/put helpers, 2479 * so the driver's own RPM reference tracking asserts also work on 2480 * platforms without RPM support. 2481 */ 2482 if (!HAS_RUNTIME_PM(dev)) { 2483 pm_runtime_dont_use_autosuspend(device); 2484 pm_runtime_get_sync(device); 2485 } else { 2486 pm_runtime_use_autosuspend(device); 2487 } 2488 2489 /* 2490 * The core calls the driver load handler with an RPM reference held. 2491 * We drop that here and will reacquire it during unloading in 2492 * intel_power_domains_fini(). 2493 */ 2494 pm_runtime_put_autosuspend(device); 2495 #endif 2496 } 2497 2498