1 #ifndef _INTEL_RINGBUFFER_H_ 2 #define _INTEL_RINGBUFFER_H_ 3 4 #include <linux/hashtable.h> 5 #include "i915_gem_batch_pool.h" 6 #include "i915_gem_request.h" 7 8 #define I915_CMD_HASH_ORDER 9 9 10 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, 11 * but keeps the logic simple. Indeed, the whole purpose of this macro is just 12 * to give some inclination as to some of the magic values used in the various 13 * workarounds! 14 */ 15 #define CACHELINE_BYTES 64 16 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) 17 18 /* 19 * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" 20 * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" 21 * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" 22 * 23 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same 24 * cacheline, the Head Pointer must not be greater than the Tail 25 * Pointer." 26 */ 27 #define I915_RING_FREE_SPACE 64 28 29 struct intel_hw_status_page { 30 u32 *page_addr; 31 unsigned int gfx_addr; 32 struct drm_i915_gem_object *obj; 33 }; 34 35 #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base)) 36 #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val) 37 38 #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base)) 39 #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val) 40 41 #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base)) 42 #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val) 43 44 #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base)) 45 #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val) 46 47 #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base)) 48 #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val) 49 50 #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base)) 51 #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val) 52 53 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to 54 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. 55 */ 56 #define gen8_semaphore_seqno_size sizeof(uint64_t) 57 #define GEN8_SEMAPHORE_OFFSET(__from, __to) \ 58 (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size) 59 #define GEN8_SIGNAL_OFFSET(__ring, to) \ 60 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ 61 GEN8_SEMAPHORE_OFFSET((__ring)->id, (to))) 62 #define GEN8_WAIT_OFFSET(__ring, from) \ 63 (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ 64 GEN8_SEMAPHORE_OFFSET(from, (__ring)->id)) 65 66 enum intel_engine_hangcheck_action { 67 HANGCHECK_IDLE = 0, 68 HANGCHECK_WAIT, 69 HANGCHECK_ACTIVE, 70 HANGCHECK_KICK, 71 HANGCHECK_HUNG, 72 }; 73 74 #define HANGCHECK_SCORE_RING_HUNG 31 75 76 struct intel_engine_hangcheck { 77 u64 acthd; 78 unsigned long user_interrupts; 79 u32 seqno; 80 int score; 81 enum intel_engine_hangcheck_action action; 82 int deadlock; 83 u32 instdone[I915_NUM_INSTDONE_REG]; 84 }; 85 86 struct intel_ring { 87 struct drm_i915_gem_object *obj; 88 void *vaddr; 89 struct i915_vma *vma; 90 91 struct intel_engine_cs *engine; 92 struct list_head link; 93 94 struct list_head request_list; 95 96 u32 head; 97 u32 tail; 98 int space; 99 int size; 100 int effective_size; 101 102 /** We track the position of the requests in the ring buffer, and 103 * when each is retired we increment last_retired_head as the GPU 104 * must have finished processing the request and so we know we 105 * can advance the ringbuffer up to that position. 106 * 107 * last_retired_head is set to -1 after the value is consumed so 108 * we can detect new retirements. 109 */ 110 u32 last_retired_head; 111 }; 112 113 struct i915_gem_context; 114 struct drm_i915_reg_table; 115 116 /* 117 * we use a single page to load ctx workarounds so all of these 118 * values are referred in terms of dwords 119 * 120 * struct i915_wa_ctx_bb: 121 * offset: specifies batch starting position, also helpful in case 122 * if we want to have multiple batches at different offsets based on 123 * some criteria. It is not a requirement at the moment but provides 124 * an option for future use. 125 * size: size of the batch in DWORDS 126 */ 127 struct i915_ctx_workarounds { 128 struct i915_wa_ctx_bb { 129 u32 offset; 130 u32 size; 131 } indirect_ctx, per_ctx; 132 struct drm_i915_gem_object *obj; 133 }; 134 135 struct drm_i915_gem_request; 136 137 struct intel_engine_cs { 138 struct drm_i915_private *i915; 139 const char *name; 140 enum intel_engine_id { 141 RCS = 0, 142 BCS, 143 VCS, 144 VCS2, /* Keep instances of the same type engine together. */ 145 VECS 146 } id; 147 #define I915_NUM_ENGINES 5 148 #define _VCS(n) (VCS + (n)) 149 unsigned int exec_id; 150 unsigned int hw_id; 151 unsigned int guc_id; /* XXX same as hw_id? */ 152 u64 fence_context; 153 u32 mmio_base; 154 unsigned int irq_shift; 155 struct intel_ring *buffer; 156 struct list_head buffers; 157 158 /* Rather than have every client wait upon all user interrupts, 159 * with the herd waking after every interrupt and each doing the 160 * heavyweight seqno dance, we delegate the task (of being the 161 * bottom-half of the user interrupt) to the first client. After 162 * every interrupt, we wake up one client, who does the heavyweight 163 * coherent seqno read and either goes back to sleep (if incomplete), 164 * or wakes up all the completed clients in parallel, before then 165 * transferring the bottom-half status to the next client in the queue. 166 * 167 * Compared to walking the entire list of waiters in a single dedicated 168 * bottom-half, we reduce the latency of the first waiter by avoiding 169 * a context switch, but incur additional coherent seqno reads when 170 * following the chain of request breadcrumbs. Since it is most likely 171 * that we have a single client waiting on each seqno, then reducing 172 * the overhead of waking that client is much preferred. 173 */ 174 struct intel_breadcrumbs { 175 struct task_struct *irq_seqno_bh; /* bh for user interrupts */ 176 unsigned long irq_wakeups; 177 bool irq_posted; 178 179 spinlock_t lock; /* protects the lists of requests */ 180 struct rb_root waiters; /* sorted by retirement, priority */ 181 struct rb_root signals; /* sorted by retirement */ 182 struct intel_wait *first_wait; /* oldest waiter by retirement */ 183 struct task_struct *signaler; /* used for fence signalling */ 184 struct drm_i915_gem_request *first_signal; 185 struct timer_list fake_irq; /* used after a missed interrupt */ 186 187 bool irq_enabled : 1; 188 bool rpm_wakelock : 1; 189 } breadcrumbs; 190 191 /* 192 * A pool of objects to use as shadow copies of client batch buffers 193 * when the command parser is enabled. Prevents the client from 194 * modifying the batch contents after software parsing. 195 */ 196 struct i915_gem_batch_pool batch_pool; 197 198 struct intel_hw_status_page status_page; 199 struct i915_ctx_workarounds wa_ctx; 200 201 u32 irq_keep_mask; /* always keep these interrupts */ 202 u32 irq_enable_mask; /* bitmask to enable ring interrupt */ 203 void (*irq_enable)(struct intel_engine_cs *engine); 204 void (*irq_disable)(struct intel_engine_cs *engine); 205 206 int (*init_hw)(struct intel_engine_cs *engine); 207 208 int (*init_context)(struct drm_i915_gem_request *req); 209 210 int (*emit_flush)(struct drm_i915_gem_request *request, 211 u32 mode); 212 #define EMIT_INVALIDATE BIT(0) 213 #define EMIT_FLUSH BIT(1) 214 #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH) 215 int (*emit_bb_start)(struct drm_i915_gem_request *req, 216 u64 offset, u32 length, 217 unsigned int dispatch_flags); 218 #define I915_DISPATCH_SECURE BIT(0) 219 #define I915_DISPATCH_PINNED BIT(1) 220 #define I915_DISPATCH_RS BIT(2) 221 int (*emit_request)(struct drm_i915_gem_request *req); 222 void (*submit_request)(struct drm_i915_gem_request *req); 223 /* Some chipsets are not quite as coherent as advertised and need 224 * an expensive kick to force a true read of the up-to-date seqno. 225 * However, the up-to-date seqno is not always required and the last 226 * seen value is good enough. Note that the seqno will always be 227 * monotonic, even if not coherent. 228 */ 229 void (*irq_seqno_barrier)(struct intel_engine_cs *engine); 230 void (*cleanup)(struct intel_engine_cs *engine); 231 232 /* GEN8 signal/wait table - never trust comments! 233 * signal to signal to signal to signal to signal to 234 * RCS VCS BCS VECS VCS2 235 * -------------------------------------------------------------------- 236 * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | 237 * |------------------------------------------------------------------- 238 * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | 239 * |------------------------------------------------------------------- 240 * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | 241 * |------------------------------------------------------------------- 242 * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | 243 * |------------------------------------------------------------------- 244 * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | 245 * |------------------------------------------------------------------- 246 * 247 * Generalization: 248 * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) 249 * ie. transpose of g(x, y) 250 * 251 * sync from sync from sync from sync from sync from 252 * RCS VCS BCS VECS VCS2 253 * -------------------------------------------------------------------- 254 * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | 255 * |------------------------------------------------------------------- 256 * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | 257 * |------------------------------------------------------------------- 258 * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | 259 * |------------------------------------------------------------------- 260 * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | 261 * |------------------------------------------------------------------- 262 * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | 263 * |------------------------------------------------------------------- 264 * 265 * Generalization: 266 * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) 267 * ie. transpose of f(x, y) 268 */ 269 struct { 270 u32 sync_seqno[I915_NUM_ENGINES-1]; 271 272 union { 273 struct { 274 /* our mbox written by others */ 275 u32 wait[I915_NUM_ENGINES]; 276 /* mboxes this ring signals to */ 277 i915_reg_t signal[I915_NUM_ENGINES]; 278 } mbox; 279 u64 signal_ggtt[I915_NUM_ENGINES]; 280 }; 281 282 /* AKA wait() */ 283 int (*sync_to)(struct drm_i915_gem_request *req, 284 struct drm_i915_gem_request *signal); 285 int (*signal)(struct drm_i915_gem_request *req); 286 } semaphore; 287 288 /* Execlists */ 289 struct tasklet_struct irq_tasklet; 290 spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */ 291 struct list_head execlist_queue; 292 unsigned int fw_domains; 293 unsigned int next_context_status_buffer; 294 unsigned int idle_lite_restore_wa; 295 bool disable_lite_restore_wa; 296 u32 ctx_desc_template; 297 298 /** 299 * List of breadcrumbs associated with GPU requests currently 300 * outstanding. 301 */ 302 struct list_head request_list; 303 304 /** 305 * Seqno of request most recently submitted to request_list. 306 * Used exclusively by hang checker to avoid grabbing lock while 307 * inspecting request list. 308 */ 309 u32 last_submitted_seqno; 310 311 /* An RCU guarded pointer to the last request. No reference is 312 * held to the request, users must carefully acquire a reference to 313 * the request using i915_gem_active_get_request_rcu(), or hold the 314 * struct_mutex. 315 */ 316 struct i915_gem_active last_request; 317 318 struct i915_gem_context *last_context; 319 320 struct intel_engine_hangcheck hangcheck; 321 322 struct { 323 struct drm_i915_gem_object *obj; 324 u32 gtt_offset; 325 } scratch; 326 327 bool needs_cmd_parser; 328 329 /* 330 * Table of commands the command parser needs to know about 331 * for this engine. 332 */ 333 DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); 334 335 /* 336 * Table of registers allowed in commands that read/write registers. 337 */ 338 const struct drm_i915_reg_table *reg_tables; 339 int reg_table_count; 340 341 /* 342 * Returns the bitmask for the length field of the specified command. 343 * Return 0 for an unrecognized/invalid command. 344 * 345 * If the command parser finds an entry for a command in the engine's 346 * cmd_tables, it gets the command's length based on the table entry. 347 * If not, it calls this function to determine the per-engine length 348 * field encoding for the command (i.e. different opcode ranges use 349 * certain bits to encode the command length in the header). 350 */ 351 u32 (*get_cmd_length_mask)(u32 cmd_header); 352 }; 353 354 static inline bool 355 intel_engine_initialized(const struct intel_engine_cs *engine) 356 { 357 return engine->i915 != NULL; 358 } 359 360 static inline unsigned 361 intel_engine_flag(const struct intel_engine_cs *engine) 362 { 363 return 1 << engine->id; 364 } 365 366 static inline u32 367 intel_engine_sync_index(struct intel_engine_cs *engine, 368 struct intel_engine_cs *other) 369 { 370 int idx; 371 372 /* 373 * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; 374 * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; 375 * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; 376 * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; 377 * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; 378 */ 379 380 idx = (other - engine) - 1; 381 if (idx < 0) 382 idx += I915_NUM_ENGINES; 383 384 return idx; 385 } 386 387 static inline void 388 intel_flush_status_page(struct intel_engine_cs *engine, int reg) 389 { 390 mb(); 391 linux_clflush(&engine->status_page.page_addr[reg]); 392 mb(); 393 } 394 395 static inline u32 396 intel_read_status_page(struct intel_engine_cs *engine, int reg) 397 { 398 /* Ensure that the compiler doesn't optimize away the load. */ 399 return READ_ONCE(engine->status_page.page_addr[reg]); 400 } 401 402 static inline void 403 intel_write_status_page(struct intel_engine_cs *engine, 404 int reg, u32 value) 405 { 406 engine->status_page.page_addr[reg] = value; 407 } 408 409 /* 410 * Reads a dword out of the status page, which is written to from the command 411 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or 412 * MI_STORE_DATA_IMM. 413 * 414 * The following dwords have a reserved meaning: 415 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. 416 * 0x04: ring 0 head pointer 417 * 0x05: ring 1 head pointer (915-class) 418 * 0x06: ring 2 head pointer (915-class) 419 * 0x10-0x1b: Context status DWords (GM45) 420 * 0x1f: Last written status offset. (GM45) 421 * 0x20-0x2f: Reserved (Gen6+) 422 * 423 * The area from dword 0x30 to 0x3ff is available for driver usage. 424 */ 425 #define I915_GEM_HWS_INDEX 0x30 426 #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) 427 #define I915_GEM_HWS_SCRATCH_INDEX 0x40 428 #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) 429 430 struct intel_ring * 431 intel_engine_create_ring(struct intel_engine_cs *engine, int size); 432 int intel_ring_pin(struct intel_ring *ring); 433 void intel_ring_unpin(struct intel_ring *ring); 434 void intel_ring_free(struct intel_ring *ring); 435 436 void intel_engine_stop(struct intel_engine_cs *engine); 437 void intel_engine_cleanup(struct intel_engine_cs *engine); 438 439 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request); 440 441 int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n); 442 int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); 443 444 static inline void intel_ring_emit(struct intel_ring *ring, u32 data) 445 { 446 *(uint32_t *)(ring->vaddr + ring->tail) = data; 447 ring->tail += 4; 448 } 449 450 static inline void intel_ring_emit_reg(struct intel_ring *ring, i915_reg_t reg) 451 { 452 intel_ring_emit(ring, i915_mmio_reg_offset(reg)); 453 } 454 455 static inline void intel_ring_advance(struct intel_ring *ring) 456 { 457 /* Dummy function. 458 * 459 * This serves as a placeholder in the code so that the reader 460 * can compare against the preceding intel_ring_begin() and 461 * check that the number of dwords emitted matches the space 462 * reserved for the command packet (i.e. the value passed to 463 * intel_ring_begin()). 464 */ 465 } 466 467 static inline u32 intel_ring_offset(struct intel_ring *ring, u32 value) 468 { 469 /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */ 470 return value & (ring->size - 1); 471 } 472 473 int __intel_ring_space(int head, int tail, int size); 474 void intel_ring_update_space(struct intel_ring *ring); 475 476 void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno); 477 478 int intel_init_pipe_control(struct intel_engine_cs *engine, int size); 479 void intel_fini_pipe_control(struct intel_engine_cs *engine); 480 481 void intel_engine_setup_common(struct intel_engine_cs *engine); 482 int intel_engine_init_common(struct intel_engine_cs *engine); 483 void intel_engine_cleanup_common(struct intel_engine_cs *engine); 484 485 static inline int intel_engine_idle(struct intel_engine_cs *engine, 486 bool interruptible) 487 { 488 /* Wait upon the last request to be completed */ 489 return i915_gem_active_wait_unlocked(&engine->last_request, 490 interruptible, NULL, NULL); 491 } 492 493 int intel_init_render_ring_buffer(struct intel_engine_cs *engine); 494 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine); 495 int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine); 496 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine); 497 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine); 498 499 u64 intel_engine_get_active_head(struct intel_engine_cs *engine); 500 static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine) 501 { 502 return intel_read_status_page(engine, I915_GEM_HWS_INDEX); 503 } 504 505 int init_workarounds_ring(struct intel_engine_cs *engine); 506 507 /* 508 * Arbitrary size for largest possible 'add request' sequence. The code paths 509 * are complex and variable. Empirical measurement shows that the worst case 510 * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However, 511 * we need to allocate double the largest single packet within that emission 512 * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW). 513 */ 514 #define MIN_SPACE_FOR_ADD_REQUEST 336 515 516 static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine) 517 { 518 return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR; 519 } 520 521 /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */ 522 int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); 523 524 static inline void intel_wait_init(struct intel_wait *wait, u32 seqno) 525 { 526 wait->tsk = current; 527 wait->seqno = seqno; 528 } 529 530 static inline bool intel_wait_complete(const struct intel_wait *wait) 531 { 532 return RB_EMPTY_NODE(&wait->node); 533 } 534 535 bool intel_engine_add_wait(struct intel_engine_cs *engine, 536 struct intel_wait *wait); 537 void intel_engine_remove_wait(struct intel_engine_cs *engine, 538 struct intel_wait *wait); 539 void intel_engine_enable_signaling(struct drm_i915_gem_request *request); 540 541 static inline bool intel_engine_has_waiter(struct intel_engine_cs *engine) 542 { 543 return READ_ONCE(engine->breadcrumbs.irq_seqno_bh); 544 } 545 546 static inline bool intel_engine_wakeup(struct intel_engine_cs *engine) 547 { 548 bool wakeup = false; 549 struct task_struct *tsk = READ_ONCE(engine->breadcrumbs.irq_seqno_bh); 550 /* Note that for this not to dangerously chase a dangling pointer, 551 * the caller is responsible for ensure that the task remain valid for 552 * wake_up_process() i.e. that the RCU grace period cannot expire. 553 * 554 * Also note that tsk is likely to be in !TASK_RUNNING state so an 555 * early test for tsk->state != TASK_RUNNING before wake_up_process() 556 * is unlikely to be beneficial. 557 */ 558 if (tsk) 559 wakeup = wake_up_process(tsk); 560 return wakeup; 561 } 562 563 void intel_engine_enable_fake_irq(struct intel_engine_cs *engine); 564 void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); 565 unsigned int intel_kick_waiters(struct drm_i915_private *i915); 566 unsigned int intel_kick_signalers(struct drm_i915_private *i915); 567 568 static inline bool intel_engine_is_active(struct intel_engine_cs *engine) 569 { 570 return i915_gem_active_isset(&engine->last_request); 571 } 572 573 #endif /* _INTEL_RINGBUFFER_H_ */ 574