1 /* 2 * Copyright © 2008-2010 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * Zou Nan hai <nanhai.zou@intel.com> 26 * Xiang Hai hao<haihao.xiang@intel.com> 27 * 28 */ 29 30 #include <linux/log2.h> 31 #include <drm/drmP.h> 32 #include "i915_drv.h" 33 #include <drm/i915_drm.h> 34 #include "i915_trace.h" 35 #include "intel_drv.h" 36 37 /* Rough estimate of the typical request size, performing a flush, 38 * set-context and then emitting the batch. 39 */ 40 #define LEGACY_REQUEST_SIZE 200 41 42 int __intel_ring_space(int head, int tail, int size) 43 { 44 int space = head - tail; 45 if (space <= 0) 46 space += size; 47 return space - I915_RING_FREE_SPACE; 48 } 49 50 void intel_ring_update_space(struct intel_ring *ring) 51 { 52 if (ring->last_retired_head != -1) { 53 ring->head = ring->last_retired_head; 54 ring->last_retired_head = -1; 55 } 56 57 ring->space = __intel_ring_space(ring->head & HEAD_ADDR, 58 ring->tail, ring->size); 59 } 60 61 static int 62 gen2_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) 63 { 64 struct intel_ring *ring = req->ring; 65 u32 cmd; 66 int ret; 67 68 cmd = MI_FLUSH; 69 70 if (mode & EMIT_INVALIDATE) 71 cmd |= MI_READ_FLUSH; 72 73 ret = intel_ring_begin(req, 2); 74 if (ret) 75 return ret; 76 77 intel_ring_emit(ring, cmd); 78 intel_ring_emit(ring, MI_NOOP); 79 intel_ring_advance(ring); 80 81 return 0; 82 } 83 84 static int 85 gen4_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) 86 { 87 struct intel_ring *ring = req->ring; 88 u32 cmd; 89 int ret; 90 91 /* 92 * read/write caches: 93 * 94 * I915_GEM_DOMAIN_RENDER is always invalidated, but is 95 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is 96 * also flushed at 2d versus 3d pipeline switches. 97 * 98 * read-only caches: 99 * 100 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if 101 * MI_READ_FLUSH is set, and is always flushed on 965. 102 * 103 * I915_GEM_DOMAIN_COMMAND may not exist? 104 * 105 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is 106 * invalidated when MI_EXE_FLUSH is set. 107 * 108 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is 109 * invalidated with every MI_FLUSH. 110 * 111 * TLBs: 112 * 113 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND 114 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and 115 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER 116 * are flushed at any MI_FLUSH. 117 */ 118 119 cmd = MI_FLUSH; 120 if (mode & EMIT_INVALIDATE) { 121 cmd |= MI_EXE_FLUSH; 122 if (IS_G4X(req->i915) || IS_GEN5(req->i915)) 123 cmd |= MI_INVALIDATE_ISP; 124 } 125 126 ret = intel_ring_begin(req, 2); 127 if (ret) 128 return ret; 129 130 intel_ring_emit(ring, cmd); 131 intel_ring_emit(ring, MI_NOOP); 132 intel_ring_advance(ring); 133 134 return 0; 135 } 136 137 /** 138 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for 139 * implementing two workarounds on gen6. From section 1.4.7.1 140 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: 141 * 142 * [DevSNB-C+{W/A}] Before any depth stall flush (including those 143 * produced by non-pipelined state commands), software needs to first 144 * send a PIPE_CONTROL with no bits set except Post-Sync Operation != 145 * 0. 146 * 147 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable 148 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. 149 * 150 * And the workaround for these two requires this workaround first: 151 * 152 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent 153 * BEFORE the pipe-control with a post-sync op and no write-cache 154 * flushes. 155 * 156 * And this last workaround is tricky because of the requirements on 157 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM 158 * volume 2 part 1: 159 * 160 * "1 of the following must also be set: 161 * - Render Target Cache Flush Enable ([12] of DW1) 162 * - Depth Cache Flush Enable ([0] of DW1) 163 * - Stall at Pixel Scoreboard ([1] of DW1) 164 * - Depth Stall ([13] of DW1) 165 * - Post-Sync Operation ([13] of DW1) 166 * - Notify Enable ([8] of DW1)" 167 * 168 * The cache flushes require the workaround flush that triggered this 169 * one, so we can't use it. Depth stall would trigger the same. 170 * Post-sync nonzero is what triggered this second workaround, so we 171 * can't use that one either. Notify enable is IRQs, which aren't 172 * really our business. That leaves only stall at scoreboard. 173 */ 174 static int 175 intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req) 176 { 177 struct intel_ring *ring = req->ring; 178 u32 scratch_addr = 179 req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; 180 int ret; 181 182 ret = intel_ring_begin(req, 6); 183 if (ret) 184 return ret; 185 186 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); 187 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | 188 PIPE_CONTROL_STALL_AT_SCOREBOARD); 189 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); 190 intel_ring_emit(ring, 0); /* low dword */ 191 intel_ring_emit(ring, 0); /* high dword */ 192 intel_ring_emit(ring, MI_NOOP); 193 intel_ring_advance(ring); 194 195 ret = intel_ring_begin(req, 6); 196 if (ret) 197 return ret; 198 199 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); 200 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); 201 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); 202 intel_ring_emit(ring, 0); 203 intel_ring_emit(ring, 0); 204 intel_ring_emit(ring, MI_NOOP); 205 intel_ring_advance(ring); 206 207 return 0; 208 } 209 210 static int 211 gen6_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) 212 { 213 struct intel_ring *ring = req->ring; 214 u32 scratch_addr = 215 req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; 216 u32 flags = 0; 217 int ret; 218 219 /* Force SNB workarounds for PIPE_CONTROL flushes */ 220 ret = intel_emit_post_sync_nonzero_flush(req); 221 if (ret) 222 return ret; 223 224 /* Just flush everything. Experiments have shown that reducing the 225 * number of bits based on the write domains has little performance 226 * impact. 227 */ 228 if (mode & EMIT_FLUSH) { 229 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 230 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 231 /* 232 * Ensure that any following seqno writes only happen 233 * when the render cache is indeed flushed. 234 */ 235 flags |= PIPE_CONTROL_CS_STALL; 236 } 237 if (mode & EMIT_INVALIDATE) { 238 flags |= PIPE_CONTROL_TLB_INVALIDATE; 239 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 240 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 241 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 242 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 243 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 244 /* 245 * TLB invalidate requires a post-sync write. 246 */ 247 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; 248 } 249 250 ret = intel_ring_begin(req, 4); 251 if (ret) 252 return ret; 253 254 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); 255 intel_ring_emit(ring, flags); 256 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); 257 intel_ring_emit(ring, 0); 258 intel_ring_advance(ring); 259 260 return 0; 261 } 262 263 static int 264 gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req) 265 { 266 struct intel_ring *ring = req->ring; 267 int ret; 268 269 ret = intel_ring_begin(req, 4); 270 if (ret) 271 return ret; 272 273 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); 274 intel_ring_emit(ring, 275 PIPE_CONTROL_CS_STALL | 276 PIPE_CONTROL_STALL_AT_SCOREBOARD); 277 intel_ring_emit(ring, 0); 278 intel_ring_emit(ring, 0); 279 intel_ring_advance(ring); 280 281 return 0; 282 } 283 284 static int 285 gen7_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) 286 { 287 struct intel_ring *ring = req->ring; 288 u32 scratch_addr = 289 req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; 290 u32 flags = 0; 291 int ret; 292 293 /* 294 * Ensure that any following seqno writes only happen when the render 295 * cache is indeed flushed. 296 * 297 * Workaround: 4th PIPE_CONTROL command (except the ones with only 298 * read-cache invalidate bits set) must have the CS_STALL bit set. We 299 * don't try to be clever and just set it unconditionally. 300 */ 301 flags |= PIPE_CONTROL_CS_STALL; 302 303 /* Just flush everything. Experiments have shown that reducing the 304 * number of bits based on the write domains has little performance 305 * impact. 306 */ 307 if (mode & EMIT_FLUSH) { 308 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 309 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 310 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 311 flags |= PIPE_CONTROL_FLUSH_ENABLE; 312 } 313 if (mode & EMIT_INVALIDATE) { 314 flags |= PIPE_CONTROL_TLB_INVALIDATE; 315 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 316 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 317 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 318 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 319 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 320 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; 321 /* 322 * TLB invalidate requires a post-sync write. 323 */ 324 flags |= PIPE_CONTROL_QW_WRITE; 325 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 326 327 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; 328 329 /* Workaround: we must issue a pipe_control with CS-stall bit 330 * set before a pipe_control command that has the state cache 331 * invalidate bit set. */ 332 gen7_render_ring_cs_stall_wa(req); 333 } 334 335 ret = intel_ring_begin(req, 4); 336 if (ret) 337 return ret; 338 339 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); 340 intel_ring_emit(ring, flags); 341 intel_ring_emit(ring, scratch_addr); 342 intel_ring_emit(ring, 0); 343 intel_ring_advance(ring); 344 345 return 0; 346 } 347 348 static int 349 gen8_emit_pipe_control(struct drm_i915_gem_request *req, 350 u32 flags, u32 scratch_addr) 351 { 352 struct intel_ring *ring = req->ring; 353 int ret; 354 355 ret = intel_ring_begin(req, 6); 356 if (ret) 357 return ret; 358 359 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); 360 intel_ring_emit(ring, flags); 361 intel_ring_emit(ring, scratch_addr); 362 intel_ring_emit(ring, 0); 363 intel_ring_emit(ring, 0); 364 intel_ring_emit(ring, 0); 365 intel_ring_advance(ring); 366 367 return 0; 368 } 369 370 static int 371 gen8_render_ring_flush(struct drm_i915_gem_request *req, u32 mode) 372 { 373 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES; 374 u32 flags = 0; 375 int ret; 376 377 flags |= PIPE_CONTROL_CS_STALL; 378 379 if (mode & EMIT_FLUSH) { 380 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 381 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 382 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; 383 flags |= PIPE_CONTROL_FLUSH_ENABLE; 384 } 385 if (mode & EMIT_INVALIDATE) { 386 flags |= PIPE_CONTROL_TLB_INVALIDATE; 387 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 388 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 389 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 390 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 391 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 392 flags |= PIPE_CONTROL_QW_WRITE; 393 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 394 395 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ 396 ret = gen8_emit_pipe_control(req, 397 PIPE_CONTROL_CS_STALL | 398 PIPE_CONTROL_STALL_AT_SCOREBOARD, 399 0); 400 if (ret) 401 return ret; 402 } 403 404 return gen8_emit_pipe_control(req, flags, scratch_addr); 405 } 406 407 u64 intel_engine_get_active_head(struct intel_engine_cs *engine) 408 { 409 struct drm_i915_private *dev_priv = engine->i915; 410 u64 acthd; 411 412 if (INTEL_GEN(dev_priv) >= 8) 413 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), 414 RING_ACTHD_UDW(engine->mmio_base)); 415 else if (INTEL_GEN(dev_priv) >= 4) 416 acthd = I915_READ(RING_ACTHD(engine->mmio_base)); 417 else 418 acthd = I915_READ(ACTHD); 419 420 return acthd; 421 } 422 423 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) 424 { 425 struct drm_i915_private *dev_priv = engine->i915; 426 u32 addr; 427 428 addr = dev_priv->status_page_dmah->busaddr; 429 if (INTEL_GEN(dev_priv) >= 4) 430 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; 431 I915_WRITE(HWS_PGA, addr); 432 } 433 434 static void intel_ring_setup_status_page(struct intel_engine_cs *engine) 435 { 436 struct drm_i915_private *dev_priv = engine->i915; 437 i915_reg_t mmio; 438 439 /* The ring status page addresses are no longer next to the rest of 440 * the ring registers as of gen7. 441 */ 442 if (IS_GEN7(dev_priv)) { 443 switch (engine->id) { 444 case RCS: 445 mmio = RENDER_HWS_PGA_GEN7; 446 break; 447 case BCS: 448 mmio = BLT_HWS_PGA_GEN7; 449 break; 450 /* 451 * VCS2 actually doesn't exist on Gen7. Only shut up 452 * gcc switch check warning 453 */ 454 case VCS2: 455 case VCS: 456 mmio = BSD_HWS_PGA_GEN7; 457 break; 458 case VECS: 459 mmio = VEBOX_HWS_PGA_GEN7; 460 break; 461 } 462 } else if (IS_GEN6(dev_priv)) { 463 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); 464 } else { 465 /* XXX: gen8 returns to sanity */ 466 mmio = RING_HWS_PGA(engine->mmio_base); 467 } 468 469 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr); 470 POSTING_READ(mmio); 471 472 /* 473 * Flush the TLB for this page 474 * 475 * FIXME: These two bits have disappeared on gen8, so a question 476 * arises: do we still need this and if so how should we go about 477 * invalidating the TLB? 478 */ 479 if (IS_GEN(dev_priv, 6, 7)) { 480 i915_reg_t reg = RING_INSTPM(engine->mmio_base); 481 482 /* ring should be idle before issuing a sync flush*/ 483 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); 484 485 I915_WRITE(reg, 486 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | 487 INSTPM_SYNC_FLUSH)); 488 if (intel_wait_for_register(dev_priv, 489 reg, INSTPM_SYNC_FLUSH, 0, 490 1000)) 491 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", 492 engine->name); 493 } 494 } 495 496 static bool stop_ring(struct intel_engine_cs *engine) 497 { 498 struct drm_i915_private *dev_priv = engine->i915; 499 500 if (!IS_GEN2(dev_priv)) { 501 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); 502 if (intel_wait_for_register(dev_priv, 503 RING_MI_MODE(engine->mmio_base), 504 MODE_IDLE, 505 MODE_IDLE, 506 1000)) { 507 DRM_ERROR("%s : timed out trying to stop ring\n", 508 engine->name); 509 /* Sometimes we observe that the idle flag is not 510 * set even though the ring is empty. So double 511 * check before giving up. 512 */ 513 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) 514 return false; 515 } 516 } 517 518 I915_WRITE_CTL(engine, 0); 519 I915_WRITE_HEAD(engine, 0); 520 I915_WRITE_TAIL(engine, 0); 521 522 if (!IS_GEN2(dev_priv)) { 523 (void)I915_READ_CTL(engine); 524 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); 525 } 526 527 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; 528 } 529 530 static int init_ring_common(struct intel_engine_cs *engine) 531 { 532 struct drm_i915_private *dev_priv = engine->i915; 533 struct intel_ring *ring = engine->buffer; 534 struct drm_i915_gem_object *obj = ring->obj; 535 int ret = 0; 536 537 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 538 539 if (!stop_ring(engine)) { 540 /* G45 ring initialization often fails to reset head to zero */ 541 DRM_DEBUG_KMS("%s head not reset to zero " 542 "ctl %08x head %08x tail %08x start %08x\n", 543 engine->name, 544 I915_READ_CTL(engine), 545 I915_READ_HEAD(engine), 546 I915_READ_TAIL(engine), 547 I915_READ_START(engine)); 548 549 if (!stop_ring(engine)) { 550 DRM_ERROR("failed to set %s head to zero " 551 "ctl %08x head %08x tail %08x start %08x\n", 552 engine->name, 553 I915_READ_CTL(engine), 554 I915_READ_HEAD(engine), 555 I915_READ_TAIL(engine), 556 I915_READ_START(engine)); 557 ret = -EIO; 558 goto out; 559 } 560 } 561 562 if (I915_NEED_GFX_HWS(dev_priv)) 563 intel_ring_setup_status_page(engine); 564 else 565 ring_setup_phys_status_page(engine); 566 567 /* Enforce ordering by reading HEAD register back */ 568 I915_READ_HEAD(engine); 569 570 /* Initialize the ring. This must happen _after_ we've cleared the ring 571 * registers with the above sequence (the readback of the HEAD registers 572 * also enforces ordering), otherwise the hw might lose the new ring 573 * register values. */ 574 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj)); 575 576 /* WaClearRingBufHeadRegAtInit:ctg,elk */ 577 if (I915_READ_HEAD(engine)) 578 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", 579 engine->name, I915_READ_HEAD(engine)); 580 I915_WRITE_HEAD(engine, 0); 581 (void)I915_READ_HEAD(engine); 582 583 I915_WRITE_CTL(engine, 584 ((ring->size - PAGE_SIZE) & RING_NR_PAGES) 585 | RING_VALID); 586 587 /* If the head is still not zero, the ring is dead */ 588 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 && 589 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) && 590 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) { 591 DRM_ERROR("%s initialization failed " 592 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", 593 engine->name, 594 I915_READ_CTL(engine), 595 I915_READ_CTL(engine) & RING_VALID, 596 I915_READ_HEAD(engine), I915_READ_TAIL(engine), 597 I915_READ_START(engine), 598 (unsigned long)i915_gem_obj_ggtt_offset(obj)); 599 ret = -EIO; 600 goto out; 601 } 602 603 ring->last_retired_head = -1; 604 ring->head = I915_READ_HEAD(engine); 605 ring->tail = I915_READ_TAIL(engine) & TAIL_ADDR; 606 intel_ring_update_space(ring); 607 608 intel_engine_init_hangcheck(engine); 609 610 out: 611 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 612 613 return ret; 614 } 615 616 void intel_fini_pipe_control(struct intel_engine_cs *engine) 617 { 618 if (engine->scratch.obj == NULL) 619 return; 620 621 i915_gem_object_ggtt_unpin(engine->scratch.obj); 622 i915_gem_object_put(engine->scratch.obj); 623 engine->scratch.obj = NULL; 624 } 625 626 int intel_init_pipe_control(struct intel_engine_cs *engine, int size) 627 { 628 struct drm_i915_gem_object *obj; 629 int ret; 630 631 WARN_ON(engine->scratch.obj); 632 633 obj = i915_gem_object_create_stolen(&engine->i915->drm, size); 634 if (!obj) 635 obj = i915_gem_object_create(&engine->i915->drm, size); 636 if (IS_ERR(obj)) { 637 DRM_ERROR("Failed to allocate scratch page\n"); 638 ret = PTR_ERR(obj); 639 goto err; 640 } 641 642 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 4096, PIN_HIGH); 643 if (ret) 644 goto err_unref; 645 646 engine->scratch.obj = obj; 647 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); 648 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", 649 engine->name, engine->scratch.gtt_offset); 650 return 0; 651 652 err_unref: 653 i915_gem_object_put(engine->scratch.obj); 654 err: 655 return ret; 656 } 657 658 static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req) 659 { 660 struct intel_ring *ring = req->ring; 661 struct i915_workarounds *w = &req->i915->workarounds; 662 int ret, i; 663 664 if (w->count == 0) 665 return 0; 666 667 ret = req->engine->emit_flush(req, EMIT_BARRIER); 668 if (ret) 669 return ret; 670 671 ret = intel_ring_begin(req, (w->count * 2 + 2)); 672 if (ret) 673 return ret; 674 675 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); 676 for (i = 0; i < w->count; i++) { 677 intel_ring_emit_reg(ring, w->reg[i].addr); 678 intel_ring_emit(ring, w->reg[i].value); 679 } 680 intel_ring_emit(ring, MI_NOOP); 681 682 intel_ring_advance(ring); 683 684 ret = req->engine->emit_flush(req, EMIT_BARRIER); 685 if (ret) 686 return ret; 687 688 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); 689 690 return 0; 691 } 692 693 static int intel_rcs_ctx_init(struct drm_i915_gem_request *req) 694 { 695 int ret; 696 697 ret = intel_ring_workarounds_emit(req); 698 if (ret != 0) 699 return ret; 700 701 ret = i915_gem_render_state_init(req); 702 if (ret) 703 return ret; 704 705 return 0; 706 } 707 708 static int wa_add(struct drm_i915_private *dev_priv, 709 i915_reg_t addr, 710 const u32 mask, const u32 val) 711 { 712 const u32 idx = dev_priv->workarounds.count; 713 714 if (WARN_ON(idx >= I915_MAX_WA_REGS)) 715 return -ENOSPC; 716 717 dev_priv->workarounds.reg[idx].addr = addr; 718 dev_priv->workarounds.reg[idx].value = val; 719 dev_priv->workarounds.reg[idx].mask = mask; 720 721 dev_priv->workarounds.count++; 722 723 return 0; 724 } 725 726 #define WA_REG(addr, mask, val) do { \ 727 const int r = wa_add(dev_priv, (addr), (mask), (val)); \ 728 if (r) \ 729 return r; \ 730 } while (0) 731 732 #define WA_SET_BIT_MASKED(addr, mask) \ 733 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) 734 735 #define WA_CLR_BIT_MASKED(addr, mask) \ 736 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) 737 738 #define WA_SET_FIELD_MASKED(addr, mask, value) \ 739 WA_REG(addr, mask, _MASKED_FIELD(mask, value)) 740 741 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) 742 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) 743 744 #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) 745 746 static int wa_ring_whitelist_reg(struct intel_engine_cs *engine, 747 i915_reg_t reg) 748 { 749 struct drm_i915_private *dev_priv = engine->i915; 750 struct i915_workarounds *wa = &dev_priv->workarounds; 751 const uint32_t index = wa->hw_whitelist_count[engine->id]; 752 753 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS)) 754 return -EINVAL; 755 756 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index), 757 i915_mmio_reg_offset(reg)); 758 wa->hw_whitelist_count[engine->id]++; 759 760 return 0; 761 } 762 763 static int gen8_init_workarounds(struct intel_engine_cs *engine) 764 { 765 struct drm_i915_private *dev_priv = engine->i915; 766 767 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING); 768 769 /* WaDisableAsyncFlipPerfMode:bdw,chv */ 770 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE); 771 772 /* WaDisablePartialInstShootdown:bdw,chv */ 773 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 774 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 775 776 /* Use Force Non-Coherent whenever executing a 3D context. This is a 777 * workaround for for a possible hang in the unlikely event a TLB 778 * invalidation occurs during a PSD flush. 779 */ 780 /* WaForceEnableNonCoherent:bdw,chv */ 781 /* WaHdcDisableFetchWhenMasked:bdw,chv */ 782 WA_SET_BIT_MASKED(HDC_CHICKEN0, 783 HDC_DONOT_FETCH_MEM_WHEN_MASKED | 784 HDC_FORCE_NON_COHERENT); 785 786 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: 787 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping 788 * polygons in the same 8x4 pixel/sample area to be processed without 789 * stalling waiting for the earlier ones to write to Hierarchical Z 790 * buffer." 791 * 792 * This optimization is off by default for BDW and CHV; turn it on. 793 */ 794 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); 795 796 /* Wa4x4STCOptimizationDisable:bdw,chv */ 797 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); 798 799 /* 800 * BSpec recommends 8x4 when MSAA is used, 801 * however in practice 16x4 seems fastest. 802 * 803 * Note that PS/WM thread counts depend on the WIZ hashing 804 * disable bit, which we don't touch here, but it's good 805 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 806 */ 807 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 808 GEN6_WIZ_HASHING_MASK, 809 GEN6_WIZ_HASHING_16x4); 810 811 return 0; 812 } 813 814 static int bdw_init_workarounds(struct intel_engine_cs *engine) 815 { 816 struct drm_i915_private *dev_priv = engine->i915; 817 int ret; 818 819 ret = gen8_init_workarounds(engine); 820 if (ret) 821 return ret; 822 823 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ 824 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 825 826 /* WaDisableDopClockGating:bdw */ 827 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, 828 DOP_CLOCK_GATING_DISABLE); 829 830 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 831 GEN8_SAMPLER_POWER_BYPASS_DIS); 832 833 WA_SET_BIT_MASKED(HDC_CHICKEN0, 834 /* WaForceContextSaveRestoreNonCoherent:bdw */ 835 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 836 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ 837 (IS_BDW_GT3(dev_priv) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); 838 839 return 0; 840 } 841 842 static int chv_init_workarounds(struct intel_engine_cs *engine) 843 { 844 struct drm_i915_private *dev_priv = engine->i915; 845 int ret; 846 847 ret = gen8_init_workarounds(engine); 848 if (ret) 849 return ret; 850 851 /* WaDisableThreadStallDopClockGating:chv */ 852 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); 853 854 /* Improve HiZ throughput on CHV. */ 855 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); 856 857 return 0; 858 } 859 860 static int gen9_init_workarounds(struct intel_engine_cs *engine) 861 { 862 struct drm_i915_private *dev_priv = engine->i915; 863 int ret; 864 865 /* WaConextSwitchWithConcurrentTLBInvalidate:skl,bxt,kbl */ 866 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, _MASKED_BIT_ENABLE(GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE)); 867 868 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */ 869 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | 870 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 871 872 /* WaDisableKillLogic:bxt,skl,kbl */ 873 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | 874 ECOCHK_DIS_TLB); 875 876 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */ 877 /* WaDisablePartialInstShootdown:skl,bxt,kbl */ 878 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 879 FLOW_CONTROL_ENABLE | 880 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); 881 882 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */ 883 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 884 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); 885 886 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */ 887 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || 888 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) 889 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 890 GEN9_DG_MIRROR_FIX_ENABLE); 891 892 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ 893 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || 894 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { 895 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, 896 GEN9_RHWO_OPTIMIZATION_DISABLE); 897 /* 898 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set 899 * but we do that in per ctx batchbuffer as there is an issue 900 * with this register not getting restored on ctx restore 901 */ 902 } 903 904 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */ 905 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */ 906 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, 907 GEN9_ENABLE_YV12_BUGFIX | 908 GEN9_ENABLE_GPGPU_PREEMPTION); 909 910 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */ 911 /* WaDisablePartialResolveInVc:skl,bxt,kbl */ 912 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE | 913 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE)); 914 915 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */ 916 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5, 917 GEN9_CCS_TLB_PREFETCH_ENABLE); 918 919 /* WaDisableMaskBasedCammingInRCC:skl,bxt */ 920 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_C0) || 921 IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) 922 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0, 923 PIXEL_MASK_CAMMING_DISABLE); 924 925 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */ 926 WA_SET_BIT_MASKED(HDC_CHICKEN0, 927 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | 928 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE); 929 930 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are 931 * both tied to WaForceContextSaveRestoreNonCoherent 932 * in some hsds for skl. We keep the tie for all gen9. The 933 * documentation is a bit hazy and so we want to get common behaviour, 934 * even though there is no clear evidence we would need both on kbl/bxt. 935 * This area has been source of system hangs so we play it safe 936 * and mimic the skl regardless of what bspec says. 937 * 938 * Use Force Non-Coherent whenever executing a 3D context. This 939 * is a workaround for a possible hang in the unlikely event 940 * a TLB invalidation occurs during a PSD flush. 941 */ 942 943 /* WaForceEnableNonCoherent:skl,bxt,kbl */ 944 WA_SET_BIT_MASKED(HDC_CHICKEN0, 945 HDC_FORCE_NON_COHERENT); 946 947 /* WaDisableHDCInvalidation:skl,bxt,kbl */ 948 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | 949 BDW_DISABLE_HDC_INVALIDATION); 950 951 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */ 952 if (IS_SKYLAKE(dev_priv) || 953 IS_KABYLAKE(dev_priv) || 954 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) 955 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, 956 GEN8_SAMPLER_POWER_BYPASS_DIS); 957 958 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */ 959 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); 960 961 /* WaOCLCoherentLineFlush:skl,bxt,kbl */ 962 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | 963 GEN8_LQSC_FLUSH_COHERENT_LINES)); 964 965 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */ 966 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG); 967 if (ret) 968 return ret; 969 970 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */ 971 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); 972 if (ret) 973 return ret; 974 975 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */ 976 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1); 977 if (ret) 978 return ret; 979 980 return 0; 981 } 982 983 static int skl_tune_iz_hashing(struct intel_engine_cs *engine) 984 { 985 struct drm_i915_private *dev_priv = engine->i915; 986 u8 vals[3] = { 0, 0, 0 }; 987 unsigned int i; 988 989 for (i = 0; i < 3; i++) { 990 u8 ss; 991 992 /* 993 * Only consider slices where one, and only one, subslice has 7 994 * EUs 995 */ 996 if (!is_power_of_2(dev_priv->info.subslice_7eu[i])) 997 continue; 998 999 /* 1000 * subslice_7eu[i] != 0 (because of the check above) and 1001 * ss_max == 4 (maximum number of subslices possible per slice) 1002 * 1003 * -> 0 <= ss <= 3; 1004 */ 1005 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1; 1006 vals[i] = 3 - ss; 1007 } 1008 1009 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0) 1010 return 0; 1011 1012 /* Tune IZ hashing. See intel_device_info_runtime_init() */ 1013 WA_SET_FIELD_MASKED(GEN7_GT_MODE, 1014 GEN9_IZ_HASHING_MASK(2) | 1015 GEN9_IZ_HASHING_MASK(1) | 1016 GEN9_IZ_HASHING_MASK(0), 1017 GEN9_IZ_HASHING(2, vals[2]) | 1018 GEN9_IZ_HASHING(1, vals[1]) | 1019 GEN9_IZ_HASHING(0, vals[0])); 1020 1021 return 0; 1022 } 1023 1024 static int skl_init_workarounds(struct intel_engine_cs *engine) 1025 { 1026 struct drm_i915_private *dev_priv = engine->i915; 1027 int ret; 1028 1029 ret = gen9_init_workarounds(engine); 1030 if (ret) 1031 return ret; 1032 1033 /* 1034 * Actual WA is to disable percontext preemption granularity control 1035 * until D0 which is the default case so this is equivalent to 1036 * !WaDisablePerCtxtPreemptionGranularityControl:skl 1037 */ 1038 if (IS_SKL_REVID(dev_priv, SKL_REVID_E0, REVID_FOREVER)) { 1039 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1, 1040 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL)); 1041 } 1042 1043 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) { 1044 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ 1045 I915_WRITE(FF_SLICE_CS_CHICKEN2, 1046 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); 1047 } 1048 1049 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes 1050 * involving this register should also be added to WA batch as required. 1051 */ 1052 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0)) 1053 /* WaDisableLSQCROPERFforOCL:skl */ 1054 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | 1055 GEN8_LQSC_RO_PERF_DIS); 1056 1057 /* WaEnableGapsTsvCreditFix:skl */ 1058 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) { 1059 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | 1060 GEN9_GAPS_TSV_CREDIT_DISABLE)); 1061 } 1062 1063 /* WaDisablePowerCompilerClockGating:skl */ 1064 if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0)) 1065 WA_SET_BIT_MASKED(HIZ_CHICKEN, 1066 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); 1067 1068 /* WaBarrierPerformanceFixDisable:skl */ 1069 if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0)) 1070 WA_SET_BIT_MASKED(HDC_CHICKEN0, 1071 HDC_FENCE_DEST_SLM_DISABLE | 1072 HDC_BARRIER_PERFORMANCE_DISABLE); 1073 1074 /* WaDisableSbeCacheDispatchPortSharing:skl */ 1075 if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0)) 1076 WA_SET_BIT_MASKED( 1077 GEN7_HALF_SLICE_CHICKEN1, 1078 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 1079 1080 /* WaDisableGafsUnitClkGating:skl */ 1081 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1082 1083 /* WaInPlaceDecompressionHang:skl */ 1084 if (IS_SKL_REVID(dev_priv, SKL_REVID_H0, REVID_FOREVER)) 1085 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, 1086 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1087 1088 /* WaDisableLSQCROPERFforOCL:skl */ 1089 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); 1090 if (ret) 1091 return ret; 1092 1093 return skl_tune_iz_hashing(engine); 1094 } 1095 1096 static int bxt_init_workarounds(struct intel_engine_cs *engine) 1097 { 1098 struct drm_i915_private *dev_priv = engine->i915; 1099 int ret; 1100 1101 ret = gen9_init_workarounds(engine); 1102 if (ret) 1103 return ret; 1104 1105 /* WaStoreMultiplePTEenable:bxt */ 1106 /* This is a requirement according to Hardware specification */ 1107 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) 1108 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); 1109 1110 /* WaSetClckGatingDisableMedia:bxt */ 1111 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { 1112 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & 1113 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE)); 1114 } 1115 1116 /* WaDisableThreadStallDopClockGating:bxt */ 1117 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, 1118 STALL_DOP_GATING_DISABLE); 1119 1120 /* WaDisablePooledEuLoadBalancingFix:bxt */ 1121 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) { 1122 WA_SET_BIT_MASKED(FF_SLICE_CS_CHICKEN2, 1123 GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); 1124 } 1125 1126 /* WaDisableSbeCacheDispatchPortSharing:bxt */ 1127 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) { 1128 WA_SET_BIT_MASKED( 1129 GEN7_HALF_SLICE_CHICKEN1, 1130 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 1131 } 1132 1133 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */ 1134 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */ 1135 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */ 1136 /* WaDisableLSQCROPERFforOCL:bxt */ 1137 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) { 1138 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1); 1139 if (ret) 1140 return ret; 1141 1142 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); 1143 if (ret) 1144 return ret; 1145 } 1146 1147 /* WaProgramL3SqcReg1DefaultForPerf:bxt */ 1148 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) 1149 I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) | 1150 L3_HIGH_PRIO_CREDITS(2)); 1151 1152 /* WaToEnableHwFixForPushConstHWBug:bxt */ 1153 if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) 1154 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 1155 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 1156 1157 /* WaInPlaceDecompressionHang:bxt */ 1158 if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER)) 1159 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, 1160 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1161 1162 return 0; 1163 } 1164 1165 static int kbl_init_workarounds(struct intel_engine_cs *engine) 1166 { 1167 struct drm_i915_private *dev_priv = engine->i915; 1168 int ret; 1169 1170 ret = gen9_init_workarounds(engine); 1171 if (ret) 1172 return ret; 1173 1174 /* WaEnableGapsTsvCreditFix:kbl */ 1175 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | 1176 GEN9_GAPS_TSV_CREDIT_DISABLE)); 1177 1178 /* WaDisableDynamicCreditSharing:kbl */ 1179 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) 1180 WA_SET_BIT(GAMT_CHKN_BIT_REG, 1181 GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING); 1182 1183 /* WaDisableFenceDestinationToSLM:kbl (pre-prod) */ 1184 if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0)) 1185 WA_SET_BIT_MASKED(HDC_CHICKEN0, 1186 HDC_FENCE_DEST_SLM_DISABLE); 1187 1188 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes 1189 * involving this register should also be added to WA batch as required. 1190 */ 1191 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) 1192 /* WaDisableLSQCROPERFforOCL:kbl */ 1193 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | 1194 GEN8_LQSC_RO_PERF_DIS); 1195 1196 /* WaToEnableHwFixForPushConstHWBug:kbl */ 1197 if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER)) 1198 WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2, 1199 GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION); 1200 1201 /* WaDisableGafsUnitClkGating:kbl */ 1202 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE); 1203 1204 /* WaDisableSbeCacheDispatchPortSharing:kbl */ 1205 WA_SET_BIT_MASKED( 1206 GEN7_HALF_SLICE_CHICKEN1, 1207 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE); 1208 1209 /* WaInPlaceDecompressionHang:kbl */ 1210 WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA, 1211 GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS); 1212 1213 /* WaDisableLSQCROPERFforOCL:kbl */ 1214 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4); 1215 if (ret) 1216 return ret; 1217 1218 return 0; 1219 } 1220 1221 int init_workarounds_ring(struct intel_engine_cs *engine) 1222 { 1223 struct drm_i915_private *dev_priv = engine->i915; 1224 1225 WARN_ON(engine->id != RCS); 1226 1227 dev_priv->workarounds.count = 0; 1228 dev_priv->workarounds.hw_whitelist_count[RCS] = 0; 1229 1230 if (IS_BROADWELL(dev_priv)) 1231 return bdw_init_workarounds(engine); 1232 1233 if (IS_CHERRYVIEW(dev_priv)) 1234 return chv_init_workarounds(engine); 1235 1236 if (IS_SKYLAKE(dev_priv)) 1237 return skl_init_workarounds(engine); 1238 1239 if (IS_BROXTON(dev_priv)) 1240 return bxt_init_workarounds(engine); 1241 1242 if (IS_KABYLAKE(dev_priv)) 1243 return kbl_init_workarounds(engine); 1244 1245 return 0; 1246 } 1247 1248 static int init_render_ring(struct intel_engine_cs *engine) 1249 { 1250 struct drm_i915_private *dev_priv = engine->i915; 1251 int ret = init_ring_common(engine); 1252 if (ret) 1253 return ret; 1254 1255 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ 1256 if (IS_GEN(dev_priv, 4, 6)) 1257 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); 1258 1259 /* We need to disable the AsyncFlip performance optimisations in order 1260 * to use MI_WAIT_FOR_EVENT within the CS. It should already be 1261 * programmed to '1' on all products. 1262 * 1263 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv 1264 */ 1265 if (IS_GEN(dev_priv, 6, 7)) 1266 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); 1267 1268 /* Required for the hardware to program scanline values for waiting */ 1269 /* WaEnableFlushTlbInvalidationMode:snb */ 1270 if (IS_GEN6(dev_priv)) 1271 I915_WRITE(GFX_MODE, 1272 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); 1273 1274 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ 1275 if (IS_GEN7(dev_priv)) 1276 I915_WRITE(GFX_MODE_GEN7, 1277 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | 1278 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); 1279 1280 if (IS_GEN6(dev_priv)) { 1281 /* From the Sandybridge PRM, volume 1 part 3, page 24: 1282 * "If this bit is set, STCunit will have LRA as replacement 1283 * policy. [...] This bit must be reset. LRA replacement 1284 * policy is not supported." 1285 */ 1286 I915_WRITE(CACHE_MODE_0, 1287 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 1288 } 1289 1290 if (IS_GEN(dev_priv, 6, 7)) 1291 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); 1292 1293 if (INTEL_INFO(dev_priv)->gen >= 6) 1294 I915_WRITE_IMR(engine, ~engine->irq_keep_mask); 1295 1296 return init_workarounds_ring(engine); 1297 } 1298 1299 static void render_ring_cleanup(struct intel_engine_cs *engine) 1300 { 1301 struct drm_i915_private *dev_priv = engine->i915; 1302 1303 if (dev_priv->semaphore_obj) { 1304 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); 1305 i915_gem_object_put(dev_priv->semaphore_obj); 1306 dev_priv->semaphore_obj = NULL; 1307 } 1308 1309 intel_fini_pipe_control(engine); 1310 } 1311 1312 static int gen8_rcs_signal(struct drm_i915_gem_request *req) 1313 { 1314 struct intel_ring *ring = req->ring; 1315 struct drm_i915_private *dev_priv = req->i915; 1316 struct intel_engine_cs *waiter; 1317 enum intel_engine_id id; 1318 int ret, num_rings; 1319 1320 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); 1321 ret = intel_ring_begin(req, (num_rings-1) * 8); 1322 if (ret) 1323 return ret; 1324 1325 for_each_engine_id(waiter, dev_priv, id) { 1326 u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; 1327 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) 1328 continue; 1329 1330 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); 1331 intel_ring_emit(ring, 1332 PIPE_CONTROL_GLOBAL_GTT_IVB | 1333 PIPE_CONTROL_QW_WRITE | 1334 PIPE_CONTROL_CS_STALL); 1335 intel_ring_emit(ring, lower_32_bits(gtt_offset)); 1336 intel_ring_emit(ring, upper_32_bits(gtt_offset)); 1337 intel_ring_emit(ring, req->fence.seqno); 1338 intel_ring_emit(ring, 0); 1339 intel_ring_emit(ring, 1340 MI_SEMAPHORE_SIGNAL | 1341 MI_SEMAPHORE_TARGET(waiter->hw_id)); 1342 intel_ring_emit(ring, 0); 1343 } 1344 intel_ring_advance(ring); 1345 1346 return 0; 1347 } 1348 1349 static int gen8_xcs_signal(struct drm_i915_gem_request *req) 1350 { 1351 struct intel_ring *ring = req->ring; 1352 struct drm_i915_private *dev_priv = req->i915; 1353 struct intel_engine_cs *waiter; 1354 enum intel_engine_id id; 1355 int ret, num_rings; 1356 1357 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); 1358 ret = intel_ring_begin(req, (num_rings-1) * 6); 1359 if (ret) 1360 return ret; 1361 1362 for_each_engine_id(waiter, dev_priv, id) { 1363 u64 gtt_offset = req->engine->semaphore.signal_ggtt[id]; 1364 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) 1365 continue; 1366 1367 intel_ring_emit(ring, 1368 (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); 1369 intel_ring_emit(ring, 1370 lower_32_bits(gtt_offset) | 1371 MI_FLUSH_DW_USE_GTT); 1372 intel_ring_emit(ring, upper_32_bits(gtt_offset)); 1373 intel_ring_emit(ring, req->fence.seqno); 1374 intel_ring_emit(ring, 1375 MI_SEMAPHORE_SIGNAL | 1376 MI_SEMAPHORE_TARGET(waiter->hw_id)); 1377 intel_ring_emit(ring, 0); 1378 } 1379 intel_ring_advance(ring); 1380 1381 return 0; 1382 } 1383 1384 static int gen6_signal(struct drm_i915_gem_request *req) 1385 { 1386 struct intel_ring *ring = req->ring; 1387 struct drm_i915_private *dev_priv = req->i915; 1388 struct intel_engine_cs *useless; 1389 enum intel_engine_id id; 1390 int ret, num_rings; 1391 1392 num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask); 1393 ret = intel_ring_begin(req, round_up((num_rings-1) * 3, 2)); 1394 if (ret) 1395 return ret; 1396 1397 for_each_engine_id(useless, dev_priv, id) { 1398 i915_reg_t mbox_reg = req->engine->semaphore.mbox.signal[id]; 1399 1400 if (i915_mmio_reg_valid(mbox_reg)) { 1401 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 1402 intel_ring_emit_reg(ring, mbox_reg); 1403 intel_ring_emit(ring, req->fence.seqno); 1404 } 1405 } 1406 1407 /* If num_dwords was rounded, make sure the tail pointer is correct */ 1408 if (num_rings % 2 == 0) 1409 intel_ring_emit(ring, MI_NOOP); 1410 intel_ring_advance(ring); 1411 1412 return 0; 1413 } 1414 1415 static void i9xx_submit_request(struct drm_i915_gem_request *request) 1416 { 1417 struct drm_i915_private *dev_priv = request->i915; 1418 1419 I915_WRITE_TAIL(request->engine, 1420 intel_ring_offset(request->ring, request->tail)); 1421 } 1422 1423 static int i9xx_emit_request(struct drm_i915_gem_request *req) 1424 { 1425 struct intel_ring *ring = req->ring; 1426 int ret; 1427 1428 ret = intel_ring_begin(req, 4); 1429 if (ret) 1430 return ret; 1431 1432 intel_ring_emit(ring, MI_STORE_DWORD_INDEX); 1433 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 1434 intel_ring_emit(ring, req->fence.seqno); 1435 intel_ring_emit(ring, MI_USER_INTERRUPT); 1436 intel_ring_advance(ring); 1437 1438 req->tail = ring->tail; 1439 1440 return 0; 1441 } 1442 1443 /** 1444 * gen6_sema_emit_request - Update the semaphore mailbox registers 1445 * 1446 * @request - request to write to the ring 1447 * 1448 * Update the mailbox registers in the *other* rings with the current seqno. 1449 * This acts like a signal in the canonical semaphore. 1450 */ 1451 static int gen6_sema_emit_request(struct drm_i915_gem_request *req) 1452 { 1453 int ret; 1454 1455 ret = req->engine->semaphore.signal(req); 1456 if (ret) 1457 return ret; 1458 1459 return i9xx_emit_request(req); 1460 } 1461 1462 static int gen8_render_emit_request(struct drm_i915_gem_request *req) 1463 { 1464 struct intel_engine_cs *engine = req->engine; 1465 struct intel_ring *ring = req->ring; 1466 int ret; 1467 1468 if (engine->semaphore.signal) { 1469 ret = engine->semaphore.signal(req); 1470 if (ret) 1471 return ret; 1472 } 1473 1474 ret = intel_ring_begin(req, 8); 1475 if (ret) 1476 return ret; 1477 1478 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); 1479 intel_ring_emit(ring, (PIPE_CONTROL_GLOBAL_GTT_IVB | 1480 PIPE_CONTROL_CS_STALL | 1481 PIPE_CONTROL_QW_WRITE)); 1482 intel_ring_emit(ring, intel_hws_seqno_address(engine)); 1483 intel_ring_emit(ring, 0); 1484 intel_ring_emit(ring, i915_gem_request_get_seqno(req)); 1485 /* We're thrashing one dword of HWS. */ 1486 intel_ring_emit(ring, 0); 1487 intel_ring_emit(ring, MI_USER_INTERRUPT); 1488 intel_ring_emit(ring, MI_NOOP); 1489 intel_ring_advance(ring); 1490 1491 req->tail = ring->tail; 1492 1493 return 0; 1494 } 1495 1496 /** 1497 * intel_ring_sync - sync the waiter to the signaller on seqno 1498 * 1499 * @waiter - ring that is waiting 1500 * @signaller - ring which has, or will signal 1501 * @seqno - seqno which the waiter will block on 1502 */ 1503 1504 static int 1505 gen8_ring_sync_to(struct drm_i915_gem_request *req, 1506 struct drm_i915_gem_request *signal) 1507 { 1508 struct intel_ring *ring = req->ring; 1509 struct drm_i915_private *dev_priv = req->i915; 1510 u64 offset = GEN8_WAIT_OFFSET(req->engine, signal->engine->id); 1511 struct i915_hw_ppgtt *ppgtt; 1512 int ret; 1513 1514 ret = intel_ring_begin(req, 4); 1515 if (ret) 1516 return ret; 1517 1518 intel_ring_emit(ring, 1519 MI_SEMAPHORE_WAIT | 1520 MI_SEMAPHORE_GLOBAL_GTT | 1521 MI_SEMAPHORE_SAD_GTE_SDD); 1522 intel_ring_emit(ring, signal->fence.seqno); 1523 intel_ring_emit(ring, lower_32_bits(offset)); 1524 intel_ring_emit(ring, upper_32_bits(offset)); 1525 intel_ring_advance(ring); 1526 1527 /* When the !RCS engines idle waiting upon a semaphore, they lose their 1528 * pagetables and we must reload them before executing the batch. 1529 * We do this on the i915_switch_context() following the wait and 1530 * before the dispatch. 1531 */ 1532 ppgtt = req->ctx->ppgtt; 1533 if (ppgtt && req->engine->id != RCS) 1534 ppgtt->pd_dirty_rings |= intel_engine_flag(req->engine); 1535 return 0; 1536 } 1537 1538 static int 1539 gen6_ring_sync_to(struct drm_i915_gem_request *req, 1540 struct drm_i915_gem_request *signal) 1541 { 1542 struct intel_ring *ring = req->ring; 1543 u32 dw1 = MI_SEMAPHORE_MBOX | 1544 MI_SEMAPHORE_COMPARE | 1545 MI_SEMAPHORE_REGISTER; 1546 u32 wait_mbox = signal->engine->semaphore.mbox.wait[req->engine->id]; 1547 int ret; 1548 1549 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); 1550 1551 ret = intel_ring_begin(req, 4); 1552 if (ret) 1553 return ret; 1554 1555 intel_ring_emit(ring, dw1 | wait_mbox); 1556 /* Throughout all of the GEM code, seqno passed implies our current 1557 * seqno is >= the last seqno executed. However for hardware the 1558 * comparison is strictly greater than. 1559 */ 1560 intel_ring_emit(ring, signal->fence.seqno - 1); 1561 intel_ring_emit(ring, 0); 1562 intel_ring_emit(ring, MI_NOOP); 1563 intel_ring_advance(ring); 1564 1565 return 0; 1566 } 1567 1568 static void 1569 gen5_seqno_barrier(struct intel_engine_cs *engine) 1570 { 1571 /* MI_STORE are internally buffered by the GPU and not flushed 1572 * either by MI_FLUSH or SyncFlush or any other combination of 1573 * MI commands. 1574 * 1575 * "Only the submission of the store operation is guaranteed. 1576 * The write result will be complete (coherent) some time later 1577 * (this is practically a finite period but there is no guaranteed 1578 * latency)." 1579 * 1580 * Empirically, we observe that we need a delay of at least 75us to 1581 * be sure that the seqno write is visible by the CPU. 1582 */ 1583 usleep_range(125, 250); 1584 } 1585 1586 static void 1587 gen6_seqno_barrier(struct intel_engine_cs *engine) 1588 { 1589 struct drm_i915_private *dev_priv = engine->i915; 1590 1591 /* Workaround to force correct ordering between irq and seqno writes on 1592 * ivb (and maybe also on snb) by reading from a CS register (like 1593 * ACTHD) before reading the status page. 1594 * 1595 * Note that this effectively stalls the read by the time it takes to 1596 * do a memory transaction, which more or less ensures that the write 1597 * from the GPU has sufficient time to invalidate the CPU cacheline. 1598 * Alternatively we could delay the interrupt from the CS ring to give 1599 * the write time to land, but that would incur a delay after every 1600 * batch i.e. much more frequent than a delay when waiting for the 1601 * interrupt (with the same net latency). 1602 * 1603 * Also note that to prevent whole machine hangs on gen7, we have to 1604 * take the spinlock to guard against concurrent cacheline access. 1605 */ 1606 spin_lock_irq(&dev_priv->uncore.lock); 1607 POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); 1608 spin_unlock_irq(&dev_priv->uncore.lock); 1609 } 1610 1611 static void 1612 gen5_irq_enable(struct intel_engine_cs *engine) 1613 { 1614 gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); 1615 } 1616 1617 static void 1618 gen5_irq_disable(struct intel_engine_cs *engine) 1619 { 1620 gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); 1621 } 1622 1623 static void 1624 i9xx_irq_enable(struct intel_engine_cs *engine) 1625 { 1626 struct drm_i915_private *dev_priv = engine->i915; 1627 1628 dev_priv->irq_mask &= ~engine->irq_enable_mask; 1629 I915_WRITE(IMR, dev_priv->irq_mask); 1630 POSTING_READ_FW(RING_IMR(engine->mmio_base)); 1631 } 1632 1633 static void 1634 i9xx_irq_disable(struct intel_engine_cs *engine) 1635 { 1636 struct drm_i915_private *dev_priv = engine->i915; 1637 1638 dev_priv->irq_mask |= engine->irq_enable_mask; 1639 I915_WRITE(IMR, dev_priv->irq_mask); 1640 } 1641 1642 static void 1643 i8xx_irq_enable(struct intel_engine_cs *engine) 1644 { 1645 struct drm_i915_private *dev_priv = engine->i915; 1646 1647 dev_priv->irq_mask &= ~engine->irq_enable_mask; 1648 I915_WRITE16(IMR, dev_priv->irq_mask); 1649 POSTING_READ16(RING_IMR(engine->mmio_base)); 1650 } 1651 1652 static void 1653 i8xx_irq_disable(struct intel_engine_cs *engine) 1654 { 1655 struct drm_i915_private *dev_priv = engine->i915; 1656 1657 dev_priv->irq_mask |= engine->irq_enable_mask; 1658 I915_WRITE16(IMR, dev_priv->irq_mask); 1659 } 1660 1661 static int 1662 bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) 1663 { 1664 struct intel_ring *ring = req->ring; 1665 int ret; 1666 1667 ret = intel_ring_begin(req, 2); 1668 if (ret) 1669 return ret; 1670 1671 intel_ring_emit(ring, MI_FLUSH); 1672 intel_ring_emit(ring, MI_NOOP); 1673 intel_ring_advance(ring); 1674 return 0; 1675 } 1676 1677 static void 1678 gen6_irq_enable(struct intel_engine_cs *engine) 1679 { 1680 struct drm_i915_private *dev_priv = engine->i915; 1681 1682 I915_WRITE_IMR(engine, 1683 ~(engine->irq_enable_mask | 1684 engine->irq_keep_mask)); 1685 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); 1686 } 1687 1688 static void 1689 gen6_irq_disable(struct intel_engine_cs *engine) 1690 { 1691 struct drm_i915_private *dev_priv = engine->i915; 1692 1693 I915_WRITE_IMR(engine, ~engine->irq_keep_mask); 1694 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); 1695 } 1696 1697 static void 1698 hsw_vebox_irq_enable(struct intel_engine_cs *engine) 1699 { 1700 struct drm_i915_private *dev_priv = engine->i915; 1701 1702 I915_WRITE_IMR(engine, ~engine->irq_enable_mask); 1703 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask); 1704 } 1705 1706 static void 1707 hsw_vebox_irq_disable(struct intel_engine_cs *engine) 1708 { 1709 struct drm_i915_private *dev_priv = engine->i915; 1710 1711 I915_WRITE_IMR(engine, ~0); 1712 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask); 1713 } 1714 1715 static void 1716 gen8_irq_enable(struct intel_engine_cs *engine) 1717 { 1718 struct drm_i915_private *dev_priv = engine->i915; 1719 1720 I915_WRITE_IMR(engine, 1721 ~(engine->irq_enable_mask | 1722 engine->irq_keep_mask)); 1723 POSTING_READ_FW(RING_IMR(engine->mmio_base)); 1724 } 1725 1726 static void 1727 gen8_irq_disable(struct intel_engine_cs *engine) 1728 { 1729 struct drm_i915_private *dev_priv = engine->i915; 1730 1731 I915_WRITE_IMR(engine, ~engine->irq_keep_mask); 1732 } 1733 1734 static int 1735 i965_emit_bb_start(struct drm_i915_gem_request *req, 1736 u64 offset, u32 length, 1737 unsigned int dispatch_flags) 1738 { 1739 struct intel_ring *ring = req->ring; 1740 int ret; 1741 1742 ret = intel_ring_begin(req, 2); 1743 if (ret) 1744 return ret; 1745 1746 intel_ring_emit(ring, 1747 MI_BATCH_BUFFER_START | 1748 MI_BATCH_GTT | 1749 (dispatch_flags & I915_DISPATCH_SECURE ? 1750 0 : MI_BATCH_NON_SECURE_I965)); 1751 intel_ring_emit(ring, offset); 1752 intel_ring_advance(ring); 1753 1754 return 0; 1755 } 1756 1757 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ 1758 #define I830_BATCH_LIMIT (256*1024) 1759 #define I830_TLB_ENTRIES (2) 1760 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) 1761 static int 1762 i830_emit_bb_start(struct drm_i915_gem_request *req, 1763 u64 offset, u32 len, 1764 unsigned int dispatch_flags) 1765 { 1766 struct intel_ring *ring = req->ring; 1767 u32 cs_offset = req->engine->scratch.gtt_offset; 1768 int ret; 1769 1770 ret = intel_ring_begin(req, 6); 1771 if (ret) 1772 return ret; 1773 1774 /* Evict the invalid PTE TLBs */ 1775 intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); 1776 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); 1777 intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ 1778 intel_ring_emit(ring, cs_offset); 1779 intel_ring_emit(ring, 0xdeadbeef); 1780 intel_ring_emit(ring, MI_NOOP); 1781 intel_ring_advance(ring); 1782 1783 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) { 1784 if (len > I830_BATCH_LIMIT) 1785 return -ENOSPC; 1786 1787 ret = intel_ring_begin(req, 6 + 2); 1788 if (ret) 1789 return ret; 1790 1791 /* Blit the batch (which has now all relocs applied) to the 1792 * stable batch scratch bo area (so that the CS never 1793 * stumbles over its tlb invalidation bug) ... 1794 */ 1795 intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); 1796 intel_ring_emit(ring, 1797 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); 1798 intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); 1799 intel_ring_emit(ring, cs_offset); 1800 intel_ring_emit(ring, 4096); 1801 intel_ring_emit(ring, offset); 1802 1803 intel_ring_emit(ring, MI_FLUSH); 1804 intel_ring_emit(ring, MI_NOOP); 1805 intel_ring_advance(ring); 1806 1807 /* ... and execute it. */ 1808 offset = cs_offset; 1809 } 1810 1811 ret = intel_ring_begin(req, 2); 1812 if (ret) 1813 return ret; 1814 1815 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); 1816 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? 1817 0 : MI_BATCH_NON_SECURE)); 1818 intel_ring_advance(ring); 1819 1820 return 0; 1821 } 1822 1823 static int 1824 i915_emit_bb_start(struct drm_i915_gem_request *req, 1825 u64 offset, u32 len, 1826 unsigned int dispatch_flags) 1827 { 1828 struct intel_ring *ring = req->ring; 1829 int ret; 1830 1831 ret = intel_ring_begin(req, 2); 1832 if (ret) 1833 return ret; 1834 1835 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); 1836 intel_ring_emit(ring, offset | (dispatch_flags & I915_DISPATCH_SECURE ? 1837 0 : MI_BATCH_NON_SECURE)); 1838 intel_ring_advance(ring); 1839 1840 return 0; 1841 } 1842 1843 static void cleanup_phys_status_page(struct intel_engine_cs *engine) 1844 { 1845 struct drm_i915_private *dev_priv = engine->i915; 1846 1847 if (!dev_priv->status_page_dmah) 1848 return; 1849 1850 drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah); 1851 engine->status_page.page_addr = NULL; 1852 } 1853 1854 static void cleanup_status_page(struct intel_engine_cs *engine) 1855 { 1856 struct drm_i915_gem_object *obj; 1857 1858 obj = engine->status_page.obj; 1859 if (obj == NULL) 1860 return; 1861 1862 kunmap(sg_page(obj->pages->sgl)); 1863 i915_gem_object_ggtt_unpin(obj); 1864 i915_gem_object_put(obj); 1865 engine->status_page.obj = NULL; 1866 } 1867 1868 static int init_status_page(struct intel_engine_cs *engine) 1869 { 1870 struct drm_i915_gem_object *obj = engine->status_page.obj; 1871 1872 if (obj == NULL) { 1873 unsigned flags; 1874 int ret; 1875 1876 obj = i915_gem_object_create(&engine->i915->drm, 4096); 1877 if (IS_ERR(obj)) { 1878 DRM_ERROR("Failed to allocate status page\n"); 1879 return PTR_ERR(obj); 1880 } 1881 1882 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); 1883 if (ret) 1884 goto err_unref; 1885 1886 flags = 0; 1887 if (!HAS_LLC(engine->i915)) 1888 /* On g33, we cannot place HWS above 256MiB, so 1889 * restrict its pinning to the low mappable arena. 1890 * Though this restriction is not documented for 1891 * gen4, gen5, or byt, they also behave similarly 1892 * and hang if the HWS is placed at the top of the 1893 * GTT. To generalise, it appears that all !llc 1894 * platforms have issues with us placing the HWS 1895 * above the mappable region (even though we never 1896 * actualy map it). 1897 */ 1898 flags |= PIN_MAPPABLE; 1899 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 4096, flags); 1900 if (ret) { 1901 err_unref: 1902 i915_gem_object_put(obj); 1903 return ret; 1904 } 1905 1906 engine->status_page.obj = obj; 1907 } 1908 1909 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); 1910 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); 1911 memset(engine->status_page.page_addr, 0, PAGE_SIZE); 1912 1913 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", 1914 engine->name, engine->status_page.gfx_addr); 1915 1916 return 0; 1917 } 1918 1919 static int init_phys_status_page(struct intel_engine_cs *engine) 1920 { 1921 struct drm_i915_private *dev_priv = engine->i915; 1922 1923 if (!dev_priv->status_page_dmah) { 1924 dev_priv->status_page_dmah = 1925 drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE); 1926 if (!dev_priv->status_page_dmah) 1927 return -ENOMEM; 1928 } 1929 1930 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr; 1931 memset(engine->status_page.page_addr, 0, PAGE_SIZE); 1932 1933 return 0; 1934 } 1935 1936 int intel_ring_pin(struct intel_ring *ring) 1937 { 1938 struct drm_i915_private *dev_priv = ring->engine->i915; 1939 struct drm_i915_gem_object *obj = ring->obj; 1940 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */ 1941 unsigned flags = PIN_OFFSET_BIAS | 4096; 1942 void *addr; 1943 int ret; 1944 1945 if (HAS_LLC(dev_priv) && !obj->stolen) { 1946 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, flags); 1947 if (ret) 1948 return ret; 1949 1950 ret = i915_gem_object_set_to_cpu_domain(obj, true); 1951 if (ret) 1952 goto err_unpin; 1953 1954 addr = i915_gem_object_pin_map(obj); 1955 if (IS_ERR(addr)) { 1956 ret = PTR_ERR(addr); 1957 goto err_unpin; 1958 } 1959 } else { 1960 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, PAGE_SIZE, 1961 flags | PIN_MAPPABLE); 1962 if (ret) 1963 return ret; 1964 1965 ret = i915_gem_object_set_to_gtt_domain(obj, true); 1966 if (ret) 1967 goto err_unpin; 1968 1969 /* Access through the GTT requires the device to be awake. */ 1970 assert_rpm_wakelock_held(dev_priv); 1971 1972 addr = (void __force *) 1973 i915_vma_pin_iomap(i915_gem_obj_to_ggtt(obj)); 1974 if (IS_ERR(addr)) { 1975 ret = PTR_ERR(addr); 1976 goto err_unpin; 1977 } 1978 } 1979 1980 ring->vaddr = addr; 1981 ring->vma = i915_gem_obj_to_ggtt(obj); 1982 return 0; 1983 1984 err_unpin: 1985 i915_gem_object_ggtt_unpin(obj); 1986 return ret; 1987 } 1988 1989 void intel_ring_unpin(struct intel_ring *ring) 1990 { 1991 GEM_BUG_ON(!ring->vma); 1992 GEM_BUG_ON(!ring->vaddr); 1993 1994 if (HAS_LLC(ring->engine->i915) && !ring->obj->stolen) 1995 i915_gem_object_unpin_map(ring->obj); 1996 else 1997 i915_vma_unpin_iomap(ring->vma); 1998 ring->vaddr = NULL; 1999 2000 i915_gem_object_ggtt_unpin(ring->obj); 2001 ring->vma = NULL; 2002 } 2003 2004 static void intel_destroy_ringbuffer_obj(struct intel_ring *ring) 2005 { 2006 i915_gem_object_put(ring->obj); 2007 ring->obj = NULL; 2008 } 2009 2010 static int intel_alloc_ringbuffer_obj(struct drm_device *dev, 2011 struct intel_ring *ring) 2012 { 2013 struct drm_i915_gem_object *obj; 2014 2015 obj = NULL; 2016 if (!HAS_LLC(dev)) 2017 obj = i915_gem_object_create_stolen(dev, ring->size); 2018 if (obj == NULL) 2019 obj = i915_gem_object_create(dev, ring->size); 2020 if (IS_ERR(obj)) 2021 return PTR_ERR(obj); 2022 2023 /* mark ring buffers as read-only from GPU side by default */ 2024 obj->gt_ro = 1; 2025 2026 ring->obj = obj; 2027 2028 return 0; 2029 } 2030 2031 struct intel_ring * 2032 intel_engine_create_ring(struct intel_engine_cs *engine, int size) 2033 { 2034 struct intel_ring *ring; 2035 int ret; 2036 2037 GEM_BUG_ON(!is_power_of_2(size)); 2038 2039 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 2040 if (ring == NULL) { 2041 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", 2042 engine->name); 2043 return ERR_PTR(-ENOMEM); 2044 } 2045 2046 ring->engine = engine; 2047 list_add(&ring->link, &engine->buffers); 2048 2049 INIT_LIST_HEAD(&ring->request_list); 2050 2051 ring->size = size; 2052 /* Workaround an erratum on the i830 which causes a hang if 2053 * the TAIL pointer points to within the last 2 cachelines 2054 * of the buffer. 2055 */ 2056 ring->effective_size = size; 2057 if (IS_I830(engine->i915) || IS_845G(engine->i915)) 2058 ring->effective_size -= 2 * CACHELINE_BYTES; 2059 2060 ring->last_retired_head = -1; 2061 intel_ring_update_space(ring); 2062 2063 ret = intel_alloc_ringbuffer_obj(&engine->i915->drm, ring); 2064 if (ret) { 2065 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n", 2066 engine->name, ret); 2067 list_del(&ring->link); 2068 kfree(ring); 2069 return ERR_PTR(ret); 2070 } 2071 2072 return ring; 2073 } 2074 2075 void 2076 intel_ring_free(struct intel_ring *ring) 2077 { 2078 intel_destroy_ringbuffer_obj(ring); 2079 list_del(&ring->link); 2080 kfree(ring); 2081 } 2082 2083 static int intel_ring_context_pin(struct i915_gem_context *ctx, 2084 struct intel_engine_cs *engine) 2085 { 2086 struct intel_context *ce = &ctx->engine[engine->id]; 2087 int ret; 2088 2089 lockdep_assert_held(&ctx->i915->drm.struct_mutex); 2090 2091 if (ce->pin_count++) 2092 return 0; 2093 2094 if (ce->state) { 2095 ret = i915_gem_object_ggtt_pin(ce->state, NULL, 0, 2096 ctx->ggtt_alignment, 0); 2097 if (ret) 2098 goto error; 2099 } 2100 2101 /* The kernel context is only used as a placeholder for flushing the 2102 * active context. It is never used for submitting user rendering and 2103 * as such never requires the golden render context, and so we can skip 2104 * emitting it when we switch to the kernel context. This is required 2105 * as during eviction we cannot allocate and pin the renderstate in 2106 * order to initialise the context. 2107 */ 2108 if (ctx == ctx->i915->kernel_context) 2109 ce->initialised = true; 2110 2111 i915_gem_context_get(ctx); 2112 return 0; 2113 2114 error: 2115 ce->pin_count = 0; 2116 return ret; 2117 } 2118 2119 static void intel_ring_context_unpin(struct i915_gem_context *ctx, 2120 struct intel_engine_cs *engine) 2121 { 2122 struct intel_context *ce = &ctx->engine[engine->id]; 2123 2124 lockdep_assert_held(&ctx->i915->drm.struct_mutex); 2125 2126 if (--ce->pin_count) 2127 return; 2128 2129 if (ce->state) 2130 i915_gem_object_ggtt_unpin(ce->state); 2131 2132 i915_gem_context_put(ctx); 2133 } 2134 2135 static int intel_init_ring_buffer(struct intel_engine_cs *engine) 2136 { 2137 struct drm_i915_private *dev_priv = engine->i915; 2138 struct intel_ring *ring; 2139 int ret; 2140 2141 WARN_ON(engine->buffer); 2142 2143 intel_engine_setup_common(engine); 2144 2145 memset(engine->semaphore.sync_seqno, 0, 2146 sizeof(engine->semaphore.sync_seqno)); 2147 2148 ret = intel_engine_init_common(engine); 2149 if (ret) 2150 goto error; 2151 2152 /* We may need to do things with the shrinker which 2153 * require us to immediately switch back to the default 2154 * context. This can cause a problem as pinning the 2155 * default context also requires GTT space which may not 2156 * be available. To avoid this we always pin the default 2157 * context. 2158 */ 2159 ret = intel_ring_context_pin(dev_priv->kernel_context, engine); 2160 if (ret) 2161 goto error; 2162 2163 ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE); 2164 if (IS_ERR(ring)) { 2165 ret = PTR_ERR(ring); 2166 goto error; 2167 } 2168 engine->buffer = ring; 2169 2170 if (I915_NEED_GFX_HWS(dev_priv)) { 2171 ret = init_status_page(engine); 2172 if (ret) 2173 goto error; 2174 } else { 2175 WARN_ON(engine->id != RCS); 2176 ret = init_phys_status_page(engine); 2177 if (ret) 2178 goto error; 2179 } 2180 2181 ret = intel_ring_pin(ring); 2182 if (ret) { 2183 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", 2184 engine->name, ret); 2185 intel_destroy_ringbuffer_obj(ring); 2186 goto error; 2187 } 2188 2189 return 0; 2190 2191 error: 2192 intel_engine_cleanup(engine); 2193 return ret; 2194 } 2195 2196 void intel_engine_cleanup(struct intel_engine_cs *engine) 2197 { 2198 struct drm_i915_private *dev_priv; 2199 2200 if (!intel_engine_initialized(engine)) 2201 return; 2202 2203 dev_priv = engine->i915; 2204 2205 if (engine->buffer) { 2206 WARN_ON(!IS_GEN2(dev_priv) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); 2207 2208 intel_ring_unpin(engine->buffer); 2209 intel_ring_free(engine->buffer); 2210 engine->buffer = NULL; 2211 } 2212 2213 if (engine->cleanup) 2214 engine->cleanup(engine); 2215 2216 if (I915_NEED_GFX_HWS(dev_priv)) { 2217 cleanup_status_page(engine); 2218 } else { 2219 WARN_ON(engine->id != RCS); 2220 cleanup_phys_status_page(engine); 2221 } 2222 2223 intel_engine_cleanup_common(engine); 2224 2225 intel_ring_context_unpin(dev_priv->kernel_context, engine); 2226 2227 engine->i915 = NULL; 2228 } 2229 2230 int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request) 2231 { 2232 int ret; 2233 2234 /* Flush enough space to reduce the likelihood of waiting after 2235 * we start building the request - in which case we will just 2236 * have to repeat work. 2237 */ 2238 request->reserved_space += LEGACY_REQUEST_SIZE; 2239 2240 request->ring = request->engine->buffer; 2241 2242 ret = intel_ring_begin(request, 0); 2243 if (ret) 2244 return ret; 2245 2246 request->reserved_space -= LEGACY_REQUEST_SIZE; 2247 return 0; 2248 } 2249 2250 static int wait_for_space(struct drm_i915_gem_request *req, int bytes) 2251 { 2252 struct intel_ring *ring = req->ring; 2253 struct drm_i915_gem_request *target; 2254 int ret; 2255 2256 intel_ring_update_space(ring); 2257 if (ring->space >= bytes) 2258 return 0; 2259 2260 /* 2261 * Space is reserved in the ringbuffer for finalising the request, 2262 * as that cannot be allowed to fail. During request finalisation, 2263 * reserved_space is set to 0 to stop the overallocation and the 2264 * assumption is that then we never need to wait (which has the 2265 * risk of failing with EINTR). 2266 * 2267 * See also i915_gem_request_alloc() and i915_add_request(). 2268 */ 2269 GEM_BUG_ON(!req->reserved_space); 2270 2271 list_for_each_entry(target, &ring->request_list, ring_link) { 2272 unsigned space; 2273 2274 /* Would completion of this request free enough space? */ 2275 space = __intel_ring_space(target->postfix, ring->tail, 2276 ring->size); 2277 if (space >= bytes) 2278 break; 2279 } 2280 2281 if (WARN_ON(&target->ring_link == &ring->request_list)) 2282 return -ENOSPC; 2283 2284 ret = i915_wait_request(target, true, NULL, NO_WAITBOOST); 2285 if (ret) 2286 return ret; 2287 2288 if (i915_reset_in_progress(&target->i915->gpu_error)) 2289 return -EAGAIN; 2290 2291 i915_gem_request_retire_upto(target); 2292 2293 intel_ring_update_space(ring); 2294 GEM_BUG_ON(ring->space < bytes); 2295 return 0; 2296 } 2297 2298 int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords) 2299 { 2300 struct intel_ring *ring = req->ring; 2301 int remain_actual = ring->size - ring->tail; 2302 int remain_usable = ring->effective_size - ring->tail; 2303 int bytes = num_dwords * sizeof(u32); 2304 int total_bytes, wait_bytes; 2305 bool need_wrap = false; 2306 2307 total_bytes = bytes + req->reserved_space; 2308 2309 if (unlikely(bytes > remain_usable)) { 2310 /* 2311 * Not enough space for the basic request. So need to flush 2312 * out the remainder and then wait for base + reserved. 2313 */ 2314 wait_bytes = remain_actual + total_bytes; 2315 need_wrap = true; 2316 } else if (unlikely(total_bytes > remain_usable)) { 2317 /* 2318 * The base request will fit but the reserved space 2319 * falls off the end. So we don't need an immediate wrap 2320 * and only need to effectively wait for the reserved 2321 * size space from the start of ringbuffer. 2322 */ 2323 wait_bytes = remain_actual + req->reserved_space; 2324 } else { 2325 /* No wrapping required, just waiting. */ 2326 wait_bytes = total_bytes; 2327 } 2328 2329 if (wait_bytes > ring->space) { 2330 int ret = wait_for_space(req, wait_bytes); 2331 if (unlikely(ret)) 2332 return ret; 2333 } 2334 2335 if (unlikely(need_wrap)) { 2336 GEM_BUG_ON(remain_actual > ring->space); 2337 GEM_BUG_ON(ring->tail + remain_actual > ring->size); 2338 2339 /* Fill the tail with MI_NOOP */ 2340 memset(ring->vaddr + ring->tail, 0, remain_actual); 2341 ring->tail = 0; 2342 ring->space -= remain_actual; 2343 } 2344 2345 ring->space -= bytes; 2346 GEM_BUG_ON(ring->space < 0); 2347 return 0; 2348 } 2349 2350 /* Align the ring tail to a cacheline boundary */ 2351 int intel_ring_cacheline_align(struct drm_i915_gem_request *req) 2352 { 2353 struct intel_ring *ring = req->ring; 2354 int num_dwords = 2355 (ring->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); 2356 int ret; 2357 2358 if (num_dwords == 0) 2359 return 0; 2360 2361 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; 2362 ret = intel_ring_begin(req, num_dwords); 2363 if (ret) 2364 return ret; 2365 2366 while (num_dwords--) 2367 intel_ring_emit(ring, MI_NOOP); 2368 2369 intel_ring_advance(ring); 2370 2371 return 0; 2372 } 2373 2374 void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno) 2375 { 2376 struct drm_i915_private *dev_priv = engine->i915; 2377 2378 /* Our semaphore implementation is strictly monotonic (i.e. we proceed 2379 * so long as the semaphore value in the register/page is greater 2380 * than the sync value), so whenever we reset the seqno, 2381 * so long as we reset the tracking semaphore value to 0, it will 2382 * always be before the next request's seqno. If we don't reset 2383 * the semaphore value, then when the seqno moves backwards all 2384 * future waits will complete instantly (causing rendering corruption). 2385 */ 2386 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { 2387 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); 2388 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); 2389 if (HAS_VEBOX(dev_priv)) 2390 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0); 2391 } 2392 if (dev_priv->semaphore_obj) { 2393 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj; 2394 struct page *page = i915_gem_object_get_dirty_page(obj, 0); 2395 void *semaphores = kmap(page); 2396 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0), 2397 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size); 2398 kunmap(page); 2399 } 2400 memset(engine->semaphore.sync_seqno, 0, 2401 sizeof(engine->semaphore.sync_seqno)); 2402 2403 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno); 2404 if (engine->irq_seqno_barrier) 2405 engine->irq_seqno_barrier(engine); 2406 engine->last_submitted_seqno = seqno; 2407 2408 engine->hangcheck.seqno = seqno; 2409 2410 /* After manually advancing the seqno, fake the interrupt in case 2411 * there are any waiters for that seqno. 2412 */ 2413 rcu_read_lock(); 2414 intel_engine_wakeup(engine); 2415 rcu_read_unlock(); 2416 } 2417 2418 static void gen6_bsd_submit_request(struct drm_i915_gem_request *request) 2419 { 2420 struct drm_i915_private *dev_priv = request->i915; 2421 2422 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 2423 2424 /* Every tail move must follow the sequence below */ 2425 2426 /* Disable notification that the ring is IDLE. The GT 2427 * will then assume that it is busy and bring it out of rc6. 2428 */ 2429 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, 2430 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 2431 2432 /* Clear the context id. Here be magic! */ 2433 I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0); 2434 2435 /* Wait for the ring not to be idle, i.e. for it to wake up. */ 2436 if (intel_wait_for_register_fw(dev_priv, 2437 GEN6_BSD_SLEEP_PSMI_CONTROL, 2438 GEN6_BSD_SLEEP_INDICATOR, 2439 0, 2440 50)) 2441 DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); 2442 2443 /* Now that the ring is fully powered up, update the tail */ 2444 i9xx_submit_request(request); 2445 2446 /* Let the ring send IDLE messages to the GT again, 2447 * and so let it sleep to conserve power when idle. 2448 */ 2449 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL, 2450 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); 2451 2452 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 2453 } 2454 2455 static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req, u32 mode) 2456 { 2457 struct intel_ring *ring = req->ring; 2458 uint32_t cmd; 2459 int ret; 2460 2461 ret = intel_ring_begin(req, 4); 2462 if (ret) 2463 return ret; 2464 2465 cmd = MI_FLUSH_DW; 2466 if (INTEL_GEN(req->i915) >= 8) 2467 cmd += 1; 2468 2469 /* We always require a command barrier so that subsequent 2470 * commands, such as breadcrumb interrupts, are strictly ordered 2471 * wrt the contents of the write cache being flushed to memory 2472 * (and thus being coherent from the CPU). 2473 */ 2474 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 2475 2476 /* 2477 * Bspec vol 1c.5 - video engine command streamer: 2478 * "If ENABLED, all TLBs will be invalidated once the flush 2479 * operation is complete. This bit is only valid when the 2480 * Post-Sync Operation field is a value of 1h or 3h." 2481 */ 2482 if (mode & EMIT_INVALIDATE) 2483 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; 2484 2485 intel_ring_emit(ring, cmd); 2486 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); 2487 if (INTEL_GEN(req->i915) >= 8) { 2488 intel_ring_emit(ring, 0); /* upper addr */ 2489 intel_ring_emit(ring, 0); /* value */ 2490 } else { 2491 intel_ring_emit(ring, 0); 2492 intel_ring_emit(ring, MI_NOOP); 2493 } 2494 intel_ring_advance(ring); 2495 return 0; 2496 } 2497 2498 static int 2499 gen8_emit_bb_start(struct drm_i915_gem_request *req, 2500 u64 offset, u32 len, 2501 unsigned int dispatch_flags) 2502 { 2503 struct intel_ring *ring = req->ring; 2504 bool ppgtt = USES_PPGTT(req->i915) && 2505 !(dispatch_flags & I915_DISPATCH_SECURE); 2506 int ret; 2507 2508 ret = intel_ring_begin(req, 4); 2509 if (ret) 2510 return ret; 2511 2512 /* FIXME(BDW): Address space and security selectors. */ 2513 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) | 2514 (dispatch_flags & I915_DISPATCH_RS ? 2515 MI_BATCH_RESOURCE_STREAMER : 0)); 2516 intel_ring_emit(ring, lower_32_bits(offset)); 2517 intel_ring_emit(ring, upper_32_bits(offset)); 2518 intel_ring_emit(ring, MI_NOOP); 2519 intel_ring_advance(ring); 2520 2521 return 0; 2522 } 2523 2524 static int 2525 hsw_emit_bb_start(struct drm_i915_gem_request *req, 2526 u64 offset, u32 len, 2527 unsigned int dispatch_flags) 2528 { 2529 struct intel_ring *ring = req->ring; 2530 int ret; 2531 2532 ret = intel_ring_begin(req, 2); 2533 if (ret) 2534 return ret; 2535 2536 intel_ring_emit(ring, 2537 MI_BATCH_BUFFER_START | 2538 (dispatch_flags & I915_DISPATCH_SECURE ? 2539 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) | 2540 (dispatch_flags & I915_DISPATCH_RS ? 2541 MI_BATCH_RESOURCE_STREAMER : 0)); 2542 /* bit0-7 is the length on GEN6+ */ 2543 intel_ring_emit(ring, offset); 2544 intel_ring_advance(ring); 2545 2546 return 0; 2547 } 2548 2549 static int 2550 gen6_emit_bb_start(struct drm_i915_gem_request *req, 2551 u64 offset, u32 len, 2552 unsigned int dispatch_flags) 2553 { 2554 struct intel_ring *ring = req->ring; 2555 int ret; 2556 2557 ret = intel_ring_begin(req, 2); 2558 if (ret) 2559 return ret; 2560 2561 intel_ring_emit(ring, 2562 MI_BATCH_BUFFER_START | 2563 (dispatch_flags & I915_DISPATCH_SECURE ? 2564 0 : MI_BATCH_NON_SECURE_I965)); 2565 /* bit0-7 is the length on GEN6+ */ 2566 intel_ring_emit(ring, offset); 2567 intel_ring_advance(ring); 2568 2569 return 0; 2570 } 2571 2572 /* Blitter support (SandyBridge+) */ 2573 2574 static int gen6_ring_flush(struct drm_i915_gem_request *req, u32 mode) 2575 { 2576 struct intel_ring *ring = req->ring; 2577 uint32_t cmd; 2578 int ret; 2579 2580 ret = intel_ring_begin(req, 4); 2581 if (ret) 2582 return ret; 2583 2584 cmd = MI_FLUSH_DW; 2585 if (INTEL_GEN(req->i915) >= 8) 2586 cmd += 1; 2587 2588 /* We always require a command barrier so that subsequent 2589 * commands, such as breadcrumb interrupts, are strictly ordered 2590 * wrt the contents of the write cache being flushed to memory 2591 * (and thus being coherent from the CPU). 2592 */ 2593 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 2594 2595 /* 2596 * Bspec vol 1c.3 - blitter engine command streamer: 2597 * "If ENABLED, all TLBs will be invalidated once the flush 2598 * operation is complete. This bit is only valid when the 2599 * Post-Sync Operation field is a value of 1h or 3h." 2600 */ 2601 if (mode & EMIT_INVALIDATE) 2602 cmd |= MI_INVALIDATE_TLB; 2603 intel_ring_emit(ring, cmd); 2604 intel_ring_emit(ring, 2605 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); 2606 if (INTEL_GEN(req->i915) >= 8) { 2607 intel_ring_emit(ring, 0); /* upper addr */ 2608 intel_ring_emit(ring, 0); /* value */ 2609 } else { 2610 intel_ring_emit(ring, 0); 2611 intel_ring_emit(ring, MI_NOOP); 2612 } 2613 intel_ring_advance(ring); 2614 2615 return 0; 2616 } 2617 2618 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, 2619 struct intel_engine_cs *engine) 2620 { 2621 struct drm_i915_gem_object *obj; 2622 int ret, i; 2623 2624 if (!i915.semaphores) 2625 return; 2626 2627 if (INTEL_GEN(dev_priv) >= 8 && !dev_priv->semaphore_obj) { 2628 obj = i915_gem_object_create(&dev_priv->drm, 4096); 2629 if (IS_ERR(obj)) { 2630 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); 2631 i915.semaphores = 0; 2632 } else { 2633 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); 2634 ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); 2635 if (ret != 0) { 2636 i915_gem_object_put(obj); 2637 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); 2638 i915.semaphores = 0; 2639 } else { 2640 dev_priv->semaphore_obj = obj; 2641 } 2642 } 2643 } 2644 2645 if (!i915.semaphores) 2646 return; 2647 2648 if (INTEL_GEN(dev_priv) >= 8) { 2649 u64 offset = i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj); 2650 2651 engine->semaphore.sync_to = gen8_ring_sync_to; 2652 engine->semaphore.signal = gen8_xcs_signal; 2653 2654 for (i = 0; i < I915_NUM_ENGINES; i++) { 2655 u64 ring_offset; 2656 2657 if (i != engine->id) 2658 ring_offset = offset + GEN8_SEMAPHORE_OFFSET(engine->id, i); 2659 else 2660 ring_offset = MI_SEMAPHORE_SYNC_INVALID; 2661 2662 engine->semaphore.signal_ggtt[i] = ring_offset; 2663 } 2664 } else if (INTEL_GEN(dev_priv) >= 6) { 2665 engine->semaphore.sync_to = gen6_ring_sync_to; 2666 engine->semaphore.signal = gen6_signal; 2667 2668 /* 2669 * The current semaphore is only applied on pre-gen8 2670 * platform. And there is no VCS2 ring on the pre-gen8 2671 * platform. So the semaphore between RCS and VCS2 is 2672 * initialized as INVALID. Gen8 will initialize the 2673 * sema between VCS2 and RCS later. 2674 */ 2675 for (i = 0; i < I915_NUM_ENGINES; i++) { 2676 static const struct { 2677 u32 wait_mbox; 2678 i915_reg_t mbox_reg; 2679 } sem_data[I915_NUM_ENGINES][I915_NUM_ENGINES] = { 2680 [RCS] = { 2681 [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC }, 2682 [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC }, 2683 [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC }, 2684 }, 2685 [VCS] = { 2686 [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC }, 2687 [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC }, 2688 [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC }, 2689 }, 2690 [BCS] = { 2691 [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC }, 2692 [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC }, 2693 [VECS] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC }, 2694 }, 2695 [VECS] = { 2696 [RCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC }, 2697 [VCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC }, 2698 [BCS] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC }, 2699 }, 2700 }; 2701 u32 wait_mbox; 2702 i915_reg_t mbox_reg; 2703 2704 if (i == engine->id || i == VCS2) { 2705 wait_mbox = MI_SEMAPHORE_SYNC_INVALID; 2706 mbox_reg = GEN6_NOSYNC; 2707 } else { 2708 wait_mbox = sem_data[engine->id][i].wait_mbox; 2709 mbox_reg = sem_data[engine->id][i].mbox_reg; 2710 } 2711 2712 engine->semaphore.mbox.wait[i] = wait_mbox; 2713 engine->semaphore.mbox.signal[i] = mbox_reg; 2714 } 2715 } 2716 } 2717 2718 static void intel_ring_init_irq(struct drm_i915_private *dev_priv, 2719 struct intel_engine_cs *engine) 2720 { 2721 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift; 2722 2723 if (INTEL_GEN(dev_priv) >= 8) { 2724 engine->irq_enable = gen8_irq_enable; 2725 engine->irq_disable = gen8_irq_disable; 2726 engine->irq_seqno_barrier = gen6_seqno_barrier; 2727 } else if (INTEL_GEN(dev_priv) >= 6) { 2728 engine->irq_enable = gen6_irq_enable; 2729 engine->irq_disable = gen6_irq_disable; 2730 engine->irq_seqno_barrier = gen6_seqno_barrier; 2731 } else if (INTEL_GEN(dev_priv) >= 5) { 2732 engine->irq_enable = gen5_irq_enable; 2733 engine->irq_disable = gen5_irq_disable; 2734 engine->irq_seqno_barrier = gen5_seqno_barrier; 2735 } else if (INTEL_GEN(dev_priv) >= 3) { 2736 engine->irq_enable = i9xx_irq_enable; 2737 engine->irq_disable = i9xx_irq_disable; 2738 } else { 2739 engine->irq_enable = i8xx_irq_enable; 2740 engine->irq_disable = i8xx_irq_disable; 2741 } 2742 } 2743 2744 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, 2745 struct intel_engine_cs *engine) 2746 { 2747 intel_ring_init_irq(dev_priv, engine); 2748 intel_ring_init_semaphores(dev_priv, engine); 2749 2750 engine->init_hw = init_ring_common; 2751 2752 engine->emit_request = i9xx_emit_request; 2753 if (i915.semaphores) 2754 engine->emit_request = gen6_sema_emit_request; 2755 engine->submit_request = i9xx_submit_request; 2756 2757 if (INTEL_GEN(dev_priv) >= 8) 2758 engine->emit_bb_start = gen8_emit_bb_start; 2759 else if (INTEL_GEN(dev_priv) >= 6) 2760 engine->emit_bb_start = gen6_emit_bb_start; 2761 else if (INTEL_GEN(dev_priv) >= 4) 2762 engine->emit_bb_start = i965_emit_bb_start; 2763 else if (IS_I830(dev_priv) || IS_845G(dev_priv)) 2764 engine->emit_bb_start = i830_emit_bb_start; 2765 else 2766 engine->emit_bb_start = i915_emit_bb_start; 2767 } 2768 2769 int intel_init_render_ring_buffer(struct intel_engine_cs *engine) 2770 { 2771 struct drm_i915_private *dev_priv = engine->i915; 2772 int ret; 2773 2774 intel_ring_default_vfuncs(dev_priv, engine); 2775 2776 if (HAS_L3_DPF(dev_priv)) 2777 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; 2778 2779 if (INTEL_GEN(dev_priv) >= 8) { 2780 engine->init_context = intel_rcs_ctx_init; 2781 engine->emit_request = gen8_render_emit_request; 2782 engine->emit_flush = gen8_render_ring_flush; 2783 if (i915.semaphores) 2784 engine->semaphore.signal = gen8_rcs_signal; 2785 } else if (INTEL_GEN(dev_priv) >= 6) { 2786 engine->init_context = intel_rcs_ctx_init; 2787 engine->emit_flush = gen7_render_ring_flush; 2788 if (IS_GEN6(dev_priv)) 2789 engine->emit_flush = gen6_render_ring_flush; 2790 } else if (IS_GEN5(dev_priv)) { 2791 engine->emit_flush = gen4_render_ring_flush; 2792 } else { 2793 if (INTEL_GEN(dev_priv) < 4) 2794 engine->emit_flush = gen2_render_ring_flush; 2795 else 2796 engine->emit_flush = gen4_render_ring_flush; 2797 engine->irq_enable_mask = I915_USER_INTERRUPT; 2798 } 2799 2800 if (IS_HASWELL(dev_priv)) 2801 engine->emit_bb_start = hsw_emit_bb_start; 2802 2803 engine->init_hw = init_render_ring; 2804 engine->cleanup = render_ring_cleanup; 2805 2806 ret = intel_init_ring_buffer(engine); 2807 if (ret) 2808 return ret; 2809 2810 if (INTEL_GEN(dev_priv) >= 6) { 2811 ret = intel_init_pipe_control(engine, 4096); 2812 if (ret) 2813 return ret; 2814 } else if (HAS_BROKEN_CS_TLB(dev_priv)) { 2815 ret = intel_init_pipe_control(engine, I830_WA_SIZE); 2816 if (ret) 2817 return ret; 2818 } 2819 2820 return 0; 2821 } 2822 2823 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) 2824 { 2825 struct drm_i915_private *dev_priv = engine->i915; 2826 2827 intel_ring_default_vfuncs(dev_priv, engine); 2828 2829 if (INTEL_GEN(dev_priv) >= 6) { 2830 /* gen6 bsd needs a special wa for tail updates */ 2831 if (IS_GEN6(dev_priv)) 2832 engine->submit_request = gen6_bsd_submit_request; 2833 engine->emit_flush = gen6_bsd_ring_flush; 2834 if (INTEL_GEN(dev_priv) < 8) 2835 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; 2836 } else { 2837 engine->mmio_base = BSD_RING_BASE; 2838 engine->emit_flush = bsd_ring_flush; 2839 if (IS_GEN5(dev_priv)) 2840 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; 2841 else 2842 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; 2843 } 2844 2845 return intel_init_ring_buffer(engine); 2846 } 2847 2848 /** 2849 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) 2850 */ 2851 int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine) 2852 { 2853 struct drm_i915_private *dev_priv = engine->i915; 2854 2855 intel_ring_default_vfuncs(dev_priv, engine); 2856 2857 engine->emit_flush = gen6_bsd_ring_flush; 2858 2859 return intel_init_ring_buffer(engine); 2860 } 2861 2862 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) 2863 { 2864 struct drm_i915_private *dev_priv = engine->i915; 2865 2866 intel_ring_default_vfuncs(dev_priv, engine); 2867 2868 engine->emit_flush = gen6_ring_flush; 2869 if (INTEL_GEN(dev_priv) < 8) 2870 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; 2871 2872 return intel_init_ring_buffer(engine); 2873 } 2874 2875 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) 2876 { 2877 struct drm_i915_private *dev_priv = engine->i915; 2878 2879 intel_ring_default_vfuncs(dev_priv, engine); 2880 2881 engine->emit_flush = gen6_ring_flush; 2882 2883 if (INTEL_GEN(dev_priv) < 8) { 2884 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; 2885 engine->irq_enable = hsw_vebox_irq_enable; 2886 engine->irq_disable = hsw_vebox_irq_disable; 2887 } 2888 2889 return intel_init_ring_buffer(engine); 2890 } 2891