1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include <drm/drmP.h> 29 #include "intel_drv.h" 30 #include "i915_drv.h" 31 32 #define FORCEWAKE_ACK_TIMEOUT_MS 2 33 34 void i8xx_disable_fbc(struct drm_device *dev) 35 { 36 struct drm_i915_private *dev_priv = dev->dev_private; 37 u32 fbc_ctl; 38 39 /* Disable compression */ 40 fbc_ctl = I915_READ(FBC_CONTROL); 41 if ((fbc_ctl & FBC_CTL_EN) == 0) 42 return; 43 44 fbc_ctl &= ~FBC_CTL_EN; 45 I915_WRITE(FBC_CONTROL, fbc_ctl); 46 47 /* Wait for compressing bit to clear */ 48 if (_intel_wait_for(dev, 49 (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10, 50 1, "915fbd")) { 51 DRM_DEBUG_KMS("FBC idle timed out\n"); 52 return; 53 } 54 55 DRM_DEBUG_KMS("disabled FBC\n"); 56 } 57 58 void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 59 { 60 struct drm_device *dev = crtc->dev; 61 struct drm_i915_private *dev_priv = dev->dev_private; 62 struct drm_framebuffer *fb = crtc->fb; 63 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 64 struct drm_i915_gem_object *obj = intel_fb->obj; 65 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 66 int cfb_pitch; 67 int plane, i; 68 u32 fbc_ctl, fbc_ctl2; 69 70 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; 71 if (fb->pitches[0] < cfb_pitch) 72 cfb_pitch = fb->pitches[0]; 73 74 /* FBC_CTL wants 64B units */ 75 cfb_pitch = (cfb_pitch / 64) - 1; 76 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; 77 78 /* Clear old tags */ 79 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) 80 I915_WRITE(FBC_TAG + (i * 4), 0); 81 82 /* Set it up... */ 83 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; 84 fbc_ctl2 |= plane; 85 I915_WRITE(FBC_CONTROL2, fbc_ctl2); 86 I915_WRITE(FBC_FENCE_OFF, crtc->y); 87 88 /* enable it... */ 89 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; 90 if (IS_I945GM(dev)) 91 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ 92 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 93 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; 94 fbc_ctl |= obj->fence_reg; 95 I915_WRITE(FBC_CONTROL, fbc_ctl); 96 97 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ", 98 cfb_pitch, crtc->y, intel_crtc->plane); 99 } 100 101 bool i8xx_fbc_enabled(struct drm_device *dev) 102 { 103 struct drm_i915_private *dev_priv = dev->dev_private; 104 105 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; 106 } 107 108 void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 109 { 110 struct drm_device *dev = crtc->dev; 111 struct drm_i915_private *dev_priv = dev->dev_private; 112 struct drm_framebuffer *fb = crtc->fb; 113 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 114 struct drm_i915_gem_object *obj = intel_fb->obj; 115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 116 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 117 unsigned long stall_watermark = 200; 118 u32 dpfc_ctl; 119 120 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; 121 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; 122 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); 123 124 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 125 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 126 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 127 I915_WRITE(DPFC_FENCE_YOFF, crtc->y); 128 129 /* enable it... */ 130 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); 131 132 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 133 } 134 135 void g4x_disable_fbc(struct drm_device *dev) 136 { 137 struct drm_i915_private *dev_priv = dev->dev_private; 138 u32 dpfc_ctl; 139 140 /* Disable compression */ 141 dpfc_ctl = I915_READ(DPFC_CONTROL); 142 if (dpfc_ctl & DPFC_CTL_EN) { 143 dpfc_ctl &= ~DPFC_CTL_EN; 144 I915_WRITE(DPFC_CONTROL, dpfc_ctl); 145 146 DRM_DEBUG_KMS("disabled FBC\n"); 147 } 148 } 149 150 bool g4x_fbc_enabled(struct drm_device *dev) 151 { 152 struct drm_i915_private *dev_priv = dev->dev_private; 153 154 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; 155 } 156 157 static void sandybridge_blit_fbc_update(struct drm_device *dev) 158 { 159 struct drm_i915_private *dev_priv = dev->dev_private; 160 u32 blt_ecoskpd; 161 162 /* Make sure blitter notifies FBC of writes */ 163 gen6_gt_force_wake_get(dev_priv); 164 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 165 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 166 GEN6_BLITTER_LOCK_SHIFT; 167 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 168 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; 169 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 170 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << 171 GEN6_BLITTER_LOCK_SHIFT); 172 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 173 POSTING_READ(GEN6_BLITTER_ECOSKPD); 174 gen6_gt_force_wake_put(dev_priv); 175 } 176 177 void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 178 { 179 struct drm_device *dev = crtc->dev; 180 struct drm_i915_private *dev_priv = dev->dev_private; 181 struct drm_framebuffer *fb = crtc->fb; 182 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 183 struct drm_i915_gem_object *obj = intel_fb->obj; 184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 185 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; 186 unsigned long stall_watermark = 200; 187 u32 dpfc_ctl; 188 189 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 190 dpfc_ctl &= DPFC_RESERVED; 191 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); 192 /* Set persistent mode for front-buffer rendering, ala X. */ 193 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; 194 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); 195 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); 196 197 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 198 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | 199 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); 200 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); 201 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); 202 /* enable it... */ 203 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); 204 205 if (IS_GEN6(dev)) { 206 I915_WRITE(SNB_DPFC_CTL_SA, 207 SNB_CPU_FENCE_ENABLE | obj->fence_reg); 208 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); 209 sandybridge_blit_fbc_update(dev); 210 } 211 212 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 213 } 214 215 void ironlake_disable_fbc(struct drm_device *dev) 216 { 217 struct drm_i915_private *dev_priv = dev->dev_private; 218 u32 dpfc_ctl; 219 220 /* Disable compression */ 221 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); 222 if (dpfc_ctl & DPFC_CTL_EN) { 223 dpfc_ctl &= ~DPFC_CTL_EN; 224 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); 225 226 DRM_DEBUG_KMS("disabled FBC\n"); 227 } 228 } 229 230 bool ironlake_fbc_enabled(struct drm_device *dev) 231 { 232 struct drm_i915_private *dev_priv = dev->dev_private; 233 234 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; 235 } 236 237 bool intel_fbc_enabled(struct drm_device *dev) 238 { 239 struct drm_i915_private *dev_priv = dev->dev_private; 240 241 if (!dev_priv->display.fbc_enabled) 242 return false; 243 244 return dev_priv->display.fbc_enabled(dev); 245 } 246 247 static void intel_fbc_work_fn(struct work_struct *__work) 248 { 249 struct intel_fbc_work *work = 250 container_of(to_delayed_work(__work), 251 struct intel_fbc_work, work); 252 struct drm_device *dev = work->crtc->dev; 253 struct drm_i915_private *dev_priv = dev->dev_private; 254 255 DRM_LOCK(dev); 256 if (work == dev_priv->fbc_work) { 257 /* Double check that we haven't switched fb without cancelling 258 * the prior work. 259 */ 260 if (work->crtc->fb == work->fb) { 261 dev_priv->display.enable_fbc(work->crtc, 262 work->interval); 263 264 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; 265 dev_priv->cfb_fb = work->crtc->fb->base.id; 266 dev_priv->cfb_y = work->crtc->y; 267 } 268 269 dev_priv->fbc_work = NULL; 270 } 271 DRM_UNLOCK(dev); 272 273 drm_free(work, DRM_MEM_KMS); 274 } 275 276 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) 277 { 278 if (dev_priv->fbc_work == NULL) 279 return; 280 281 DRM_DEBUG_KMS("cancelling pending FBC enable\n"); 282 283 /* Synchronisation is provided by struct_mutex and checking of 284 * dev_priv->fbc_work, so we can perform the cancellation 285 * entirely asynchronously. 286 */ 287 if (cancel_delayed_work(&dev_priv->fbc_work->work)) 288 /* tasklet was killed before being run, clean up */ 289 kfree(dev_priv->fbc_work, DRM_MEM_KMS); 290 291 /* Mark the work as no longer wanted so that if it does 292 * wake-up (because the work was already running and waiting 293 * for our mutex), it will discover that is no longer 294 * necessary to run. 295 */ 296 dev_priv->fbc_work = NULL; 297 } 298 299 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 300 { 301 struct intel_fbc_work *work; 302 struct drm_device *dev = crtc->dev; 303 struct drm_i915_private *dev_priv = dev->dev_private; 304 305 if (!dev_priv->display.enable_fbc) 306 return; 307 308 intel_cancel_fbc_work(dev_priv); 309 310 work = kmalloc(sizeof(*work), DRM_MEM_KMS, M_WAITOK | M_ZERO); 311 work->crtc = crtc; 312 work->fb = crtc->fb; 313 work->interval = interval; 314 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); 315 316 dev_priv->fbc_work = work; 317 318 DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); 319 320 /* Delay the actual enabling to let pageflipping cease and the 321 * display to settle before starting the compression. Note that 322 * this delay also serves a second purpose: it allows for a 323 * vblank to pass after disabling the FBC before we attempt 324 * to modify the control registers. 325 * 326 * A more complicated solution would involve tracking vblanks 327 * following the termination of the page-flipping sequence 328 * and indeed performing the enable as a co-routine and not 329 * waiting synchronously upon the vblank. 330 */ 331 schedule_delayed_work(&work->work, msecs_to_jiffies(50)); 332 } 333 334 void intel_disable_fbc(struct drm_device *dev) 335 { 336 struct drm_i915_private *dev_priv = dev->dev_private; 337 338 intel_cancel_fbc_work(dev_priv); 339 340 if (!dev_priv->display.disable_fbc) 341 return; 342 343 dev_priv->display.disable_fbc(dev); 344 dev_priv->cfb_plane = -1; 345 } 346 347 /** 348 * intel_update_fbc - enable/disable FBC as needed 349 * @dev: the drm_device 350 * 351 * Set up the framebuffer compression hardware at mode set time. We 352 * enable it if possible: 353 * - plane A only (on pre-965) 354 * - no pixel mulitply/line duplication 355 * - no alpha buffer discard 356 * - no dual wide 357 * - framebuffer <= 2048 in width, 1536 in height 358 * 359 * We can't assume that any compression will take place (worst case), 360 * so the compressed buffer has to be the same size as the uncompressed 361 * one. It also must reside (along with the line length buffer) in 362 * stolen memory. 363 * 364 * We need to enable/disable FBC on a global basis. 365 */ 366 void intel_update_fbc(struct drm_device *dev) 367 { 368 struct drm_i915_private *dev_priv = dev->dev_private; 369 struct drm_crtc *crtc = NULL, *tmp_crtc; 370 struct intel_crtc *intel_crtc; 371 struct drm_framebuffer *fb; 372 struct intel_framebuffer *intel_fb; 373 struct drm_i915_gem_object *obj; 374 int enable_fbc; 375 376 DRM_DEBUG_KMS("\n"); 377 378 if (!i915_powersave) 379 return; 380 381 if (!I915_HAS_FBC(dev)) 382 return; 383 384 /* 385 * If FBC is already on, we just have to verify that we can 386 * keep it that way... 387 * Need to disable if: 388 * - more than one pipe is active 389 * - changing FBC params (stride, fence, mode) 390 * - new fb is too large to fit in compressed buffer 391 * - going to an unsupported config (interlace, pixel multiply, etc.) 392 */ 393 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { 394 if (tmp_crtc->enabled && tmp_crtc->fb) { 395 if (crtc) { 396 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); 397 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; 398 goto out_disable; 399 } 400 crtc = tmp_crtc; 401 } 402 } 403 404 if (!crtc || crtc->fb == NULL) { 405 DRM_DEBUG_KMS("no output, disabling\n"); 406 dev_priv->no_fbc_reason = FBC_NO_OUTPUT; 407 goto out_disable; 408 } 409 410 intel_crtc = to_intel_crtc(crtc); 411 fb = crtc->fb; 412 intel_fb = to_intel_framebuffer(fb); 413 obj = intel_fb->obj; 414 415 enable_fbc = i915_enable_fbc; 416 if (enable_fbc < 0) { 417 DRM_DEBUG_KMS("fbc set to per-chip default\n"); 418 enable_fbc = 1; 419 if (INTEL_INFO(dev)->gen <= 6) 420 enable_fbc = 0; 421 } 422 if (!enable_fbc) { 423 DRM_DEBUG_KMS("fbc disabled per module param\n"); 424 dev_priv->no_fbc_reason = FBC_MODULE_PARAM; 425 goto out_disable; 426 } 427 if (intel_fb->obj->base.size > dev_priv->cfb_size) { 428 DRM_DEBUG_KMS("framebuffer too large, disabling " 429 "compression\n"); 430 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; 431 goto out_disable; 432 } 433 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || 434 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { 435 DRM_DEBUG_KMS("mode incompatible with compression, " 436 "disabling\n"); 437 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; 438 goto out_disable; 439 } 440 if ((crtc->mode.hdisplay > 2048) || 441 (crtc->mode.vdisplay > 1536)) { 442 DRM_DEBUG_KMS("mode too large for compression, disabling\n"); 443 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; 444 goto out_disable; 445 } 446 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { 447 DRM_DEBUG_KMS("plane not 0, disabling compression\n"); 448 dev_priv->no_fbc_reason = FBC_BAD_PLANE; 449 goto out_disable; 450 } 451 if (obj->tiling_mode != I915_TILING_X || 452 obj->fence_reg == I915_FENCE_REG_NONE) { 453 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); 454 dev_priv->no_fbc_reason = FBC_NOT_TILED; 455 goto out_disable; 456 } 457 458 #ifdef DDB 459 /* If the kernel debugger is active, always disable compression */ 460 if (db_active) 461 goto out_disable; 462 #endif 463 464 /* If the scanout has not changed, don't modify the FBC settings. 465 * Note that we make the fundamental assumption that the fb->obj 466 * cannot be unpinned (and have its GTT offset and fence revoked) 467 * without first being decoupled from the scanout and FBC disabled. 468 */ 469 if (dev_priv->cfb_plane == intel_crtc->plane && 470 dev_priv->cfb_fb == fb->base.id && 471 dev_priv->cfb_y == crtc->y) 472 return; 473 474 if (intel_fbc_enabled(dev)) { 475 /* We update FBC along two paths, after changing fb/crtc 476 * configuration (modeswitching) and after page-flipping 477 * finishes. For the latter, we know that not only did 478 * we disable the FBC at the start of the page-flip 479 * sequence, but also more than one vblank has passed. 480 * 481 * For the former case of modeswitching, it is possible 482 * to switch between two FBC valid configurations 483 * instantaneously so we do need to disable the FBC 484 * before we can modify its control registers. We also 485 * have to wait for the next vblank for that to take 486 * effect. However, since we delay enabling FBC we can 487 * assume that a vblank has passed since disabling and 488 * that we can safely alter the registers in the deferred 489 * callback. 490 * 491 * In the scenario that we go from a valid to invalid 492 * and then back to valid FBC configuration we have 493 * no strict enforcement that a vblank occurred since 494 * disabling the FBC. However, along all current pipe 495 * disabling paths we do need to wait for a vblank at 496 * some point. And we wait before enabling FBC anyway. 497 */ 498 DRM_DEBUG_KMS("disabling active FBC for update\n"); 499 intel_disable_fbc(dev); 500 } 501 502 intel_enable_fbc(crtc, 500); 503 return; 504 505 out_disable: 506 /* Multiple disables should be harmless */ 507 if (intel_fbc_enabled(dev)) { 508 DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); 509 intel_disable_fbc(dev); 510 } 511 } 512 513 void i915_ironlake_get_mem_freq(struct drm_device *dev); 514 void i915_pineview_get_mem_freq(struct drm_device *dev); 515 516 void i915_pineview_get_mem_freq(struct drm_device *dev) 517 { 518 drm_i915_private_t *dev_priv = dev->dev_private; 519 u32 tmp; 520 521 tmp = I915_READ(CLKCFG); 522 523 switch (tmp & CLKCFG_FSB_MASK) { 524 case CLKCFG_FSB_533: 525 dev_priv->fsb_freq = 533; /* 133*4 */ 526 break; 527 case CLKCFG_FSB_800: 528 dev_priv->fsb_freq = 800; /* 200*4 */ 529 break; 530 case CLKCFG_FSB_667: 531 dev_priv->fsb_freq = 667; /* 167*4 */ 532 break; 533 case CLKCFG_FSB_400: 534 dev_priv->fsb_freq = 400; /* 100*4 */ 535 break; 536 } 537 538 switch (tmp & CLKCFG_MEM_MASK) { 539 case CLKCFG_MEM_533: 540 dev_priv->mem_freq = 533; 541 break; 542 case CLKCFG_MEM_667: 543 dev_priv->mem_freq = 667; 544 break; 545 case CLKCFG_MEM_800: 546 dev_priv->mem_freq = 800; 547 break; 548 } 549 550 /* detect pineview DDR3 setting */ 551 tmp = I915_READ(CSHRDDR3CTL); 552 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 553 } 554 555 void i915_ironlake_get_mem_freq(struct drm_device *dev) 556 { 557 drm_i915_private_t *dev_priv = dev->dev_private; 558 u16 ddrpll, csipll; 559 560 ddrpll = I915_READ16(DDRMPLL1); 561 csipll = I915_READ16(CSIPLL0); 562 563 switch (ddrpll & 0xff) { 564 case 0xc: 565 dev_priv->mem_freq = 800; 566 break; 567 case 0x10: 568 dev_priv->mem_freq = 1066; 569 break; 570 case 0x14: 571 dev_priv->mem_freq = 1333; 572 break; 573 case 0x18: 574 dev_priv->mem_freq = 1600; 575 break; 576 default: 577 DRM_DEBUG("unknown memory frequency 0x%02x\n", 578 ddrpll & 0xff); 579 dev_priv->mem_freq = 0; 580 break; 581 } 582 583 dev_priv->r_t = dev_priv->mem_freq; 584 585 switch (csipll & 0x3ff) { 586 case 0x00c: 587 dev_priv->fsb_freq = 3200; 588 break; 589 case 0x00e: 590 dev_priv->fsb_freq = 3733; 591 break; 592 case 0x010: 593 dev_priv->fsb_freq = 4266; 594 break; 595 case 0x012: 596 dev_priv->fsb_freq = 4800; 597 break; 598 case 0x014: 599 dev_priv->fsb_freq = 5333; 600 break; 601 case 0x016: 602 dev_priv->fsb_freq = 5866; 603 break; 604 case 0x018: 605 dev_priv->fsb_freq = 6400; 606 break; 607 default: 608 DRM_DEBUG("unknown fsb frequency 0x%04x\n", 609 csipll & 0x3ff); 610 dev_priv->fsb_freq = 0; 611 break; 612 } 613 614 if (dev_priv->fsb_freq == 3200) { 615 dev_priv->c_m = 0; 616 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 617 dev_priv->c_m = 1; 618 } else { 619 dev_priv->c_m = 2; 620 } 621 } 622 623 /* Pineview has different values for various configs */ 624 static const struct intel_watermark_params pineview_display_wm = { 625 PINEVIEW_DISPLAY_FIFO, 626 PINEVIEW_MAX_WM, 627 PINEVIEW_DFT_WM, 628 PINEVIEW_GUARD_WM, 629 PINEVIEW_FIFO_LINE_SIZE 630 }; 631 static const struct intel_watermark_params pineview_display_hplloff_wm = { 632 PINEVIEW_DISPLAY_FIFO, 633 PINEVIEW_MAX_WM, 634 PINEVIEW_DFT_HPLLOFF_WM, 635 PINEVIEW_GUARD_WM, 636 PINEVIEW_FIFO_LINE_SIZE 637 }; 638 static const struct intel_watermark_params pineview_cursor_wm = { 639 PINEVIEW_CURSOR_FIFO, 640 PINEVIEW_CURSOR_MAX_WM, 641 PINEVIEW_CURSOR_DFT_WM, 642 PINEVIEW_CURSOR_GUARD_WM, 643 PINEVIEW_FIFO_LINE_SIZE, 644 }; 645 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 646 PINEVIEW_CURSOR_FIFO, 647 PINEVIEW_CURSOR_MAX_WM, 648 PINEVIEW_CURSOR_DFT_WM, 649 PINEVIEW_CURSOR_GUARD_WM, 650 PINEVIEW_FIFO_LINE_SIZE 651 }; 652 static const struct intel_watermark_params g4x_wm_info = { 653 G4X_FIFO_SIZE, 654 G4X_MAX_WM, 655 G4X_MAX_WM, 656 2, 657 G4X_FIFO_LINE_SIZE, 658 }; 659 static const struct intel_watermark_params g4x_cursor_wm_info = { 660 I965_CURSOR_FIFO, 661 I965_CURSOR_MAX_WM, 662 I965_CURSOR_DFT_WM, 663 2, 664 G4X_FIFO_LINE_SIZE, 665 }; 666 static const struct intel_watermark_params i965_cursor_wm_info = { 667 I965_CURSOR_FIFO, 668 I965_CURSOR_MAX_WM, 669 I965_CURSOR_DFT_WM, 670 2, 671 I915_FIFO_LINE_SIZE, 672 }; 673 static const struct intel_watermark_params i945_wm_info = { 674 I945_FIFO_SIZE, 675 I915_MAX_WM, 676 1, 677 2, 678 I915_FIFO_LINE_SIZE 679 }; 680 static const struct intel_watermark_params i915_wm_info = { 681 I915_FIFO_SIZE, 682 I915_MAX_WM, 683 1, 684 2, 685 I915_FIFO_LINE_SIZE 686 }; 687 static const struct intel_watermark_params i855_wm_info = { 688 I855GM_FIFO_SIZE, 689 I915_MAX_WM, 690 1, 691 2, 692 I830_FIFO_LINE_SIZE 693 }; 694 static const struct intel_watermark_params i830_wm_info = { 695 I830_FIFO_SIZE, 696 I915_MAX_WM, 697 1, 698 2, 699 I830_FIFO_LINE_SIZE 700 }; 701 702 static const struct intel_watermark_params ironlake_display_wm_info = { 703 ILK_DISPLAY_FIFO, 704 ILK_DISPLAY_MAXWM, 705 ILK_DISPLAY_DFTWM, 706 2, 707 ILK_FIFO_LINE_SIZE 708 }; 709 static const struct intel_watermark_params ironlake_cursor_wm_info = { 710 ILK_CURSOR_FIFO, 711 ILK_CURSOR_MAXWM, 712 ILK_CURSOR_DFTWM, 713 2, 714 ILK_FIFO_LINE_SIZE 715 }; 716 static const struct intel_watermark_params ironlake_display_srwm_info = { 717 ILK_DISPLAY_SR_FIFO, 718 ILK_DISPLAY_MAX_SRWM, 719 ILK_DISPLAY_DFT_SRWM, 720 2, 721 ILK_FIFO_LINE_SIZE 722 }; 723 static const struct intel_watermark_params ironlake_cursor_srwm_info = { 724 ILK_CURSOR_SR_FIFO, 725 ILK_CURSOR_MAX_SRWM, 726 ILK_CURSOR_DFT_SRWM, 727 2, 728 ILK_FIFO_LINE_SIZE 729 }; 730 731 static const struct intel_watermark_params sandybridge_display_wm_info = { 732 SNB_DISPLAY_FIFO, 733 SNB_DISPLAY_MAXWM, 734 SNB_DISPLAY_DFTWM, 735 2, 736 SNB_FIFO_LINE_SIZE 737 }; 738 static const struct intel_watermark_params sandybridge_cursor_wm_info = { 739 SNB_CURSOR_FIFO, 740 SNB_CURSOR_MAXWM, 741 SNB_CURSOR_DFTWM, 742 2, 743 SNB_FIFO_LINE_SIZE 744 }; 745 static const struct intel_watermark_params sandybridge_display_srwm_info = { 746 SNB_DISPLAY_SR_FIFO, 747 SNB_DISPLAY_MAX_SRWM, 748 SNB_DISPLAY_DFT_SRWM, 749 2, 750 SNB_FIFO_LINE_SIZE 751 }; 752 static const struct intel_watermark_params sandybridge_cursor_srwm_info = { 753 SNB_CURSOR_SR_FIFO, 754 SNB_CURSOR_MAX_SRWM, 755 SNB_CURSOR_DFT_SRWM, 756 2, 757 SNB_FIFO_LINE_SIZE 758 }; 759 760 761 /** 762 * intel_calculate_wm - calculate watermark level 763 * @clock_in_khz: pixel clock 764 * @wm: chip FIFO params 765 * @pixel_size: display pixel size 766 * @latency_ns: memory latency for the platform 767 * 768 * Calculate the watermark level (the level at which the display plane will 769 * start fetching from memory again). Each chip has a different display 770 * FIFO size and allocation, so the caller needs to figure that out and pass 771 * in the correct intel_watermark_params structure. 772 * 773 * As the pixel clock runs, the FIFO will be drained at a rate that depends 774 * on the pixel size. When it reaches the watermark level, it'll start 775 * fetching FIFO line sized based chunks from memory until the FIFO fills 776 * past the watermark point. If the FIFO drains completely, a FIFO underrun 777 * will occur, and a display engine hang could result. 778 */ 779 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 780 const struct intel_watermark_params *wm, 781 int fifo_size, 782 int pixel_size, 783 unsigned long latency_ns) 784 { 785 long entries_required, wm_size; 786 787 /* 788 * Note: we need to make sure we don't overflow for various clock & 789 * latency values. 790 * clocks go from a few thousand to several hundred thousand. 791 * latency is usually a few thousand 792 */ 793 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 794 1000; 795 entries_required = howmany(entries_required, wm->cacheline_size); 796 797 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 798 799 wm_size = fifo_size - (entries_required + wm->guard_size); 800 801 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 802 803 /* Don't promote wm_size to unsigned... */ 804 if (wm_size > (long)wm->max_wm) 805 wm_size = wm->max_wm; 806 if (wm_size <= 0) 807 wm_size = wm->default_wm; 808 return wm_size; 809 } 810 811 struct cxsr_latency { 812 int is_desktop; 813 int is_ddr3; 814 unsigned long fsb_freq; 815 unsigned long mem_freq; 816 unsigned long display_sr; 817 unsigned long display_hpll_disable; 818 unsigned long cursor_sr; 819 unsigned long cursor_hpll_disable; 820 }; 821 822 static const struct cxsr_latency cxsr_latency_table[] = { 823 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 824 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 825 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 826 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 827 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 828 829 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 830 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 831 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 832 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 833 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 834 835 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 836 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 837 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 838 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 839 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 840 841 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 842 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 843 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 844 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 845 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 846 847 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 848 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 849 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 850 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 851 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 852 853 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 854 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 855 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 856 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 857 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 858 }; 859 860 const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 861 int is_ddr3, 862 int fsb, 863 int mem) 864 { 865 const struct cxsr_latency *latency; 866 int i; 867 868 if (fsb == 0 || mem == 0) 869 return NULL; 870 871 for (i = 0; i < DRM_ARRAY_SIZE(cxsr_latency_table); i++) { 872 latency = &cxsr_latency_table[i]; 873 if (is_desktop == latency->is_desktop && 874 is_ddr3 == latency->is_ddr3 && 875 fsb == latency->fsb_freq && mem == latency->mem_freq) 876 return latency; 877 } 878 879 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 880 881 return NULL; 882 } 883 884 void pineview_disable_cxsr(struct drm_device *dev) 885 { 886 struct drm_i915_private *dev_priv = dev->dev_private; 887 888 /* deactivate cxsr */ 889 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); 890 } 891 892 /* 893 * Latency for FIFO fetches is dependent on several factors: 894 * - memory configuration (speed, channels) 895 * - chipset 896 * - current MCH state 897 * It can be fairly high in some situations, so here we assume a fairly 898 * pessimal value. It's a tradeoff between extra memory fetches (if we 899 * set this value too high, the FIFO will fetch frequently to stay full) 900 * and power consumption (set it too low to save power and we might see 901 * FIFO underruns and display "flicker"). 902 * 903 * A value of 5us seems to be a good balance; safe for very low end 904 * platforms but not overly aggressive on lower latency configs. 905 */ 906 static const int latency_ns = 5000; 907 908 int i9xx_get_fifo_size(struct drm_device *dev, int plane) 909 { 910 struct drm_i915_private *dev_priv = dev->dev_private; 911 uint32_t dsparb = I915_READ(DSPARB); 912 int size; 913 914 size = dsparb & 0x7f; 915 if (plane) 916 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 917 918 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 919 plane ? "B" : "A", size); 920 921 return size; 922 } 923 924 int i85x_get_fifo_size(struct drm_device *dev, int plane) 925 { 926 struct drm_i915_private *dev_priv = dev->dev_private; 927 uint32_t dsparb = I915_READ(DSPARB); 928 int size; 929 930 size = dsparb & 0x1ff; 931 if (plane) 932 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 933 size >>= 1; /* Convert to cachelines */ 934 935 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 936 plane ? "B" : "A", size); 937 938 return size; 939 } 940 941 int i845_get_fifo_size(struct drm_device *dev, int plane) 942 { 943 struct drm_i915_private *dev_priv = dev->dev_private; 944 uint32_t dsparb = I915_READ(DSPARB); 945 int size; 946 947 size = dsparb & 0x7f; 948 size >>= 2; /* Convert to cachelines */ 949 950 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 951 plane ? "B" : "A", 952 size); 953 954 return size; 955 } 956 957 int i830_get_fifo_size(struct drm_device *dev, int plane) 958 { 959 struct drm_i915_private *dev_priv = dev->dev_private; 960 uint32_t dsparb = I915_READ(DSPARB); 961 int size; 962 963 size = dsparb & 0x7f; 964 size >>= 1; /* Convert to cachelines */ 965 966 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 967 plane ? "B" : "A", size); 968 969 return size; 970 } 971 972 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 973 { 974 struct drm_crtc *crtc, *enabled = NULL; 975 976 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 977 if (crtc->enabled && crtc->fb) { 978 if (enabled) 979 return NULL; 980 enabled = crtc; 981 } 982 } 983 984 return enabled; 985 } 986 987 void pineview_update_wm(struct drm_device *dev) 988 { 989 struct drm_i915_private *dev_priv = dev->dev_private; 990 struct drm_crtc *crtc; 991 const struct cxsr_latency *latency; 992 u32 reg; 993 unsigned long wm; 994 995 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 996 dev_priv->fsb_freq, dev_priv->mem_freq); 997 if (!latency) { 998 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 999 pineview_disable_cxsr(dev); 1000 return; 1001 } 1002 1003 crtc = single_enabled_crtc(dev); 1004 if (crtc) { 1005 int clock = crtc->mode.clock; 1006 int pixel_size = crtc->fb->bits_per_pixel / 8; 1007 1008 /* Display SR */ 1009 wm = intel_calculate_wm(clock, &pineview_display_wm, 1010 pineview_display_wm.fifo_size, 1011 pixel_size, latency->display_sr); 1012 reg = I915_READ(DSPFW1); 1013 reg &= ~DSPFW_SR_MASK; 1014 reg |= wm << DSPFW_SR_SHIFT; 1015 I915_WRITE(DSPFW1, reg); 1016 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 1017 1018 /* cursor SR */ 1019 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 1020 pineview_display_wm.fifo_size, 1021 pixel_size, latency->cursor_sr); 1022 reg = I915_READ(DSPFW3); 1023 reg &= ~DSPFW_CURSOR_SR_MASK; 1024 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; 1025 I915_WRITE(DSPFW3, reg); 1026 1027 /* Display HPLL off SR */ 1028 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 1029 pineview_display_hplloff_wm.fifo_size, 1030 pixel_size, latency->display_hpll_disable); 1031 reg = I915_READ(DSPFW3); 1032 reg &= ~DSPFW_HPLL_SR_MASK; 1033 reg |= wm & DSPFW_HPLL_SR_MASK; 1034 I915_WRITE(DSPFW3, reg); 1035 1036 /* cursor HPLL off SR */ 1037 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 1038 pineview_display_hplloff_wm.fifo_size, 1039 pixel_size, latency->cursor_hpll_disable); 1040 reg = I915_READ(DSPFW3); 1041 reg &= ~DSPFW_HPLL_CURSOR_MASK; 1042 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; 1043 I915_WRITE(DSPFW3, reg); 1044 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 1045 1046 /* activate cxsr */ 1047 I915_WRITE(DSPFW3, 1048 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); 1049 DRM_DEBUG_KMS("Self-refresh is enabled\n"); 1050 } else { 1051 pineview_disable_cxsr(dev); 1052 DRM_DEBUG_KMS("Self-refresh is disabled\n"); 1053 } 1054 } 1055 1056 static bool g4x_compute_wm0(struct drm_device *dev, 1057 int plane, 1058 const struct intel_watermark_params *display, 1059 int display_latency_ns, 1060 const struct intel_watermark_params *cursor, 1061 int cursor_latency_ns, 1062 int *plane_wm, 1063 int *cursor_wm) 1064 { 1065 struct drm_crtc *crtc; 1066 int htotal, hdisplay, clock, pixel_size; 1067 int line_time_us, line_count; 1068 int entries, tlb_miss; 1069 1070 crtc = intel_get_crtc_for_plane(dev, plane); 1071 if (crtc->fb == NULL || !crtc->enabled) { 1072 *cursor_wm = cursor->guard_size; 1073 *plane_wm = display->guard_size; 1074 return false; 1075 } 1076 1077 htotal = crtc->mode.htotal; 1078 hdisplay = crtc->mode.hdisplay; 1079 clock = crtc->mode.clock; 1080 pixel_size = crtc->fb->bits_per_pixel / 8; 1081 1082 /* Use the small buffer method to calculate plane watermark */ 1083 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 1084 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 1085 if (tlb_miss > 0) 1086 entries += tlb_miss; 1087 entries = howmany(entries, display->cacheline_size); 1088 *plane_wm = entries + display->guard_size; 1089 if (*plane_wm > (int)display->max_wm) 1090 *plane_wm = display->max_wm; 1091 1092 /* Use the large buffer method to calculate cursor watermark */ 1093 line_time_us = ((htotal * 1000) / clock); 1094 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 1095 entries = line_count * 64 * pixel_size; 1096 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 1097 if (tlb_miss > 0) 1098 entries += tlb_miss; 1099 entries = howmany(entries, cursor->cacheline_size); 1100 *cursor_wm = entries + cursor->guard_size; 1101 if (*cursor_wm > (int)cursor->max_wm) 1102 *cursor_wm = (int)cursor->max_wm; 1103 1104 return true; 1105 } 1106 1107 /* 1108 * Check the wm result. 1109 * 1110 * If any calculated watermark values is larger than the maximum value that 1111 * can be programmed into the associated watermark register, that watermark 1112 * must be disabled. 1113 */ 1114 static bool g4x_check_srwm(struct drm_device *dev, 1115 int display_wm, int cursor_wm, 1116 const struct intel_watermark_params *display, 1117 const struct intel_watermark_params *cursor) 1118 { 1119 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 1120 display_wm, cursor_wm); 1121 1122 if (display_wm > display->max_wm) { 1123 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 1124 display_wm, display->max_wm); 1125 return false; 1126 } 1127 1128 if (cursor_wm > cursor->max_wm) { 1129 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 1130 cursor_wm, cursor->max_wm); 1131 return false; 1132 } 1133 1134 if (!(display_wm || cursor_wm)) { 1135 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 1136 return false; 1137 } 1138 1139 return true; 1140 } 1141 1142 static bool g4x_compute_srwm(struct drm_device *dev, 1143 int plane, 1144 int latency_ns, 1145 const struct intel_watermark_params *display, 1146 const struct intel_watermark_params *cursor, 1147 int *display_wm, int *cursor_wm) 1148 { 1149 struct drm_crtc *crtc; 1150 int hdisplay, htotal, pixel_size, clock; 1151 unsigned long line_time_us; 1152 int line_count, line_size; 1153 int small, large; 1154 int entries; 1155 1156 if (!latency_ns) { 1157 *display_wm = *cursor_wm = 0; 1158 return false; 1159 } 1160 1161 crtc = intel_get_crtc_for_plane(dev, plane); 1162 hdisplay = crtc->mode.hdisplay; 1163 htotal = crtc->mode.htotal; 1164 clock = crtc->mode.clock; 1165 pixel_size = crtc->fb->bits_per_pixel / 8; 1166 1167 line_time_us = (htotal * 1000) / clock; 1168 line_count = (latency_ns / line_time_us + 1000) / 1000; 1169 line_size = hdisplay * pixel_size; 1170 1171 /* Use the minimum of the small and large buffer method for primary */ 1172 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1173 large = line_count * line_size; 1174 1175 entries = howmany(min(small, large), display->cacheline_size); 1176 *display_wm = entries + display->guard_size; 1177 1178 /* calculate the self-refresh watermark for display cursor */ 1179 entries = line_count * pixel_size * 64; 1180 entries = howmany(entries, cursor->cacheline_size); 1181 *cursor_wm = entries + cursor->guard_size; 1182 1183 return g4x_check_srwm(dev, 1184 *display_wm, *cursor_wm, 1185 display, cursor); 1186 } 1187 1188 #define single_plane_enabled(mask) ((mask) != 0 && powerof2(mask)) 1189 1190 void g4x_update_wm(struct drm_device *dev) 1191 { 1192 static const int sr_latency_ns = 12000; 1193 struct drm_i915_private *dev_priv = dev->dev_private; 1194 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1195 int plane_sr, cursor_sr; 1196 unsigned int enabled = 0; 1197 1198 if (g4x_compute_wm0(dev, 0, 1199 &g4x_wm_info, latency_ns, 1200 &g4x_cursor_wm_info, latency_ns, 1201 &planea_wm, &cursora_wm)) 1202 enabled |= 1; 1203 1204 if (g4x_compute_wm0(dev, 1, 1205 &g4x_wm_info, latency_ns, 1206 &g4x_cursor_wm_info, latency_ns, 1207 &planeb_wm, &cursorb_wm)) 1208 enabled |= 2; 1209 1210 plane_sr = cursor_sr = 0; 1211 if (single_plane_enabled(enabled) && 1212 g4x_compute_srwm(dev, ffs(enabled) - 1, 1213 sr_latency_ns, 1214 &g4x_wm_info, 1215 &g4x_cursor_wm_info, 1216 &plane_sr, &cursor_sr)) 1217 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1218 else 1219 I915_WRITE(FW_BLC_SELF, 1220 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); 1221 1222 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1223 planea_wm, cursora_wm, 1224 planeb_wm, cursorb_wm, 1225 plane_sr, cursor_sr); 1226 1227 I915_WRITE(DSPFW1, 1228 (plane_sr << DSPFW_SR_SHIFT) | 1229 (cursorb_wm << DSPFW_CURSORB_SHIFT) | 1230 (planeb_wm << DSPFW_PLANEB_SHIFT) | 1231 planea_wm); 1232 I915_WRITE(DSPFW2, 1233 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) | 1234 (cursora_wm << DSPFW_CURSORA_SHIFT)); 1235 /* HPLL off in SR has some issues on G4x... disable it */ 1236 I915_WRITE(DSPFW3, 1237 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) | 1238 (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1239 } 1240 1241 void i965_update_wm(struct drm_device *dev) 1242 { 1243 struct drm_i915_private *dev_priv = dev->dev_private; 1244 struct drm_crtc *crtc; 1245 int srwm = 1; 1246 int cursor_sr = 16; 1247 1248 /* Calc sr entries for one plane configs */ 1249 crtc = single_enabled_crtc(dev); 1250 if (crtc) { 1251 /* self-refresh has much higher latency */ 1252 static const int sr_latency_ns = 12000; 1253 int clock = crtc->mode.clock; 1254 int htotal = crtc->mode.htotal; 1255 int hdisplay = crtc->mode.hdisplay; 1256 int pixel_size = crtc->fb->bits_per_pixel / 8; 1257 unsigned long line_time_us; 1258 int entries; 1259 1260 line_time_us = ((htotal * 1000) / clock); 1261 1262 /* Use ns/us then divide to preserve precision */ 1263 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1264 pixel_size * hdisplay; 1265 entries = howmany(entries, I915_FIFO_LINE_SIZE); 1266 srwm = I965_FIFO_SIZE - entries; 1267 if (srwm < 0) 1268 srwm = 1; 1269 srwm &= 0x1ff; 1270 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1271 entries, srwm); 1272 1273 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1274 pixel_size * 64; 1275 entries = howmany(entries, i965_cursor_wm_info.cacheline_size); 1276 cursor_sr = i965_cursor_wm_info.fifo_size - 1277 (entries + i965_cursor_wm_info.guard_size); 1278 1279 if (cursor_sr > i965_cursor_wm_info.max_wm) 1280 cursor_sr = i965_cursor_wm_info.max_wm; 1281 1282 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1283 "cursor %d\n", srwm, cursor_sr); 1284 1285 if (IS_CRESTLINE(dev)) 1286 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); 1287 } else { 1288 /* Turn off self refresh if both pipes are enabled */ 1289 if (IS_CRESTLINE(dev)) 1290 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) 1291 & ~FW_BLC_SELF_EN); 1292 } 1293 1294 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1295 srwm); 1296 1297 /* 965 has limitations... */ 1298 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | 1299 (8 << 16) | (8 << 8) | (8 << 0)); 1300 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); 1301 /* update cursor SR watermark */ 1302 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); 1303 } 1304 1305 void i9xx_update_wm(struct drm_device *dev) 1306 { 1307 struct drm_i915_private *dev_priv = dev->dev_private; 1308 const struct intel_watermark_params *wm_info; 1309 uint32_t fwater_lo; 1310 uint32_t fwater_hi; 1311 int cwm, srwm = 1; 1312 int fifo_size; 1313 int planea_wm, planeb_wm; 1314 struct drm_crtc *crtc, *enabled = NULL; 1315 1316 if (IS_I945GM(dev)) 1317 wm_info = &i945_wm_info; 1318 else if (!IS_GEN2(dev)) 1319 wm_info = &i915_wm_info; 1320 else 1321 wm_info = &i855_wm_info; 1322 1323 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1324 crtc = intel_get_crtc_for_plane(dev, 0); 1325 if (crtc->enabled && crtc->fb) { 1326 planea_wm = intel_calculate_wm(crtc->mode.clock, 1327 wm_info, fifo_size, 1328 crtc->fb->bits_per_pixel / 8, 1329 latency_ns); 1330 enabled = crtc; 1331 } else 1332 planea_wm = fifo_size - wm_info->guard_size; 1333 1334 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1335 crtc = intel_get_crtc_for_plane(dev, 1); 1336 if (crtc->enabled && crtc->fb) { 1337 planeb_wm = intel_calculate_wm(crtc->mode.clock, 1338 wm_info, fifo_size, 1339 crtc->fb->bits_per_pixel / 8, 1340 latency_ns); 1341 if (enabled == NULL) 1342 enabled = crtc; 1343 else 1344 enabled = NULL; 1345 } else 1346 planeb_wm = fifo_size - wm_info->guard_size; 1347 1348 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1349 1350 /* 1351 * Overlay gets an aggressive default since video jitter is bad. 1352 */ 1353 cwm = 2; 1354 1355 /* Play safe and disable self-refresh before adjusting watermarks. */ 1356 if (IS_I945G(dev) || IS_I945GM(dev)) 1357 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); 1358 else if (IS_I915GM(dev)) 1359 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); 1360 1361 /* Calc sr entries for one plane configs */ 1362 if (HAS_FW_BLC(dev) && enabled) { 1363 /* self-refresh has much higher latency */ 1364 static const int sr_latency_ns = 6000; 1365 int clock = enabled->mode.clock; 1366 int htotal = enabled->mode.htotal; 1367 int hdisplay = enabled->mode.hdisplay; 1368 int pixel_size = enabled->fb->bits_per_pixel / 8; 1369 unsigned long line_time_us; 1370 int entries; 1371 1372 line_time_us = (htotal * 1000) / clock; 1373 1374 /* Use ns/us then divide to preserve precision */ 1375 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1376 pixel_size * hdisplay; 1377 entries = howmany(entries, wm_info->cacheline_size); 1378 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1379 srwm = wm_info->fifo_size - entries; 1380 if (srwm < 0) 1381 srwm = 1; 1382 1383 if (IS_I945G(dev) || IS_I945GM(dev)) 1384 I915_WRITE(FW_BLC_SELF, 1385 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1386 else if (IS_I915GM(dev)) 1387 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1388 } 1389 1390 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1391 planea_wm, planeb_wm, cwm, srwm); 1392 1393 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1394 fwater_hi = (cwm & 0x1f); 1395 1396 /* Set request length to 8 cachelines per fetch */ 1397 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1398 fwater_hi = fwater_hi | (1 << 8); 1399 1400 I915_WRITE(FW_BLC, fwater_lo); 1401 I915_WRITE(FW_BLC2, fwater_hi); 1402 1403 if (HAS_FW_BLC(dev)) { 1404 if (enabled) { 1405 if (IS_I945G(dev) || IS_I945GM(dev)) 1406 I915_WRITE(FW_BLC_SELF, 1407 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); 1408 else if (IS_I915GM(dev)) 1409 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); 1410 DRM_DEBUG_KMS("memory self refresh enabled\n"); 1411 } else 1412 DRM_DEBUG_KMS("memory self refresh disabled\n"); 1413 } 1414 } 1415 1416 void i830_update_wm(struct drm_device *dev) 1417 { 1418 struct drm_i915_private *dev_priv = dev->dev_private; 1419 struct drm_crtc *crtc; 1420 uint32_t fwater_lo; 1421 int planea_wm; 1422 1423 crtc = single_enabled_crtc(dev); 1424 if (crtc == NULL) 1425 return; 1426 1427 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, 1428 dev_priv->display.get_fifo_size(dev, 0), 1429 crtc->fb->bits_per_pixel / 8, 1430 latency_ns); 1431 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1432 fwater_lo |= (3<<8) | planea_wm; 1433 1434 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1435 1436 I915_WRITE(FW_BLC, fwater_lo); 1437 } 1438 1439 #define ILK_LP0_PLANE_LATENCY 700 1440 #define ILK_LP0_CURSOR_LATENCY 1300 1441 1442 /* 1443 * Check the wm result. 1444 * 1445 * If any calculated watermark values is larger than the maximum value that 1446 * can be programmed into the associated watermark register, that watermark 1447 * must be disabled. 1448 */ 1449 static bool ironlake_check_srwm(struct drm_device *dev, int level, 1450 int fbc_wm, int display_wm, int cursor_wm, 1451 const struct intel_watermark_params *display, 1452 const struct intel_watermark_params *cursor) 1453 { 1454 struct drm_i915_private *dev_priv = dev->dev_private; 1455 1456 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," 1457 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); 1458 1459 if (fbc_wm > SNB_FBC_MAX_SRWM) { 1460 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", 1461 fbc_wm, SNB_FBC_MAX_SRWM, level); 1462 1463 /* fbc has it's own way to disable FBC WM */ 1464 I915_WRITE(DISP_ARB_CTL, 1465 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); 1466 return false; 1467 } 1468 1469 if (display_wm > display->max_wm) { 1470 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", 1471 display_wm, SNB_DISPLAY_MAX_SRWM, level); 1472 return false; 1473 } 1474 1475 if (cursor_wm > cursor->max_wm) { 1476 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", 1477 cursor_wm, SNB_CURSOR_MAX_SRWM, level); 1478 return false; 1479 } 1480 1481 if (!(fbc_wm || display_wm || cursor_wm)) { 1482 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); 1483 return false; 1484 } 1485 1486 return true; 1487 } 1488 1489 /* 1490 * Compute watermark values of WM[1-3], 1491 */ 1492 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, 1493 int latency_ns, 1494 const struct intel_watermark_params *display, 1495 const struct intel_watermark_params *cursor, 1496 int *fbc_wm, int *display_wm, int *cursor_wm) 1497 { 1498 struct drm_crtc *crtc; 1499 unsigned long line_time_us; 1500 int hdisplay, htotal, pixel_size, clock; 1501 int line_count, line_size; 1502 int small, large; 1503 int entries; 1504 1505 if (!latency_ns) { 1506 *fbc_wm = *display_wm = *cursor_wm = 0; 1507 return false; 1508 } 1509 1510 crtc = intel_get_crtc_for_plane(dev, plane); 1511 hdisplay = crtc->mode.hdisplay; 1512 htotal = crtc->mode.htotal; 1513 clock = crtc->mode.clock; 1514 pixel_size = crtc->fb->bits_per_pixel / 8; 1515 1516 line_time_us = (htotal * 1000) / clock; 1517 line_count = (latency_ns / line_time_us + 1000) / 1000; 1518 line_size = hdisplay * pixel_size; 1519 1520 /* Use the minimum of the small and large buffer method for primary */ 1521 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1522 large = line_count * line_size; 1523 1524 entries = howmany(min(small, large), display->cacheline_size); 1525 *display_wm = entries + display->guard_size; 1526 1527 /* 1528 * Spec says: 1529 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 1530 */ 1531 *fbc_wm = howmany(*display_wm * 64, line_size) + 2; 1532 1533 /* calculate the self-refresh watermark for display cursor */ 1534 entries = line_count * pixel_size * 64; 1535 entries = howmany(entries, cursor->cacheline_size); 1536 *cursor_wm = entries + cursor->guard_size; 1537 1538 return ironlake_check_srwm(dev, level, 1539 *fbc_wm, *display_wm, *cursor_wm, 1540 display, cursor); 1541 } 1542 1543 void ironlake_update_wm(struct drm_device *dev) 1544 { 1545 struct drm_i915_private *dev_priv = dev->dev_private; 1546 int fbc_wm, plane_wm, cursor_wm; 1547 unsigned int enabled; 1548 1549 enabled = 0; 1550 if (g4x_compute_wm0(dev, 0, 1551 &ironlake_display_wm_info, 1552 ILK_LP0_PLANE_LATENCY, 1553 &ironlake_cursor_wm_info, 1554 ILK_LP0_CURSOR_LATENCY, 1555 &plane_wm, &cursor_wm)) { 1556 I915_WRITE(WM0_PIPEA_ILK, 1557 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1558 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1559 " plane %d, " "cursor: %d\n", 1560 plane_wm, cursor_wm); 1561 enabled |= 1; 1562 } 1563 1564 if (g4x_compute_wm0(dev, 1, 1565 &ironlake_display_wm_info, 1566 ILK_LP0_PLANE_LATENCY, 1567 &ironlake_cursor_wm_info, 1568 ILK_LP0_CURSOR_LATENCY, 1569 &plane_wm, &cursor_wm)) { 1570 I915_WRITE(WM0_PIPEB_ILK, 1571 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); 1572 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1573 " plane %d, cursor: %d\n", 1574 plane_wm, cursor_wm); 1575 enabled |= 2; 1576 } 1577 1578 /* 1579 * Calculate and update the self-refresh watermark only when one 1580 * display plane is used. 1581 */ 1582 I915_WRITE(WM3_LP_ILK, 0); 1583 I915_WRITE(WM2_LP_ILK, 0); 1584 I915_WRITE(WM1_LP_ILK, 0); 1585 1586 if (!single_plane_enabled(enabled)) 1587 return; 1588 enabled = ffs(enabled) - 1; 1589 1590 /* WM1 */ 1591 if (!ironlake_compute_srwm(dev, 1, enabled, 1592 ILK_READ_WM1_LATENCY() * 500, 1593 &ironlake_display_srwm_info, 1594 &ironlake_cursor_srwm_info, 1595 &fbc_wm, &plane_wm, &cursor_wm)) 1596 return; 1597 1598 I915_WRITE(WM1_LP_ILK, 1599 WM1_LP_SR_EN | 1600 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1601 (fbc_wm << WM1_LP_FBC_SHIFT) | 1602 (plane_wm << WM1_LP_SR_SHIFT) | 1603 cursor_wm); 1604 1605 /* WM2 */ 1606 if (!ironlake_compute_srwm(dev, 2, enabled, 1607 ILK_READ_WM2_LATENCY() * 500, 1608 &ironlake_display_srwm_info, 1609 &ironlake_cursor_srwm_info, 1610 &fbc_wm, &plane_wm, &cursor_wm)) 1611 return; 1612 1613 I915_WRITE(WM2_LP_ILK, 1614 WM2_LP_EN | 1615 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1616 (fbc_wm << WM1_LP_FBC_SHIFT) | 1617 (plane_wm << WM1_LP_SR_SHIFT) | 1618 cursor_wm); 1619 1620 /* 1621 * WM3 is unsupported on ILK, probably because we don't have latency 1622 * data for that power state 1623 */ 1624 } 1625 1626 void sandybridge_update_wm(struct drm_device *dev) 1627 { 1628 struct drm_i915_private *dev_priv = dev->dev_private; 1629 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1630 u32 val; 1631 int fbc_wm, plane_wm, cursor_wm; 1632 unsigned int enabled; 1633 1634 enabled = 0; 1635 if (g4x_compute_wm0(dev, 0, 1636 &sandybridge_display_wm_info, latency, 1637 &sandybridge_cursor_wm_info, latency, 1638 &plane_wm, &cursor_wm)) { 1639 val = I915_READ(WM0_PIPEA_ILK); 1640 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1641 I915_WRITE(WM0_PIPEA_ILK, val | 1642 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1643 DRM_DEBUG_KMS("FIFO watermarks For pipe A -" 1644 " plane %d, " "cursor: %d\n", 1645 plane_wm, cursor_wm); 1646 enabled |= 1; 1647 } 1648 1649 if (g4x_compute_wm0(dev, 1, 1650 &sandybridge_display_wm_info, latency, 1651 &sandybridge_cursor_wm_info, latency, 1652 &plane_wm, &cursor_wm)) { 1653 val = I915_READ(WM0_PIPEB_ILK); 1654 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1655 I915_WRITE(WM0_PIPEB_ILK, val | 1656 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1657 DRM_DEBUG_KMS("FIFO watermarks For pipe B -" 1658 " plane %d, cursor: %d\n", 1659 plane_wm, cursor_wm); 1660 enabled |= 2; 1661 } 1662 1663 /* IVB has 3 pipes */ 1664 if (IS_IVYBRIDGE(dev) && 1665 g4x_compute_wm0(dev, 2, 1666 &sandybridge_display_wm_info, latency, 1667 &sandybridge_cursor_wm_info, latency, 1668 &plane_wm, &cursor_wm)) { 1669 val = I915_READ(WM0_PIPEC_IVB); 1670 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); 1671 I915_WRITE(WM0_PIPEC_IVB, val | 1672 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); 1673 DRM_DEBUG_KMS("FIFO watermarks For pipe C -" 1674 " plane %d, cursor: %d\n", 1675 plane_wm, cursor_wm); 1676 enabled |= 3; 1677 } 1678 1679 /* 1680 * Calculate and update the self-refresh watermark only when one 1681 * display plane is used. 1682 * 1683 * SNB support 3 levels of watermark. 1684 * 1685 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, 1686 * and disabled in the descending order 1687 * 1688 */ 1689 I915_WRITE(WM3_LP_ILK, 0); 1690 I915_WRITE(WM2_LP_ILK, 0); 1691 I915_WRITE(WM1_LP_ILK, 0); 1692 1693 if (!single_plane_enabled(enabled) || 1694 dev_priv->sprite_scaling_enabled) 1695 return; 1696 enabled = ffs(enabled) - 1; 1697 1698 /* WM1 */ 1699 if (!ironlake_compute_srwm(dev, 1, enabled, 1700 SNB_READ_WM1_LATENCY() * 500, 1701 &sandybridge_display_srwm_info, 1702 &sandybridge_cursor_srwm_info, 1703 &fbc_wm, &plane_wm, &cursor_wm)) 1704 return; 1705 1706 I915_WRITE(WM1_LP_ILK, 1707 WM1_LP_SR_EN | 1708 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1709 (fbc_wm << WM1_LP_FBC_SHIFT) | 1710 (plane_wm << WM1_LP_SR_SHIFT) | 1711 cursor_wm); 1712 1713 /* WM2 */ 1714 if (!ironlake_compute_srwm(dev, 2, enabled, 1715 SNB_READ_WM2_LATENCY() * 500, 1716 &sandybridge_display_srwm_info, 1717 &sandybridge_cursor_srwm_info, 1718 &fbc_wm, &plane_wm, &cursor_wm)) 1719 return; 1720 1721 I915_WRITE(WM2_LP_ILK, 1722 WM2_LP_EN | 1723 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1724 (fbc_wm << WM1_LP_FBC_SHIFT) | 1725 (plane_wm << WM1_LP_SR_SHIFT) | 1726 cursor_wm); 1727 1728 /* WM3 */ 1729 if (!ironlake_compute_srwm(dev, 3, enabled, 1730 SNB_READ_WM3_LATENCY() * 500, 1731 &sandybridge_display_srwm_info, 1732 &sandybridge_cursor_srwm_info, 1733 &fbc_wm, &plane_wm, &cursor_wm)) 1734 return; 1735 1736 I915_WRITE(WM3_LP_ILK, 1737 WM3_LP_EN | 1738 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | 1739 (fbc_wm << WM1_LP_FBC_SHIFT) | 1740 (plane_wm << WM1_LP_SR_SHIFT) | 1741 cursor_wm); 1742 } 1743 1744 static bool 1745 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, 1746 uint32_t sprite_width, int pixel_size, 1747 const struct intel_watermark_params *display, 1748 int display_latency_ns, int *sprite_wm) 1749 { 1750 struct drm_crtc *crtc; 1751 int clock; 1752 int entries, tlb_miss; 1753 1754 crtc = intel_get_crtc_for_plane(dev, plane); 1755 if (crtc->fb == NULL || !crtc->enabled) { 1756 *sprite_wm = display->guard_size; 1757 return false; 1758 } 1759 1760 clock = crtc->mode.clock; 1761 1762 /* Use the small buffer method to calculate the sprite watermark */ 1763 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 1764 tlb_miss = display->fifo_size*display->cacheline_size - 1765 sprite_width * 8; 1766 if (tlb_miss > 0) 1767 entries += tlb_miss; 1768 entries = howmany(entries, display->cacheline_size); 1769 *sprite_wm = entries + display->guard_size; 1770 if (*sprite_wm > (int)display->max_wm) 1771 *sprite_wm = display->max_wm; 1772 1773 return true; 1774 } 1775 1776 static bool 1777 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, 1778 uint32_t sprite_width, int pixel_size, 1779 const struct intel_watermark_params *display, 1780 int latency_ns, int *sprite_wm) 1781 { 1782 struct drm_crtc *crtc; 1783 unsigned long line_time_us; 1784 int clock; 1785 int line_count, line_size; 1786 int small, large; 1787 int entries; 1788 1789 if (!latency_ns) { 1790 *sprite_wm = 0; 1791 return false; 1792 } 1793 1794 crtc = intel_get_crtc_for_plane(dev, plane); 1795 clock = crtc->mode.clock; 1796 if (!clock) { 1797 *sprite_wm = 0; 1798 return false; 1799 } 1800 1801 line_time_us = (sprite_width * 1000) / clock; 1802 if (!line_time_us) { 1803 *sprite_wm = 0; 1804 return false; 1805 } 1806 1807 line_count = (latency_ns / line_time_us + 1000) / 1000; 1808 line_size = sprite_width * pixel_size; 1809 1810 /* Use the minimum of the small and large buffer method for primary */ 1811 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 1812 large = line_count * line_size; 1813 1814 entries = howmany(min(small, large), display->cacheline_size); 1815 *sprite_wm = entries + display->guard_size; 1816 1817 return *sprite_wm > 0x3ff ? false : true; 1818 } 1819 1820 void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, 1821 uint32_t sprite_width, int pixel_size) 1822 { 1823 struct drm_i915_private *dev_priv = dev->dev_private; 1824 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ 1825 u32 val; 1826 int sprite_wm, reg; 1827 int ret; 1828 1829 switch (pipe) { 1830 case 0: 1831 reg = WM0_PIPEA_ILK; 1832 break; 1833 case 1: 1834 reg = WM0_PIPEB_ILK; 1835 break; 1836 case 2: 1837 reg = WM0_PIPEC_IVB; 1838 break; 1839 default: 1840 return; /* bad pipe */ 1841 } 1842 1843 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, 1844 &sandybridge_display_wm_info, 1845 latency, &sprite_wm); 1846 if (!ret) { 1847 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n", 1848 pipe); 1849 return; 1850 } 1851 1852 val = I915_READ(reg); 1853 val &= ~WM0_PIPE_SPRITE_MASK; 1854 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); 1855 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm); 1856 1857 1858 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 1859 pixel_size, 1860 &sandybridge_display_srwm_info, 1861 SNB_READ_WM1_LATENCY() * 500, 1862 &sprite_wm); 1863 if (!ret) { 1864 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n", 1865 pipe); 1866 return; 1867 } 1868 I915_WRITE(WM1S_LP_ILK, sprite_wm); 1869 1870 /* Only IVB has two more LP watermarks for sprite */ 1871 if (!IS_IVYBRIDGE(dev)) 1872 return; 1873 1874 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 1875 pixel_size, 1876 &sandybridge_display_srwm_info, 1877 SNB_READ_WM2_LATENCY() * 500, 1878 &sprite_wm); 1879 if (!ret) { 1880 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n", 1881 pipe); 1882 return; 1883 } 1884 I915_WRITE(WM2S_LP_IVB, sprite_wm); 1885 1886 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, 1887 pixel_size, 1888 &sandybridge_display_srwm_info, 1889 SNB_READ_WM3_LATENCY() * 500, 1890 &sprite_wm); 1891 if (!ret) { 1892 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n", 1893 pipe); 1894 return; 1895 } 1896 I915_WRITE(WM3S_LP_IVB, sprite_wm); 1897 } 1898 1899 /** 1900 * intel_update_watermarks - update FIFO watermark values based on current modes 1901 * 1902 * Calculate watermark values for the various WM regs based on current mode 1903 * and plane configuration. 1904 * 1905 * There are several cases to deal with here: 1906 * - normal (i.e. non-self-refresh) 1907 * - self-refresh (SR) mode 1908 * - lines are large relative to FIFO size (buffer can hold up to 2) 1909 * - lines are small relative to FIFO size (buffer can hold more than 2 1910 * lines), so need to account for TLB latency 1911 * 1912 * The normal calculation is: 1913 * watermark = dotclock * bytes per pixel * latency 1914 * where latency is platform & configuration dependent (we assume pessimal 1915 * values here). 1916 * 1917 * The SR calculation is: 1918 * watermark = (trunc(latency/line time)+1) * surface width * 1919 * bytes per pixel 1920 * where 1921 * line time = htotal / dotclock 1922 * surface width = hdisplay for normal plane and 64 for cursor 1923 * and latency is assumed to be high, as above. 1924 * 1925 * The final value programmed to the register should always be rounded up, 1926 * and include an extra 2 entries to account for clock crossings. 1927 * 1928 * We don't use the sprite, so we can ignore that. And on Crestline we have 1929 * to set the non-SR watermarks to 8. 1930 */ 1931 void intel_update_watermarks(struct drm_device *dev) 1932 { 1933 struct drm_i915_private *dev_priv = dev->dev_private; 1934 1935 if (dev_priv->display.update_wm) 1936 dev_priv->display.update_wm(dev); 1937 } 1938 1939 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 1940 uint32_t sprite_width, int pixel_size) 1941 { 1942 struct drm_i915_private *dev_priv = dev->dev_private; 1943 1944 if (dev_priv->display.update_sprite_wm) 1945 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, 1946 pixel_size); 1947 } 1948 1949 static struct drm_i915_gem_object * 1950 intel_alloc_context_page(struct drm_device *dev) 1951 { 1952 struct drm_i915_gem_object *ctx; 1953 int ret; 1954 1955 DRM_LOCK_ASSERT(dev); 1956 1957 ctx = i915_gem_alloc_object(dev, 4096); 1958 if (!ctx) { 1959 DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); 1960 return NULL; 1961 } 1962 1963 ret = i915_gem_object_pin(ctx, 4096, true); 1964 if (ret) { 1965 DRM_ERROR("failed to pin power context: %d\n", ret); 1966 goto err_unref; 1967 } 1968 1969 ret = i915_gem_object_set_to_gtt_domain(ctx, 1); 1970 if (ret) { 1971 DRM_ERROR("failed to set-domain on power context: %d\n", ret); 1972 goto err_unpin; 1973 } 1974 1975 return ctx; 1976 1977 err_unpin: 1978 i915_gem_object_unpin(ctx); 1979 err_unref: 1980 drm_gem_object_unreference(&ctx->base); 1981 DRM_UNLOCK(dev); 1982 return NULL; 1983 } 1984 1985 /** 1986 * Lock protecting IPS related data structures 1987 */ 1988 struct lock mchdev_lock; 1989 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE); 1990 1991 /* Global for IPS driver to get at the current i915 device. Protected by 1992 * mchdev_lock. */ 1993 struct drm_i915_private *i915_mch_dev; 1994 1995 bool ironlake_set_drps(struct drm_device *dev, u8 val) 1996 { 1997 struct drm_i915_private *dev_priv = dev->dev_private; 1998 u16 rgvswctl; 1999 2000 rgvswctl = I915_READ16(MEMSWCTL); 2001 if (rgvswctl & MEMCTL_CMD_STS) { 2002 DRM_DEBUG("gpu busy, RCS change rejected\n"); 2003 return false; /* still busy with another command */ 2004 } 2005 2006 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 2007 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 2008 I915_WRITE16(MEMSWCTL, rgvswctl); 2009 POSTING_READ16(MEMSWCTL); 2010 2011 rgvswctl |= MEMCTL_CMD_STS; 2012 I915_WRITE16(MEMSWCTL, rgvswctl); 2013 2014 return true; 2015 } 2016 2017 void ironlake_enable_drps(struct drm_device *dev) 2018 { 2019 struct drm_i915_private *dev_priv = dev->dev_private; 2020 u32 rgvmodectl = I915_READ(MEMMODECTL); 2021 u8 fmax, fmin, fstart, vstart; 2022 2023 /* Enable temp reporting */ 2024 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 2025 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 2026 2027 /* 100ms RC evaluation intervals */ 2028 I915_WRITE(RCUPEI, 100000); 2029 I915_WRITE(RCDNEI, 100000); 2030 2031 /* Set max/min thresholds to 90ms and 80ms respectively */ 2032 I915_WRITE(RCBMAXAVG, 90000); 2033 I915_WRITE(RCBMINAVG, 80000); 2034 2035 I915_WRITE(MEMIHYST, 1); 2036 2037 /* Set up min, max, and cur for interrupt handling */ 2038 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 2039 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 2040 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 2041 MEMMODE_FSTART_SHIFT; 2042 2043 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> 2044 PXVFREQ_PX_SHIFT; 2045 2046 dev_priv->fmax = fmax; /* IPS callback will increase this */ 2047 dev_priv->fstart = fstart; 2048 2049 dev_priv->rps.max_delay = fstart; 2050 dev_priv->rps.min_delay = fmin; 2051 dev_priv->rps.cur_delay = fstart; 2052 2053 DRM_DEBUG("fmax: %d, fmin: %d, fstart: %d\n", 2054 fmax, fmin, fstart); 2055 2056 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 2057 2058 /* 2059 * Interrupts will be enabled in ironlake_irq_postinstall 2060 */ 2061 2062 I915_WRITE(VIDSTART, vstart); 2063 POSTING_READ(VIDSTART); 2064 2065 rgvmodectl |= MEMMODE_SWMODE_EN; 2066 I915_WRITE(MEMMODECTL, rgvmodectl); 2067 2068 if (_intel_wait_for(dev, 2069 (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10, 2070 1, "915per")) 2071 DRM_ERROR("stuck trying to change perf mode\n"); 2072 DELAY(1000); 2073 2074 ironlake_set_drps(dev, fstart); 2075 2076 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + 2077 I915_READ(0x112e0); 2078 dev_priv->last_time1 = jiffies_to_msecs(jiffies); 2079 dev_priv->last_count2 = I915_READ(0x112f4); 2080 nanotime(&dev_priv->last_time2); 2081 } 2082 2083 void ironlake_disable_drps(struct drm_device *dev) 2084 { 2085 struct drm_i915_private *dev_priv = dev->dev_private; 2086 u16 rgvswctl = I915_READ16(MEMSWCTL); 2087 2088 /* Ack interrupts, disable EFC interrupt */ 2089 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 2090 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 2091 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 2092 I915_WRITE(DEIIR, DE_PCU_EVENT); 2093 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 2094 2095 /* Go back to the starting frequency */ 2096 ironlake_set_drps(dev, dev_priv->fstart); 2097 DELAY(1000); 2098 rgvswctl |= MEMCTL_CMD_STS; 2099 I915_WRITE(MEMSWCTL, rgvswctl); 2100 DELAY(1000); 2101 2102 } 2103 2104 void gen6_set_rps(struct drm_device *dev, u8 val) 2105 { 2106 struct drm_i915_private *dev_priv = dev->dev_private; 2107 u32 swreq; 2108 2109 swreq = (val & 0x3ff) << 25; 2110 I915_WRITE(GEN6_RPNSWREQ, swreq); 2111 } 2112 2113 void gen6_disable_rps(struct drm_device *dev) 2114 { 2115 struct drm_i915_private *dev_priv = dev->dev_private; 2116 2117 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 2118 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 2119 I915_WRITE(GEN6_PMIER, 0); 2120 /* Complete PM interrupt masking here doesn't race with the rps work 2121 * item again unmasking PM interrupts because that is using a different 2122 * register (PMIMR) to mask PM interrupts. The only risk is in leaving 2123 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ 2124 2125 spin_lock(&dev_priv->rps.lock); 2126 dev_priv->rps.pm_iir = 0; 2127 spin_unlock(&dev_priv->rps.lock); 2128 2129 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 2130 } 2131 2132 static unsigned long intel_pxfreq(u32 vidfreq) 2133 { 2134 unsigned long freq; 2135 int div = (vidfreq & 0x3f0000) >> 16; 2136 int post = (vidfreq & 0x3000) >> 12; 2137 int pre = (vidfreq & 0x7); 2138 2139 if (!pre) 2140 return 0; 2141 2142 freq = ((div * 133333) / ((1<<post) * pre)); 2143 2144 return freq; 2145 } 2146 2147 static const struct cparams { 2148 u16 i; 2149 u16 t; 2150 u16 m; 2151 u16 c; 2152 } cparams[] = { 2153 { 1, 1333, 301, 28664 }, 2154 { 1, 1066, 294, 24460 }, 2155 { 1, 800, 294, 25192 }, 2156 { 0, 1333, 276, 27605 }, 2157 { 0, 1066, 276, 27605 }, 2158 { 0, 800, 231, 23784 }, 2159 }; 2160 2161 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 2162 { 2163 u64 total_count, diff, ret; 2164 u32 count1, count2, count3, m = 0, c = 0; 2165 unsigned long now = jiffies_to_msecs(jiffies), diff1; 2166 int i; 2167 2168 diff1 = now - dev_priv->last_time1; 2169 /* 2170 * sysctl(8) reads the value of sysctl twice in rapid 2171 * succession. There is high chance that it happens in the 2172 * same timer tick. Use the cached value to not divide by 2173 * zero and give the hw a chance to gather more samples. 2174 */ 2175 if (diff1 <= 10) 2176 return (dev_priv->chipset_power); 2177 2178 count1 = I915_READ(DMIEC); 2179 count2 = I915_READ(DDREC); 2180 count3 = I915_READ(CSIEC); 2181 2182 total_count = count1 + count2 + count3; 2183 2184 /* FIXME: handle per-counter overflow */ 2185 if (total_count < dev_priv->last_count1) { 2186 diff = ~0UL - dev_priv->last_count1; 2187 diff += total_count; 2188 } else { 2189 diff = total_count - dev_priv->last_count1; 2190 } 2191 2192 for (i = 0; i < DRM_ARRAY_SIZE(cparams); i++) { 2193 if (cparams[i].i == dev_priv->c_m && 2194 cparams[i].t == dev_priv->r_t) { 2195 m = cparams[i].m; 2196 c = cparams[i].c; 2197 break; 2198 } 2199 } 2200 2201 diff = diff / diff1; 2202 ret = ((m * diff) + c); 2203 ret = ret / 10; 2204 2205 dev_priv->last_count1 = total_count; 2206 dev_priv->last_time1 = now; 2207 2208 dev_priv->chipset_power = ret; 2209 return (ret); 2210 } 2211 2212 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 2213 { 2214 unsigned long m, x, b; 2215 u32 tsfs; 2216 2217 tsfs = I915_READ(TSFS); 2218 2219 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 2220 x = I915_READ8(TR1); 2221 2222 b = tsfs & TSFS_INTR_MASK; 2223 2224 return ((m * x) / 127) - b; 2225 } 2226 2227 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 2228 { 2229 static const struct v_table { 2230 u16 vd; /* in .1 mil */ 2231 u16 vm; /* in .1 mil */ 2232 } v_table[] = { 2233 { 0, 0, }, 2234 { 375, 0, }, 2235 { 500, 0, }, 2236 { 625, 0, }, 2237 { 750, 0, }, 2238 { 875, 0, }, 2239 { 1000, 0, }, 2240 { 1125, 0, }, 2241 { 4125, 3000, }, 2242 { 4125, 3000, }, 2243 { 4125, 3000, }, 2244 { 4125, 3000, }, 2245 { 4125, 3000, }, 2246 { 4125, 3000, }, 2247 { 4125, 3000, }, 2248 { 4125, 3000, }, 2249 { 4125, 3000, }, 2250 { 4125, 3000, }, 2251 { 4125, 3000, }, 2252 { 4125, 3000, }, 2253 { 4125, 3000, }, 2254 { 4125, 3000, }, 2255 { 4125, 3000, }, 2256 { 4125, 3000, }, 2257 { 4125, 3000, }, 2258 { 4125, 3000, }, 2259 { 4125, 3000, }, 2260 { 4125, 3000, }, 2261 { 4125, 3000, }, 2262 { 4125, 3000, }, 2263 { 4125, 3000, }, 2264 { 4125, 3000, }, 2265 { 4250, 3125, }, 2266 { 4375, 3250, }, 2267 { 4500, 3375, }, 2268 { 4625, 3500, }, 2269 { 4750, 3625, }, 2270 { 4875, 3750, }, 2271 { 5000, 3875, }, 2272 { 5125, 4000, }, 2273 { 5250, 4125, }, 2274 { 5375, 4250, }, 2275 { 5500, 4375, }, 2276 { 5625, 4500, }, 2277 { 5750, 4625, }, 2278 { 5875, 4750, }, 2279 { 6000, 4875, }, 2280 { 6125, 5000, }, 2281 { 6250, 5125, }, 2282 { 6375, 5250, }, 2283 { 6500, 5375, }, 2284 { 6625, 5500, }, 2285 { 6750, 5625, }, 2286 { 6875, 5750, }, 2287 { 7000, 5875, }, 2288 { 7125, 6000, }, 2289 { 7250, 6125, }, 2290 { 7375, 6250, }, 2291 { 7500, 6375, }, 2292 { 7625, 6500, }, 2293 { 7750, 6625, }, 2294 { 7875, 6750, }, 2295 { 8000, 6875, }, 2296 { 8125, 7000, }, 2297 { 8250, 7125, }, 2298 { 8375, 7250, }, 2299 { 8500, 7375, }, 2300 { 8625, 7500, }, 2301 { 8750, 7625, }, 2302 { 8875, 7750, }, 2303 { 9000, 7875, }, 2304 { 9125, 8000, }, 2305 { 9250, 8125, }, 2306 { 9375, 8250, }, 2307 { 9500, 8375, }, 2308 { 9625, 8500, }, 2309 { 9750, 8625, }, 2310 { 9875, 8750, }, 2311 { 10000, 8875, }, 2312 { 10125, 9000, }, 2313 { 10250, 9125, }, 2314 { 10375, 9250, }, 2315 { 10500, 9375, }, 2316 { 10625, 9500, }, 2317 { 10750, 9625, }, 2318 { 10875, 9750, }, 2319 { 11000, 9875, }, 2320 { 11125, 10000, }, 2321 { 11250, 10125, }, 2322 { 11375, 10250, }, 2323 { 11500, 10375, }, 2324 { 11625, 10500, }, 2325 { 11750, 10625, }, 2326 { 11875, 10750, }, 2327 { 12000, 10875, }, 2328 { 12125, 11000, }, 2329 { 12250, 11125, }, 2330 { 12375, 11250, }, 2331 { 12500, 11375, }, 2332 { 12625, 11500, }, 2333 { 12750, 11625, }, 2334 { 12875, 11750, }, 2335 { 13000, 11875, }, 2336 { 13125, 12000, }, 2337 { 13250, 12125, }, 2338 { 13375, 12250, }, 2339 { 13500, 12375, }, 2340 { 13625, 12500, }, 2341 { 13750, 12625, }, 2342 { 13875, 12750, }, 2343 { 14000, 12875, }, 2344 { 14125, 13000, }, 2345 { 14250, 13125, }, 2346 { 14375, 13250, }, 2347 { 14500, 13375, }, 2348 { 14625, 13500, }, 2349 { 14750, 13625, }, 2350 { 14875, 13750, }, 2351 { 15000, 13875, }, 2352 { 15125, 14000, }, 2353 { 15250, 14125, }, 2354 { 15375, 14250, }, 2355 { 15500, 14375, }, 2356 { 15625, 14500, }, 2357 { 15750, 14625, }, 2358 { 15875, 14750, }, 2359 { 16000, 14875, }, 2360 { 16125, 15000, }, 2361 }; 2362 if (dev_priv->info->is_mobile) 2363 return v_table[pxvid].vm; 2364 else 2365 return v_table[pxvid].vd; 2366 } 2367 2368 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 2369 { 2370 struct timespec now, diff1; 2371 u64 diff; 2372 unsigned long diffms; 2373 u32 count; 2374 2375 if (dev_priv->info->gen != 5) 2376 return; 2377 2378 nanotime(&now); 2379 diff1 = now; 2380 timespecsub(&diff1, &dev_priv->last_time2); 2381 2382 /* Don't divide by 0 */ 2383 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; 2384 if (!diffms) 2385 return; 2386 2387 count = I915_READ(GFXEC); 2388 2389 if (count < dev_priv->last_count2) { 2390 diff = ~0UL - dev_priv->last_count2; 2391 diff += count; 2392 } else { 2393 diff = count - dev_priv->last_count2; 2394 } 2395 2396 dev_priv->last_count2 = count; 2397 dev_priv->last_time2 = now; 2398 2399 /* More magic constants... */ 2400 diff = diff * 1181; 2401 diff = diff / (diffms * 10); 2402 dev_priv->gfx_power = diff; 2403 } 2404 2405 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 2406 { 2407 unsigned long t, corr, state1, corr2, state2; 2408 u32 pxvid, ext_v; 2409 2410 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); 2411 pxvid = (pxvid >> 24) & 0x7f; 2412 ext_v = pvid_to_extvid(dev_priv, pxvid); 2413 2414 state1 = ext_v; 2415 2416 t = i915_mch_val(dev_priv); 2417 2418 /* Revel in the empirically derived constants */ 2419 2420 /* Correction factor in 1/100000 units */ 2421 if (t > 80) 2422 corr = ((t * 2349) + 135940); 2423 else if (t >= 50) 2424 corr = ((t * 964) + 29317); 2425 else /* < 50 */ 2426 corr = ((t * 301) + 1004); 2427 2428 corr = corr * ((150142 * state1) / 10000 - 78642); 2429 corr /= 100000; 2430 corr2 = (corr * dev_priv->corr); 2431 2432 state2 = (corr2 * state1) / 10000; 2433 state2 /= 100; /* convert to mW */ 2434 2435 i915_update_gfx_val(dev_priv); 2436 2437 return dev_priv->gfx_power + state2; 2438 } 2439 2440 /** 2441 * i915_read_mch_val - return value for IPS use 2442 * 2443 * Calculate and return a value for the IPS driver to use when deciding whether 2444 * we have thermal and power headroom to increase CPU or GPU power budget. 2445 */ 2446 unsigned long i915_read_mch_val(void) 2447 { 2448 struct drm_i915_private *dev_priv; 2449 unsigned long chipset_val, graphics_val, ret = 0; 2450 2451 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2452 if (!i915_mch_dev) 2453 goto out_unlock; 2454 dev_priv = i915_mch_dev; 2455 2456 chipset_val = i915_chipset_val(dev_priv); 2457 graphics_val = i915_gfx_val(dev_priv); 2458 2459 ret = chipset_val + graphics_val; 2460 2461 out_unlock: 2462 lockmgr(&mchdev_lock, LK_RELEASE); 2463 2464 return ret; 2465 } 2466 2467 /** 2468 * i915_gpu_raise - raise GPU frequency limit 2469 * 2470 * Raise the limit; IPS indicates we have thermal headroom. 2471 */ 2472 bool i915_gpu_raise(void) 2473 { 2474 struct drm_i915_private *dev_priv; 2475 bool ret = true; 2476 2477 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2478 if (!i915_mch_dev) { 2479 ret = false; 2480 goto out_unlock; 2481 } 2482 dev_priv = i915_mch_dev; 2483 2484 if (dev_priv->rps.max_delay > dev_priv->fmax) 2485 dev_priv->rps.max_delay--; 2486 2487 out_unlock: 2488 lockmgr(&mchdev_lock, LK_RELEASE); 2489 2490 return ret; 2491 } 2492 2493 /** 2494 * i915_gpu_lower - lower GPU frequency limit 2495 * 2496 * IPS indicates we're close to a thermal limit, so throttle back the GPU 2497 * frequency maximum. 2498 */ 2499 bool i915_gpu_lower(void) 2500 { 2501 struct drm_i915_private *dev_priv; 2502 bool ret = true; 2503 2504 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2505 if (!i915_mch_dev) { 2506 ret = false; 2507 goto out_unlock; 2508 } 2509 dev_priv = i915_mch_dev; 2510 2511 if (dev_priv->rps.max_delay < dev_priv->rps.min_delay) 2512 dev_priv->rps.max_delay++; 2513 2514 out_unlock: 2515 lockmgr(&mchdev_lock, LK_RELEASE); 2516 2517 return ret; 2518 } 2519 2520 /** 2521 * i915_gpu_busy - indicate GPU business to IPS 2522 * 2523 * Tell the IPS driver whether or not the GPU is busy. 2524 */ 2525 bool i915_gpu_busy(void) 2526 { 2527 struct drm_i915_private *dev_priv; 2528 bool ret = false; 2529 2530 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2531 if (!i915_mch_dev) 2532 goto out_unlock; 2533 dev_priv = i915_mch_dev; 2534 2535 ret = dev_priv->busy; 2536 2537 out_unlock: 2538 lockmgr(&mchdev_lock, LK_RELEASE); 2539 2540 return ret; 2541 } 2542 2543 /** 2544 * i915_gpu_turbo_disable - disable graphics turbo 2545 * 2546 * Disable graphics turbo by resetting the max frequency and setting the 2547 * current frequency to the default. 2548 */ 2549 bool i915_gpu_turbo_disable(void) 2550 { 2551 struct drm_i915_private *dev_priv; 2552 bool ret = true; 2553 2554 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 2555 if (!i915_mch_dev) { 2556 ret = false; 2557 goto out_unlock; 2558 } 2559 dev_priv = i915_mch_dev; 2560 2561 dev_priv->rps.max_delay = dev_priv->fstart; 2562 2563 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart)) 2564 ret = false; 2565 2566 out_unlock: 2567 lockmgr(&mchdev_lock, LK_RELEASE); 2568 2569 return ret; 2570 } 2571 2572 void intel_init_emon(struct drm_device *dev) 2573 { 2574 struct drm_i915_private *dev_priv = dev->dev_private; 2575 u32 lcfuse; 2576 u8 pxw[16]; 2577 int i; 2578 2579 /* Disable to program */ 2580 I915_WRITE(ECR, 0); 2581 POSTING_READ(ECR); 2582 2583 /* Program energy weights for various events */ 2584 I915_WRITE(SDEW, 0x15040d00); 2585 I915_WRITE(CSIEW0, 0x007f0000); 2586 I915_WRITE(CSIEW1, 0x1e220004); 2587 I915_WRITE(CSIEW2, 0x04000004); 2588 2589 for (i = 0; i < 5; i++) 2590 I915_WRITE(PEW + (i * 4), 0); 2591 for (i = 0; i < 3; i++) 2592 I915_WRITE(DEW + (i * 4), 0); 2593 2594 /* Program P-state weights to account for frequency power adjustment */ 2595 for (i = 0; i < 16; i++) { 2596 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); 2597 unsigned long freq = intel_pxfreq(pxvidfreq); 2598 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 2599 PXVFREQ_PX_SHIFT; 2600 unsigned long val; 2601 2602 val = vid * vid; 2603 val *= (freq / 1000); 2604 val *= 255; 2605 val /= (127*127*900); 2606 if (val > 0xff) 2607 DRM_ERROR("bad pxval: %ld\n", val); 2608 pxw[i] = val; 2609 } 2610 /* Render standby states get 0 weight */ 2611 pxw[14] = 0; 2612 pxw[15] = 0; 2613 2614 for (i = 0; i < 4; i++) { 2615 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 2616 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 2617 I915_WRITE(PXW + (i * 4), val); 2618 } 2619 2620 /* Adjust magic regs to magic values (more experimental results) */ 2621 I915_WRITE(OGW0, 0); 2622 I915_WRITE(OGW1, 0); 2623 I915_WRITE(EG0, 0x00007f00); 2624 I915_WRITE(EG1, 0x0000000e); 2625 I915_WRITE(EG2, 0x000e0000); 2626 I915_WRITE(EG3, 0x68000300); 2627 I915_WRITE(EG4, 0x42000000); 2628 I915_WRITE(EG5, 0x00140031); 2629 I915_WRITE(EG6, 0); 2630 I915_WRITE(EG7, 0); 2631 2632 for (i = 0; i < 8; i++) 2633 I915_WRITE(PXWL + (i * 4), 0); 2634 2635 /* Enable PMON + select events */ 2636 I915_WRITE(ECR, 0x80000019); 2637 2638 lcfuse = I915_READ(LCFUSE02); 2639 2640 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); 2641 } 2642 2643 void intel_disable_gt_powersave(struct drm_device *dev) 2644 { 2645 struct drm_i915_private *dev_priv = dev->dev_private; 2646 2647 if (IS_IRONLAKE_M(dev)) { 2648 ironlake_disable_drps(dev); 2649 ironlake_disable_rc6(dev); 2650 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { 2651 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); 2652 lockmgr(&dev_priv->rps.hw_lock, LK_EXCLUSIVE); 2653 gen6_disable_rps(dev); 2654 lockmgr(&dev_priv->rps.hw_lock, LK_RELEASE); 2655 } 2656 } 2657 2658 static int intel_enable_rc6(struct drm_device *dev) 2659 { 2660 /* 2661 * Respect the kernel parameter if it is set 2662 */ 2663 if (i915_enable_rc6 >= 0) 2664 return i915_enable_rc6; 2665 2666 /* 2667 * Disable RC6 on Ironlake 2668 */ 2669 if (INTEL_INFO(dev)->gen == 5) 2670 return 0; 2671 2672 /* 2673 * Enable rc6 on Sandybridge if DMA remapping is disabled 2674 */ 2675 if (INTEL_INFO(dev)->gen == 6) { 2676 DRM_DEBUG_DRIVER( 2677 "Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n", 2678 intel_iommu_enabled ? "true" : "false", 2679 !intel_iommu_enabled ? "en" : "dis"); 2680 return (intel_iommu_enabled ? 0 : INTEL_RC6_ENABLE); 2681 } 2682 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); 2683 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 2684 } 2685 2686 void gen6_enable_rps(struct drm_i915_private *dev_priv) 2687 { 2688 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 2689 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 2690 u32 pcu_mbox, rc6_mask = 0; 2691 u32 gtfifodbg; 2692 int cur_freq, min_freq, max_freq; 2693 int rc6_mode; 2694 int i; 2695 2696 /* Here begins a magic sequence of register writes to enable 2697 * auto-downclocking. 2698 * 2699 * Perhaps there might be some value in exposing these to 2700 * userspace... 2701 */ 2702 I915_WRITE(GEN6_RC_STATE, 0); 2703 2704 /* Clear the DBG now so we don't confuse earlier errors */ 2705 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 2706 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 2707 I915_WRITE(GTFIFODBG, gtfifodbg); 2708 } 2709 2710 gen6_gt_force_wake_get(dev_priv); 2711 2712 /* disable the counters and set deterministic thresholds */ 2713 I915_WRITE(GEN6_RC_CONTROL, 0); 2714 2715 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 2716 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 2717 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 2718 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 2719 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 2720 2721 for (i = 0; i < I915_NUM_RINGS; i++) 2722 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10); 2723 2724 I915_WRITE(GEN6_RC_SLEEP, 0); 2725 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 2726 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 2727 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); 2728 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 2729 2730 rc6_mode = intel_enable_rc6(dev_priv->dev); 2731 if (rc6_mode & INTEL_RC6_ENABLE) 2732 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 2733 2734 if (rc6_mode & INTEL_RC6p_ENABLE) 2735 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 2736 2737 if (rc6_mode & INTEL_RC6pp_ENABLE) 2738 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 2739 2740 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", 2741 (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off", 2742 (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off", 2743 (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off"); 2744 2745 I915_WRITE(GEN6_RC_CONTROL, 2746 rc6_mask | 2747 GEN6_RC_CTL_EI_MODE(1) | 2748 GEN6_RC_CTL_HW_ENABLE); 2749 2750 I915_WRITE(GEN6_RPNSWREQ, 2751 GEN6_FREQUENCY(10) | 2752 GEN6_OFFSET(0) | 2753 GEN6_AGGRESSIVE_TURBO); 2754 I915_WRITE(GEN6_RC_VIDEO_FREQ, 2755 GEN6_FREQUENCY(12)); 2756 2757 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 2758 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 2759 18 << 24 | 2760 6 << 16); 2761 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000); 2762 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000); 2763 I915_WRITE(GEN6_RP_UP_EI, 100000); 2764 I915_WRITE(GEN6_RP_DOWN_EI, 5000000); 2765 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 2766 I915_WRITE(GEN6_RP_CONTROL, 2767 GEN6_RP_MEDIA_TURBO | 2768 GEN6_RP_MEDIA_HW_MODE | 2769 GEN6_RP_MEDIA_IS_GFX | 2770 GEN6_RP_ENABLE | 2771 GEN6_RP_UP_BUSY_AVG | 2772 GEN6_RP_DOWN_IDLE_CONT); 2773 2774 if (_intel_wait_for(dev, 2775 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500, 2776 1, "915pr1")) 2777 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); 2778 2779 I915_WRITE(GEN6_PCODE_DATA, 0); 2780 I915_WRITE(GEN6_PCODE_MAILBOX, 2781 GEN6_PCODE_READY | 2782 GEN6_PCODE_WRITE_MIN_FREQ_TABLE); 2783 if (_intel_wait_for(dev, 2784 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500, 2785 1, "915pr2")) 2786 DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); 2787 2788 min_freq = (rp_state_cap & 0xff0000) >> 16; 2789 max_freq = rp_state_cap & 0xff; 2790 cur_freq = (gt_perf_status & 0xff00) >> 8; 2791 2792 /* Check for overclock support */ 2793 if (_intel_wait_for(dev, 2794 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500, 2795 1, "915pr3")) 2796 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n"); 2797 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS); 2798 pcu_mbox = I915_READ(GEN6_PCODE_DATA); 2799 if (_intel_wait_for(dev, 2800 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 500, 2801 1, "915pr4")) 2802 DRM_ERROR("timeout waiting for pcode mailbox to finish\n"); 2803 if (pcu_mbox & (1<<31)) { /* OC supported */ 2804 max_freq = pcu_mbox & 0xff; 2805 DRM_DEBUG("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50); 2806 } 2807 2808 /* In units of 100MHz */ 2809 dev_priv->rps.max_delay = max_freq; 2810 dev_priv->rps.min_delay = min_freq; 2811 dev_priv->rps.cur_delay = cur_freq; 2812 2813 /* requires MSI enabled */ 2814 I915_WRITE(GEN6_PMIER, 2815 GEN6_PM_MBOX_EVENT | 2816 GEN6_PM_THERMAL_EVENT | 2817 GEN6_PM_RP_DOWN_TIMEOUT | 2818 GEN6_PM_RP_UP_THRESHOLD | 2819 GEN6_PM_RP_DOWN_THRESHOLD | 2820 GEN6_PM_RP_UP_EI_EXPIRED | 2821 GEN6_PM_RP_DOWN_EI_EXPIRED); 2822 spin_lock(&dev_priv->rps.lock); 2823 WARN_ON(dev_priv->rps.pm_iir != 0); 2824 I915_WRITE(GEN6_PMIMR, 0); 2825 spin_unlock(&dev_priv->rps.lock); 2826 /* enable all PM interrupts */ 2827 I915_WRITE(GEN6_PMINTRMSK, 0); 2828 2829 gen6_gt_force_wake_put(dev_priv); 2830 } 2831 2832 void gen6_update_ring_freq(struct drm_i915_private *dev_priv) 2833 { 2834 struct drm_device *dev; 2835 int min_freq = 15; 2836 int gpu_freq, ia_freq, max_ia_freq; 2837 int scaling_factor = 180; 2838 uint64_t tsc_freq; 2839 2840 dev = dev_priv->dev; 2841 #if 0 2842 max_ia_freq = cpufreq_quick_get_max(0); 2843 /* 2844 * Default to measured freq if none found, PCU will ensure we don't go 2845 * over 2846 */ 2847 if (!max_ia_freq) 2848 max_ia_freq = tsc_freq; 2849 2850 /* Convert from Hz to MHz */ 2851 max_ia_freq /= 1000; 2852 #else 2853 tsc_freq = atomic_load_acq_64(&tsc_freq); 2854 max_ia_freq = tsc_freq / 1000 / 1000; 2855 #endif 2856 2857 DRM_LOCK(dev); 2858 2859 /* 2860 * For each potential GPU frequency, load a ring frequency we'd like 2861 * to use for memory access. We do this by specifying the IA frequency 2862 * the PCU should use as a reference to determine the ring frequency. 2863 */ 2864 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; 2865 gpu_freq--) { 2866 int diff = dev_priv->rps.max_delay - gpu_freq; 2867 int d; 2868 2869 /* 2870 * For GPU frequencies less than 750MHz, just use the lowest 2871 * ring freq. 2872 */ 2873 if (gpu_freq < min_freq) 2874 ia_freq = 800; 2875 else 2876 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 2877 d = 100; 2878 ia_freq = (ia_freq + d / 2) / d; 2879 2880 I915_WRITE(GEN6_PCODE_DATA, 2881 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) | 2882 gpu_freq); 2883 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | 2884 GEN6_PCODE_WRITE_MIN_FREQ_TABLE); 2885 if (_intel_wait_for(dev, 2886 (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 2887 10, 1, "915frq")) { 2888 DRM_ERROR("pcode write of freq table timed out\n"); 2889 continue; 2890 } 2891 } 2892 2893 DRM_UNLOCK(dev); 2894 } 2895 2896 void ironlake_init_clock_gating(struct drm_device *dev) 2897 { 2898 struct drm_i915_private *dev_priv = dev->dev_private; 2899 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 2900 2901 /* Required for FBC */ 2902 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 2903 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 2904 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 2905 2906 I915_WRITE(PCH_3DCGDIS0, 2907 MARIUNIT_CLOCK_GATE_DISABLE | 2908 SVSMUNIT_CLOCK_GATE_DISABLE); 2909 I915_WRITE(PCH_3DCGDIS1, 2910 VFMUNIT_CLOCK_GATE_DISABLE); 2911 2912 /* 2913 * According to the spec the following bits should be set in 2914 * order to enable memory self-refresh 2915 * The bit 22/21 of 0x42004 2916 * The bit 5 of 0x42020 2917 * The bit 15 of 0x45000 2918 */ 2919 I915_WRITE(ILK_DISPLAY_CHICKEN2, 2920 (I915_READ(ILK_DISPLAY_CHICKEN2) | 2921 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 2922 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 2923 I915_WRITE(DISP_ARB_CTL, 2924 (I915_READ(DISP_ARB_CTL) | 2925 DISP_FBC_WM_DIS)); 2926 I915_WRITE(WM3_LP_ILK, 0); 2927 I915_WRITE(WM2_LP_ILK, 0); 2928 I915_WRITE(WM1_LP_ILK, 0); 2929 2930 /* 2931 * Based on the document from hardware guys the following bits 2932 * should be set unconditionally in order to enable FBC. 2933 * The bit 22 of 0x42000 2934 * The bit 22 of 0x42004 2935 * The bit 7,8,9 of 0x42020. 2936 */ 2937 if (IS_IRONLAKE_M(dev)) { 2938 I915_WRITE(ILK_DISPLAY_CHICKEN1, 2939 I915_READ(ILK_DISPLAY_CHICKEN1) | 2940 ILK_FBCQ_DIS); 2941 I915_WRITE(ILK_DISPLAY_CHICKEN2, 2942 I915_READ(ILK_DISPLAY_CHICKEN2) | 2943 ILK_DPARB_GATE); 2944 } 2945 2946 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 2947 2948 I915_WRITE(ILK_DISPLAY_CHICKEN2, 2949 I915_READ(ILK_DISPLAY_CHICKEN2) | 2950 ILK_ELPIN_409_SELECT); 2951 I915_WRITE(_3D_CHICKEN2, 2952 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 2953 _3D_CHICKEN2_WM_READ_PIPELINED); 2954 2955 /* WaDisableRenderCachePipelinedFlush */ 2956 I915_WRITE(CACHE_MODE_0, 2957 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 2958 2959 ibx_init_clock_gating(dev); 2960 } 2961 2962 void cpt_init_clock_gating(struct drm_device *dev) 2963 { 2964 struct drm_i915_private *dev_priv = dev->dev_private; 2965 int pipe; 2966 2967 /* 2968 * On Ibex Peak and Cougar Point, we need to disable clock 2969 * gating for the panel power sequencer or it will fail to 2970 * start up when no ports are active. 2971 */ 2972 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 2973 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 2974 DPLS_EDP_PPS_FIX_DIS); 2975 /* The below fixes the weird display corruption, a few pixels shifted 2976 * downward, on (only) LVDS of some HP laptops with IVY. 2977 */ 2978 for_each_pipe(pipe) 2979 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE); 2980 /* WADP0ClockGatingDisable */ 2981 for_each_pipe(pipe) { 2982 I915_WRITE(TRANS_CHICKEN1(pipe), 2983 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 2984 } 2985 } 2986 2987 void gen6_init_clock_gating(struct drm_device *dev) 2988 { 2989 struct drm_i915_private *dev_priv = dev->dev_private; 2990 int pipe; 2991 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 2992 2993 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 2994 2995 I915_WRITE(ILK_DISPLAY_CHICKEN2, 2996 I915_READ(ILK_DISPLAY_CHICKEN2) | 2997 ILK_ELPIN_409_SELECT); 2998 2999 /* WaDisableHiZPlanesWhenMSAAEnabled */ 3000 I915_WRITE(_3D_CHICKEN, 3001 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 3002 3003 /* WaSetupGtModeTdRowDispatch */ 3004 if (IS_SNB_GT1(dev)) 3005 I915_WRITE(GEN6_GT_MODE, 3006 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); 3007 3008 I915_WRITE(WM3_LP_ILK, 0); 3009 I915_WRITE(WM2_LP_ILK, 0); 3010 I915_WRITE(WM1_LP_ILK, 0); 3011 3012 I915_WRITE(CACHE_MODE_0, 3013 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 3014 3015 I915_WRITE(GEN6_UCGCTL1, 3016 I915_READ(GEN6_UCGCTL1) | 3017 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 3018 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 3019 3020 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 3021 * gating disable must be set. Failure to set it results in 3022 * flickering pixels due to Z write ordering failures after 3023 * some amount of runtime in the Mesa "fire" demo, and Unigine 3024 * Sanctuary and Tropics, and apparently anything else with 3025 * alpha test or pixel discard. 3026 * 3027 * According to the spec, bit 11 (RCCUNIT) must also be set, 3028 * but we didn't debug actual testcases to find it out. 3029 * 3030 * Also apply WaDisableVDSUnitClockGating and 3031 * WaDisableRCPBUnitClockGating. 3032 */ 3033 I915_WRITE(GEN6_UCGCTL2, 3034 GEN7_VDSUNIT_CLOCK_GATE_DISABLE | 3035 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 3036 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 3037 3038 /* Bspec says we need to always set all mask bits. */ 3039 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | 3040 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); 3041 3042 /* 3043 * According to the spec the following bits should be 3044 * set in order to enable memory self-refresh and fbc: 3045 * The bit21 and bit22 of 0x42000 3046 * The bit21 and bit22 of 0x42004 3047 * The bit5 and bit7 of 0x42020 3048 * The bit14 of 0x70180 3049 * The bit14 of 0x71180 3050 */ 3051 I915_WRITE(ILK_DISPLAY_CHICKEN1, 3052 I915_READ(ILK_DISPLAY_CHICKEN1) | 3053 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 3054 I915_WRITE(ILK_DISPLAY_CHICKEN2, 3055 I915_READ(ILK_DISPLAY_CHICKEN2) | 3056 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 3057 I915_WRITE(ILK_DSPCLK_GATE_D, 3058 I915_READ(ILK_DSPCLK_GATE_D) | 3059 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 3060 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 3061 3062 /* WaMbcDriverBootEnable */ 3063 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | 3064 GEN6_MBCTL_ENABLE_BOOT_FETCH); 3065 3066 for_each_pipe(pipe) { 3067 I915_WRITE(DSPCNTR(pipe), 3068 I915_READ(DSPCNTR(pipe)) | 3069 DISPPLANE_TRICKLE_FEED_DISABLE); 3070 intel_flush_display_plane(dev_priv, pipe); 3071 } 3072 3073 /* The default value should be 0x200 according to docs, but the two 3074 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ 3075 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); 3076 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); 3077 3078 cpt_init_clock_gating(dev); 3079 } 3080 3081 void ivybridge_init_clock_gating(struct drm_device *dev) 3082 { 3083 struct drm_i915_private *dev_priv = dev->dev_private; 3084 int pipe; 3085 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE; 3086 3087 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 3088 3089 I915_WRITE(WM3_LP_ILK, 0); 3090 I915_WRITE(WM2_LP_ILK, 0); 3091 I915_WRITE(WM1_LP_ILK, 0); 3092 3093 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. 3094 * This implements the WaDisableRCZUnitClockGating workaround. 3095 */ 3096 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 3097 3098 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 3099 3100 I915_WRITE(IVB_CHICKEN3, 3101 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 3102 CHICKEN3_DGMG_DONE_FIX_DISABLE); 3103 3104 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ 3105 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 3106 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 3107 3108 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */ 3109 I915_WRITE(GEN7_L3CNTLREG1, 3110 GEN7_WA_FOR_GEN7_L3_CONTROL); 3111 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 3112 GEN7_WA_L3_CHICKEN_MODE); 3113 3114 /* This is required by WaCatErrorRejectionIssue */ 3115 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 3116 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 3117 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 3118 3119 for_each_pipe(pipe) { 3120 I915_WRITE(DSPCNTR(pipe), 3121 I915_READ(DSPCNTR(pipe)) | 3122 DISPPLANE_TRICKLE_FEED_DISABLE); 3123 intel_flush_display_plane(dev_priv, pipe); 3124 } 3125 } 3126 3127 void g4x_init_clock_gating(struct drm_device *dev) 3128 { 3129 struct drm_i915_private *dev_priv = dev->dev_private; 3130 uint32_t dspclk_gate; 3131 3132 I915_WRITE(RENCLK_GATE_D1, 0); 3133 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 3134 GS_UNIT_CLOCK_GATE_DISABLE | 3135 CL_UNIT_CLOCK_GATE_DISABLE); 3136 I915_WRITE(RAMCLK_GATE_D, 0); 3137 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 3138 OVRUNIT_CLOCK_GATE_DISABLE | 3139 OVCUNIT_CLOCK_GATE_DISABLE; 3140 if (IS_GM45(dev)) 3141 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 3142 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 3143 } 3144 3145 void crestline_init_clock_gating(struct drm_device *dev) 3146 { 3147 struct drm_i915_private *dev_priv = dev->dev_private; 3148 3149 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 3150 I915_WRITE(RENCLK_GATE_D2, 0); 3151 I915_WRITE(DSPCLK_GATE_D, 0); 3152 I915_WRITE(RAMCLK_GATE_D, 0); 3153 I915_WRITE16(DEUC, 0); 3154 } 3155 3156 void broadwater_init_clock_gating(struct drm_device *dev) 3157 { 3158 struct drm_i915_private *dev_priv = dev->dev_private; 3159 3160 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 3161 I965_RCC_CLOCK_GATE_DISABLE | 3162 I965_RCPB_CLOCK_GATE_DISABLE | 3163 I965_ISC_CLOCK_GATE_DISABLE | 3164 I965_FBC_CLOCK_GATE_DISABLE); 3165 I915_WRITE(RENCLK_GATE_D2, 0); 3166 } 3167 3168 void gen3_init_clock_gating(struct drm_device *dev) 3169 { 3170 struct drm_i915_private *dev_priv = dev->dev_private; 3171 u32 dstate = I915_READ(D_STATE); 3172 3173 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 3174 DSTATE_DOT_CLOCK_GATING; 3175 I915_WRITE(D_STATE, dstate); 3176 } 3177 3178 void i85x_init_clock_gating(struct drm_device *dev) 3179 { 3180 struct drm_i915_private *dev_priv = dev->dev_private; 3181 3182 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 3183 } 3184 3185 void i830_init_clock_gating(struct drm_device *dev) 3186 { 3187 struct drm_i915_private *dev_priv = dev->dev_private; 3188 3189 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 3190 } 3191 3192 void ibx_init_clock_gating(struct drm_device *dev) 3193 { 3194 struct drm_i915_private *dev_priv = dev->dev_private; 3195 3196 /* 3197 * On Ibex Peak and Cougar Point, we need to disable clock 3198 * gating for the panel power sequencer or it will fail to 3199 * start up when no ports are active. 3200 */ 3201 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 3202 } 3203 3204 static void ironlake_teardown_rc6(struct drm_device *dev) 3205 { 3206 struct drm_i915_private *dev_priv = dev->dev_private; 3207 3208 if (dev_priv->renderctx) { 3209 i915_gem_object_unpin(dev_priv->renderctx); 3210 drm_gem_object_unreference(&dev_priv->renderctx->base); 3211 dev_priv->renderctx = NULL; 3212 } 3213 3214 if (dev_priv->pwrctx) { 3215 i915_gem_object_unpin(dev_priv->pwrctx); 3216 drm_gem_object_unreference(&dev_priv->pwrctx->base); 3217 dev_priv->pwrctx = NULL; 3218 } 3219 } 3220 3221 void ironlake_disable_rc6(struct drm_device *dev) 3222 { 3223 struct drm_i915_private *dev_priv = dev->dev_private; 3224 3225 if (I915_READ(PWRCTXA)) { 3226 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ 3227 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); 3228 (void)_intel_wait_for(dev, 3229 ((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), 3230 50, 1, "915pro"); 3231 3232 I915_WRITE(PWRCTXA, 0); 3233 POSTING_READ(PWRCTXA); 3234 3235 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 3236 POSTING_READ(RSTDBYCTL); 3237 } 3238 3239 ironlake_teardown_rc6(dev); 3240 } 3241 3242 static int ironlake_setup_rc6(struct drm_device *dev) 3243 { 3244 struct drm_i915_private *dev_priv = dev->dev_private; 3245 3246 if (dev_priv->renderctx == NULL) 3247 dev_priv->renderctx = intel_alloc_context_page(dev); 3248 if (!dev_priv->renderctx) 3249 return -ENOMEM; 3250 3251 if (dev_priv->pwrctx == NULL) 3252 dev_priv->pwrctx = intel_alloc_context_page(dev); 3253 if (!dev_priv->pwrctx) { 3254 ironlake_teardown_rc6(dev); 3255 return -ENOMEM; 3256 } 3257 3258 return 0; 3259 } 3260 3261 void ironlake_enable_rc6(struct drm_device *dev) 3262 { 3263 struct drm_i915_private *dev_priv = dev->dev_private; 3264 int ret; 3265 3266 /* rc6 disabled by default due to repeated reports of hanging during 3267 * boot and resume. 3268 */ 3269 if (!intel_enable_rc6(dev)) 3270 return; 3271 3272 DRM_LOCK(dev); 3273 ret = ironlake_setup_rc6(dev); 3274 if (ret) { 3275 DRM_UNLOCK(dev); 3276 return; 3277 } 3278 3279 /* 3280 * GPU can automatically power down the render unit if given a page 3281 * to save state. 3282 */ 3283 ret = BEGIN_LP_RING(6); 3284 if (ret) { 3285 ironlake_teardown_rc6(dev); 3286 DRM_UNLOCK(dev); 3287 return; 3288 } 3289 3290 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); 3291 OUT_RING(MI_SET_CONTEXT); 3292 OUT_RING(dev_priv->renderctx->gtt_offset | 3293 MI_MM_SPACE_GTT | 3294 MI_SAVE_EXT_STATE_EN | 3295 MI_RESTORE_EXT_STATE_EN | 3296 MI_RESTORE_INHIBIT); 3297 OUT_RING(MI_SUSPEND_FLUSH); 3298 OUT_RING(MI_NOOP); 3299 OUT_RING(MI_FLUSH); 3300 ADVANCE_LP_RING(); 3301 3302 /* 3303 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW 3304 * does an implicit flush, combined with MI_FLUSH above, it should be 3305 * safe to assume that renderctx is valid 3306 */ 3307 ret = intel_wait_ring_idle(LP_RING(dev_priv)); 3308 if (ret) { 3309 DRM_ERROR("failed to enable ironlake power savings\n"); 3310 ironlake_teardown_rc6(dev); 3311 DRM_UNLOCK(dev); 3312 return; 3313 } 3314 3315 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); 3316 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); 3317 DRM_UNLOCK(dev); 3318 } 3319 3320 void intel_init_clock_gating(struct drm_device *dev) 3321 { 3322 struct drm_i915_private *dev_priv = dev->dev_private; 3323 3324 dev_priv->display.init_clock_gating(dev); 3325 3326 if (dev_priv->display.init_pch_clock_gating) 3327 dev_priv->display.init_pch_clock_gating(dev); 3328 } 3329 3330 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) 3331 { 3332 u32 gt_thread_status_mask; 3333 3334 if (IS_HASWELL(dev_priv->dev)) 3335 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; 3336 else 3337 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; 3338 3339 /* w/a for a sporadic read returning 0 by waiting for the GT 3340 * thread to wake up. 3341 */ 3342 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) 3343 DRM_ERROR("GT thread status wait timed out\n"); 3344 } 3345 3346 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) 3347 { 3348 I915_WRITE_NOTRACE(FORCEWAKE, 0); 3349 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 3350 } 3351 3352 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 3353 { 3354 u32 forcewake_ack; 3355 3356 if (IS_HASWELL(dev_priv->dev)) 3357 forcewake_ack = FORCEWAKE_ACK_HSW; 3358 else 3359 forcewake_ack = FORCEWAKE_ACK; 3360 3361 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0, 3362 FORCEWAKE_ACK_TIMEOUT_MS)) 3363 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 3364 3365 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL); 3366 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ 3367 3368 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1), 3369 FORCEWAKE_ACK_TIMEOUT_MS)) 3370 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 3371 3372 __gen6_gt_wait_for_thread_c0(dev_priv); 3373 } 3374 3375 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) 3376 { 3377 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); 3378 /* something from same cacheline, but !FORCEWAKE_MT */ 3379 POSTING_READ(ECOBUS); 3380 } 3381 3382 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) 3383 { 3384 int count; 3385 3386 count = 0; 3387 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) 3388 DELAY(10); 3389 3390 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1); 3391 POSTING_READ(FORCEWAKE_MT); 3392 3393 count = 0; 3394 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) 3395 DELAY(10); 3396 } 3397 3398 /* 3399 * Generally this is called implicitly by the register read function. However, 3400 * if some sequence requires the GT to not power down then this function should 3401 * be called at the beginning of the sequence followed by a call to 3402 * gen6_gt_force_wake_put() at the end of the sequence. 3403 */ 3404 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 3405 { 3406 3407 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); 3408 if (dev_priv->forcewake_count++ == 0) 3409 dev_priv->gt.force_wake_get(dev_priv); 3410 lockmgr(&dev_priv->gt_lock, LK_RELEASE); 3411 } 3412 3413 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) 3414 { 3415 u32 gtfifodbg; 3416 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); 3417 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, 3418 "MMIO read or write has been dropped %x\n", gtfifodbg)) 3419 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); 3420 } 3421 3422 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 3423 { 3424 I915_WRITE_NOTRACE(FORCEWAKE, 0); 3425 /* something from same cacheline, but !FORCEWAKE */ 3426 POSTING_READ(ECOBUS); 3427 gen6_gt_check_fifodbg(dev_priv); 3428 } 3429 3430 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 3431 { 3432 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 3433 /* something from same cacheline, but !FORCEWAKE_MT */ 3434 POSTING_READ(ECOBUS); 3435 gen6_gt_check_fifodbg(dev_priv); 3436 } 3437 3438 /* 3439 * see gen6_gt_force_wake_get() 3440 */ 3441 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 3442 { 3443 lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE); 3444 if (--dev_priv->forcewake_count == 0) 3445 dev_priv->gt.force_wake_put(dev_priv); 3446 lockmgr(&dev_priv->gt_lock, LK_RELEASE); 3447 } 3448 3449 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) 3450 { 3451 int ret = 0; 3452 3453 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 3454 int loop = 500; 3455 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 3456 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 3457 udelay(10); 3458 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); 3459 } 3460 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) { 3461 kprintf("%s loop\n", __func__); 3462 ++ret; 3463 } 3464 dev_priv->gt_fifo_count = fifo; 3465 } 3466 dev_priv->gt_fifo_count--; 3467 3468 return ret; 3469 } 3470 3471 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) 3472 { 3473 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); 3474 /* something from same cacheline, but !FORCEWAKE_VLV */ 3475 POSTING_READ(FORCEWAKE_ACK_VLV); 3476 } 3477 3478 static void vlv_force_wake_get(struct drm_i915_private *dev_priv) 3479 { 3480 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0, 3481 FORCEWAKE_ACK_TIMEOUT_MS)) 3482 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 3483 3484 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 3485 3486 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 3487 FORCEWAKE_ACK_TIMEOUT_MS)) 3488 DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); 3489 3490 __gen6_gt_wait_for_thread_c0(dev_priv); 3491 } 3492 3493 static void vlv_force_wake_put(struct drm_i915_private *dev_priv) 3494 { 3495 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 3496 /* something from same cacheline, but !FORCEWAKE_VLV */ 3497 POSTING_READ(FORCEWAKE_ACK_VLV); 3498 gen6_gt_check_fifodbg(dev_priv); 3499 } 3500 3501 void intel_gt_reset(struct drm_device *dev) 3502 { 3503 struct drm_i915_private *dev_priv = dev->dev_private; 3504 3505 if (IS_VALLEYVIEW(dev)) { 3506 vlv_force_wake_reset(dev_priv); 3507 } else if (INTEL_INFO(dev)->gen >= 6) { 3508 __gen6_gt_force_wake_reset(dev_priv); 3509 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 3510 __gen6_gt_force_wake_mt_reset(dev_priv); 3511 } 3512 } 3513 3514 void intel_gt_init(struct drm_device *dev) 3515 { 3516 struct drm_i915_private *dev_priv = dev->dev_private; 3517 3518 lockinit(&dev_priv->gt_lock, "915gt", 0, LK_CANRECURSE); 3519 3520 intel_gt_reset(dev); 3521 3522 if (IS_VALLEYVIEW(dev)) { 3523 dev_priv->gt.force_wake_get = vlv_force_wake_get; 3524 dev_priv->gt.force_wake_put = vlv_force_wake_put; 3525 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 3526 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; 3527 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; 3528 } else if (IS_GEN6(dev)) { 3529 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; 3530 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; 3531 } 3532 #if 0 3533 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 3534 intel_gen6_powersave_work); 3535 #endif 3536 } 3537