1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <linux/module.h> 31 #include <machine/clock.h> 32 33 /** 34 * DOC: RC6 35 * 36 * RC6 is a special power stage which allows the GPU to enter an very 37 * low-voltage mode when idle, using down to 0V while at this stage. This 38 * stage is entered automatically when the GPU is idle when RC6 support is 39 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 40 * 41 * There are different RC6 modes available in Intel GPU, which differentiate 42 * among each other with the latency required to enter and leave RC6 and 43 * voltage consumed by the GPU in different states. 44 * 45 * The combination of the following flags define which states GPU is allowed 46 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 47 * RC6pp is deepest RC6. Their support by hardware varies according to the 48 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 49 * which brings the most power savings; deeper states save more power, but 50 * require higher latency to switch to and wake up. 51 */ 52 #define INTEL_RC6_ENABLE (1<<0) 53 #define INTEL_RC6p_ENABLE (1<<1) 54 #define INTEL_RC6pp_ENABLE (1<<2) 55 56 static void bxt_init_clock_gating(struct drm_device *dev) 57 { 58 struct drm_i915_private *dev_priv = dev->dev_private; 59 60 /* WaDisableSDEUnitClockGating:bxt */ 61 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 62 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 63 64 /* 65 * FIXME: 66 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 67 */ 68 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 69 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 70 71 /* 72 * Wa: Backlight PWM may stop in the asserted state, causing backlight 73 * to stay fully on. 74 */ 75 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) 76 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | 77 PWM1_GATING_DIS | PWM2_GATING_DIS); 78 } 79 80 static void i915_pineview_get_mem_freq(struct drm_device *dev) 81 { 82 struct drm_i915_private *dev_priv = dev->dev_private; 83 u32 tmp; 84 85 tmp = I915_READ(CLKCFG); 86 87 switch (tmp & CLKCFG_FSB_MASK) { 88 case CLKCFG_FSB_533: 89 dev_priv->fsb_freq = 533; /* 133*4 */ 90 break; 91 case CLKCFG_FSB_800: 92 dev_priv->fsb_freq = 800; /* 200*4 */ 93 break; 94 case CLKCFG_FSB_667: 95 dev_priv->fsb_freq = 667; /* 167*4 */ 96 break; 97 case CLKCFG_FSB_400: 98 dev_priv->fsb_freq = 400; /* 100*4 */ 99 break; 100 } 101 102 switch (tmp & CLKCFG_MEM_MASK) { 103 case CLKCFG_MEM_533: 104 dev_priv->mem_freq = 533; 105 break; 106 case CLKCFG_MEM_667: 107 dev_priv->mem_freq = 667; 108 break; 109 case CLKCFG_MEM_800: 110 dev_priv->mem_freq = 800; 111 break; 112 } 113 114 /* detect pineview DDR3 setting */ 115 tmp = I915_READ(CSHRDDR3CTL); 116 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 117 } 118 119 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 120 { 121 struct drm_i915_private *dev_priv = dev->dev_private; 122 u16 ddrpll, csipll; 123 124 ddrpll = I915_READ16(DDRMPLL1); 125 csipll = I915_READ16(CSIPLL0); 126 127 switch (ddrpll & 0xff) { 128 case 0xc: 129 dev_priv->mem_freq = 800; 130 break; 131 case 0x10: 132 dev_priv->mem_freq = 1066; 133 break; 134 case 0x14: 135 dev_priv->mem_freq = 1333; 136 break; 137 case 0x18: 138 dev_priv->mem_freq = 1600; 139 break; 140 default: 141 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 142 ddrpll & 0xff); 143 dev_priv->mem_freq = 0; 144 break; 145 } 146 147 dev_priv->ips.r_t = dev_priv->mem_freq; 148 149 switch (csipll & 0x3ff) { 150 case 0x00c: 151 dev_priv->fsb_freq = 3200; 152 break; 153 case 0x00e: 154 dev_priv->fsb_freq = 3733; 155 break; 156 case 0x010: 157 dev_priv->fsb_freq = 4266; 158 break; 159 case 0x012: 160 dev_priv->fsb_freq = 4800; 161 break; 162 case 0x014: 163 dev_priv->fsb_freq = 5333; 164 break; 165 case 0x016: 166 dev_priv->fsb_freq = 5866; 167 break; 168 case 0x018: 169 dev_priv->fsb_freq = 6400; 170 break; 171 default: 172 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 173 csipll & 0x3ff); 174 dev_priv->fsb_freq = 0; 175 break; 176 } 177 178 if (dev_priv->fsb_freq == 3200) { 179 dev_priv->ips.c_m = 0; 180 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 181 dev_priv->ips.c_m = 1; 182 } else { 183 dev_priv->ips.c_m = 2; 184 } 185 } 186 187 static const struct cxsr_latency cxsr_latency_table[] = { 188 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 189 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 190 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 191 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 192 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 193 194 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 195 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 196 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 197 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 198 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 199 200 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 201 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 202 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 203 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 204 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 205 206 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 207 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 208 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 209 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 210 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 211 212 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 213 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 214 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 215 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 216 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 217 218 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 219 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 220 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 221 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 222 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 223 }; 224 225 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 226 int is_ddr3, 227 int fsb, 228 int mem) 229 { 230 const struct cxsr_latency *latency; 231 int i; 232 233 if (fsb == 0 || mem == 0) 234 return NULL; 235 236 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 237 latency = &cxsr_latency_table[i]; 238 if (is_desktop == latency->is_desktop && 239 is_ddr3 == latency->is_ddr3 && 240 fsb == latency->fsb_freq && mem == latency->mem_freq) 241 return latency; 242 } 243 244 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 245 246 return NULL; 247 } 248 249 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) 250 { 251 u32 val; 252 253 mutex_lock(&dev_priv->rps.hw_lock); 254 255 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 256 if (enable) 257 val &= ~FORCE_DDR_HIGH_FREQ; 258 else 259 val |= FORCE_DDR_HIGH_FREQ; 260 val &= ~FORCE_DDR_LOW_FREQ; 261 val |= FORCE_DDR_FREQ_REQ_ACK; 262 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 263 264 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 265 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) 266 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); 267 268 mutex_unlock(&dev_priv->rps.hw_lock); 269 } 270 271 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 272 { 273 u32 val; 274 275 mutex_lock(&dev_priv->rps.hw_lock); 276 277 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 278 if (enable) 279 val |= DSP_MAXFIFO_PM5_ENABLE; 280 else 281 val &= ~DSP_MAXFIFO_PM5_ENABLE; 282 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 283 284 mutex_unlock(&dev_priv->rps.hw_lock); 285 } 286 287 #define FW_WM(value, plane) \ 288 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) 289 290 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 291 { 292 struct drm_device *dev = dev_priv->dev; 293 u32 val; 294 295 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 296 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); 297 POSTING_READ(FW_BLC_SELF_VLV); 298 dev_priv->wm.vlv.cxsr = enable; 299 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { 300 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); 301 POSTING_READ(FW_BLC_SELF); 302 } else if (IS_PINEVIEW(dev)) { 303 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; 304 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; 305 I915_WRITE(DSPFW3, val); 306 POSTING_READ(DSPFW3); 307 } else if (IS_I945G(dev) || IS_I945GM(dev)) { 308 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : 309 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); 310 I915_WRITE(FW_BLC_SELF, val); 311 POSTING_READ(FW_BLC_SELF); 312 } else if (IS_I915GM(dev)) { 313 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : 314 _MASKED_BIT_DISABLE(INSTPM_SELF_EN); 315 I915_WRITE(INSTPM, val); 316 POSTING_READ(INSTPM); 317 } else { 318 return; 319 } 320 321 DRM_DEBUG_KMS("memory self-refresh is %s\n", 322 enable ? "enabled" : "disabled"); 323 } 324 325 326 /* 327 * Latency for FIFO fetches is dependent on several factors: 328 * - memory configuration (speed, channels) 329 * - chipset 330 * - current MCH state 331 * It can be fairly high in some situations, so here we assume a fairly 332 * pessimal value. It's a tradeoff between extra memory fetches (if we 333 * set this value too high, the FIFO will fetch frequently to stay full) 334 * and power consumption (set it too low to save power and we might see 335 * FIFO underruns and display "flicker"). 336 * 337 * A value of 5us seems to be a good balance; safe for very low end 338 * platforms but not overly aggressive on lower latency configs. 339 */ 340 static const int pessimal_latency_ns = 5000; 341 342 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ 343 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) 344 345 static int vlv_get_fifo_size(struct drm_device *dev, 346 enum i915_pipe pipe, int plane) 347 { 348 struct drm_i915_private *dev_priv = dev->dev_private; 349 int sprite0_start, sprite1_start, size; 350 351 switch (pipe) { 352 uint32_t dsparb, dsparb2, dsparb3; 353 case PIPE_A: 354 dsparb = I915_READ(DSPARB); 355 dsparb2 = I915_READ(DSPARB2); 356 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); 357 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); 358 break; 359 case PIPE_B: 360 dsparb = I915_READ(DSPARB); 361 dsparb2 = I915_READ(DSPARB2); 362 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); 363 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); 364 break; 365 case PIPE_C: 366 dsparb2 = I915_READ(DSPARB2); 367 dsparb3 = I915_READ(DSPARB3); 368 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); 369 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); 370 break; 371 default: 372 return 0; 373 } 374 375 switch (plane) { 376 case 0: 377 size = sprite0_start; 378 break; 379 case 1: 380 size = sprite1_start - sprite0_start; 381 break; 382 case 2: 383 size = 512 - 1 - sprite1_start; 384 break; 385 default: 386 return 0; 387 } 388 389 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", 390 pipe_name(pipe), plane == 0 ? "primary" : "sprite", 391 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), 392 size); 393 394 return size; 395 } 396 397 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 398 { 399 struct drm_i915_private *dev_priv = dev->dev_private; 400 uint32_t dsparb = I915_READ(DSPARB); 401 int size; 402 403 size = dsparb & 0x7f; 404 if (plane) 405 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 406 407 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 408 plane ? "B" : "A", size); 409 410 return size; 411 } 412 413 static int i830_get_fifo_size(struct drm_device *dev, int plane) 414 { 415 struct drm_i915_private *dev_priv = dev->dev_private; 416 uint32_t dsparb = I915_READ(DSPARB); 417 int size; 418 419 size = dsparb & 0x1ff; 420 if (plane) 421 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 422 size >>= 1; /* Convert to cachelines */ 423 424 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 425 plane ? "B" : "A", size); 426 427 return size; 428 } 429 430 static int i845_get_fifo_size(struct drm_device *dev, int plane) 431 { 432 struct drm_i915_private *dev_priv = dev->dev_private; 433 uint32_t dsparb = I915_READ(DSPARB); 434 int size; 435 436 size = dsparb & 0x7f; 437 size >>= 2; /* Convert to cachelines */ 438 439 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 440 plane ? "B" : "A", 441 size); 442 443 return size; 444 } 445 446 /* Pineview has different values for various configs */ 447 static const struct intel_watermark_params pineview_display_wm = { 448 .fifo_size = PINEVIEW_DISPLAY_FIFO, 449 .max_wm = PINEVIEW_MAX_WM, 450 .default_wm = PINEVIEW_DFT_WM, 451 .guard_size = PINEVIEW_GUARD_WM, 452 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 453 }; 454 static const struct intel_watermark_params pineview_display_hplloff_wm = { 455 .fifo_size = PINEVIEW_DISPLAY_FIFO, 456 .max_wm = PINEVIEW_MAX_WM, 457 .default_wm = PINEVIEW_DFT_HPLLOFF_WM, 458 .guard_size = PINEVIEW_GUARD_WM, 459 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 460 }; 461 static const struct intel_watermark_params pineview_cursor_wm = { 462 .fifo_size = PINEVIEW_CURSOR_FIFO, 463 .max_wm = PINEVIEW_CURSOR_MAX_WM, 464 .default_wm = PINEVIEW_CURSOR_DFT_WM, 465 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 466 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 467 }; 468 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 469 .fifo_size = PINEVIEW_CURSOR_FIFO, 470 .max_wm = PINEVIEW_CURSOR_MAX_WM, 471 .default_wm = PINEVIEW_CURSOR_DFT_WM, 472 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 473 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 474 }; 475 static const struct intel_watermark_params g4x_wm_info = { 476 .fifo_size = G4X_FIFO_SIZE, 477 .max_wm = G4X_MAX_WM, 478 .default_wm = G4X_MAX_WM, 479 .guard_size = 2, 480 .cacheline_size = G4X_FIFO_LINE_SIZE, 481 }; 482 static const struct intel_watermark_params g4x_cursor_wm_info = { 483 .fifo_size = I965_CURSOR_FIFO, 484 .max_wm = I965_CURSOR_MAX_WM, 485 .default_wm = I965_CURSOR_DFT_WM, 486 .guard_size = 2, 487 .cacheline_size = G4X_FIFO_LINE_SIZE, 488 }; 489 static const struct intel_watermark_params valleyview_wm_info = { 490 .fifo_size = VALLEYVIEW_FIFO_SIZE, 491 .max_wm = VALLEYVIEW_MAX_WM, 492 .default_wm = VALLEYVIEW_MAX_WM, 493 .guard_size = 2, 494 .cacheline_size = G4X_FIFO_LINE_SIZE, 495 }; 496 static const struct intel_watermark_params valleyview_cursor_wm_info = { 497 .fifo_size = I965_CURSOR_FIFO, 498 .max_wm = VALLEYVIEW_CURSOR_MAX_WM, 499 .default_wm = I965_CURSOR_DFT_WM, 500 .guard_size = 2, 501 .cacheline_size = G4X_FIFO_LINE_SIZE, 502 }; 503 static const struct intel_watermark_params i965_cursor_wm_info = { 504 .fifo_size = I965_CURSOR_FIFO, 505 .max_wm = I965_CURSOR_MAX_WM, 506 .default_wm = I965_CURSOR_DFT_WM, 507 .guard_size = 2, 508 .cacheline_size = I915_FIFO_LINE_SIZE, 509 }; 510 static const struct intel_watermark_params i945_wm_info = { 511 .fifo_size = I945_FIFO_SIZE, 512 .max_wm = I915_MAX_WM, 513 .default_wm = 1, 514 .guard_size = 2, 515 .cacheline_size = I915_FIFO_LINE_SIZE, 516 }; 517 static const struct intel_watermark_params i915_wm_info = { 518 .fifo_size = I915_FIFO_SIZE, 519 .max_wm = I915_MAX_WM, 520 .default_wm = 1, 521 .guard_size = 2, 522 .cacheline_size = I915_FIFO_LINE_SIZE, 523 }; 524 static const struct intel_watermark_params i830_a_wm_info = { 525 .fifo_size = I855GM_FIFO_SIZE, 526 .max_wm = I915_MAX_WM, 527 .default_wm = 1, 528 .guard_size = 2, 529 .cacheline_size = I830_FIFO_LINE_SIZE, 530 }; 531 static const struct intel_watermark_params i830_bc_wm_info = { 532 .fifo_size = I855GM_FIFO_SIZE, 533 .max_wm = I915_MAX_WM/2, 534 .default_wm = 1, 535 .guard_size = 2, 536 .cacheline_size = I830_FIFO_LINE_SIZE, 537 }; 538 static const struct intel_watermark_params i845_wm_info = { 539 .fifo_size = I830_FIFO_SIZE, 540 .max_wm = I915_MAX_WM, 541 .default_wm = 1, 542 .guard_size = 2, 543 .cacheline_size = I830_FIFO_LINE_SIZE, 544 }; 545 546 /** 547 * intel_calculate_wm - calculate watermark level 548 * @clock_in_khz: pixel clock 549 * @wm: chip FIFO params 550 * @cpp: bytes per pixel 551 * @latency_ns: memory latency for the platform 552 * 553 * Calculate the watermark level (the level at which the display plane will 554 * start fetching from memory again). Each chip has a different display 555 * FIFO size and allocation, so the caller needs to figure that out and pass 556 * in the correct intel_watermark_params structure. 557 * 558 * As the pixel clock runs, the FIFO will be drained at a rate that depends 559 * on the pixel size. When it reaches the watermark level, it'll start 560 * fetching FIFO line sized based chunks from memory until the FIFO fills 561 * past the watermark point. If the FIFO drains completely, a FIFO underrun 562 * will occur, and a display engine hang could result. 563 */ 564 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 565 const struct intel_watermark_params *wm, 566 int fifo_size, int cpp, 567 unsigned long latency_ns) 568 { 569 long entries_required, wm_size; 570 571 /* 572 * Note: we need to make sure we don't overflow for various clock & 573 * latency values. 574 * clocks go from a few thousand to several hundred thousand. 575 * latency is usually a few thousand 576 */ 577 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) / 578 1000; 579 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 580 581 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 582 583 wm_size = fifo_size - (entries_required + wm->guard_size); 584 585 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 586 587 /* Don't promote wm_size to unsigned... */ 588 if (wm_size > (long)wm->max_wm) 589 wm_size = wm->max_wm; 590 if (wm_size <= 0) 591 wm_size = wm->default_wm; 592 593 /* 594 * Bspec seems to indicate that the value shouldn't be lower than 595 * 'burst size + 1'. Certainly 830 is quite unhappy with low values. 596 * Lets go for 8 which is the burst size since certain platforms 597 * already use a hardcoded 8 (which is what the spec says should be 598 * done). 599 */ 600 if (wm_size <= 8) 601 wm_size = 8; 602 603 return wm_size; 604 } 605 606 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 607 { 608 struct drm_crtc *crtc, *enabled = NULL; 609 610 for_each_crtc(dev, crtc) { 611 if (intel_crtc_active(crtc)) { 612 if (enabled) 613 return NULL; 614 enabled = crtc; 615 } 616 } 617 618 return enabled; 619 } 620 621 static void pineview_update_wm(struct drm_crtc *unused_crtc) 622 { 623 struct drm_device *dev = unused_crtc->dev; 624 struct drm_i915_private *dev_priv = dev->dev_private; 625 struct drm_crtc *crtc; 626 const struct cxsr_latency *latency; 627 u32 reg; 628 unsigned long wm; 629 630 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 631 dev_priv->fsb_freq, dev_priv->mem_freq); 632 if (!latency) { 633 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 634 intel_set_memory_cxsr(dev_priv, false); 635 return; 636 } 637 638 crtc = single_enabled_crtc(dev); 639 if (crtc) { 640 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 641 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); 642 int clock = adjusted_mode->crtc_clock; 643 644 /* Display SR */ 645 wm = intel_calculate_wm(clock, &pineview_display_wm, 646 pineview_display_wm.fifo_size, 647 cpp, latency->display_sr); 648 reg = I915_READ(DSPFW1); 649 reg &= ~DSPFW_SR_MASK; 650 reg |= FW_WM(wm, SR); 651 I915_WRITE(DSPFW1, reg); 652 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 653 654 /* cursor SR */ 655 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 656 pineview_display_wm.fifo_size, 657 cpp, latency->cursor_sr); 658 reg = I915_READ(DSPFW3); 659 reg &= ~DSPFW_CURSOR_SR_MASK; 660 reg |= FW_WM(wm, CURSOR_SR); 661 I915_WRITE(DSPFW3, reg); 662 663 /* Display HPLL off SR */ 664 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 665 pineview_display_hplloff_wm.fifo_size, 666 cpp, latency->display_hpll_disable); 667 reg = I915_READ(DSPFW3); 668 reg &= ~DSPFW_HPLL_SR_MASK; 669 reg |= FW_WM(wm, HPLL_SR); 670 I915_WRITE(DSPFW3, reg); 671 672 /* cursor HPLL off SR */ 673 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 674 pineview_display_hplloff_wm.fifo_size, 675 cpp, latency->cursor_hpll_disable); 676 reg = I915_READ(DSPFW3); 677 reg &= ~DSPFW_HPLL_CURSOR_MASK; 678 reg |= FW_WM(wm, HPLL_CURSOR); 679 I915_WRITE(DSPFW3, reg); 680 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 681 682 intel_set_memory_cxsr(dev_priv, true); 683 } else { 684 intel_set_memory_cxsr(dev_priv, false); 685 } 686 } 687 688 static bool g4x_compute_wm0(struct drm_device *dev, 689 int plane, 690 const struct intel_watermark_params *display, 691 int display_latency_ns, 692 const struct intel_watermark_params *cursor, 693 int cursor_latency_ns, 694 int *plane_wm, 695 int *cursor_wm) 696 { 697 struct drm_crtc *crtc; 698 const struct drm_display_mode *adjusted_mode; 699 int htotal, hdisplay, clock, cpp; 700 int line_time_us, line_count; 701 int entries, tlb_miss; 702 703 crtc = intel_get_crtc_for_plane(dev, plane); 704 if (!intel_crtc_active(crtc)) { 705 *cursor_wm = cursor->guard_size; 706 *plane_wm = display->guard_size; 707 return false; 708 } 709 710 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 711 clock = adjusted_mode->crtc_clock; 712 htotal = adjusted_mode->crtc_htotal; 713 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 714 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); 715 716 /* Use the small buffer method to calculate plane watermark */ 717 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000; 718 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 719 if (tlb_miss > 0) 720 entries += tlb_miss; 721 entries = DIV_ROUND_UP(entries, display->cacheline_size); 722 *plane_wm = entries + display->guard_size; 723 if (*plane_wm > (int)display->max_wm) 724 *plane_wm = display->max_wm; 725 726 /* Use the large buffer method to calculate cursor watermark */ 727 line_time_us = max(htotal * 1000 / clock, 1); 728 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 729 entries = line_count * crtc->cursor->state->crtc_w * cpp; 730 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 731 if (tlb_miss > 0) 732 entries += tlb_miss; 733 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 734 *cursor_wm = entries + cursor->guard_size; 735 if (*cursor_wm > (int)cursor->max_wm) 736 *cursor_wm = (int)cursor->max_wm; 737 738 return true; 739 } 740 741 /* 742 * Check the wm result. 743 * 744 * If any calculated watermark values is larger than the maximum value that 745 * can be programmed into the associated watermark register, that watermark 746 * must be disabled. 747 */ 748 static bool g4x_check_srwm(struct drm_device *dev, 749 int display_wm, int cursor_wm, 750 const struct intel_watermark_params *display, 751 const struct intel_watermark_params *cursor) 752 { 753 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 754 display_wm, cursor_wm); 755 756 if (display_wm > display->max_wm) { 757 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 758 display_wm, display->max_wm); 759 return false; 760 } 761 762 if (cursor_wm > cursor->max_wm) { 763 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 764 cursor_wm, cursor->max_wm); 765 return false; 766 } 767 768 if (!(display_wm || cursor_wm)) { 769 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 770 return false; 771 } 772 773 return true; 774 } 775 776 static bool g4x_compute_srwm(struct drm_device *dev, 777 int plane, 778 int latency_ns, 779 const struct intel_watermark_params *display, 780 const struct intel_watermark_params *cursor, 781 int *display_wm, int *cursor_wm) 782 { 783 struct drm_crtc *crtc; 784 const struct drm_display_mode *adjusted_mode; 785 int hdisplay, htotal, cpp, clock; 786 unsigned long line_time_us; 787 int line_count, line_size; 788 int small, large; 789 int entries; 790 791 if (!latency_ns) { 792 *display_wm = *cursor_wm = 0; 793 return false; 794 } 795 796 crtc = intel_get_crtc_for_plane(dev, plane); 797 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 798 clock = adjusted_mode->crtc_clock; 799 htotal = adjusted_mode->crtc_htotal; 800 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 801 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); 802 803 line_time_us = max(htotal * 1000 / clock, 1); 804 line_count = (latency_ns / line_time_us + 1000) / 1000; 805 line_size = hdisplay * cpp; 806 807 /* Use the minimum of the small and large buffer method for primary */ 808 small = ((clock * cpp / 1000) * latency_ns) / 1000; 809 large = line_count * line_size; 810 811 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 812 *display_wm = entries + display->guard_size; 813 814 /* calculate the self-refresh watermark for display cursor */ 815 entries = line_count * cpp * crtc->cursor->state->crtc_w; 816 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 817 *cursor_wm = entries + cursor->guard_size; 818 819 return g4x_check_srwm(dev, 820 *display_wm, *cursor_wm, 821 display, cursor); 822 } 823 824 #define FW_WM_VLV(value, plane) \ 825 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) 826 827 static void vlv_write_wm_values(struct intel_crtc *crtc, 828 const struct vlv_wm_values *wm) 829 { 830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 831 enum i915_pipe pipe = crtc->pipe; 832 833 I915_WRITE(VLV_DDL(pipe), 834 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | 835 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | 836 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | 837 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); 838 839 I915_WRITE(DSPFW1, 840 FW_WM(wm->sr.plane, SR) | 841 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | 842 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | 843 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); 844 I915_WRITE(DSPFW2, 845 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | 846 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | 847 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); 848 I915_WRITE(DSPFW3, 849 FW_WM(wm->sr.cursor, CURSOR_SR)); 850 851 if (IS_CHERRYVIEW(dev_priv)) { 852 I915_WRITE(DSPFW7_CHV, 853 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 855 I915_WRITE(DSPFW8_CHV, 856 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | 857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); 858 I915_WRITE(DSPFW9_CHV, 859 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | 860 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); 861 I915_WRITE(DSPHOWM, 862 FW_WM(wm->sr.plane >> 9, SR_HI) | 863 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | 864 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | 865 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | 866 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 867 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 868 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 869 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 870 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 871 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 872 } else { 873 I915_WRITE(DSPFW7, 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 876 I915_WRITE(DSPHOWM, 877 FW_WM(wm->sr.plane >> 9, SR_HI) | 878 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 879 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 880 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 881 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 882 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 883 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 884 } 885 886 /* zero (unused) WM1 watermarks */ 887 I915_WRITE(DSPFW4, 0); 888 I915_WRITE(DSPFW5, 0); 889 I915_WRITE(DSPFW6, 0); 890 I915_WRITE(DSPHOWM1, 0); 891 892 POSTING_READ(DSPFW1); 893 } 894 895 #undef FW_WM_VLV 896 897 enum vlv_wm_level { 898 VLV_WM_LEVEL_PM2, 899 VLV_WM_LEVEL_PM5, 900 VLV_WM_LEVEL_DDR_DVFS, 901 }; 902 903 /* latency must be in 0.1us units. */ 904 static unsigned int vlv_wm_method2(unsigned int pixel_rate, 905 unsigned int pipe_htotal, 906 unsigned int horiz_pixels, 907 unsigned int cpp, 908 unsigned int latency) 909 { 910 unsigned int ret; 911 912 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 913 ret = (ret + 1) * horiz_pixels * cpp; 914 ret = DIV_ROUND_UP(ret, 64); 915 916 return ret; 917 } 918 919 static void vlv_setup_wm_latency(struct drm_device *dev) 920 { 921 struct drm_i915_private *dev_priv = dev->dev_private; 922 923 /* all latencies in usec */ 924 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; 925 926 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; 927 928 if (IS_CHERRYVIEW(dev_priv)) { 929 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; 930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; 931 932 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; 933 } 934 } 935 936 static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 937 struct intel_crtc *crtc, 938 const struct intel_plane_state *state, 939 int level) 940 { 941 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 942 int clock, htotal, cpp, width, wm; 943 944 if (dev_priv->wm.pri_latency[level] == 0) 945 return USHRT_MAX; 946 947 if (!state->visible) 948 return 0; 949 950 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 951 clock = crtc->config->base.adjusted_mode.crtc_clock; 952 htotal = crtc->config->base.adjusted_mode.crtc_htotal; 953 width = crtc->config->pipe_src_w; 954 if (WARN_ON(htotal == 0)) 955 htotal = 1; 956 957 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 958 /* 959 * FIXME the formula gives values that are 960 * too big for the cursor FIFO, and hence we 961 * would never be able to use cursors. For 962 * now just hardcode the watermark. 963 */ 964 wm = 63; 965 } else { 966 wm = vlv_wm_method2(clock, htotal, width, cpp, 967 dev_priv->wm.pri_latency[level] * 10); 968 } 969 970 return min_t(int, wm, USHRT_MAX); 971 } 972 973 static void vlv_compute_fifo(struct intel_crtc *crtc) 974 { 975 struct drm_device *dev = crtc->base.dev; 976 struct vlv_wm_state *wm_state = &crtc->wm_state; 977 struct intel_plane *plane; 978 unsigned int total_rate = 0; 979 const int fifo_size = 512 - 1; 980 int fifo_extra, fifo_left = fifo_size; 981 982 for_each_intel_plane_on_crtc(dev, crtc, plane) { 983 struct intel_plane_state *state = 984 to_intel_plane_state(plane->base.state); 985 986 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 987 continue; 988 989 if (state->visible) { 990 wm_state->num_active_planes++; 991 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); 992 } 993 } 994 995 for_each_intel_plane_on_crtc(dev, crtc, plane) { 996 struct intel_plane_state *state = 997 to_intel_plane_state(plane->base.state); 998 unsigned int rate; 999 1000 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1001 plane->wm.fifo_size = 63; 1002 continue; 1003 } 1004 1005 if (!state->visible) { 1006 plane->wm.fifo_size = 0; 1007 continue; 1008 } 1009 1010 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1011 plane->wm.fifo_size = fifo_size * rate / total_rate; 1012 fifo_left -= plane->wm.fifo_size; 1013 } 1014 1015 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); 1016 1017 /* spread the remainder evenly */ 1018 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1019 int plane_extra; 1020 1021 if (fifo_left == 0) 1022 break; 1023 1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1025 continue; 1026 1027 /* give it all to the first plane if none are active */ 1028 if (plane->wm.fifo_size == 0 && 1029 wm_state->num_active_planes) 1030 continue; 1031 1032 plane_extra = min(fifo_extra, fifo_left); 1033 plane->wm.fifo_size += plane_extra; 1034 fifo_left -= plane_extra; 1035 } 1036 1037 WARN_ON(fifo_left != 0); 1038 } 1039 1040 static void vlv_invert_wms(struct intel_crtc *crtc) 1041 { 1042 struct vlv_wm_state *wm_state = &crtc->wm_state; 1043 int level; 1044 1045 for (level = 0; level < wm_state->num_levels; level++) { 1046 struct drm_device *dev = crtc->base.dev; 1047 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1048 struct intel_plane *plane; 1049 1050 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; 1051 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; 1052 1053 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1054 switch (plane->base.type) { 1055 int sprite; 1056 case DRM_PLANE_TYPE_CURSOR: 1057 wm_state->wm[level].cursor = plane->wm.fifo_size - 1058 wm_state->wm[level].cursor; 1059 break; 1060 case DRM_PLANE_TYPE_PRIMARY: 1061 wm_state->wm[level].primary = plane->wm.fifo_size - 1062 wm_state->wm[level].primary; 1063 break; 1064 case DRM_PLANE_TYPE_OVERLAY: 1065 sprite = plane->plane; 1066 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - 1067 wm_state->wm[level].sprite[sprite]; 1068 break; 1069 } 1070 } 1071 } 1072 } 1073 1074 static void vlv_compute_wm(struct intel_crtc *crtc) 1075 { 1076 struct drm_device *dev = crtc->base.dev; 1077 struct vlv_wm_state *wm_state = &crtc->wm_state; 1078 struct intel_plane *plane; 1079 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1080 int level; 1081 1082 memset(wm_state, 0, sizeof(*wm_state)); 1083 1084 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; 1085 wm_state->num_levels = to_i915(dev)->wm.max_level + 1; 1086 1087 wm_state->num_active_planes = 0; 1088 1089 vlv_compute_fifo(crtc); 1090 1091 if (wm_state->num_active_planes != 1) 1092 wm_state->cxsr = false; 1093 1094 if (wm_state->cxsr) { 1095 for (level = 0; level < wm_state->num_levels; level++) { 1096 wm_state->sr[level].plane = sr_fifo_size; 1097 wm_state->sr[level].cursor = 63; 1098 } 1099 } 1100 1101 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1102 struct intel_plane_state *state = 1103 to_intel_plane_state(plane->base.state); 1104 1105 if (!state->visible) 1106 continue; 1107 1108 /* normal watermarks */ 1109 for (level = 0; level < wm_state->num_levels; level++) { 1110 int wm = vlv_compute_wm_level(plane, crtc, state, level); 1111 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; 1112 1113 /* hack */ 1114 if (WARN_ON(level == 0 && wm > max_wm)) 1115 wm = max_wm; 1116 1117 if (wm > plane->wm.fifo_size) 1118 break; 1119 1120 switch (plane->base.type) { 1121 int sprite; 1122 case DRM_PLANE_TYPE_CURSOR: 1123 wm_state->wm[level].cursor = wm; 1124 break; 1125 case DRM_PLANE_TYPE_PRIMARY: 1126 wm_state->wm[level].primary = wm; 1127 break; 1128 case DRM_PLANE_TYPE_OVERLAY: 1129 sprite = plane->plane; 1130 wm_state->wm[level].sprite[sprite] = wm; 1131 break; 1132 } 1133 } 1134 1135 wm_state->num_levels = level; 1136 1137 if (!wm_state->cxsr) 1138 continue; 1139 1140 /* maxfifo watermarks */ 1141 switch (plane->base.type) { 1142 int sprite, level; 1143 case DRM_PLANE_TYPE_CURSOR: 1144 for (level = 0; level < wm_state->num_levels; level++) 1145 wm_state->sr[level].cursor = 1146 wm_state->wm[level].cursor; 1147 break; 1148 case DRM_PLANE_TYPE_PRIMARY: 1149 for (level = 0; level < wm_state->num_levels; level++) 1150 wm_state->sr[level].plane = 1151 min(wm_state->sr[level].plane, 1152 wm_state->wm[level].primary); 1153 break; 1154 case DRM_PLANE_TYPE_OVERLAY: 1155 sprite = plane->plane; 1156 for (level = 0; level < wm_state->num_levels; level++) 1157 wm_state->sr[level].plane = 1158 min(wm_state->sr[level].plane, 1159 wm_state->wm[level].sprite[sprite]); 1160 break; 1161 } 1162 } 1163 1164 /* clear any (partially) filled invalid levels */ 1165 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { 1166 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); 1167 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); 1168 } 1169 1170 vlv_invert_wms(crtc); 1171 } 1172 1173 #define VLV_FIFO(plane, value) \ 1174 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) 1175 1176 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) 1177 { 1178 struct drm_device *dev = crtc->base.dev; 1179 struct drm_i915_private *dev_priv = to_i915(dev); 1180 struct intel_plane *plane; 1181 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; 1182 1183 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1184 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1185 WARN_ON(plane->wm.fifo_size != 63); 1186 continue; 1187 } 1188 1189 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) 1190 sprite0_start = plane->wm.fifo_size; 1191 else if (plane->plane == 0) 1192 sprite1_start = sprite0_start + plane->wm.fifo_size; 1193 else 1194 fifo_size = sprite1_start + plane->wm.fifo_size; 1195 } 1196 1197 WARN_ON(fifo_size != 512 - 1); 1198 1199 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", 1200 pipe_name(crtc->pipe), sprite0_start, 1201 sprite1_start, fifo_size); 1202 1203 switch (crtc->pipe) { 1204 uint32_t dsparb, dsparb2, dsparb3; 1205 case PIPE_A: 1206 dsparb = I915_READ(DSPARB); 1207 dsparb2 = I915_READ(DSPARB2); 1208 1209 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | 1210 VLV_FIFO(SPRITEB, 0xff)); 1211 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | 1212 VLV_FIFO(SPRITEB, sprite1_start)); 1213 1214 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | 1215 VLV_FIFO(SPRITEB_HI, 0x1)); 1216 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | 1217 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); 1218 1219 I915_WRITE(DSPARB, dsparb); 1220 I915_WRITE(DSPARB2, dsparb2); 1221 break; 1222 case PIPE_B: 1223 dsparb = I915_READ(DSPARB); 1224 dsparb2 = I915_READ(DSPARB2); 1225 1226 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | 1227 VLV_FIFO(SPRITED, 0xff)); 1228 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | 1229 VLV_FIFO(SPRITED, sprite1_start)); 1230 1231 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | 1232 VLV_FIFO(SPRITED_HI, 0xff)); 1233 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | 1234 VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); 1235 1236 I915_WRITE(DSPARB, dsparb); 1237 I915_WRITE(DSPARB2, dsparb2); 1238 break; 1239 case PIPE_C: 1240 dsparb3 = I915_READ(DSPARB3); 1241 dsparb2 = I915_READ(DSPARB2); 1242 1243 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | 1244 VLV_FIFO(SPRITEF, 0xff)); 1245 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | 1246 VLV_FIFO(SPRITEF, sprite1_start)); 1247 1248 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | 1249 VLV_FIFO(SPRITEF_HI, 0xff)); 1250 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | 1251 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); 1252 1253 I915_WRITE(DSPARB3, dsparb3); 1254 I915_WRITE(DSPARB2, dsparb2); 1255 break; 1256 default: 1257 break; 1258 } 1259 } 1260 1261 #undef VLV_FIFO 1262 1263 static void vlv_merge_wm(struct drm_device *dev, 1264 struct vlv_wm_values *wm) 1265 { 1266 struct intel_crtc *crtc; 1267 int num_active_crtcs = 0; 1268 1269 wm->level = to_i915(dev)->wm.max_level; 1270 wm->cxsr = true; 1271 1272 for_each_intel_crtc(dev, crtc) { 1273 const struct vlv_wm_state *wm_state = &crtc->wm_state; 1274 1275 if (!crtc->active) 1276 continue; 1277 1278 if (!wm_state->cxsr) 1279 wm->cxsr = false; 1280 1281 num_active_crtcs++; 1282 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); 1283 } 1284 1285 if (num_active_crtcs != 1) 1286 wm->cxsr = false; 1287 1288 if (num_active_crtcs > 1) 1289 wm->level = VLV_WM_LEVEL_PM2; 1290 1291 for_each_intel_crtc(dev, crtc) { 1292 struct vlv_wm_state *wm_state = &crtc->wm_state; 1293 enum i915_pipe pipe = crtc->pipe; 1294 1295 if (!crtc->active) 1296 continue; 1297 1298 wm->pipe[pipe] = wm_state->wm[wm->level]; 1299 if (wm->cxsr) 1300 wm->sr = wm_state->sr[wm->level]; 1301 1302 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; 1303 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; 1304 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; 1305 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; 1306 } 1307 } 1308 1309 static void vlv_update_wm(struct drm_crtc *crtc) 1310 { 1311 struct drm_device *dev = crtc->dev; 1312 struct drm_i915_private *dev_priv = dev->dev_private; 1313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1314 enum i915_pipe pipe = intel_crtc->pipe; 1315 struct vlv_wm_values wm = {}; 1316 1317 vlv_compute_wm(intel_crtc); 1318 vlv_merge_wm(dev, &wm); 1319 1320 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { 1321 /* FIXME should be part of crtc atomic commit */ 1322 vlv_pipe_set_fifo_size(intel_crtc); 1323 return; 1324 } 1325 1326 if (wm.level < VLV_WM_LEVEL_DDR_DVFS && 1327 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) 1328 chv_set_memory_dvfs(dev_priv, false); 1329 1330 if (wm.level < VLV_WM_LEVEL_PM5 && 1331 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) 1332 chv_set_memory_pm5(dev_priv, false); 1333 1334 if (!wm.cxsr && dev_priv->wm.vlv.cxsr) 1335 intel_set_memory_cxsr(dev_priv, false); 1336 1337 /* FIXME should be part of crtc atomic commit */ 1338 vlv_pipe_set_fifo_size(intel_crtc); 1339 1340 vlv_write_wm_values(intel_crtc, &wm); 1341 1342 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " 1343 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", 1344 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, 1345 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], 1346 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); 1347 1348 if (wm.cxsr && !dev_priv->wm.vlv.cxsr) 1349 intel_set_memory_cxsr(dev_priv, true); 1350 1351 if (wm.level >= VLV_WM_LEVEL_PM5 && 1352 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) 1353 chv_set_memory_pm5(dev_priv, true); 1354 1355 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && 1356 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) 1357 chv_set_memory_dvfs(dev_priv, true); 1358 1359 dev_priv->wm.vlv = wm; 1360 } 1361 1362 #define single_plane_enabled(mask) is_power_of_2(mask) 1363 1364 static void g4x_update_wm(struct drm_crtc *crtc) 1365 { 1366 struct drm_device *dev = crtc->dev; 1367 static const int sr_latency_ns = 12000; 1368 struct drm_i915_private *dev_priv = dev->dev_private; 1369 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1370 int plane_sr, cursor_sr; 1371 unsigned int enabled = 0; 1372 bool cxsr_enabled; 1373 1374 if (g4x_compute_wm0(dev, PIPE_A, 1375 &g4x_wm_info, pessimal_latency_ns, 1376 &g4x_cursor_wm_info, pessimal_latency_ns, 1377 &planea_wm, &cursora_wm)) 1378 enabled |= 1 << PIPE_A; 1379 1380 if (g4x_compute_wm0(dev, PIPE_B, 1381 &g4x_wm_info, pessimal_latency_ns, 1382 &g4x_cursor_wm_info, pessimal_latency_ns, 1383 &planeb_wm, &cursorb_wm)) 1384 enabled |= 1 << PIPE_B; 1385 1386 if (single_plane_enabled(enabled) && 1387 g4x_compute_srwm(dev, ffs(enabled) - 1, 1388 sr_latency_ns, 1389 &g4x_wm_info, 1390 &g4x_cursor_wm_info, 1391 &plane_sr, &cursor_sr)) { 1392 cxsr_enabled = true; 1393 } else { 1394 cxsr_enabled = false; 1395 intel_set_memory_cxsr(dev_priv, false); 1396 plane_sr = cursor_sr = 0; 1397 } 1398 1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " 1400 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1401 planea_wm, cursora_wm, 1402 planeb_wm, cursorb_wm, 1403 plane_sr, cursor_sr); 1404 1405 I915_WRITE(DSPFW1, 1406 FW_WM(plane_sr, SR) | 1407 FW_WM(cursorb_wm, CURSORB) | 1408 FW_WM(planeb_wm, PLANEB) | 1409 FW_WM(planea_wm, PLANEA)); 1410 I915_WRITE(DSPFW2, 1411 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1412 FW_WM(cursora_wm, CURSORA)); 1413 /* HPLL off in SR has some issues on G4x... disable it */ 1414 I915_WRITE(DSPFW3, 1415 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1416 FW_WM(cursor_sr, CURSOR_SR)); 1417 1418 if (cxsr_enabled) 1419 intel_set_memory_cxsr(dev_priv, true); 1420 } 1421 1422 static void i965_update_wm(struct drm_crtc *unused_crtc) 1423 { 1424 struct drm_device *dev = unused_crtc->dev; 1425 struct drm_i915_private *dev_priv = dev->dev_private; 1426 struct drm_crtc *crtc; 1427 int srwm = 1; 1428 int cursor_sr = 16; 1429 bool cxsr_enabled; 1430 1431 /* Calc sr entries for one plane configs */ 1432 crtc = single_enabled_crtc(dev); 1433 if (crtc) { 1434 /* self-refresh has much higher latency */ 1435 static const int sr_latency_ns = 12000; 1436 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1437 int clock = adjusted_mode->crtc_clock; 1438 int htotal = adjusted_mode->crtc_htotal; 1439 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 1440 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); 1441 unsigned long line_time_us; 1442 int entries; 1443 1444 line_time_us = max(htotal * 1000 / clock, 1); 1445 1446 /* Use ns/us then divide to preserve precision */ 1447 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1448 cpp * hdisplay; 1449 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1450 srwm = I965_FIFO_SIZE - entries; 1451 if (srwm < 0) 1452 srwm = 1; 1453 srwm &= 0x1ff; 1454 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1455 entries, srwm); 1456 1457 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1458 cpp * crtc->cursor->state->crtc_w; 1459 entries = DIV_ROUND_UP(entries, 1460 i965_cursor_wm_info.cacheline_size); 1461 cursor_sr = i965_cursor_wm_info.fifo_size - 1462 (entries + i965_cursor_wm_info.guard_size); 1463 1464 if (cursor_sr > i965_cursor_wm_info.max_wm) 1465 cursor_sr = i965_cursor_wm_info.max_wm; 1466 1467 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1468 "cursor %d\n", srwm, cursor_sr); 1469 1470 cxsr_enabled = true; 1471 } else { 1472 cxsr_enabled = false; 1473 /* Turn off self refresh if both pipes are enabled */ 1474 intel_set_memory_cxsr(dev_priv, false); 1475 } 1476 1477 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1478 srwm); 1479 1480 /* 965 has limitations... */ 1481 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | 1482 FW_WM(8, CURSORB) | 1483 FW_WM(8, PLANEB) | 1484 FW_WM(8, PLANEA)); 1485 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | 1486 FW_WM(8, PLANEC_OLD)); 1487 /* update cursor SR watermark */ 1488 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); 1489 1490 if (cxsr_enabled) 1491 intel_set_memory_cxsr(dev_priv, true); 1492 } 1493 1494 #undef FW_WM 1495 1496 static void i9xx_update_wm(struct drm_crtc *unused_crtc) 1497 { 1498 struct drm_device *dev = unused_crtc->dev; 1499 struct drm_i915_private *dev_priv = dev->dev_private; 1500 const struct intel_watermark_params *wm_info; 1501 uint32_t fwater_lo; 1502 uint32_t fwater_hi; 1503 int cwm, srwm = 1; 1504 int fifo_size; 1505 int planea_wm, planeb_wm; 1506 struct drm_crtc *crtc, *enabled = NULL; 1507 1508 if (IS_I945GM(dev)) 1509 wm_info = &i945_wm_info; 1510 else if (!IS_GEN2(dev)) 1511 wm_info = &i915_wm_info; 1512 else 1513 wm_info = &i830_a_wm_info; 1514 1515 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1516 crtc = intel_get_crtc_for_plane(dev, 0); 1517 if (intel_crtc_active(crtc)) { 1518 const struct drm_display_mode *adjusted_mode; 1519 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); 1520 if (IS_GEN2(dev)) 1521 cpp = 4; 1522 1523 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1524 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1525 wm_info, fifo_size, cpp, 1526 pessimal_latency_ns); 1527 enabled = crtc; 1528 } else { 1529 planea_wm = fifo_size - wm_info->guard_size; 1530 if (planea_wm > (long)wm_info->max_wm) 1531 planea_wm = wm_info->max_wm; 1532 } 1533 1534 if (IS_GEN2(dev)) 1535 wm_info = &i830_bc_wm_info; 1536 1537 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1538 crtc = intel_get_crtc_for_plane(dev, 1); 1539 if (intel_crtc_active(crtc)) { 1540 const struct drm_display_mode *adjusted_mode; 1541 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0); 1542 if (IS_GEN2(dev)) 1543 cpp = 4; 1544 1545 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1546 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1547 wm_info, fifo_size, cpp, 1548 pessimal_latency_ns); 1549 if (enabled == NULL) 1550 enabled = crtc; 1551 else 1552 enabled = NULL; 1553 } else { 1554 planeb_wm = fifo_size - wm_info->guard_size; 1555 if (planeb_wm > (long)wm_info->max_wm) 1556 planeb_wm = wm_info->max_wm; 1557 } 1558 1559 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1560 1561 if (IS_I915GM(dev) && enabled) { 1562 struct drm_i915_gem_object *obj; 1563 1564 obj = intel_fb_obj(enabled->primary->state->fb); 1565 1566 /* self-refresh seems busted with untiled */ 1567 if (obj->tiling_mode == I915_TILING_NONE) 1568 enabled = NULL; 1569 } 1570 1571 /* 1572 * Overlay gets an aggressive default since video jitter is bad. 1573 */ 1574 cwm = 2; 1575 1576 /* Play safe and disable self-refresh before adjusting watermarks. */ 1577 intel_set_memory_cxsr(dev_priv, false); 1578 1579 /* Calc sr entries for one plane configs */ 1580 if (HAS_FW_BLC(dev) && enabled) { 1581 /* self-refresh has much higher latency */ 1582 static const int sr_latency_ns = 6000; 1583 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode; 1584 int clock = adjusted_mode->crtc_clock; 1585 int htotal = adjusted_mode->crtc_htotal; 1586 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; 1587 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0); 1588 unsigned long line_time_us; 1589 int entries; 1590 1591 line_time_us = max(htotal * 1000 / clock, 1); 1592 1593 /* Use ns/us then divide to preserve precision */ 1594 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1595 cpp * hdisplay; 1596 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1597 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1598 srwm = wm_info->fifo_size - entries; 1599 if (srwm < 0) 1600 srwm = 1; 1601 1602 if (IS_I945G(dev) || IS_I945GM(dev)) 1603 I915_WRITE(FW_BLC_SELF, 1604 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1605 else if (IS_I915GM(dev)) 1606 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1607 } 1608 1609 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1610 planea_wm, planeb_wm, cwm, srwm); 1611 1612 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1613 fwater_hi = (cwm & 0x1f); 1614 1615 /* Set request length to 8 cachelines per fetch */ 1616 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1617 fwater_hi = fwater_hi | (1 << 8); 1618 1619 I915_WRITE(FW_BLC, fwater_lo); 1620 I915_WRITE(FW_BLC2, fwater_hi); 1621 1622 if (enabled) 1623 intel_set_memory_cxsr(dev_priv, true); 1624 } 1625 1626 static void i845_update_wm(struct drm_crtc *unused_crtc) 1627 { 1628 struct drm_device *dev = unused_crtc->dev; 1629 struct drm_i915_private *dev_priv = dev->dev_private; 1630 struct drm_crtc *crtc; 1631 const struct drm_display_mode *adjusted_mode; 1632 uint32_t fwater_lo; 1633 int planea_wm; 1634 1635 crtc = single_enabled_crtc(dev); 1636 if (crtc == NULL) 1637 return; 1638 1639 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1641 &i845_wm_info, 1642 dev_priv->display.get_fifo_size(dev, 0), 1643 4, pessimal_latency_ns); 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1645 fwater_lo |= (3<<8) | planea_wm; 1646 1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1648 1649 I915_WRITE(FW_BLC, fwater_lo); 1650 } 1651 1652 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) 1653 { 1654 uint32_t pixel_rate; 1655 1656 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; 1657 1658 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 1659 * adjust the pixel_rate here. */ 1660 1661 if (pipe_config->pch_pfit.enabled) { 1662 uint64_t pipe_w, pipe_h, pfit_w, pfit_h; 1663 uint32_t pfit_size = pipe_config->pch_pfit.size; 1664 1665 pipe_w = pipe_config->pipe_src_w; 1666 pipe_h = pipe_config->pipe_src_h; 1667 1668 pfit_w = (pfit_size >> 16) & 0xFFFF; 1669 pfit_h = pfit_size & 0xFFFF; 1670 if (pipe_w < pfit_w) 1671 pipe_w = pfit_w; 1672 if (pipe_h < pfit_h) 1673 pipe_h = pfit_h; 1674 1675 if (WARN_ON(!pfit_w || !pfit_h)) 1676 return pixel_rate; 1677 1678 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, 1679 pfit_w * pfit_h); 1680 } 1681 1682 return pixel_rate; 1683 } 1684 1685 /* latency must be in 0.1us units. */ 1686 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency) 1687 { 1688 uint64_t ret; 1689 1690 if (WARN(latency == 0, "Latency value missing\n")) 1691 return UINT_MAX; 1692 1693 ret = (uint64_t) pixel_rate * cpp * latency; 1694 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; 1695 1696 return ret; 1697 } 1698 1699 /* latency must be in 0.1us units. */ 1700 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 1701 uint32_t horiz_pixels, uint8_t cpp, 1702 uint32_t latency) 1703 { 1704 uint32_t ret; 1705 1706 if (WARN(latency == 0, "Latency value missing\n")) 1707 return UINT_MAX; 1708 if (WARN_ON(!pipe_htotal)) 1709 return UINT_MAX; 1710 1711 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 1712 ret = (ret + 1) * horiz_pixels * cpp; 1713 ret = DIV_ROUND_UP(ret, 64) + 2; 1714 return ret; 1715 } 1716 1717 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, 1718 uint8_t cpp) 1719 { 1720 /* 1721 * Neither of these should be possible since this function shouldn't be 1722 * called if the CRTC is off or the plane is invisible. But let's be 1723 * extra paranoid to avoid a potential divide-by-zero if we screw up 1724 * elsewhere in the driver. 1725 */ 1726 if (WARN_ON(!cpp)) 1727 return 0; 1728 if (WARN_ON(!horiz_pixels)) 1729 return 0; 1730 1731 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2; 1732 } 1733 1734 struct ilk_wm_maximums { 1735 uint16_t pri; 1736 uint16_t spr; 1737 uint16_t cur; 1738 uint16_t fbc; 1739 }; 1740 1741 /* 1742 * For both WM_PIPE and WM_LP. 1743 * mem_value must be in 0.1us units. 1744 */ 1745 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, 1746 const struct intel_plane_state *pstate, 1747 uint32_t mem_value, 1748 bool is_lp) 1749 { 1750 int cpp = pstate->base.fb ? 1751 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0; 1752 uint32_t method1, method2; 1753 1754 if (!cstate->base.active || !pstate->visible) 1755 return 0; 1756 1757 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value); 1758 1759 if (!is_lp) 1760 return method1; 1761 1762 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1763 cstate->base.adjusted_mode.crtc_htotal, 1764 drm_rect_width(&pstate->dst), 1765 cpp, mem_value); 1766 1767 return min(method1, method2); 1768 } 1769 1770 /* 1771 * For both WM_PIPE and WM_LP. 1772 * mem_value must be in 0.1us units. 1773 */ 1774 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, 1775 const struct intel_plane_state *pstate, 1776 uint32_t mem_value) 1777 { 1778 int cpp = pstate->base.fb ? 1779 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0; 1780 uint32_t method1, method2; 1781 1782 if (!cstate->base.active || !pstate->visible) 1783 return 0; 1784 1785 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value); 1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1787 cstate->base.adjusted_mode.crtc_htotal, 1788 drm_rect_width(&pstate->dst), 1789 cpp, mem_value); 1790 return min(method1, method2); 1791 } 1792 1793 /* 1794 * For both WM_PIPE and WM_LP. 1795 * mem_value must be in 0.1us units. 1796 */ 1797 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, 1798 const struct intel_plane_state *pstate, 1799 uint32_t mem_value) 1800 { 1801 /* 1802 * We treat the cursor plane as always-on for the purposes of watermark 1803 * calculation. Until we have two-stage watermark programming merged, 1804 * this is necessary to avoid flickering. 1805 */ 1806 int cpp = 4; 1807 int width = pstate->visible ? pstate->base.crtc_w : 64; 1808 1809 if (!cstate->base.active) 1810 return 0; 1811 1812 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate), 1813 cstate->base.adjusted_mode.crtc_htotal, 1814 width, cpp, mem_value); 1815 } 1816 1817 /* Only for WM_LP. */ 1818 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, 1819 const struct intel_plane_state *pstate, 1820 uint32_t pri_val) 1821 { 1822 int cpp = pstate->base.fb ? 1823 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0; 1824 1825 if (!cstate->base.active || !pstate->visible) 1826 return 0; 1827 1828 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp); 1829 } 1830 1831 static unsigned int ilk_display_fifo_size(const struct drm_device *dev) 1832 { 1833 if (INTEL_INFO(dev)->gen >= 8) 1834 return 3072; 1835 else if (INTEL_INFO(dev)->gen >= 7) 1836 return 768; 1837 else 1838 return 512; 1839 } 1840 1841 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, 1842 int level, bool is_sprite) 1843 { 1844 if (INTEL_INFO(dev)->gen >= 8) 1845 /* BDW primary/sprite plane watermarks */ 1846 return level == 0 ? 255 : 2047; 1847 else if (INTEL_INFO(dev)->gen >= 7) 1848 /* IVB/HSW primary/sprite plane watermarks */ 1849 return level == 0 ? 127 : 1023; 1850 else if (!is_sprite) 1851 /* ILK/SNB primary plane watermarks */ 1852 return level == 0 ? 127 : 511; 1853 else 1854 /* ILK/SNB sprite plane watermarks */ 1855 return level == 0 ? 63 : 255; 1856 } 1857 1858 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, 1859 int level) 1860 { 1861 if (INTEL_INFO(dev)->gen >= 7) 1862 return level == 0 ? 63 : 255; 1863 else 1864 return level == 0 ? 31 : 63; 1865 } 1866 1867 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) 1868 { 1869 if (INTEL_INFO(dev)->gen >= 8) 1870 return 31; 1871 else 1872 return 15; 1873 } 1874 1875 /* Calculate the maximum primary/sprite plane watermark */ 1876 static unsigned int ilk_plane_wm_max(const struct drm_device *dev, 1877 int level, 1878 const struct intel_wm_config *config, 1879 enum intel_ddb_partitioning ddb_partitioning, 1880 bool is_sprite) 1881 { 1882 unsigned int fifo_size = ilk_display_fifo_size(dev); 1883 1884 /* if sprites aren't enabled, sprites get nothing */ 1885 if (is_sprite && !config->sprites_enabled) 1886 return 0; 1887 1888 /* HSW allows LP1+ watermarks even with multiple pipes */ 1889 if (level == 0 || config->num_pipes_active > 1) { 1890 fifo_size /= INTEL_INFO(dev)->num_pipes; 1891 1892 /* 1893 * For some reason the non self refresh 1894 * FIFO size is only half of the self 1895 * refresh FIFO size on ILK/SNB. 1896 */ 1897 if (INTEL_INFO(dev)->gen <= 6) 1898 fifo_size /= 2; 1899 } 1900 1901 if (config->sprites_enabled) { 1902 /* level 0 is always calculated with 1:1 split */ 1903 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { 1904 if (is_sprite) 1905 fifo_size *= 5; 1906 fifo_size /= 6; 1907 } else { 1908 fifo_size /= 2; 1909 } 1910 } 1911 1912 /* clamp to max that the registers can hold */ 1913 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); 1914 } 1915 1916 /* Calculate the maximum cursor plane watermark */ 1917 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, 1918 int level, 1919 const struct intel_wm_config *config) 1920 { 1921 /* HSW LP1+ watermarks w/ multiple pipes */ 1922 if (level > 0 && config->num_pipes_active > 1) 1923 return 64; 1924 1925 /* otherwise just report max that registers can hold */ 1926 return ilk_cursor_wm_reg_max(dev, level); 1927 } 1928 1929 static void ilk_compute_wm_maximums(const struct drm_device *dev, 1930 int level, 1931 const struct intel_wm_config *config, 1932 enum intel_ddb_partitioning ddb_partitioning, 1933 struct ilk_wm_maximums *max) 1934 { 1935 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); 1936 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); 1937 max->cur = ilk_cursor_wm_max(dev, level, config); 1938 max->fbc = ilk_fbc_wm_reg_max(dev); 1939 } 1940 1941 static void ilk_compute_wm_reg_maximums(struct drm_device *dev, 1942 int level, 1943 struct ilk_wm_maximums *max) 1944 { 1945 max->pri = ilk_plane_wm_reg_max(dev, level, false); 1946 max->spr = ilk_plane_wm_reg_max(dev, level, true); 1947 max->cur = ilk_cursor_wm_reg_max(dev, level); 1948 max->fbc = ilk_fbc_wm_reg_max(dev); 1949 } 1950 1951 static bool ilk_validate_wm_level(int level, 1952 const struct ilk_wm_maximums *max, 1953 struct intel_wm_level *result) 1954 { 1955 bool ret; 1956 1957 /* already determined to be invalid? */ 1958 if (!result->enable) 1959 return false; 1960 1961 result->enable = result->pri_val <= max->pri && 1962 result->spr_val <= max->spr && 1963 result->cur_val <= max->cur; 1964 1965 ret = result->enable; 1966 1967 /* 1968 * HACK until we can pre-compute everything, 1969 * and thus fail gracefully if LP0 watermarks 1970 * are exceeded... 1971 */ 1972 if (level == 0 && !result->enable) { 1973 if (result->pri_val > max->pri) 1974 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", 1975 level, result->pri_val, max->pri); 1976 if (result->spr_val > max->spr) 1977 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", 1978 level, result->spr_val, max->spr); 1979 if (result->cur_val > max->cur) 1980 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", 1981 level, result->cur_val, max->cur); 1982 1983 result->pri_val = min_t(uint32_t, result->pri_val, max->pri); 1984 result->spr_val = min_t(uint32_t, result->spr_val, max->spr); 1985 result->cur_val = min_t(uint32_t, result->cur_val, max->cur); 1986 result->enable = true; 1987 } 1988 1989 return ret; 1990 } 1991 1992 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, 1993 const struct intel_crtc *intel_crtc, 1994 int level, 1995 struct intel_crtc_state *cstate, 1996 struct intel_plane_state *pristate, 1997 struct intel_plane_state *sprstate, 1998 struct intel_plane_state *curstate, 1999 struct intel_wm_level *result) 2000 { 2001 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; 2002 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; 2003 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; 2004 2005 /* WM1+ latency values stored in 0.5us units */ 2006 if (level > 0) { 2007 pri_latency *= 5; 2008 spr_latency *= 5; 2009 cur_latency *= 5; 2010 } 2011 2012 result->pri_val = ilk_compute_pri_wm(cstate, pristate, 2013 pri_latency, level); 2014 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency); 2015 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency); 2016 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); 2017 result->enable = true; 2018 } 2019 2020 static uint32_t 2021 hsw_compute_linetime_wm(struct drm_device *dev, 2022 struct intel_crtc_state *cstate) 2023 { 2024 struct drm_i915_private *dev_priv = dev->dev_private; 2025 const struct drm_display_mode *adjusted_mode = 2026 &cstate->base.adjusted_mode; 2027 u32 linetime, ips_linetime; 2028 2029 if (!cstate->base.active) 2030 return 0; 2031 if (WARN_ON(adjusted_mode->crtc_clock == 0)) 2032 return 0; 2033 if (WARN_ON(dev_priv->cdclk_freq == 0)) 2034 return 0; 2035 2036 /* The WM are computed with base on how long it takes to fill a single 2037 * row at the given clock rate, multiplied by 8. 2038 * */ 2039 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2040 adjusted_mode->crtc_clock); 2041 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, 2042 dev_priv->cdclk_freq); 2043 2044 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | 2045 PIPE_WM_LINETIME_TIME(linetime); 2046 } 2047 2048 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) 2049 { 2050 struct drm_i915_private *dev_priv = dev->dev_private; 2051 2052 if (IS_GEN9(dev)) { 2053 uint32_t val; 2054 int ret, i; 2055 int level, max_level = ilk_wm_max_level(dev); 2056 2057 /* read the first set of memory latencies[0:3] */ 2058 val = 0; /* data0 to be programmed to 0 for first set */ 2059 mutex_lock(&dev_priv->rps.hw_lock); 2060 ret = sandybridge_pcode_read(dev_priv, 2061 GEN9_PCODE_READ_MEM_LATENCY, 2062 &val); 2063 mutex_unlock(&dev_priv->rps.hw_lock); 2064 2065 if (ret) { 2066 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2067 return; 2068 } 2069 2070 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2071 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2072 GEN9_MEM_LATENCY_LEVEL_MASK; 2073 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2074 GEN9_MEM_LATENCY_LEVEL_MASK; 2075 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2076 GEN9_MEM_LATENCY_LEVEL_MASK; 2077 2078 /* read the second set of memory latencies[4:7] */ 2079 val = 1; /* data0 to be programmed to 1 for second set */ 2080 mutex_lock(&dev_priv->rps.hw_lock); 2081 ret = sandybridge_pcode_read(dev_priv, 2082 GEN9_PCODE_READ_MEM_LATENCY, 2083 &val); 2084 mutex_unlock(&dev_priv->rps.hw_lock); 2085 if (ret) { 2086 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2087 return; 2088 } 2089 2090 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2091 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2092 GEN9_MEM_LATENCY_LEVEL_MASK; 2093 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2094 GEN9_MEM_LATENCY_LEVEL_MASK; 2095 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2096 GEN9_MEM_LATENCY_LEVEL_MASK; 2097 2098 /* 2099 * WaWmMemoryReadLatency:skl 2100 * 2101 * punit doesn't take into account the read latency so we need 2102 * to add 2us to the various latency levels we retrieve from 2103 * the punit. 2104 * - W0 is a bit special in that it's the only level that 2105 * can't be disabled if we want to have display working, so 2106 * we always add 2us there. 2107 * - For levels >=1, punit returns 0us latency when they are 2108 * disabled, so we respect that and don't add 2us then 2109 * 2110 * Additionally, if a level n (n > 1) has a 0us latency, all 2111 * levels m (m >= n) need to be disabled. We make sure to 2112 * sanitize the values out of the punit to satisfy this 2113 * requirement. 2114 */ 2115 wm[0] += 2; 2116 for (level = 1; level <= max_level; level++) 2117 if (wm[level] != 0) 2118 wm[level] += 2; 2119 else { 2120 for (i = level + 1; i <= max_level; i++) 2121 wm[i] = 0; 2122 2123 break; 2124 } 2125 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2126 uint64_t sskpd = I915_READ64(MCH_SSKPD); 2127 2128 wm[0] = (sskpd >> 56) & 0xFF; 2129 if (wm[0] == 0) 2130 wm[0] = sskpd & 0xF; 2131 wm[1] = (sskpd >> 4) & 0xFF; 2132 wm[2] = (sskpd >> 12) & 0xFF; 2133 wm[3] = (sskpd >> 20) & 0x1FF; 2134 wm[4] = (sskpd >> 32) & 0x1FF; 2135 } else if (INTEL_INFO(dev)->gen >= 6) { 2136 uint32_t sskpd = I915_READ(MCH_SSKPD); 2137 2138 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; 2139 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; 2140 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; 2141 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; 2142 } else if (INTEL_INFO(dev)->gen >= 5) { 2143 uint32_t mltr = I915_READ(MLTR_ILK); 2144 2145 /* ILK primary LP0 latency is 700 ns */ 2146 wm[0] = 7; 2147 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; 2148 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; 2149 } 2150 } 2151 2152 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2153 { 2154 /* ILK sprite LP0 latency is 1300 ns */ 2155 if (INTEL_INFO(dev)->gen == 5) 2156 wm[0] = 13; 2157 } 2158 2159 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2160 { 2161 /* ILK cursor LP0 latency is 1300 ns */ 2162 if (INTEL_INFO(dev)->gen == 5) 2163 wm[0] = 13; 2164 2165 /* WaDoubleCursorLP3Latency:ivb */ 2166 if (IS_IVYBRIDGE(dev)) 2167 wm[3] *= 2; 2168 } 2169 2170 int ilk_wm_max_level(const struct drm_device *dev) 2171 { 2172 /* how many WM levels are we expecting */ 2173 if (INTEL_INFO(dev)->gen >= 9) 2174 return 7; 2175 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2176 return 4; 2177 else if (INTEL_INFO(dev)->gen >= 6) 2178 return 3; 2179 else 2180 return 2; 2181 } 2182 2183 static void intel_print_wm_latency(struct drm_device *dev, 2184 const char *name, 2185 const uint16_t wm[8]) 2186 { 2187 int level, max_level = ilk_wm_max_level(dev); 2188 2189 for (level = 0; level <= max_level; level++) { 2190 unsigned int latency = wm[level]; 2191 2192 if (latency == 0) { 2193 DRM_ERROR("%s WM%d latency not provided\n", 2194 name, level); 2195 continue; 2196 } 2197 2198 /* 2199 * - latencies are in us on gen9. 2200 * - before then, WM1+ latency values are in 0.5us units 2201 */ 2202 if (IS_GEN9(dev)) 2203 latency *= 10; 2204 else if (level > 0) 2205 latency *= 5; 2206 2207 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", 2208 name, level, wm[level], 2209 latency / 10, latency % 10); 2210 } 2211 } 2212 2213 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, 2214 uint16_t wm[5], uint16_t min) 2215 { 2216 int level, max_level = ilk_wm_max_level(dev_priv->dev); 2217 2218 if (wm[0] >= min) 2219 return false; 2220 2221 wm[0] = max(wm[0], min); 2222 for (level = 1; level <= max_level; level++) 2223 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); 2224 2225 return true; 2226 } 2227 2228 static void snb_wm_latency_quirk(struct drm_device *dev) 2229 { 2230 struct drm_i915_private *dev_priv = dev->dev_private; 2231 bool changed; 2232 2233 /* 2234 * The BIOS provided WM memory latency values are often 2235 * inadequate for high resolution displays. Adjust them. 2236 */ 2237 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | 2238 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | 2239 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); 2240 2241 if (!changed) 2242 return; 2243 2244 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); 2245 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2246 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2247 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2248 } 2249 2250 static void ilk_setup_wm_latency(struct drm_device *dev) 2251 { 2252 struct drm_i915_private *dev_priv = dev->dev_private; 2253 2254 intel_read_wm_latency(dev, dev_priv->wm.pri_latency); 2255 2256 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, 2257 sizeof(dev_priv->wm.pri_latency)); 2258 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, 2259 sizeof(dev_priv->wm.pri_latency)); 2260 2261 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); 2262 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); 2263 2264 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2265 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2266 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2267 2268 if (IS_GEN6(dev)) 2269 snb_wm_latency_quirk(dev); 2270 } 2271 2272 static void skl_setup_wm_latency(struct drm_device *dev) 2273 { 2274 struct drm_i915_private *dev_priv = dev->dev_private; 2275 2276 intel_read_wm_latency(dev, dev_priv->wm.skl_latency); 2277 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); 2278 } 2279 2280 /* Compute new watermarks for the pipe */ 2281 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc, 2282 struct drm_atomic_state *state) 2283 { 2284 struct intel_pipe_wm *pipe_wm; 2285 struct drm_device *dev = intel_crtc->base.dev; 2286 const struct drm_i915_private *dev_priv = dev->dev_private; 2287 struct intel_crtc_state *cstate = NULL; 2288 struct intel_plane *intel_plane; 2289 struct drm_plane_state *ps; 2290 struct intel_plane_state *pristate = NULL; 2291 struct intel_plane_state *sprstate = NULL; 2292 struct intel_plane_state *curstate = NULL; 2293 int level, max_level = ilk_wm_max_level(dev); 2294 /* LP0 watermark maximums depend on this pipe alone */ 2295 struct intel_wm_config config = { 2296 .num_pipes_active = 1, 2297 }; 2298 struct ilk_wm_maximums max; 2299 2300 cstate = intel_atomic_get_crtc_state(state, intel_crtc); 2301 if (IS_ERR(cstate)) 2302 return PTR_ERR(cstate); 2303 2304 pipe_wm = &cstate->wm.optimal.ilk; 2305 memset(pipe_wm, 0, sizeof(*pipe_wm)); 2306 2307 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 2308 ps = drm_atomic_get_plane_state(state, 2309 &intel_plane->base); 2310 if (IS_ERR(ps)) 2311 return PTR_ERR(ps); 2312 2313 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY) 2314 pristate = to_intel_plane_state(ps); 2315 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) 2316 sprstate = to_intel_plane_state(ps); 2317 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) 2318 curstate = to_intel_plane_state(ps); 2319 } 2320 2321 config.sprites_enabled = sprstate->visible; 2322 config.sprites_scaled = sprstate->visible && 2323 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 || 2324 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16); 2325 2326 pipe_wm->pipe_enabled = cstate->base.active; 2327 pipe_wm->sprites_enabled = config.sprites_enabled; 2328 pipe_wm->sprites_scaled = config.sprites_scaled; 2329 2330 /* ILK/SNB: LP2+ watermarks only w/o sprites */ 2331 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible) 2332 max_level = 1; 2333 2334 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ 2335 if (config.sprites_scaled) 2336 max_level = 0; 2337 2338 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, 2339 pristate, sprstate, curstate, &pipe_wm->wm[0]); 2340 2341 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2342 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate); 2343 2344 /* LP0 watermarks always use 1/2 DDB partitioning */ 2345 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); 2346 2347 /* At least LP0 must be valid */ 2348 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) 2349 return -EINVAL; 2350 2351 ilk_compute_wm_reg_maximums(dev, 1, &max); 2352 2353 for (level = 1; level <= max_level; level++) { 2354 struct intel_wm_level wm = {}; 2355 2356 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, 2357 pristate, sprstate, curstate, &wm); 2358 2359 /* 2360 * Disable any watermark level that exceeds the 2361 * register maximums since such watermarks are 2362 * always invalid. 2363 */ 2364 if (!ilk_validate_wm_level(level, &max, &wm)) 2365 break; 2366 2367 pipe_wm->wm[level] = wm; 2368 } 2369 2370 return 0; 2371 } 2372 2373 /* 2374 * Merge the watermarks from all active pipes for a specific level. 2375 */ 2376 static void ilk_merge_wm_level(struct drm_device *dev, 2377 int level, 2378 struct intel_wm_level *ret_wm) 2379 { 2380 struct intel_crtc *intel_crtc; 2381 2382 ret_wm->enable = true; 2383 2384 for_each_intel_crtc(dev, intel_crtc) { 2385 const struct intel_crtc_state *cstate = 2386 to_intel_crtc_state(intel_crtc->base.state); 2387 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk; 2388 const struct intel_wm_level *wm = &active->wm[level]; 2389 2390 if (!active->pipe_enabled) 2391 continue; 2392 2393 /* 2394 * The watermark values may have been used in the past, 2395 * so we must maintain them in the registers for some 2396 * time even if the level is now disabled. 2397 */ 2398 if (!wm->enable) 2399 ret_wm->enable = false; 2400 2401 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); 2402 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); 2403 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); 2404 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); 2405 } 2406 } 2407 2408 /* 2409 * Merge all low power watermarks for all active pipes. 2410 */ 2411 static void ilk_wm_merge(struct drm_device *dev, 2412 const struct intel_wm_config *config, 2413 const struct ilk_wm_maximums *max, 2414 struct intel_pipe_wm *merged) 2415 { 2416 struct drm_i915_private *dev_priv = dev->dev_private; 2417 int level, max_level = ilk_wm_max_level(dev); 2418 int last_enabled_level = max_level; 2419 2420 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ 2421 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && 2422 config->num_pipes_active > 1) 2423 return; 2424 2425 /* ILK: FBC WM must be disabled always */ 2426 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; 2427 2428 /* merge each WM1+ level */ 2429 for (level = 1; level <= max_level; level++) { 2430 struct intel_wm_level *wm = &merged->wm[level]; 2431 2432 ilk_merge_wm_level(dev, level, wm); 2433 2434 if (level > last_enabled_level) 2435 wm->enable = false; 2436 else if (!ilk_validate_wm_level(level, max, wm)) 2437 /* make sure all following levels get disabled */ 2438 last_enabled_level = level - 1; 2439 2440 /* 2441 * The spec says it is preferred to disable 2442 * FBC WMs instead of disabling a WM level. 2443 */ 2444 if (wm->fbc_val > max->fbc) { 2445 if (wm->enable) 2446 merged->fbc_wm_enabled = false; 2447 wm->fbc_val = 0; 2448 } 2449 } 2450 2451 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ 2452 /* 2453 * FIXME this is racy. FBC might get enabled later. 2454 * What we should check here is whether FBC can be 2455 * enabled sometime later. 2456 */ 2457 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && 2458 intel_fbc_is_active(dev_priv)) { 2459 for (level = 2; level <= max_level; level++) { 2460 struct intel_wm_level *wm = &merged->wm[level]; 2461 2462 wm->enable = false; 2463 } 2464 } 2465 } 2466 2467 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) 2468 { 2469 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ 2470 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); 2471 } 2472 2473 /* The value we need to program into the WM_LPx latency field */ 2474 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) 2475 { 2476 struct drm_i915_private *dev_priv = dev->dev_private; 2477 2478 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2479 return 2 * level; 2480 else 2481 return dev_priv->wm.pri_latency[level]; 2482 } 2483 2484 static void ilk_compute_wm_results(struct drm_device *dev, 2485 const struct intel_pipe_wm *merged, 2486 enum intel_ddb_partitioning partitioning, 2487 struct ilk_wm_values *results) 2488 { 2489 struct intel_crtc *intel_crtc; 2490 int level, wm_lp; 2491 2492 results->enable_fbc_wm = merged->fbc_wm_enabled; 2493 results->partitioning = partitioning; 2494 2495 /* LP1+ register values */ 2496 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2497 const struct intel_wm_level *r; 2498 2499 level = ilk_wm_lp_to_level(wm_lp, merged); 2500 2501 r = &merged->wm[level]; 2502 2503 /* 2504 * Maintain the watermark values even if the level is 2505 * disabled. Doing otherwise could cause underruns. 2506 */ 2507 results->wm_lp[wm_lp - 1] = 2508 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | 2509 (r->pri_val << WM1_LP_SR_SHIFT) | 2510 r->cur_val; 2511 2512 if (r->enable) 2513 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; 2514 2515 if (INTEL_INFO(dev)->gen >= 8) 2516 results->wm_lp[wm_lp - 1] |= 2517 r->fbc_val << WM1_LP_FBC_SHIFT_BDW; 2518 else 2519 results->wm_lp[wm_lp - 1] |= 2520 r->fbc_val << WM1_LP_FBC_SHIFT; 2521 2522 /* 2523 * Always set WM1S_LP_EN when spr_val != 0, even if the 2524 * level is disabled. Doing otherwise could cause underruns. 2525 */ 2526 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { 2527 WARN_ON(wm_lp != 1); 2528 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; 2529 } else 2530 results->wm_lp_spr[wm_lp - 1] = r->spr_val; 2531 } 2532 2533 /* LP0 register values */ 2534 for_each_intel_crtc(dev, intel_crtc) { 2535 const struct intel_crtc_state *cstate = 2536 to_intel_crtc_state(intel_crtc->base.state); 2537 enum i915_pipe pipe = intel_crtc->pipe; 2538 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0]; 2539 2540 if (WARN_ON(!r->enable)) 2541 continue; 2542 2543 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime; 2544 2545 results->wm_pipe[pipe] = 2546 (r->pri_val << WM0_PIPE_PLANE_SHIFT) | 2547 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | 2548 r->cur_val; 2549 } 2550 } 2551 2552 /* Find the result with the highest level enabled. Check for enable_fbc_wm in 2553 * case both are at the same level. Prefer r1 in case they're the same. */ 2554 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, 2555 struct intel_pipe_wm *r1, 2556 struct intel_pipe_wm *r2) 2557 { 2558 int level, max_level = ilk_wm_max_level(dev); 2559 int level1 = 0, level2 = 0; 2560 2561 for (level = 1; level <= max_level; level++) { 2562 if (r1->wm[level].enable) 2563 level1 = level; 2564 if (r2->wm[level].enable) 2565 level2 = level; 2566 } 2567 2568 if (level1 == level2) { 2569 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) 2570 return r2; 2571 else 2572 return r1; 2573 } else if (level1 > level2) { 2574 return r1; 2575 } else { 2576 return r2; 2577 } 2578 } 2579 2580 /* dirty bits used to track which watermarks need changes */ 2581 #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) 2582 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) 2583 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) 2584 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) 2585 #define WM_DIRTY_FBC (1 << 24) 2586 #define WM_DIRTY_DDB (1 << 25) 2587 2588 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, 2589 const struct ilk_wm_values *old, 2590 const struct ilk_wm_values *new) 2591 { 2592 unsigned int dirty = 0; 2593 enum i915_pipe pipe; 2594 int wm_lp; 2595 2596 for_each_pipe(dev_priv, pipe) { 2597 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { 2598 dirty |= WM_DIRTY_LINETIME(pipe); 2599 /* Must disable LP1+ watermarks too */ 2600 dirty |= WM_DIRTY_LP_ALL; 2601 } 2602 2603 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { 2604 dirty |= WM_DIRTY_PIPE(pipe); 2605 /* Must disable LP1+ watermarks too */ 2606 dirty |= WM_DIRTY_LP_ALL; 2607 } 2608 } 2609 2610 if (old->enable_fbc_wm != new->enable_fbc_wm) { 2611 dirty |= WM_DIRTY_FBC; 2612 /* Must disable LP1+ watermarks too */ 2613 dirty |= WM_DIRTY_LP_ALL; 2614 } 2615 2616 if (old->partitioning != new->partitioning) { 2617 dirty |= WM_DIRTY_DDB; 2618 /* Must disable LP1+ watermarks too */ 2619 dirty |= WM_DIRTY_LP_ALL; 2620 } 2621 2622 /* LP1+ watermarks already deemed dirty, no need to continue */ 2623 if (dirty & WM_DIRTY_LP_ALL) 2624 return dirty; 2625 2626 /* Find the lowest numbered LP1+ watermark in need of an update... */ 2627 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2628 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || 2629 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) 2630 break; 2631 } 2632 2633 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ 2634 for (; wm_lp <= 3; wm_lp++) 2635 dirty |= WM_DIRTY_LP(wm_lp); 2636 2637 return dirty; 2638 } 2639 2640 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, 2641 unsigned int dirty) 2642 { 2643 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2644 bool changed = false; 2645 2646 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { 2647 previous->wm_lp[2] &= ~WM1_LP_SR_EN; 2648 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); 2649 changed = true; 2650 } 2651 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { 2652 previous->wm_lp[1] &= ~WM1_LP_SR_EN; 2653 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); 2654 changed = true; 2655 } 2656 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { 2657 previous->wm_lp[0] &= ~WM1_LP_SR_EN; 2658 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); 2659 changed = true; 2660 } 2661 2662 /* 2663 * Don't touch WM1S_LP_EN here. 2664 * Doing so could cause underruns. 2665 */ 2666 2667 return changed; 2668 } 2669 2670 /* 2671 * The spec says we shouldn't write when we don't need, because every write 2672 * causes WMs to be re-evaluated, expending some power. 2673 */ 2674 static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 2675 struct ilk_wm_values *results) 2676 { 2677 struct drm_device *dev = dev_priv->dev; 2678 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2679 unsigned int dirty; 2680 uint32_t val; 2681 2682 dirty = ilk_compute_wm_dirty(dev_priv, previous, results); 2683 if (!dirty) 2684 return; 2685 2686 _ilk_disable_lp_wm(dev_priv, dirty); 2687 2688 if (dirty & WM_DIRTY_PIPE(PIPE_A)) 2689 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); 2690 if (dirty & WM_DIRTY_PIPE(PIPE_B)) 2691 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); 2692 if (dirty & WM_DIRTY_PIPE(PIPE_C)) 2693 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); 2694 2695 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) 2696 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); 2697 if (dirty & WM_DIRTY_LINETIME(PIPE_B)) 2698 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); 2699 if (dirty & WM_DIRTY_LINETIME(PIPE_C)) 2700 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); 2701 2702 if (dirty & WM_DIRTY_DDB) { 2703 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2704 val = I915_READ(WM_MISC); 2705 if (results->partitioning == INTEL_DDB_PART_1_2) 2706 val &= ~WM_MISC_DATA_PARTITION_5_6; 2707 else 2708 val |= WM_MISC_DATA_PARTITION_5_6; 2709 I915_WRITE(WM_MISC, val); 2710 } else { 2711 val = I915_READ(DISP_ARB_CTL2); 2712 if (results->partitioning == INTEL_DDB_PART_1_2) 2713 val &= ~DISP_DATA_PARTITION_5_6; 2714 else 2715 val |= DISP_DATA_PARTITION_5_6; 2716 I915_WRITE(DISP_ARB_CTL2, val); 2717 } 2718 } 2719 2720 if (dirty & WM_DIRTY_FBC) { 2721 val = I915_READ(DISP_ARB_CTL); 2722 if (results->enable_fbc_wm) 2723 val &= ~DISP_FBC_WM_DIS; 2724 else 2725 val |= DISP_FBC_WM_DIS; 2726 I915_WRITE(DISP_ARB_CTL, val); 2727 } 2728 2729 if (dirty & WM_DIRTY_LP(1) && 2730 previous->wm_lp_spr[0] != results->wm_lp_spr[0]) 2731 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); 2732 2733 if (INTEL_INFO(dev)->gen >= 7) { 2734 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) 2735 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); 2736 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) 2737 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); 2738 } 2739 2740 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) 2741 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); 2742 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) 2743 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); 2744 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) 2745 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); 2746 2747 dev_priv->wm.hw = *results; 2748 } 2749 2750 static bool ilk_disable_lp_wm(struct drm_device *dev) 2751 { 2752 struct drm_i915_private *dev_priv = dev->dev_private; 2753 2754 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); 2755 } 2756 2757 /* 2758 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the 2759 * different active planes. 2760 */ 2761 2762 #define SKL_DDB_SIZE 896 /* in blocks */ 2763 #define BXT_DDB_SIZE 512 2764 2765 /* 2766 * Return the index of a plane in the SKL DDB and wm result arrays. Primary 2767 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and 2768 * other universal planes are in indices 1..n. Note that this may leave unused 2769 * indices between the top "sprite" plane and the cursor. 2770 */ 2771 static int 2772 skl_wm_plane_id(const struct intel_plane *plane) 2773 { 2774 switch (plane->base.type) { 2775 case DRM_PLANE_TYPE_PRIMARY: 2776 return 0; 2777 case DRM_PLANE_TYPE_CURSOR: 2778 return PLANE_CURSOR; 2779 case DRM_PLANE_TYPE_OVERLAY: 2780 return plane->plane + 1; 2781 default: 2782 MISSING_CASE(plane->base.type); 2783 return plane->plane; 2784 } 2785 } 2786 2787 static void 2788 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, 2789 const struct intel_crtc_state *cstate, 2790 const struct intel_wm_config *config, 2791 struct skl_ddb_entry *alloc /* out */) 2792 { 2793 struct drm_crtc *for_crtc = cstate->base.crtc; 2794 struct drm_crtc *crtc; 2795 unsigned int pipe_size, ddb_size; 2796 int nth_active_pipe; 2797 2798 if (!cstate->base.active) { 2799 alloc->start = 0; 2800 alloc->end = 0; 2801 return; 2802 } 2803 2804 if (IS_BROXTON(dev)) 2805 ddb_size = BXT_DDB_SIZE; 2806 else 2807 ddb_size = SKL_DDB_SIZE; 2808 2809 ddb_size -= 4; /* 4 blocks for bypass path allocation */ 2810 2811 nth_active_pipe = 0; 2812 for_each_crtc(dev, crtc) { 2813 if (!to_intel_crtc(crtc)->active) 2814 continue; 2815 2816 if (crtc == for_crtc) 2817 break; 2818 2819 nth_active_pipe++; 2820 } 2821 2822 pipe_size = ddb_size / config->num_pipes_active; 2823 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; 2824 alloc->end = alloc->start + pipe_size; 2825 } 2826 2827 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) 2828 { 2829 if (config->num_pipes_active == 1) 2830 return 32; 2831 2832 return 8; 2833 } 2834 2835 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 2836 { 2837 entry->start = reg & 0x3ff; 2838 entry->end = (reg >> 16) & 0x3ff; 2839 if (entry->end) 2840 entry->end += 1; 2841 } 2842 2843 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 2844 struct skl_ddb_allocation *ddb /* out */) 2845 { 2846 enum i915_pipe pipe; 2847 int plane; 2848 u32 val; 2849 2850 memset(ddb, 0, sizeof(*ddb)); 2851 2852 for_each_pipe(dev_priv, pipe) { 2853 enum intel_display_power_domain power_domain; 2854 2855 power_domain = POWER_DOMAIN_PIPE(pipe); 2856 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 2857 continue; 2858 2859 for_each_plane(dev_priv, pipe, plane) { 2860 val = I915_READ(PLANE_BUF_CFG(pipe, plane)); 2861 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], 2862 val); 2863 } 2864 2865 val = I915_READ(CUR_BUF_CFG(pipe)); 2866 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR], 2867 val); 2868 2869 intel_display_power_put(dev_priv, power_domain); 2870 } 2871 } 2872 2873 static unsigned int 2874 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, 2875 struct drm_plane_state *pstate, 2876 int y) 2877 { 2878 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); 2879 struct drm_framebuffer *fb = pstate->fb; 2880 uint32_t width = 0, height = 0; 2881 2882 width = drm_rect_width(&intel_pstate->src) >> 16; 2883 height = drm_rect_height(&intel_pstate->src) >> 16; 2884 2885 if (intel_rotation_90_or_270(pstate->rotation)) 2886 swap(width, height); 2887 2888 /* for planar format */ 2889 if (fb->pixel_format == DRM_FORMAT_NV12) { 2890 if (y) /* y-plane data rate */ 2891 return width * height * 2892 drm_format_plane_cpp(fb->pixel_format, 0); 2893 else /* uv-plane data rate */ 2894 return (width / 2) * (height / 2) * 2895 drm_format_plane_cpp(fb->pixel_format, 1); 2896 } 2897 2898 /* for packed formats */ 2899 return width * height * drm_format_plane_cpp(fb->pixel_format, 0); 2900 } 2901 2902 /* 2903 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching 2904 * a 8192x4096@32bpp framebuffer: 2905 * 3 * 4096 * 8192 * 4 < 2^32 2906 */ 2907 static unsigned int 2908 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate) 2909 { 2910 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); 2911 struct drm_device *dev = intel_crtc->base.dev; 2912 struct intel_plane *intel_plane; 2913 unsigned int total_data_rate = 0; 2914 2915 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 2916 struct drm_plane_state *pstate = intel_plane->base.state; 2917 2918 if (pstate->fb == NULL) 2919 continue; 2920 2921 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) 2922 continue; 2923 2924 /* packed/uv */ 2925 total_data_rate += skl_plane_relative_data_rate(cstate, 2926 pstate, 2927 0); 2928 2929 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) 2930 /* y-plane */ 2931 total_data_rate += skl_plane_relative_data_rate(cstate, 2932 pstate, 2933 1); 2934 } 2935 2936 return total_data_rate; 2937 } 2938 2939 static void 2940 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, 2941 struct skl_ddb_allocation *ddb /* out */) 2942 { 2943 struct drm_crtc *crtc = cstate->base.crtc; 2944 struct drm_device *dev = crtc->dev; 2945 struct drm_i915_private *dev_priv = to_i915(dev); 2946 struct intel_wm_config *config = &dev_priv->wm.config; 2947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2948 struct intel_plane *intel_plane; 2949 enum i915_pipe pipe = intel_crtc->pipe; 2950 struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; 2951 uint16_t alloc_size, start, cursor_blocks; 2952 uint16_t minimum[I915_MAX_PLANES]; 2953 uint16_t y_minimum[I915_MAX_PLANES]; 2954 unsigned int total_data_rate; 2955 2956 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc); 2957 alloc_size = skl_ddb_entry_size(alloc); 2958 if (alloc_size == 0) { 2959 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); 2960 memset(&ddb->plane[pipe][PLANE_CURSOR], 0, 2961 sizeof(ddb->plane[pipe][PLANE_CURSOR])); 2962 return; 2963 } 2964 2965 cursor_blocks = skl_cursor_allocation(config); 2966 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks; 2967 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; 2968 2969 alloc_size -= cursor_blocks; 2970 alloc->end -= cursor_blocks; 2971 2972 /* 1. Allocate the mininum required blocks for each active plane */ 2973 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 2974 struct drm_plane *plane = &intel_plane->base; 2975 struct drm_framebuffer *fb = plane->state->fb; 2976 int id = skl_wm_plane_id(intel_plane); 2977 2978 if (!to_intel_plane_state(plane->state)->visible) 2979 continue; 2980 2981 if (plane->type == DRM_PLANE_TYPE_CURSOR) 2982 continue; 2983 2984 minimum[id] = 8; 2985 alloc_size -= minimum[id]; 2986 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0; 2987 alloc_size -= y_minimum[id]; 2988 } 2989 2990 /* 2991 * 2. Distribute the remaining space in proportion to the amount of 2992 * data each plane needs to fetch from memory. 2993 * 2994 * FIXME: we may not allocate every single block here. 2995 */ 2996 total_data_rate = skl_get_total_relative_data_rate(cstate); 2997 2998 start = alloc->start; 2999 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 3000 struct drm_plane *plane = &intel_plane->base; 3001 struct drm_plane_state *pstate = intel_plane->base.state; 3002 unsigned int data_rate, y_data_rate; 3003 uint16_t plane_blocks, y_plane_blocks = 0; 3004 int id = skl_wm_plane_id(intel_plane); 3005 3006 if (!to_intel_plane_state(pstate)->visible) 3007 continue; 3008 if (plane->type == DRM_PLANE_TYPE_CURSOR) 3009 continue; 3010 3011 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0); 3012 3013 /* 3014 * allocation for (packed formats) or (uv-plane part of planar format): 3015 * promote the expression to 64 bits to avoid overflowing, the 3016 * result is < available as data_rate / total_data_rate < 1 3017 */ 3018 plane_blocks = minimum[id]; 3019 plane_blocks += div_u64((uint64_t)alloc_size * data_rate, 3020 total_data_rate); 3021 3022 ddb->plane[pipe][id].start = start; 3023 ddb->plane[pipe][id].end = start + plane_blocks; 3024 3025 start += plane_blocks; 3026 3027 /* 3028 * allocation for y_plane part of planar format: 3029 */ 3030 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) { 3031 y_data_rate = skl_plane_relative_data_rate(cstate, 3032 pstate, 3033 1); 3034 y_plane_blocks = y_minimum[id]; 3035 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, 3036 total_data_rate); 3037 3038 ddb->y_plane[pipe][id].start = start; 3039 ddb->y_plane[pipe][id].end = start + y_plane_blocks; 3040 3041 start += y_plane_blocks; 3042 } 3043 3044 } 3045 3046 } 3047 3048 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) 3049 { 3050 /* TODO: Take into account the scalers once we support them */ 3051 return config->base.adjusted_mode.crtc_clock; 3052 } 3053 3054 /* 3055 * The max latency should be 257 (max the punit can code is 255 and we add 2us 3056 * for the read latency) and cpp should always be <= 8, so that 3057 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 3058 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 3059 */ 3060 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency) 3061 { 3062 uint32_t wm_intermediate_val, ret; 3063 3064 if (latency == 0) 3065 return UINT_MAX; 3066 3067 wm_intermediate_val = latency * pixel_rate * cpp / 512; 3068 ret = DIV_ROUND_UP(wm_intermediate_val, 1000); 3069 3070 return ret; 3071 } 3072 3073 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 3074 uint32_t horiz_pixels, uint8_t cpp, 3075 uint64_t tiling, uint32_t latency) 3076 { 3077 uint32_t ret; 3078 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3079 uint32_t wm_intermediate_val; 3080 3081 if (latency == 0) 3082 return UINT_MAX; 3083 3084 plane_bytes_per_line = horiz_pixels * cpp; 3085 3086 if (tiling == I915_FORMAT_MOD_Y_TILED || 3087 tiling == I915_FORMAT_MOD_Yf_TILED) { 3088 plane_bytes_per_line *= 4; 3089 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3090 plane_blocks_per_line /= 4; 3091 } else { 3092 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3093 } 3094 3095 wm_intermediate_val = latency * pixel_rate; 3096 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * 3097 plane_blocks_per_line; 3098 3099 return ret; 3100 } 3101 3102 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, 3103 const struct intel_crtc *intel_crtc) 3104 { 3105 struct drm_device *dev = intel_crtc->base.dev; 3106 struct drm_i915_private *dev_priv = dev->dev_private; 3107 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; 3108 3109 /* 3110 * If ddb allocation of pipes changed, it may require recalculation of 3111 * watermarks 3112 */ 3113 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe))) 3114 return true; 3115 3116 return false; 3117 } 3118 3119 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 3120 struct intel_crtc_state *cstate, 3121 struct intel_plane *intel_plane, 3122 uint16_t ddb_allocation, 3123 int level, 3124 uint16_t *out_blocks, /* out */ 3125 uint8_t *out_lines /* out */) 3126 { 3127 struct drm_plane *plane = &intel_plane->base; 3128 struct drm_framebuffer *fb = plane->state->fb; 3129 struct intel_plane_state *intel_pstate = 3130 to_intel_plane_state(plane->state); 3131 uint32_t latency = dev_priv->wm.skl_latency[level]; 3132 uint32_t method1, method2; 3133 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3134 uint32_t res_blocks, res_lines; 3135 uint32_t selected_result; 3136 uint8_t cpp; 3137 uint32_t width = 0, height = 0; 3138 3139 if (latency == 0 || !cstate->base.active || !intel_pstate->visible) 3140 return false; 3141 3142 width = drm_rect_width(&intel_pstate->src) >> 16; 3143 height = drm_rect_height(&intel_pstate->src) >> 16; 3144 3145 if (intel_rotation_90_or_270(plane->state->rotation)) 3146 swap(width, height); 3147 3148 cpp = drm_format_plane_cpp(fb->pixel_format, 0); 3149 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate), 3150 cpp, latency); 3151 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate), 3152 cstate->base.adjusted_mode.crtc_htotal, 3153 width, 3154 cpp, 3155 fb->modifier[0], 3156 latency); 3157 3158 plane_bytes_per_line = width * cpp; 3159 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3160 3161 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || 3162 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) { 3163 uint32_t min_scanlines = 4; 3164 uint32_t y_tile_minimum; 3165 if (intel_rotation_90_or_270(plane->state->rotation)) { 3166 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ? 3167 drm_format_plane_cpp(fb->pixel_format, 1) : 3168 drm_format_plane_cpp(fb->pixel_format, 0); 3169 3170 switch (cpp) { 3171 case 1: 3172 min_scanlines = 16; 3173 break; 3174 case 2: 3175 min_scanlines = 8; 3176 break; 3177 case 8: 3178 WARN(1, "Unsupported pixel depth for rotation"); 3179 } 3180 } 3181 y_tile_minimum = plane_blocks_per_line * min_scanlines; 3182 selected_result = max(method2, y_tile_minimum); 3183 } else { 3184 if ((ddb_allocation / plane_blocks_per_line) >= 1) 3185 selected_result = min(method1, method2); 3186 else 3187 selected_result = method1; 3188 } 3189 3190 res_blocks = selected_result + 1; 3191 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); 3192 3193 if (level >= 1 && level <= 7) { 3194 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED || 3195 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) 3196 res_lines += 4; 3197 else 3198 res_blocks++; 3199 } 3200 3201 if (res_blocks >= ddb_allocation || res_lines > 31) 3202 return false; 3203 3204 *out_blocks = res_blocks; 3205 *out_lines = res_lines; 3206 3207 return true; 3208 } 3209 3210 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, 3211 struct skl_ddb_allocation *ddb, 3212 struct intel_crtc_state *cstate, 3213 int level, 3214 struct skl_wm_level *result) 3215 { 3216 struct drm_device *dev = dev_priv->dev; 3217 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); 3218 struct intel_plane *intel_plane; 3219 uint16_t ddb_blocks; 3220 enum i915_pipe pipe = intel_crtc->pipe; 3221 3222 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { 3223 int i = skl_wm_plane_id(intel_plane); 3224 3225 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); 3226 3227 result->plane_en[i] = skl_compute_plane_wm(dev_priv, 3228 cstate, 3229 intel_plane, 3230 ddb_blocks, 3231 level, 3232 &result->plane_res_b[i], 3233 &result->plane_res_l[i]); 3234 } 3235 } 3236 3237 static uint32_t 3238 skl_compute_linetime_wm(struct intel_crtc_state *cstate) 3239 { 3240 if (!cstate->base.active) 3241 return 0; 3242 3243 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0)) 3244 return 0; 3245 3246 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000, 3247 skl_pipe_pixel_rate(cstate)); 3248 } 3249 3250 static void skl_compute_transition_wm(struct intel_crtc_state *cstate, 3251 struct skl_wm_level *trans_wm /* out */) 3252 { 3253 struct drm_crtc *crtc = cstate->base.crtc; 3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3255 struct intel_plane *intel_plane; 3256 3257 if (!cstate->base.active) 3258 return; 3259 3260 /* Until we know more, just disable transition WMs */ 3261 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) { 3262 int i = skl_wm_plane_id(intel_plane); 3263 3264 trans_wm->plane_en[i] = false; 3265 } 3266 } 3267 3268 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate, 3269 struct skl_ddb_allocation *ddb, 3270 struct skl_pipe_wm *pipe_wm) 3271 { 3272 struct drm_device *dev = cstate->base.crtc->dev; 3273 const struct drm_i915_private *dev_priv = dev->dev_private; 3274 int level, max_level = ilk_wm_max_level(dev); 3275 3276 for (level = 0; level <= max_level; level++) { 3277 skl_compute_wm_level(dev_priv, ddb, cstate, 3278 level, &pipe_wm->wm[level]); 3279 } 3280 pipe_wm->linetime = skl_compute_linetime_wm(cstate); 3281 3282 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm); 3283 } 3284 3285 static void skl_compute_wm_results(struct drm_device *dev, 3286 struct skl_pipe_wm *p_wm, 3287 struct skl_wm_values *r, 3288 struct intel_crtc *intel_crtc) 3289 { 3290 int level, max_level = ilk_wm_max_level(dev); 3291 enum i915_pipe pipe = intel_crtc->pipe; 3292 uint32_t temp; 3293 int i; 3294 3295 for (level = 0; level <= max_level; level++) { 3296 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3297 temp = 0; 3298 3299 temp |= p_wm->wm[level].plane_res_l[i] << 3300 PLANE_WM_LINES_SHIFT; 3301 temp |= p_wm->wm[level].plane_res_b[i]; 3302 if (p_wm->wm[level].plane_en[i]) 3303 temp |= PLANE_WM_EN; 3304 3305 r->plane[pipe][i][level] = temp; 3306 } 3307 3308 temp = 0; 3309 3310 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3311 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR]; 3312 3313 if (p_wm->wm[level].plane_en[PLANE_CURSOR]) 3314 temp |= PLANE_WM_EN; 3315 3316 r->plane[pipe][PLANE_CURSOR][level] = temp; 3317 3318 } 3319 3320 /* transition WMs */ 3321 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3322 temp = 0; 3323 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; 3324 temp |= p_wm->trans_wm.plane_res_b[i]; 3325 if (p_wm->trans_wm.plane_en[i]) 3326 temp |= PLANE_WM_EN; 3327 3328 r->plane_trans[pipe][i] = temp; 3329 } 3330 3331 temp = 0; 3332 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT; 3333 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR]; 3334 if (p_wm->trans_wm.plane_en[PLANE_CURSOR]) 3335 temp |= PLANE_WM_EN; 3336 3337 r->plane_trans[pipe][PLANE_CURSOR] = temp; 3338 3339 r->wm_linetime[pipe] = p_wm->linetime; 3340 } 3341 3342 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, 3343 i915_reg_t reg, 3344 const struct skl_ddb_entry *entry) 3345 { 3346 if (entry->end) 3347 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); 3348 else 3349 I915_WRITE(reg, 0); 3350 } 3351 3352 static void skl_write_wm_values(struct drm_i915_private *dev_priv, 3353 const struct skl_wm_values *new) 3354 { 3355 struct drm_device *dev = dev_priv->dev; 3356 struct intel_crtc *crtc; 3357 3358 for_each_intel_crtc(dev, crtc) { 3359 int i, level, max_level = ilk_wm_max_level(dev); 3360 enum i915_pipe pipe = crtc->pipe; 3361 3362 if (!new->dirty[pipe]) 3363 continue; 3364 3365 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); 3366 3367 for (level = 0; level <= max_level; level++) { 3368 for (i = 0; i < intel_num_planes(crtc); i++) 3369 I915_WRITE(PLANE_WM(pipe, i, level), 3370 new->plane[pipe][i][level]); 3371 I915_WRITE(CUR_WM(pipe, level), 3372 new->plane[pipe][PLANE_CURSOR][level]); 3373 } 3374 for (i = 0; i < intel_num_planes(crtc); i++) 3375 I915_WRITE(PLANE_WM_TRANS(pipe, i), 3376 new->plane_trans[pipe][i]); 3377 I915_WRITE(CUR_WM_TRANS(pipe), 3378 new->plane_trans[pipe][PLANE_CURSOR]); 3379 3380 for (i = 0; i < intel_num_planes(crtc); i++) { 3381 skl_ddb_entry_write(dev_priv, 3382 PLANE_BUF_CFG(pipe, i), 3383 &new->ddb.plane[pipe][i]); 3384 skl_ddb_entry_write(dev_priv, 3385 PLANE_NV12_BUF_CFG(pipe, i), 3386 &new->ddb.y_plane[pipe][i]); 3387 } 3388 3389 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), 3390 &new->ddb.plane[pipe][PLANE_CURSOR]); 3391 } 3392 } 3393 3394 /* 3395 * When setting up a new DDB allocation arrangement, we need to correctly 3396 * sequence the times at which the new allocations for the pipes are taken into 3397 * account or we'll have pipes fetching from space previously allocated to 3398 * another pipe. 3399 * 3400 * Roughly the sequence looks like: 3401 * 1. re-allocate the pipe(s) with the allocation being reduced and not 3402 * overlapping with a previous light-up pipe (another way to put it is: 3403 * pipes with their new allocation strickly included into their old ones). 3404 * 2. re-allocate the other pipes that get their allocation reduced 3405 * 3. allocate the pipes having their allocation increased 3406 * 3407 * Steps 1. and 2. are here to take care of the following case: 3408 * - Initially DDB looks like this: 3409 * | B | C | 3410 * - enable pipe A. 3411 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C 3412 * allocation 3413 * | A | B | C | 3414 * 3415 * We need to sequence the re-allocation: C, B, A (and not B, C, A). 3416 */ 3417 3418 static void 3419 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int pass) 3420 { 3421 int plane; 3422 3423 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); 3424 3425 for_each_plane(dev_priv, pipe, plane) { 3426 I915_WRITE(PLANE_SURF(pipe, plane), 3427 I915_READ(PLANE_SURF(pipe, plane))); 3428 } 3429 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); 3430 } 3431 3432 static bool 3433 skl_ddb_allocation_included(const struct skl_ddb_allocation *old, 3434 const struct skl_ddb_allocation *new, 3435 enum i915_pipe pipe) 3436 { 3437 uint16_t old_size, new_size; 3438 3439 old_size = skl_ddb_entry_size(&old->pipe[pipe]); 3440 new_size = skl_ddb_entry_size(&new->pipe[pipe]); 3441 3442 return old_size != new_size && 3443 new->pipe[pipe].start >= old->pipe[pipe].start && 3444 new->pipe[pipe].end <= old->pipe[pipe].end; 3445 } 3446 3447 static void skl_flush_wm_values(struct drm_i915_private *dev_priv, 3448 struct skl_wm_values *new_values) 3449 { 3450 struct drm_device *dev = dev_priv->dev; 3451 struct skl_ddb_allocation *cur_ddb, *new_ddb; 3452 bool reallocated[I915_MAX_PIPES] = {}; 3453 struct intel_crtc *crtc; 3454 enum i915_pipe pipe; 3455 3456 new_ddb = &new_values->ddb; 3457 cur_ddb = &dev_priv->wm.skl_hw.ddb; 3458 3459 /* 3460 * First pass: flush the pipes with the new allocation contained into 3461 * the old space. 3462 * 3463 * We'll wait for the vblank on those pipes to ensure we can safely 3464 * re-allocate the freed space without this pipe fetching from it. 3465 */ 3466 for_each_intel_crtc(dev, crtc) { 3467 if (!crtc->active) 3468 continue; 3469 3470 pipe = crtc->pipe; 3471 3472 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) 3473 continue; 3474 3475 skl_wm_flush_pipe(dev_priv, pipe, 1); 3476 intel_wait_for_vblank(dev, pipe); 3477 3478 reallocated[pipe] = true; 3479 } 3480 3481 3482 /* 3483 * Second pass: flush the pipes that are having their allocation 3484 * reduced, but overlapping with a previous allocation. 3485 * 3486 * Here as well we need to wait for the vblank to make sure the freed 3487 * space is not used anymore. 3488 */ 3489 for_each_intel_crtc(dev, crtc) { 3490 if (!crtc->active) 3491 continue; 3492 3493 pipe = crtc->pipe; 3494 3495 if (reallocated[pipe]) 3496 continue; 3497 3498 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < 3499 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { 3500 skl_wm_flush_pipe(dev_priv, pipe, 2); 3501 intel_wait_for_vblank(dev, pipe); 3502 reallocated[pipe] = true; 3503 } 3504 } 3505 3506 /* 3507 * Third pass: flush the pipes that got more space allocated. 3508 * 3509 * We don't need to actively wait for the update here, next vblank 3510 * will just get more DDB space with the correct WM values. 3511 */ 3512 for_each_intel_crtc(dev, crtc) { 3513 if (!crtc->active) 3514 continue; 3515 3516 pipe = crtc->pipe; 3517 3518 /* 3519 * At this point, only the pipes more space than before are 3520 * left to re-allocate. 3521 */ 3522 if (reallocated[pipe]) 3523 continue; 3524 3525 skl_wm_flush_pipe(dev_priv, pipe, 3); 3526 } 3527 } 3528 3529 static bool skl_update_pipe_wm(struct drm_crtc *crtc, 3530 struct skl_ddb_allocation *ddb, /* out */ 3531 struct skl_pipe_wm *pipe_wm /* out */) 3532 { 3533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3534 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3535 3536 skl_allocate_pipe_ddb(cstate, ddb); 3537 skl_compute_pipe_wm(cstate, ddb, pipe_wm); 3538 3539 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm))) 3540 return false; 3541 3542 intel_crtc->wm.active.skl = *pipe_wm; 3543 3544 return true; 3545 } 3546 3547 static void skl_update_other_pipe_wm(struct drm_device *dev, 3548 struct drm_crtc *crtc, 3549 struct skl_wm_values *r) 3550 { 3551 struct intel_crtc *intel_crtc; 3552 struct intel_crtc *this_crtc = to_intel_crtc(crtc); 3553 3554 /* 3555 * If the WM update hasn't changed the allocation for this_crtc (the 3556 * crtc we are currently computing the new WM values for), other 3557 * enabled crtcs will keep the same allocation and we don't need to 3558 * recompute anything for them. 3559 */ 3560 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) 3561 return; 3562 3563 /* 3564 * Otherwise, because of this_crtc being freshly enabled/disabled, the 3565 * other active pipes need new DDB allocation and WM values. 3566 */ 3567 for_each_intel_crtc(dev, intel_crtc) { 3568 struct skl_pipe_wm pipe_wm = {}; 3569 bool wm_changed; 3570 3571 if (this_crtc->pipe == intel_crtc->pipe) 3572 continue; 3573 3574 if (!intel_crtc->active) 3575 continue; 3576 3577 wm_changed = skl_update_pipe_wm(&intel_crtc->base, 3578 &r->ddb, &pipe_wm); 3579 3580 /* 3581 * If we end up re-computing the other pipe WM values, it's 3582 * because it was really needed, so we expect the WM values to 3583 * be different. 3584 */ 3585 WARN_ON(!wm_changed); 3586 3587 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc); 3588 r->dirty[intel_crtc->pipe] = true; 3589 } 3590 } 3591 3592 static void skl_clear_wm(struct skl_wm_values *watermarks, enum i915_pipe pipe) 3593 { 3594 watermarks->wm_linetime[pipe] = 0; 3595 memset(watermarks->plane[pipe], 0, 3596 sizeof(uint32_t) * 8 * I915_MAX_PLANES); 3597 memset(watermarks->plane_trans[pipe], 3598 0, sizeof(uint32_t) * I915_MAX_PLANES); 3599 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0; 3600 3601 /* Clear ddb entries for pipe */ 3602 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry)); 3603 memset(&watermarks->ddb.plane[pipe], 0, 3604 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3605 memset(&watermarks->ddb.y_plane[pipe], 0, 3606 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES); 3607 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0, 3608 sizeof(struct skl_ddb_entry)); 3609 3610 } 3611 3612 static void skl_update_wm(struct drm_crtc *crtc) 3613 { 3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3615 struct drm_device *dev = crtc->dev; 3616 struct drm_i915_private *dev_priv = dev->dev_private; 3617 struct skl_wm_values *results = &dev_priv->wm.skl_results; 3618 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3619 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl; 3620 3621 3622 /* Clear all dirty flags */ 3623 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES); 3624 3625 skl_clear_wm(results, intel_crtc->pipe); 3626 3627 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm)) 3628 return; 3629 3630 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc); 3631 results->dirty[intel_crtc->pipe] = true; 3632 3633 skl_update_other_pipe_wm(dev, crtc, results); 3634 skl_write_wm_values(dev_priv, results); 3635 skl_flush_wm_values(dev_priv, results); 3636 3637 /* store the new configuration */ 3638 dev_priv->wm.skl_hw = *results; 3639 } 3640 3641 static void ilk_compute_wm_config(struct drm_device *dev, 3642 struct intel_wm_config *config) 3643 { 3644 struct intel_crtc *crtc; 3645 3646 /* Compute the currently _active_ config */ 3647 for_each_intel_crtc(dev, crtc) { 3648 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; 3649 3650 if (!wm->pipe_enabled) 3651 continue; 3652 3653 config->sprites_enabled |= wm->sprites_enabled; 3654 config->sprites_scaled |= wm->sprites_scaled; 3655 config->num_pipes_active++; 3656 } 3657 } 3658 3659 static void ilk_program_watermarks(struct intel_crtc_state *cstate) 3660 { 3661 struct drm_crtc *crtc = cstate->base.crtc; 3662 struct drm_device *dev = crtc->dev; 3663 struct drm_i915_private *dev_priv = to_i915(dev); 3664 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; 3665 struct ilk_wm_maximums max; 3666 struct intel_wm_config config = {}; 3667 struct ilk_wm_values results = {}; 3668 enum intel_ddb_partitioning partitioning; 3669 3670 ilk_compute_wm_config(dev, &config); 3671 3672 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); 3673 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); 3674 3675 /* 5/6 split only in single pipe config on IVB+ */ 3676 if (INTEL_INFO(dev)->gen >= 7 && 3677 config.num_pipes_active == 1 && config.sprites_enabled) { 3678 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); 3679 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); 3680 3681 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); 3682 } else { 3683 best_lp_wm = &lp_wm_1_2; 3684 } 3685 3686 partitioning = (best_lp_wm == &lp_wm_1_2) ? 3687 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; 3688 3689 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); 3690 3691 ilk_write_wm_values(dev_priv, &results); 3692 } 3693 3694 static void ilk_update_wm(struct drm_crtc *crtc) 3695 { 3696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3697 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3698 3699 WARN_ON(cstate->base.active != intel_crtc->active); 3700 3701 /* 3702 * IVB workaround: must disable low power watermarks for at least 3703 * one frame before enabling scaling. LP watermarks can be re-enabled 3704 * when scaling is disabled. 3705 * 3706 * WaCxSRDisabledForSpriteScaling:ivb 3707 */ 3708 if (cstate->disable_lp_wm) { 3709 ilk_disable_lp_wm(crtc->dev); 3710 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe); 3711 } 3712 3713 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk; 3714 3715 ilk_program_watermarks(cstate); 3716 } 3717 3718 static void skl_pipe_wm_active_state(uint32_t val, 3719 struct skl_pipe_wm *active, 3720 bool is_transwm, 3721 bool is_cursor, 3722 int i, 3723 int level) 3724 { 3725 bool is_enabled = (val & PLANE_WM_EN) != 0; 3726 3727 if (!is_transwm) { 3728 if (!is_cursor) { 3729 active->wm[level].plane_en[i] = is_enabled; 3730 active->wm[level].plane_res_b[i] = 3731 val & PLANE_WM_BLOCKS_MASK; 3732 active->wm[level].plane_res_l[i] = 3733 (val >> PLANE_WM_LINES_SHIFT) & 3734 PLANE_WM_LINES_MASK; 3735 } else { 3736 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled; 3737 active->wm[level].plane_res_b[PLANE_CURSOR] = 3738 val & PLANE_WM_BLOCKS_MASK; 3739 active->wm[level].plane_res_l[PLANE_CURSOR] = 3740 (val >> PLANE_WM_LINES_SHIFT) & 3741 PLANE_WM_LINES_MASK; 3742 } 3743 } else { 3744 if (!is_cursor) { 3745 active->trans_wm.plane_en[i] = is_enabled; 3746 active->trans_wm.plane_res_b[i] = 3747 val & PLANE_WM_BLOCKS_MASK; 3748 active->trans_wm.plane_res_l[i] = 3749 (val >> PLANE_WM_LINES_SHIFT) & 3750 PLANE_WM_LINES_MASK; 3751 } else { 3752 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled; 3753 active->trans_wm.plane_res_b[PLANE_CURSOR] = 3754 val & PLANE_WM_BLOCKS_MASK; 3755 active->trans_wm.plane_res_l[PLANE_CURSOR] = 3756 (val >> PLANE_WM_LINES_SHIFT) & 3757 PLANE_WM_LINES_MASK; 3758 } 3759 } 3760 } 3761 3762 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3763 { 3764 struct drm_device *dev = crtc->dev; 3765 struct drm_i915_private *dev_priv = dev->dev_private; 3766 struct skl_wm_values *hw = &dev_priv->wm.skl_hw; 3767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3768 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3769 struct skl_pipe_wm *active = &cstate->wm.optimal.skl; 3770 enum i915_pipe pipe = intel_crtc->pipe; 3771 int level, i, max_level; 3772 uint32_t temp; 3773 3774 max_level = ilk_wm_max_level(dev); 3775 3776 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3777 3778 for (level = 0; level <= max_level; level++) { 3779 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3780 hw->plane[pipe][i][level] = 3781 I915_READ(PLANE_WM(pipe, i, level)); 3782 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level)); 3783 } 3784 3785 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3786 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); 3787 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe)); 3788 3789 if (!intel_crtc->active) 3790 return; 3791 3792 hw->dirty[pipe] = true; 3793 3794 active->linetime = hw->wm_linetime[pipe]; 3795 3796 for (level = 0; level <= max_level; level++) { 3797 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3798 temp = hw->plane[pipe][i][level]; 3799 skl_pipe_wm_active_state(temp, active, false, 3800 false, i, level); 3801 } 3802 temp = hw->plane[pipe][PLANE_CURSOR][level]; 3803 skl_pipe_wm_active_state(temp, active, false, true, i, level); 3804 } 3805 3806 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3807 temp = hw->plane_trans[pipe][i]; 3808 skl_pipe_wm_active_state(temp, active, true, false, i, 0); 3809 } 3810 3811 temp = hw->plane_trans[pipe][PLANE_CURSOR]; 3812 skl_pipe_wm_active_state(temp, active, true, true, i, 0); 3813 3814 intel_crtc->wm.active.skl = *active; 3815 } 3816 3817 void skl_wm_get_hw_state(struct drm_device *dev) 3818 { 3819 struct drm_i915_private *dev_priv = dev->dev_private; 3820 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; 3821 struct drm_crtc *crtc; 3822 3823 skl_ddb_get_hw_state(dev_priv, ddb); 3824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3825 skl_pipe_wm_get_hw_state(crtc); 3826 } 3827 3828 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3829 { 3830 struct drm_device *dev = crtc->dev; 3831 struct drm_i915_private *dev_priv = dev->dev_private; 3832 struct ilk_wm_values *hw = &dev_priv->wm.hw; 3833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3834 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); 3835 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk; 3836 enum i915_pipe pipe = intel_crtc->pipe; 3837 static const i915_reg_t wm0_pipe_reg[] = { 3838 [PIPE_A] = WM0_PIPEA_ILK, 3839 [PIPE_B] = WM0_PIPEB_ILK, 3840 [PIPE_C] = WM0_PIPEC_IVB, 3841 }; 3842 3843 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); 3844 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3845 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3846 3847 active->pipe_enabled = intel_crtc->active; 3848 3849 if (active->pipe_enabled) { 3850 u32 tmp = hw->wm_pipe[pipe]; 3851 3852 /* 3853 * For active pipes LP0 watermark is marked as 3854 * enabled, and LP1+ watermaks as disabled since 3855 * we can't really reverse compute them in case 3856 * multiple pipes are active. 3857 */ 3858 active->wm[0].enable = true; 3859 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; 3860 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; 3861 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; 3862 active->linetime = hw->wm_linetime[pipe]; 3863 } else { 3864 int level, max_level = ilk_wm_max_level(dev); 3865 3866 /* 3867 * For inactive pipes, all watermark levels 3868 * should be marked as enabled but zeroed, 3869 * which is what we'd compute them to. 3870 */ 3871 for (level = 0; level <= max_level; level++) 3872 active->wm[level].enable = true; 3873 } 3874 3875 intel_crtc->wm.active.ilk = *active; 3876 } 3877 3878 #define _FW_WM(value, plane) \ 3879 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) 3880 #define _FW_WM_VLV(value, plane) \ 3881 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) 3882 3883 static void vlv_read_wm_values(struct drm_i915_private *dev_priv, 3884 struct vlv_wm_values *wm) 3885 { 3886 enum i915_pipe pipe; 3887 uint32_t tmp; 3888 3889 for_each_pipe(dev_priv, pipe) { 3890 tmp = I915_READ(VLV_DDL(pipe)); 3891 3892 wm->ddl[pipe].primary = 3893 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3894 wm->ddl[pipe].cursor = 3895 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3896 wm->ddl[pipe].sprite[0] = 3897 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3898 wm->ddl[pipe].sprite[1] = 3899 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3900 } 3901 3902 tmp = I915_READ(DSPFW1); 3903 wm->sr.plane = _FW_WM(tmp, SR); 3904 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); 3905 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); 3906 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); 3907 3908 tmp = I915_READ(DSPFW2); 3909 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); 3910 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); 3911 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); 3912 3913 tmp = I915_READ(DSPFW3); 3914 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); 3915 3916 if (IS_CHERRYVIEW(dev_priv)) { 3917 tmp = I915_READ(DSPFW7_CHV); 3918 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 3919 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 3920 3921 tmp = I915_READ(DSPFW8_CHV); 3922 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); 3923 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); 3924 3925 tmp = I915_READ(DSPFW9_CHV); 3926 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); 3927 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); 3928 3929 tmp = I915_READ(DSPHOWM); 3930 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 3931 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; 3932 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; 3933 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; 3934 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 3935 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 3936 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 3937 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 3938 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 3939 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 3940 } else { 3941 tmp = I915_READ(DSPFW7); 3942 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 3943 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 3944 3945 tmp = I915_READ(DSPHOWM); 3946 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 3947 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 3948 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 3949 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 3950 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 3951 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 3952 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 3953 } 3954 } 3955 3956 #undef _FW_WM 3957 #undef _FW_WM_VLV 3958 3959 void vlv_wm_get_hw_state(struct drm_device *dev) 3960 { 3961 struct drm_i915_private *dev_priv = to_i915(dev); 3962 struct vlv_wm_values *wm = &dev_priv->wm.vlv; 3963 struct intel_plane *plane; 3964 enum i915_pipe pipe; 3965 u32 val; 3966 3967 vlv_read_wm_values(dev_priv, wm); 3968 3969 for_each_intel_plane(dev, plane) { 3970 switch (plane->base.type) { 3971 int sprite; 3972 case DRM_PLANE_TYPE_CURSOR: 3973 plane->wm.fifo_size = 63; 3974 break; 3975 case DRM_PLANE_TYPE_PRIMARY: 3976 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); 3977 break; 3978 case DRM_PLANE_TYPE_OVERLAY: 3979 sprite = plane->plane; 3980 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); 3981 break; 3982 } 3983 } 3984 3985 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 3986 wm->level = VLV_WM_LEVEL_PM2; 3987 3988 if (IS_CHERRYVIEW(dev_priv)) { 3989 mutex_lock(&dev_priv->rps.hw_lock); 3990 3991 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 3992 if (val & DSP_MAXFIFO_PM5_ENABLE) 3993 wm->level = VLV_WM_LEVEL_PM5; 3994 3995 /* 3996 * If DDR DVFS is disabled in the BIOS, Punit 3997 * will never ack the request. So if that happens 3998 * assume we don't have to enable/disable DDR DVFS 3999 * dynamically. To test that just set the REQ_ACK 4000 * bit to poke the Punit, but don't change the 4001 * HIGH/LOW bits so that we don't actually change 4002 * the current state. 4003 */ 4004 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4005 val |= FORCE_DDR_FREQ_REQ_ACK; 4006 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 4007 4008 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 4009 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { 4010 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " 4011 "assuming DDR DVFS is disabled\n"); 4012 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; 4013 } else { 4014 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4015 if ((val & FORCE_DDR_HIGH_FREQ) == 0) 4016 wm->level = VLV_WM_LEVEL_DDR_DVFS; 4017 } 4018 4019 mutex_unlock(&dev_priv->rps.hw_lock); 4020 } 4021 4022 for_each_pipe(dev_priv, pipe) 4023 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", 4024 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, 4025 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); 4026 4027 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", 4028 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); 4029 } 4030 4031 void ilk_wm_get_hw_state(struct drm_device *dev) 4032 { 4033 struct drm_i915_private *dev_priv = dev->dev_private; 4034 struct ilk_wm_values *hw = &dev_priv->wm.hw; 4035 struct drm_crtc *crtc; 4036 4037 for_each_crtc(dev, crtc) 4038 ilk_pipe_wm_get_hw_state(crtc); 4039 4040 hw->wm_lp[0] = I915_READ(WM1_LP_ILK); 4041 hw->wm_lp[1] = I915_READ(WM2_LP_ILK); 4042 hw->wm_lp[2] = I915_READ(WM3_LP_ILK); 4043 4044 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); 4045 if (INTEL_INFO(dev)->gen >= 7) { 4046 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); 4047 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); 4048 } 4049 4050 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4051 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? 4052 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4053 else if (IS_IVYBRIDGE(dev)) 4054 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? 4055 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4056 4057 hw->enable_fbc_wm = 4058 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); 4059 } 4060 4061 /** 4062 * intel_update_watermarks - update FIFO watermark values based on current modes 4063 * 4064 * Calculate watermark values for the various WM regs based on current mode 4065 * and plane configuration. 4066 * 4067 * There are several cases to deal with here: 4068 * - normal (i.e. non-self-refresh) 4069 * - self-refresh (SR) mode 4070 * - lines are large relative to FIFO size (buffer can hold up to 2) 4071 * - lines are small relative to FIFO size (buffer can hold more than 2 4072 * lines), so need to account for TLB latency 4073 * 4074 * The normal calculation is: 4075 * watermark = dotclock * bytes per pixel * latency 4076 * where latency is platform & configuration dependent (we assume pessimal 4077 * values here). 4078 * 4079 * The SR calculation is: 4080 * watermark = (trunc(latency/line time)+1) * surface width * 4081 * bytes per pixel 4082 * where 4083 * line time = htotal / dotclock 4084 * surface width = hdisplay for normal plane and 64 for cursor 4085 * and latency is assumed to be high, as above. 4086 * 4087 * The final value programmed to the register should always be rounded up, 4088 * and include an extra 2 entries to account for clock crossings. 4089 * 4090 * We don't use the sprite, so we can ignore that. And on Crestline we have 4091 * to set the non-SR watermarks to 8. 4092 */ 4093 void intel_update_watermarks(struct drm_crtc *crtc) 4094 { 4095 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 4096 4097 if (dev_priv->display.update_wm) 4098 dev_priv->display.update_wm(crtc); 4099 } 4100 4101 /* 4102 * Lock protecting IPS related data structures 4103 */ 4104 struct lock mchdev_lock; 4105 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE); 4106 4107 /* Global for IPS driver to get at the current i915 device. Protected by 4108 * mchdev_lock. */ 4109 static struct drm_i915_private *i915_mch_dev; 4110 4111 bool ironlake_set_drps(struct drm_device *dev, u8 val) 4112 { 4113 struct drm_i915_private *dev_priv = dev->dev_private; 4114 u16 rgvswctl; 4115 4116 assert_spin_locked(&mchdev_lock); 4117 4118 rgvswctl = I915_READ16(MEMSWCTL); 4119 if (rgvswctl & MEMCTL_CMD_STS) { 4120 DRM_DEBUG("gpu busy, RCS change rejected\n"); 4121 return false; /* still busy with another command */ 4122 } 4123 4124 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 4125 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 4126 I915_WRITE16(MEMSWCTL, rgvswctl); 4127 POSTING_READ16(MEMSWCTL); 4128 4129 rgvswctl |= MEMCTL_CMD_STS; 4130 I915_WRITE16(MEMSWCTL, rgvswctl); 4131 4132 return true; 4133 } 4134 4135 static void ironlake_enable_drps(struct drm_device *dev) 4136 { 4137 struct drm_i915_private *dev_priv = dev->dev_private; 4138 u32 rgvmodectl; 4139 u8 fmax, fmin, fstart, vstart; 4140 4141 spin_lock_irq(&mchdev_lock); 4142 4143 rgvmodectl = I915_READ(MEMMODECTL); 4144 4145 /* Enable temp reporting */ 4146 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 4147 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 4148 4149 /* 100ms RC evaluation intervals */ 4150 I915_WRITE(RCUPEI, 100000); 4151 I915_WRITE(RCDNEI, 100000); 4152 4153 /* Set max/min thresholds to 90ms and 80ms respectively */ 4154 I915_WRITE(RCBMAXAVG, 90000); 4155 I915_WRITE(RCBMINAVG, 80000); 4156 4157 I915_WRITE(MEMIHYST, 1); 4158 4159 /* Set up min, max, and cur for interrupt handling */ 4160 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 4161 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 4162 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 4163 MEMMODE_FSTART_SHIFT; 4164 4165 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> 4166 PXVFREQ_PX_SHIFT; 4167 4168 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 4169 dev_priv->ips.fstart = fstart; 4170 4171 dev_priv->ips.max_delay = fstart; 4172 dev_priv->ips.min_delay = fmin; 4173 dev_priv->ips.cur_delay = fstart; 4174 4175 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 4176 fmax, fmin, fstart); 4177 4178 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 4179 4180 /* 4181 * Interrupts will be enabled in ironlake_irq_postinstall 4182 */ 4183 4184 I915_WRITE(VIDSTART, vstart); 4185 POSTING_READ(VIDSTART); 4186 4187 rgvmodectl |= MEMMODE_SWMODE_EN; 4188 I915_WRITE(MEMMODECTL, rgvmodectl); 4189 4190 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 4191 DRM_ERROR("stuck trying to change perf mode\n"); 4192 mdelay(1); 4193 4194 ironlake_set_drps(dev, fstart); 4195 4196 dev_priv->ips.last_count1 = I915_READ(DMIEC) + 4197 I915_READ(DDREC) + I915_READ(CSIEC); 4198 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 4199 dev_priv->ips.last_count2 = I915_READ(GFXEC); 4200 dev_priv->ips.last_time2 = ktime_get_raw_ns(); 4201 4202 spin_unlock_irq(&mchdev_lock); 4203 } 4204 4205 static void ironlake_disable_drps(struct drm_device *dev) 4206 { 4207 struct drm_i915_private *dev_priv = dev->dev_private; 4208 u16 rgvswctl; 4209 4210 spin_lock_irq(&mchdev_lock); 4211 4212 rgvswctl = I915_READ16(MEMSWCTL); 4213 4214 /* Ack interrupts, disable EFC interrupt */ 4215 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 4216 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 4217 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 4218 I915_WRITE(DEIIR, DE_PCU_EVENT); 4219 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 4220 4221 /* Go back to the starting frequency */ 4222 ironlake_set_drps(dev, dev_priv->ips.fstart); 4223 mdelay(1); 4224 rgvswctl |= MEMCTL_CMD_STS; 4225 I915_WRITE(MEMSWCTL, rgvswctl); 4226 mdelay(1); 4227 4228 spin_unlock_irq(&mchdev_lock); 4229 } 4230 4231 /* There's a funny hw issue where the hw returns all 0 when reading from 4232 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 4233 * ourselves, instead of doing a rmw cycle (which might result in us clearing 4234 * all limits and the gpu stuck at whatever frequency it is at atm). 4235 */ 4236 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) 4237 { 4238 u32 limits; 4239 4240 /* Only set the down limit when we've reached the lowest level to avoid 4241 * getting more interrupts, otherwise leave this clear. This prevents a 4242 * race in the hw when coming out of rc6: There's a tiny window where 4243 * the hw runs at the minimal clock before selecting the desired 4244 * frequency, if the down threshold expires in that window we will not 4245 * receive a down interrupt. */ 4246 if (IS_GEN9(dev_priv->dev)) { 4247 limits = (dev_priv->rps.max_freq_softlimit) << 23; 4248 if (val <= dev_priv->rps.min_freq_softlimit) 4249 limits |= (dev_priv->rps.min_freq_softlimit) << 14; 4250 } else { 4251 limits = dev_priv->rps.max_freq_softlimit << 24; 4252 if (val <= dev_priv->rps.min_freq_softlimit) 4253 limits |= dev_priv->rps.min_freq_softlimit << 16; 4254 } 4255 4256 return limits; 4257 } 4258 4259 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) 4260 { 4261 int new_power; 4262 u32 threshold_up = 0, threshold_down = 0; /* in % */ 4263 u32 ei_up = 0, ei_down = 0; 4264 4265 new_power = dev_priv->rps.power; 4266 switch (dev_priv->rps.power) { 4267 case LOW_POWER: 4268 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) 4269 new_power = BETWEEN; 4270 break; 4271 4272 case BETWEEN: 4273 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) 4274 new_power = LOW_POWER; 4275 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) 4276 new_power = HIGH_POWER; 4277 break; 4278 4279 case HIGH_POWER: 4280 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) 4281 new_power = BETWEEN; 4282 break; 4283 } 4284 /* Max/min bins are special */ 4285 if (val <= dev_priv->rps.min_freq_softlimit) 4286 new_power = LOW_POWER; 4287 if (val >= dev_priv->rps.max_freq_softlimit) 4288 new_power = HIGH_POWER; 4289 if (new_power == dev_priv->rps.power) 4290 return; 4291 4292 /* Note the units here are not exactly 1us, but 1280ns. */ 4293 switch (new_power) { 4294 case LOW_POWER: 4295 /* Upclock if more than 95% busy over 16ms */ 4296 ei_up = 16000; 4297 threshold_up = 95; 4298 4299 /* Downclock if less than 85% busy over 32ms */ 4300 ei_down = 32000; 4301 threshold_down = 85; 4302 break; 4303 4304 case BETWEEN: 4305 /* Upclock if more than 90% busy over 13ms */ 4306 ei_up = 13000; 4307 threshold_up = 90; 4308 4309 /* Downclock if less than 75% busy over 32ms */ 4310 ei_down = 32000; 4311 threshold_down = 75; 4312 break; 4313 4314 case HIGH_POWER: 4315 /* Upclock if more than 85% busy over 10ms */ 4316 ei_up = 10000; 4317 threshold_up = 85; 4318 4319 /* Downclock if less than 60% busy over 32ms */ 4320 ei_down = 32000; 4321 threshold_down = 60; 4322 break; 4323 } 4324 4325 I915_WRITE(GEN6_RP_UP_EI, 4326 GT_INTERVAL_FROM_US(dev_priv, ei_up)); 4327 I915_WRITE(GEN6_RP_UP_THRESHOLD, 4328 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); 4329 4330 I915_WRITE(GEN6_RP_DOWN_EI, 4331 GT_INTERVAL_FROM_US(dev_priv, ei_down)); 4332 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 4333 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); 4334 4335 I915_WRITE(GEN6_RP_CONTROL, 4336 GEN6_RP_MEDIA_TURBO | 4337 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4338 GEN6_RP_MEDIA_IS_GFX | 4339 GEN6_RP_ENABLE | 4340 GEN6_RP_UP_BUSY_AVG | 4341 GEN6_RP_DOWN_IDLE_AVG); 4342 4343 dev_priv->rps.power = new_power; 4344 dev_priv->rps.up_threshold = threshold_up; 4345 dev_priv->rps.down_threshold = threshold_down; 4346 dev_priv->rps.last_adj = 0; 4347 } 4348 4349 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) 4350 { 4351 u32 mask = 0; 4352 4353 if (val > dev_priv->rps.min_freq_softlimit) 4354 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; 4355 if (val < dev_priv->rps.max_freq_softlimit) 4356 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 4357 4358 mask &= dev_priv->pm_rps_events; 4359 4360 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); 4361 } 4362 4363 /* gen6_set_rps is called to update the frequency request, but should also be 4364 * called when the range (min_delay and max_delay) is modified so that we can 4365 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ 4366 static void gen6_set_rps(struct drm_device *dev, u8 val) 4367 { 4368 struct drm_i915_private *dev_priv = dev->dev_private; 4369 4370 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4371 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) 4372 return; 4373 4374 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4375 WARN_ON(val > dev_priv->rps.max_freq); 4376 WARN_ON(val < dev_priv->rps.min_freq); 4377 4378 /* min/max delay may still have been modified so be sure to 4379 * write the limits value. 4380 */ 4381 if (val != dev_priv->rps.cur_freq) { 4382 gen6_set_rps_thresholds(dev_priv, val); 4383 4384 if (IS_GEN9(dev)) 4385 I915_WRITE(GEN6_RPNSWREQ, 4386 GEN9_FREQUENCY(val)); 4387 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4388 I915_WRITE(GEN6_RPNSWREQ, 4389 HSW_FREQUENCY(val)); 4390 else 4391 I915_WRITE(GEN6_RPNSWREQ, 4392 GEN6_FREQUENCY(val) | 4393 GEN6_OFFSET(0) | 4394 GEN6_AGGRESSIVE_TURBO); 4395 } 4396 4397 /* Make sure we continue to get interrupts 4398 * until we hit the minimum or maximum frequencies. 4399 */ 4400 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); 4401 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4402 4403 POSTING_READ(GEN6_RPNSWREQ); 4404 4405 dev_priv->rps.cur_freq = val; 4406 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4407 } 4408 4409 static void valleyview_set_rps(struct drm_device *dev, u8 val) 4410 { 4411 struct drm_i915_private *dev_priv = dev->dev_private; 4412 4413 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4414 WARN_ON(val > dev_priv->rps.max_freq); 4415 WARN_ON(val < dev_priv->rps.min_freq); 4416 4417 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), 4418 "Odd GPU freq value\n")) 4419 val &= ~1; 4420 4421 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4422 4423 if (val != dev_priv->rps.cur_freq) { 4424 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 4425 if (!IS_CHERRYVIEW(dev_priv)) 4426 gen6_set_rps_thresholds(dev_priv, val); 4427 } 4428 4429 dev_priv->rps.cur_freq = val; 4430 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4431 } 4432 4433 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down 4434 * 4435 * * If Gfx is Idle, then 4436 * 1. Forcewake Media well. 4437 * 2. Request idle freq. 4438 * 3. Release Forcewake of Media well. 4439 */ 4440 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) 4441 { 4442 u32 val = dev_priv->rps.idle_freq; 4443 4444 if (dev_priv->rps.cur_freq <= val) 4445 return; 4446 4447 /* Wake up the media well, as that takes a lot less 4448 * power than the Render well. */ 4449 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); 4450 valleyview_set_rps(dev_priv->dev, val); 4451 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); 4452 } 4453 4454 void gen6_rps_busy(struct drm_i915_private *dev_priv) 4455 { 4456 mutex_lock(&dev_priv->rps.hw_lock); 4457 if (dev_priv->rps.enabled) { 4458 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) 4459 gen6_rps_reset_ei(dev_priv); 4460 I915_WRITE(GEN6_PMINTRMSK, 4461 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); 4462 } 4463 mutex_unlock(&dev_priv->rps.hw_lock); 4464 } 4465 4466 void gen6_rps_idle(struct drm_i915_private *dev_priv) 4467 { 4468 struct drm_device *dev = dev_priv->dev; 4469 4470 mutex_lock(&dev_priv->rps.hw_lock); 4471 if (dev_priv->rps.enabled) { 4472 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 4473 vlv_set_rps_idle(dev_priv); 4474 else 4475 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4476 dev_priv->rps.last_adj = 0; 4477 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 4478 } 4479 mutex_unlock(&dev_priv->rps.hw_lock); 4480 4481 lockmgr(&dev_priv->rps.client_lock, LK_EXCLUSIVE); 4482 while (!list_empty(&dev_priv->rps.clients)) 4483 list_del_init(dev_priv->rps.clients.next); 4484 lockmgr(&dev_priv->rps.client_lock, LK_RELEASE); 4485 } 4486 4487 void gen6_rps_boost(struct drm_i915_private *dev_priv, 4488 struct intel_rps_client *rps, 4489 unsigned long submitted) 4490 { 4491 /* This is intentionally racy! We peek at the state here, then 4492 * validate inside the RPS worker. 4493 */ 4494 if (!(dev_priv->mm.busy && 4495 dev_priv->rps.enabled && 4496 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) 4497 return; 4498 4499 /* Force a RPS boost (and don't count it against the client) if 4500 * the GPU is severely congested. 4501 */ 4502 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) 4503 rps = NULL; 4504 4505 lockmgr(&dev_priv->rps.client_lock, LK_EXCLUSIVE); 4506 if (rps == NULL || list_empty(&rps->link)) { 4507 spin_lock_irq(&dev_priv->irq_lock); 4508 if (dev_priv->rps.interrupts_enabled) { 4509 dev_priv->rps.client_boost = true; 4510 queue_work(dev_priv->wq, &dev_priv->rps.work); 4511 } 4512 spin_unlock_irq(&dev_priv->irq_lock); 4513 4514 if (rps != NULL) { 4515 list_add(&rps->link, &dev_priv->rps.clients); 4516 rps->boosts++; 4517 } else 4518 dev_priv->rps.boosts++; 4519 } 4520 lockmgr(&dev_priv->rps.client_lock, LK_RELEASE); 4521 } 4522 4523 void intel_set_rps(struct drm_device *dev, u8 val) 4524 { 4525 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 4526 valleyview_set_rps(dev, val); 4527 else 4528 gen6_set_rps(dev, val); 4529 } 4530 4531 static void gen9_disable_rps(struct drm_device *dev) 4532 { 4533 struct drm_i915_private *dev_priv = dev->dev_private; 4534 4535 I915_WRITE(GEN6_RC_CONTROL, 0); 4536 I915_WRITE(GEN9_PG_ENABLE, 0); 4537 } 4538 4539 static void gen6_disable_rps(struct drm_device *dev) 4540 { 4541 struct drm_i915_private *dev_priv = dev->dev_private; 4542 4543 I915_WRITE(GEN6_RC_CONTROL, 0); 4544 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 4545 } 4546 4547 static void cherryview_disable_rps(struct drm_device *dev) 4548 { 4549 struct drm_i915_private *dev_priv = dev->dev_private; 4550 4551 I915_WRITE(GEN6_RC_CONTROL, 0); 4552 } 4553 4554 static void valleyview_disable_rps(struct drm_device *dev) 4555 { 4556 struct drm_i915_private *dev_priv = dev->dev_private; 4557 4558 /* we're doing forcewake before Disabling RC6, 4559 * This what the BIOS expects when going into suspend */ 4560 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4561 4562 I915_WRITE(GEN6_RC_CONTROL, 0); 4563 4564 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4565 } 4566 4567 static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 4568 { 4569 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 4570 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) 4571 mode = GEN6_RC_CTL_RC6_ENABLE; 4572 else 4573 mode = 0; 4574 } 4575 if (HAS_RC6p(dev)) 4576 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", 4577 onoff(mode & GEN6_RC_CTL_RC6_ENABLE), 4578 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE), 4579 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE)); 4580 4581 else 4582 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", 4583 onoff(mode & GEN6_RC_CTL_RC6_ENABLE)); 4584 } 4585 4586 static bool bxt_check_bios_rc6_setup(const struct drm_device *dev) 4587 { 4588 struct drm_i915_private *dev_priv = dev->dev_private; 4589 bool enable_rc6 = true; 4590 unsigned long rc6_ctx_base; 4591 4592 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) { 4593 DRM_DEBUG_KMS("RC6 Base location not set properly.\n"); 4594 enable_rc6 = false; 4595 } 4596 4597 /* 4598 * The exact context size is not known for BXT, so assume a page size 4599 * for this check. 4600 */ 4601 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; 4602 if (!((rc6_ctx_base >= dev_priv->gtt.stolen_reserved_base) && 4603 (rc6_ctx_base + PAGE_SIZE <= dev_priv->gtt.stolen_reserved_base + 4604 dev_priv->gtt.stolen_reserved_size))) { 4605 DRM_DEBUG_KMS("RC6 Base address not as expected.\n"); 4606 enable_rc6 = false; 4607 } 4608 4609 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) && 4610 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) && 4611 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) && 4612 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) { 4613 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n"); 4614 enable_rc6 = false; 4615 } 4616 4617 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE | 4618 GEN6_RC_CTL_HW_ENABLE)) && 4619 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) || 4620 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) { 4621 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n"); 4622 enable_rc6 = false; 4623 } 4624 4625 return enable_rc6; 4626 } 4627 4628 int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) 4629 { 4630 /* No RC6 before Ironlake and code is gone for ilk. */ 4631 if (INTEL_INFO(dev)->gen < 6) 4632 return 0; 4633 4634 if (!enable_rc6) 4635 return 0; 4636 4637 if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) { 4638 DRM_INFO("RC6 disabled by BIOS\n"); 4639 return 0; 4640 } 4641 4642 /* Respect the kernel parameter if it is set */ 4643 if (enable_rc6 >= 0) { 4644 int mask; 4645 4646 if (HAS_RC6p(dev)) 4647 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | 4648 INTEL_RC6pp_ENABLE; 4649 else 4650 mask = INTEL_RC6_ENABLE; 4651 4652 if ((enable_rc6 & mask) != enable_rc6) 4653 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", 4654 enable_rc6 & mask, enable_rc6, mask); 4655 4656 return enable_rc6 & mask; 4657 } 4658 4659 if (IS_IVYBRIDGE(dev)) 4660 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 4661 4662 return INTEL_RC6_ENABLE; 4663 } 4664 4665 int intel_enable_rc6(const struct drm_device *dev) 4666 { 4667 return i915.enable_rc6; 4668 } 4669 4670 static void gen6_init_rps_frequencies(struct drm_device *dev) 4671 { 4672 struct drm_i915_private *dev_priv = dev->dev_private; 4673 uint32_t rp_state_cap; 4674 u32 ddcc_status = 0; 4675 int ret; 4676 4677 /* All of these values are in units of 50MHz */ 4678 dev_priv->rps.cur_freq = 0; 4679 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 4680 if (IS_BROXTON(dev)) { 4681 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 4682 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; 4683 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4684 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; 4685 } else { 4686 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 4687 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; 4688 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4689 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; 4690 } 4691 4692 /* hw_max = RP0 until we check for overclocking */ 4693 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; 4694 4695 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; 4696 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || 4697 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 4698 ret = sandybridge_pcode_read(dev_priv, 4699 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 4700 &ddcc_status); 4701 if (0 == ret) 4702 dev_priv->rps.efficient_freq = 4703 clamp_t(u8, 4704 ((ddcc_status >> 8) & 0xff), 4705 dev_priv->rps.min_freq, 4706 dev_priv->rps.max_freq); 4707 } 4708 4709 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 4710 /* Store the frequency values in 16.66 MHZ units, which is 4711 the natural hardware unit for SKL */ 4712 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; 4713 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; 4714 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; 4715 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; 4716 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; 4717 } 4718 4719 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 4720 4721 /* Preserve min/max settings in case of re-init */ 4722 if (dev_priv->rps.max_freq_softlimit == 0) 4723 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 4724 4725 if (dev_priv->rps.min_freq_softlimit == 0) { 4726 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4727 dev_priv->rps.min_freq_softlimit = 4728 max_t(int, dev_priv->rps.efficient_freq, 4729 intel_freq_opcode(dev_priv, 450)); 4730 else 4731 dev_priv->rps.min_freq_softlimit = 4732 dev_priv->rps.min_freq; 4733 } 4734 } 4735 4736 /* See the Gen9_GT_PM_Programming_Guide doc for the below */ 4737 static void gen9_enable_rps(struct drm_device *dev) 4738 { 4739 struct drm_i915_private *dev_priv = dev->dev_private; 4740 4741 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4742 4743 gen6_init_rps_frequencies(dev); 4744 4745 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */ 4746 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { 4747 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4748 return; 4749 } 4750 4751 /* Program defaults and thresholds for RPS*/ 4752 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4753 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); 4754 4755 /* 1 second timeout*/ 4756 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 4757 GT_INTERVAL_FROM_US(dev_priv, 1000000)); 4758 4759 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); 4760 4761 /* Leaning on the below call to gen6_set_rps to program/setup the 4762 * Up/Down EI & threshold registers, as well as the RP_CONTROL, 4763 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ 4764 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4765 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 4766 4767 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4768 } 4769 4770 static void gen9_enable_rc6(struct drm_device *dev) 4771 { 4772 struct drm_i915_private *dev_priv = dev->dev_private; 4773 struct intel_engine_cs *ring; 4774 uint32_t rc6_mask = 0; 4775 int unused; 4776 4777 /* 1a: Software RC state - RC0 */ 4778 I915_WRITE(GEN6_RC_STATE, 0); 4779 4780 /* 1b: Get forcewake during program sequence. Although the driver 4781 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4782 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4783 4784 /* 2a: Disable RC states. */ 4785 I915_WRITE(GEN6_RC_CONTROL, 0); 4786 4787 /* 2b: Program RC6 thresholds.*/ 4788 4789 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ 4790 if (IS_SKYLAKE(dev)) 4791 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 4792 else 4793 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 4794 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4795 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4796 for_each_ring(ring, dev_priv, unused) 4797 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4798 4799 if (HAS_GUC_UCODE(dev)) 4800 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); 4801 4802 I915_WRITE(GEN6_RC_SLEEP, 0); 4803 4804 /* 2c: Program Coarse Power Gating Policies. */ 4805 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); 4806 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); 4807 4808 /* 3a: Enable RC6 */ 4809 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4810 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4811 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE)); 4812 /* WaRsUseTimeoutMode */ 4813 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) || 4814 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) { 4815 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */ 4816 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4817 GEN7_RC_CTL_TO_MODE | 4818 rc6_mask); 4819 } else { 4820 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 4821 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4822 GEN6_RC_CTL_EI_MODE(1) | 4823 rc6_mask); 4824 } 4825 4826 /* 4827 * 3b: Enable Coarse Power Gating only when RC6 is enabled. 4828 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. 4829 */ 4830 if (NEEDS_WaRsDisableCoarsePowerGating(dev)) 4831 I915_WRITE(GEN9_PG_ENABLE, 0); 4832 else 4833 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4834 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); 4835 4836 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4837 4838 } 4839 4840 static void gen8_enable_rps(struct drm_device *dev) 4841 { 4842 struct drm_i915_private *dev_priv = dev->dev_private; 4843 struct intel_engine_cs *ring; 4844 uint32_t rc6_mask = 0; 4845 int unused; 4846 4847 /* 1a: Software RC state - RC0 */ 4848 I915_WRITE(GEN6_RC_STATE, 0); 4849 4850 /* 1c & 1d: Get forcewake during program sequence. Although the driver 4851 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4852 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4853 4854 /* 2a: Disable RC states. */ 4855 I915_WRITE(GEN6_RC_CONTROL, 0); 4856 4857 /* Initialize rps frequencies */ 4858 gen6_init_rps_frequencies(dev); 4859 4860 /* 2b: Program RC6 thresholds.*/ 4861 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 4862 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4863 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4864 for_each_ring(ring, dev_priv, unused) 4865 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4866 I915_WRITE(GEN6_RC_SLEEP, 0); 4867 if (IS_BROADWELL(dev)) 4868 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 4869 else 4870 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 4871 4872 /* 3: Enable RC6 */ 4873 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4874 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4875 intel_print_rc6_info(dev, rc6_mask); 4876 if (IS_BROADWELL(dev)) 4877 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4878 GEN7_RC_CTL_TO_MODE | 4879 rc6_mask); 4880 else 4881 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4882 GEN6_RC_CTL_EI_MODE(1) | 4883 rc6_mask); 4884 4885 /* 4 Program defaults and thresholds for RPS*/ 4886 I915_WRITE(GEN6_RPNSWREQ, 4887 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4888 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4889 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4890 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ 4891 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ 4892 4893 /* Docs recommend 900MHz, and 300 MHz respectively */ 4894 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 4895 dev_priv->rps.max_freq_softlimit << 24 | 4896 dev_priv->rps.min_freq_softlimit << 16); 4897 4898 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 4899 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 4900 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ 4901 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ 4902 4903 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4904 4905 /* 5: Enable RPS */ 4906 I915_WRITE(GEN6_RP_CONTROL, 4907 GEN6_RP_MEDIA_TURBO | 4908 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4909 GEN6_RP_MEDIA_IS_GFX | 4910 GEN6_RP_ENABLE | 4911 GEN6_RP_UP_BUSY_AVG | 4912 GEN6_RP_DOWN_IDLE_AVG); 4913 4914 /* 6: Ring frequency + overclocking (our driver does this later */ 4915 4916 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4917 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4918 4919 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4920 } 4921 4922 static void gen6_enable_rps(struct drm_device *dev) 4923 { 4924 struct drm_i915_private *dev_priv = dev->dev_private; 4925 struct intel_engine_cs *ring; 4926 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; 4927 u32 gtfifodbg; 4928 int rc6_mode; 4929 int i, ret; 4930 4931 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4932 4933 /* Here begins a magic sequence of register writes to enable 4934 * auto-downclocking. 4935 * 4936 * Perhaps there might be some value in exposing these to 4937 * userspace... 4938 */ 4939 I915_WRITE(GEN6_RC_STATE, 0); 4940 4941 /* Clear the DBG now so we don't confuse earlier errors */ 4942 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 4943 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 4944 I915_WRITE(GTFIFODBG, gtfifodbg); 4945 } 4946 4947 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4948 4949 /* Initialize rps frequencies */ 4950 gen6_init_rps_frequencies(dev); 4951 4952 /* disable the counters and set deterministic thresholds */ 4953 I915_WRITE(GEN6_RC_CONTROL, 0); 4954 4955 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 4956 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 4957 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 4958 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 4959 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 4960 4961 for_each_ring(ring, dev_priv, i) 4962 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4963 4964 I915_WRITE(GEN6_RC_SLEEP, 0); 4965 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 4966 if (IS_IVYBRIDGE(dev)) 4967 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); 4968 else 4969 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 4970 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 4971 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 4972 4973 /* Check if we are enabling RC6 */ 4974 rc6_mode = intel_enable_rc6(dev_priv->dev); 4975 if (rc6_mode & INTEL_RC6_ENABLE) 4976 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 4977 4978 /* We don't use those on Haswell */ 4979 if (!IS_HASWELL(dev)) { 4980 if (rc6_mode & INTEL_RC6p_ENABLE) 4981 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 4982 4983 if (rc6_mode & INTEL_RC6pp_ENABLE) 4984 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 4985 } 4986 4987 intel_print_rc6_info(dev, rc6_mask); 4988 4989 I915_WRITE(GEN6_RC_CONTROL, 4990 rc6_mask | 4991 GEN6_RC_CTL_EI_MODE(1) | 4992 GEN6_RC_CTL_HW_ENABLE); 4993 4994 /* Power down if completely idle for over 50ms */ 4995 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); 4996 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4997 4998 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 4999 if (ret) 5000 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 5001 5002 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 5003 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ 5004 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", 5005 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, 5006 (pcu_mbox & 0xff) * 50); 5007 dev_priv->rps.max_freq = pcu_mbox & 0xff; 5008 } 5009 5010 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 5011 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 5012 5013 rc6vids = 0; 5014 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 5015 if (IS_GEN6(dev) && ret) { 5016 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 5017 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 5018 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 5019 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 5020 rc6vids &= 0xffff00; 5021 rc6vids |= GEN6_ENCODE_RC6_VID(450); 5022 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 5023 if (ret) 5024 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 5025 } 5026 5027 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5028 } 5029 5030 static void __gen6_update_ring_freq(struct drm_device *dev) 5031 { 5032 struct drm_i915_private *dev_priv = dev->dev_private; 5033 int min_freq = 15; 5034 unsigned int gpu_freq; 5035 unsigned int max_ia_freq, min_ring_freq; 5036 unsigned int max_gpu_freq, min_gpu_freq; 5037 int scaling_factor = 180; 5038 5039 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5040 5041 #if 0 5042 policy = cpufreq_cpu_get(0); 5043 if (policy) { 5044 max_ia_freq = policy->cpuinfo.max_freq; 5045 cpufreq_cpu_put(policy); 5046 } else { 5047 /* 5048 * Default to measured freq if none found, PCU will ensure we 5049 * don't go over 5050 */ 5051 max_ia_freq = tsc_khz; 5052 } 5053 #else 5054 max_ia_freq = tsc_frequency / 1000; 5055 #endif 5056 5057 /* Convert from kHz to MHz */ 5058 max_ia_freq /= 1000; 5059 5060 min_ring_freq = I915_READ(DCLK) & 0xf; 5061 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 5062 min_ring_freq = mult_frac(min_ring_freq, 8, 3); 5063 5064 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 5065 /* Convert GT frequency to 50 HZ units */ 5066 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; 5067 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; 5068 } else { 5069 min_gpu_freq = dev_priv->rps.min_freq; 5070 max_gpu_freq = dev_priv->rps.max_freq; 5071 } 5072 5073 /* 5074 * For each potential GPU frequency, load a ring frequency we'd like 5075 * to use for memory access. We do this by specifying the IA frequency 5076 * the PCU should use as a reference to determine the ring frequency. 5077 */ 5078 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { 5079 int diff = max_gpu_freq - gpu_freq; 5080 unsigned int ia_freq = 0, ring_freq = 0; 5081 5082 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { 5083 /* 5084 * ring_freq = 2 * GT. ring_freq is in 100MHz units 5085 * No floor required for ring frequency on SKL. 5086 */ 5087 ring_freq = gpu_freq; 5088 } else if (INTEL_INFO(dev)->gen >= 8) { 5089 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 5090 ring_freq = max(min_ring_freq, gpu_freq); 5091 } else if (IS_HASWELL(dev)) { 5092 ring_freq = mult_frac(gpu_freq, 5, 4); 5093 ring_freq = max(min_ring_freq, ring_freq); 5094 /* leave ia_freq as the default, chosen by cpufreq */ 5095 } else { 5096 /* On older processors, there is no separate ring 5097 * clock domain, so in order to boost the bandwidth 5098 * of the ring, we need to upclock the CPU (ia_freq). 5099 * 5100 * For GPU frequencies less than 750MHz, 5101 * just use the lowest ring freq. 5102 */ 5103 if (gpu_freq < min_freq) 5104 ia_freq = 800; 5105 else 5106 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 5107 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 5108 } 5109 5110 sandybridge_pcode_write(dev_priv, 5111 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 5112 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 5113 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 5114 gpu_freq); 5115 } 5116 } 5117 5118 void gen6_update_ring_freq(struct drm_device *dev) 5119 { 5120 struct drm_i915_private *dev_priv = dev->dev_private; 5121 5122 if (!HAS_CORE_RING_FREQ(dev)) 5123 return; 5124 5125 mutex_lock(&dev_priv->rps.hw_lock); 5126 __gen6_update_ring_freq(dev); 5127 mutex_unlock(&dev_priv->rps.hw_lock); 5128 } 5129 5130 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) 5131 { 5132 struct drm_device *dev = dev_priv->dev; 5133 u32 val, rp0; 5134 5135 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5136 5137 switch (INTEL_INFO(dev)->eu_total) { 5138 case 8: 5139 /* (2 * 4) config */ 5140 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); 5141 break; 5142 case 12: 5143 /* (2 * 6) config */ 5144 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); 5145 break; 5146 case 16: 5147 /* (2 * 8) config */ 5148 default: 5149 /* Setting (2 * 8) Min RP0 for any other combination */ 5150 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); 5151 break; 5152 } 5153 5154 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); 5155 5156 return rp0; 5157 } 5158 5159 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5160 { 5161 u32 val, rpe; 5162 5163 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); 5164 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 5165 5166 return rpe; 5167 } 5168 5169 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) 5170 { 5171 u32 val, rp1; 5172 5173 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5174 rp1 = (val & FB_GFX_FREQ_FUSE_MASK); 5175 5176 return rp1; 5177 } 5178 5179 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) 5180 { 5181 u32 val, rp1; 5182 5183 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5184 5185 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 5186 5187 return rp1; 5188 } 5189 5190 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) 5191 { 5192 u32 val, rp0; 5193 5194 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5195 5196 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 5197 /* Clamp to max */ 5198 rp0 = min_t(u32, rp0, 0xea); 5199 5200 return rp0; 5201 } 5202 5203 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5204 { 5205 u32 val, rpe; 5206 5207 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 5208 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 5209 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 5210 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 5211 5212 return rpe; 5213 } 5214 5215 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) 5216 { 5217 u32 val; 5218 5219 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; 5220 /* 5221 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value 5222 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on 5223 * a BYT-M B0 the above register contains 0xbf. Moreover when setting 5224 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 5225 * to make sure it matches what Punit accepts. 5226 */ 5227 return max_t(u32, val, 0xc0); 5228 } 5229 5230 /* Check that the pctx buffer wasn't move under us. */ 5231 static void valleyview_check_pctx(struct drm_i915_private *dev_priv) 5232 { 5233 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5234 5235 /* DragonFly - if EDID fails vlv_pctx can wind up NULL */ 5236 if (WARN_ON(!dev_priv->vlv_pctx)) 5237 return; 5238 5239 WARN_ON(pctx_addr != dev_priv->mm.stolen_base + 5240 dev_priv->vlv_pctx->stolen->start); 5241 } 5242 5243 5244 /* Check that the pcbr address is not empty. */ 5245 static void cherryview_check_pctx(struct drm_i915_private *dev_priv) 5246 { 5247 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5248 5249 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); 5250 } 5251 5252 static void cherryview_setup_pctx(struct drm_device *dev) 5253 { 5254 struct drm_i915_private *dev_priv = dev->dev_private; 5255 unsigned long pctx_paddr, paddr; 5256 struct i915_gtt *gtt = &dev_priv->gtt; 5257 u32 pcbr; 5258 int pctx_size = 32*1024; 5259 5260 pcbr = I915_READ(VLV_PCBR); 5261 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 5262 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5263 paddr = (dev_priv->mm.stolen_base + 5264 (gtt->stolen_size - pctx_size)); 5265 5266 pctx_paddr = (paddr & (~4095)); 5267 I915_WRITE(VLV_PCBR, pctx_paddr); 5268 } 5269 5270 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5271 } 5272 5273 static void valleyview_setup_pctx(struct drm_device *dev) 5274 { 5275 struct drm_i915_private *dev_priv = dev->dev_private; 5276 struct drm_i915_gem_object *pctx; 5277 unsigned long pctx_paddr; 5278 u32 pcbr; 5279 int pctx_size = 24*1024; 5280 5281 mutex_lock(&dev->struct_mutex); 5282 5283 pcbr = I915_READ(VLV_PCBR); 5284 if (pcbr) { 5285 /* BIOS set it up already, grab the pre-alloc'd space */ 5286 int pcbr_offset; 5287 5288 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; 5289 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, 5290 pcbr_offset, 5291 I915_GTT_OFFSET_NONE, 5292 pctx_size); 5293 goto out; 5294 } 5295 5296 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5297 5298 /* 5299 * From the Gunit register HAS: 5300 * The Gfx driver is expected to program this register and ensure 5301 * proper allocation within Gfx stolen memory. For example, this 5302 * register should be programmed such than the PCBR range does not 5303 * overlap with other ranges, such as the frame buffer, protected 5304 * memory, or any other relevant ranges. 5305 */ 5306 pctx = i915_gem_object_create_stolen(dev, pctx_size); 5307 if (!pctx) { 5308 DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); 5309 goto out; 5310 } 5311 5312 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; 5313 I915_WRITE(VLV_PCBR, pctx_paddr); 5314 5315 out: 5316 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5317 dev_priv->vlv_pctx = pctx; 5318 mutex_unlock(&dev->struct_mutex); 5319 } 5320 5321 static void valleyview_cleanup_pctx(struct drm_device *dev) 5322 { 5323 struct drm_i915_private *dev_priv = dev->dev_private; 5324 5325 if (WARN_ON(!dev_priv->vlv_pctx)) 5326 return; 5327 5328 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base); 5329 dev_priv->vlv_pctx = NULL; 5330 } 5331 5332 static void valleyview_init_gt_powersave(struct drm_device *dev) 5333 { 5334 struct drm_i915_private *dev_priv = dev->dev_private; 5335 u32 val; 5336 5337 valleyview_setup_pctx(dev); 5338 5339 mutex_lock(&dev_priv->rps.hw_lock); 5340 5341 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5342 switch ((val >> 6) & 3) { 5343 case 0: 5344 case 1: 5345 dev_priv->mem_freq = 800; 5346 break; 5347 case 2: 5348 dev_priv->mem_freq = 1066; 5349 break; 5350 case 3: 5351 dev_priv->mem_freq = 1333; 5352 break; 5353 } 5354 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5355 5356 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 5357 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5358 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5359 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5360 dev_priv->rps.max_freq); 5361 5362 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); 5363 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5364 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5365 dev_priv->rps.efficient_freq); 5366 5367 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); 5368 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 5369 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5370 dev_priv->rps.rp1_freq); 5371 5372 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); 5373 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5374 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5375 dev_priv->rps.min_freq); 5376 5377 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5378 5379 /* Preserve min/max settings in case of re-init */ 5380 if (dev_priv->rps.max_freq_softlimit == 0) 5381 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5382 5383 if (dev_priv->rps.min_freq_softlimit == 0) 5384 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5385 5386 mutex_unlock(&dev_priv->rps.hw_lock); 5387 } 5388 5389 static void cherryview_init_gt_powersave(struct drm_device *dev) 5390 { 5391 struct drm_i915_private *dev_priv = dev->dev_private; 5392 u32 val; 5393 5394 cherryview_setup_pctx(dev); 5395 5396 mutex_lock(&dev_priv->rps.hw_lock); 5397 5398 mutex_lock(&dev_priv->sb_lock); 5399 val = vlv_cck_read(dev_priv, CCK_FUSE_REG); 5400 mutex_unlock(&dev_priv->sb_lock); 5401 5402 switch ((val >> 2) & 0x7) { 5403 case 3: 5404 dev_priv->mem_freq = 2000; 5405 break; 5406 default: 5407 dev_priv->mem_freq = 1600; 5408 break; 5409 } 5410 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5411 5412 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); 5413 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5414 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5415 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5416 dev_priv->rps.max_freq); 5417 5418 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); 5419 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5420 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5421 dev_priv->rps.efficient_freq); 5422 5423 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); 5424 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", 5425 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5426 dev_priv->rps.rp1_freq); 5427 5428 /* PUnit validated range is only [RPe, RP0] */ 5429 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; 5430 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5431 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5432 dev_priv->rps.min_freq); 5433 5434 WARN_ONCE((dev_priv->rps.max_freq | 5435 dev_priv->rps.efficient_freq | 5436 dev_priv->rps.rp1_freq | 5437 dev_priv->rps.min_freq) & 1, 5438 "Odd GPU freq values\n"); 5439 5440 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5441 5442 /* Preserve min/max settings in case of re-init */ 5443 if (dev_priv->rps.max_freq_softlimit == 0) 5444 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5445 5446 if (dev_priv->rps.min_freq_softlimit == 0) 5447 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5448 5449 mutex_unlock(&dev_priv->rps.hw_lock); 5450 } 5451 5452 static void valleyview_cleanup_gt_powersave(struct drm_device *dev) 5453 { 5454 valleyview_cleanup_pctx(dev); 5455 } 5456 5457 static void cherryview_enable_rps(struct drm_device *dev) 5458 { 5459 struct drm_i915_private *dev_priv = dev->dev_private; 5460 struct intel_engine_cs *ring; 5461 u32 gtfifodbg, val, rc6_mode = 0, pcbr; 5462 int i; 5463 5464 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5465 5466 gtfifodbg = I915_READ(GTFIFODBG); 5467 if (gtfifodbg) { 5468 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5469 gtfifodbg); 5470 I915_WRITE(GTFIFODBG, gtfifodbg); 5471 } 5472 5473 cherryview_check_pctx(dev_priv); 5474 5475 /* 1a & 1b: Get forcewake during program sequence. Although the driver 5476 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 5477 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5478 5479 /* Disable RC states. */ 5480 I915_WRITE(GEN6_RC_CONTROL, 0); 5481 5482 /* 2a: Program RC6 thresholds.*/ 5483 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 5484 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 5485 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 5486 5487 for_each_ring(ring, dev_priv, i) 5488 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5489 I915_WRITE(GEN6_RC_SLEEP, 0); 5490 5491 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ 5492 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); 5493 5494 /* allows RC6 residency counter to work */ 5495 I915_WRITE(VLV_COUNTER_CONTROL, 5496 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 5497 VLV_MEDIA_RC6_COUNT_EN | 5498 VLV_RENDER_RC6_COUNT_EN)); 5499 5500 /* For now we assume BIOS is allocating and populating the PCBR */ 5501 pcbr = I915_READ(VLV_PCBR); 5502 5503 /* 3: Enable RC6 */ 5504 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && 5505 (pcbr >> VLV_PCBR_ADDR_SHIFT)) 5506 rc6_mode = GEN7_RC_CTL_TO_MODE; 5507 5508 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5509 5510 /* 4 Program defaults and thresholds for RPS*/ 5511 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5512 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5513 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5514 I915_WRITE(GEN6_RP_UP_EI, 66000); 5515 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5516 5517 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5518 5519 /* 5: Enable RPS */ 5520 I915_WRITE(GEN6_RP_CONTROL, 5521 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5522 GEN6_RP_MEDIA_IS_GFX | 5523 GEN6_RP_ENABLE | 5524 GEN6_RP_UP_BUSY_AVG | 5525 GEN6_RP_DOWN_IDLE_AVG); 5526 5527 /* Setting Fixed Bias */ 5528 val = VLV_OVERRIDE_EN | 5529 VLV_SOC_TDP_EN | 5530 CHV_BIAS_CPU_50_SOC_50; 5531 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5532 5533 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5534 5535 /* RPS code assumes GPLL is used */ 5536 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5537 5538 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5539 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5540 5541 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5542 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5543 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5544 dev_priv->rps.cur_freq); 5545 5546 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5547 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5548 dev_priv->rps.efficient_freq); 5549 5550 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5551 5552 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5553 } 5554 5555 static void valleyview_enable_rps(struct drm_device *dev) 5556 { 5557 struct drm_i915_private *dev_priv = dev->dev_private; 5558 struct intel_engine_cs *ring; 5559 u32 gtfifodbg, val, rc6_mode = 0; 5560 int i; 5561 5562 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5563 5564 valleyview_check_pctx(dev_priv); 5565 5566 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 5567 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5568 gtfifodbg); 5569 I915_WRITE(GTFIFODBG, gtfifodbg); 5570 } 5571 5572 /* If VLV, Forcewake all wells, else re-direct to regular path */ 5573 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5574 5575 /* Disable RC states. */ 5576 I915_WRITE(GEN6_RC_CONTROL, 0); 5577 5578 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5579 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5580 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5581 I915_WRITE(GEN6_RP_UP_EI, 66000); 5582 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5583 5584 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5585 5586 I915_WRITE(GEN6_RP_CONTROL, 5587 GEN6_RP_MEDIA_TURBO | 5588 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5589 GEN6_RP_MEDIA_IS_GFX | 5590 GEN6_RP_ENABLE | 5591 GEN6_RP_UP_BUSY_AVG | 5592 GEN6_RP_DOWN_IDLE_CONT); 5593 5594 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 5595 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 5596 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 5597 5598 for_each_ring(ring, dev_priv, i) 5599 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5600 5601 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); 5602 5603 /* allows RC6 residency counter to work */ 5604 I915_WRITE(VLV_COUNTER_CONTROL, 5605 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | 5606 VLV_RENDER_RC0_COUNT_EN | 5607 VLV_MEDIA_RC6_COUNT_EN | 5608 VLV_RENDER_RC6_COUNT_EN)); 5609 5610 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 5611 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 5612 5613 intel_print_rc6_info(dev, rc6_mode); 5614 5615 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5616 5617 /* Setting Fixed Bias */ 5618 val = VLV_OVERRIDE_EN | 5619 VLV_SOC_TDP_EN | 5620 VLV_BIAS_CPU_125_SOC_875; 5621 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5622 5623 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5624 5625 /* RPS code assumes GPLL is used */ 5626 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5627 5628 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); 5629 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5630 5631 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5632 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5633 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5634 dev_priv->rps.cur_freq); 5635 5636 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5637 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5638 dev_priv->rps.efficient_freq); 5639 5640 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5641 5642 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5643 } 5644 5645 static unsigned long intel_pxfreq(u32 vidfreq) 5646 { 5647 unsigned long freq; 5648 int div = (vidfreq & 0x3f0000) >> 16; 5649 int post = (vidfreq & 0x3000) >> 12; 5650 int pre = (vidfreq & 0x7); 5651 5652 if (!pre) 5653 return 0; 5654 5655 freq = ((div * 133333) / ((1<<post) * pre)); 5656 5657 return freq; 5658 } 5659 5660 static const struct cparams { 5661 u16 i; 5662 u16 t; 5663 u16 m; 5664 u16 c; 5665 } cparams[] = { 5666 { 1, 1333, 301, 28664 }, 5667 { 1, 1066, 294, 24460 }, 5668 { 1, 800, 294, 25192 }, 5669 { 0, 1333, 276, 27605 }, 5670 { 0, 1066, 276, 27605 }, 5671 { 0, 800, 231, 23784 }, 5672 }; 5673 5674 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 5675 { 5676 u64 total_count, diff, ret; 5677 u32 count1, count2, count3, m = 0, c = 0; 5678 unsigned long now = jiffies_to_msecs(jiffies), diff1; 5679 int i; 5680 5681 assert_spin_locked(&mchdev_lock); 5682 5683 diff1 = now - dev_priv->ips.last_time1; 5684 5685 /* Prevent division-by-zero if we are asking too fast. 5686 * Also, we don't get interesting results if we are polling 5687 * faster than once in 10ms, so just return the saved value 5688 * in such cases. 5689 */ 5690 if (diff1 <= 10) 5691 return dev_priv->ips.chipset_power; 5692 5693 count1 = I915_READ(DMIEC); 5694 count2 = I915_READ(DDREC); 5695 count3 = I915_READ(CSIEC); 5696 5697 total_count = count1 + count2 + count3; 5698 5699 /* FIXME: handle per-counter overflow */ 5700 if (total_count < dev_priv->ips.last_count1) { 5701 diff = ~0UL - dev_priv->ips.last_count1; 5702 diff += total_count; 5703 } else { 5704 diff = total_count - dev_priv->ips.last_count1; 5705 } 5706 5707 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 5708 if (cparams[i].i == dev_priv->ips.c_m && 5709 cparams[i].t == dev_priv->ips.r_t) { 5710 m = cparams[i].m; 5711 c = cparams[i].c; 5712 break; 5713 } 5714 } 5715 5716 diff = div_u64(diff, diff1); 5717 ret = ((m * diff) + c); 5718 ret = div_u64(ret, 10); 5719 5720 dev_priv->ips.last_count1 = total_count; 5721 dev_priv->ips.last_time1 = now; 5722 5723 dev_priv->ips.chipset_power = ret; 5724 5725 return ret; 5726 } 5727 5728 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 5729 { 5730 struct drm_device *dev = dev_priv->dev; 5731 unsigned long val; 5732 5733 if (INTEL_INFO(dev)->gen != 5) 5734 return 0; 5735 5736 spin_lock_irq(&mchdev_lock); 5737 5738 val = __i915_chipset_val(dev_priv); 5739 5740 spin_unlock_irq(&mchdev_lock); 5741 5742 return val; 5743 } 5744 5745 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 5746 { 5747 unsigned long m, x, b; 5748 u32 tsfs; 5749 5750 tsfs = I915_READ(TSFS); 5751 5752 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 5753 x = I915_READ8(TR1); 5754 5755 b = tsfs & TSFS_INTR_MASK; 5756 5757 return ((m * x) / 127) - b; 5758 } 5759 5760 static int _pxvid_to_vd(u8 pxvid) 5761 { 5762 if (pxvid == 0) 5763 return 0; 5764 5765 if (pxvid >= 8 && pxvid < 31) 5766 pxvid = 31; 5767 5768 return (pxvid + 2) * 125; 5769 } 5770 5771 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 5772 { 5773 struct drm_device *dev = dev_priv->dev; 5774 const int vd = _pxvid_to_vd(pxvid); 5775 const int vm = vd - 1125; 5776 5777 if (INTEL_INFO(dev)->is_mobile) 5778 return vm > 0 ? vm : 0; 5779 5780 return vd; 5781 } 5782 5783 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 5784 { 5785 u64 now, diff, diffms; 5786 u32 count; 5787 5788 assert_spin_locked(&mchdev_lock); 5789 5790 now = ktime_get_raw_ns(); 5791 diffms = now - dev_priv->ips.last_time2; 5792 do_div(diffms, NSEC_PER_MSEC); 5793 5794 /* Don't divide by 0 */ 5795 if (!diffms) 5796 return; 5797 5798 count = I915_READ(GFXEC); 5799 5800 if (count < dev_priv->ips.last_count2) { 5801 diff = ~0UL - dev_priv->ips.last_count2; 5802 diff += count; 5803 } else { 5804 diff = count - dev_priv->ips.last_count2; 5805 } 5806 5807 dev_priv->ips.last_count2 = count; 5808 dev_priv->ips.last_time2 = now; 5809 5810 /* More magic constants... */ 5811 diff = diff * 1181; 5812 diff = div_u64(diff, diffms * 10); 5813 dev_priv->ips.gfx_power = diff; 5814 } 5815 5816 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 5817 { 5818 struct drm_device *dev = dev_priv->dev; 5819 5820 if (INTEL_INFO(dev)->gen != 5) 5821 return; 5822 5823 spin_lock_irq(&mchdev_lock); 5824 5825 __i915_update_gfx_val(dev_priv); 5826 5827 spin_unlock_irq(&mchdev_lock); 5828 } 5829 5830 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 5831 { 5832 unsigned long t, corr, state1, corr2, state2; 5833 u32 pxvid, ext_v; 5834 5835 assert_spin_locked(&mchdev_lock); 5836 5837 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); 5838 pxvid = (pxvid >> 24) & 0x7f; 5839 ext_v = pvid_to_extvid(dev_priv, pxvid); 5840 5841 state1 = ext_v; 5842 5843 t = i915_mch_val(dev_priv); 5844 5845 /* Revel in the empirically derived constants */ 5846 5847 /* Correction factor in 1/100000 units */ 5848 if (t > 80) 5849 corr = ((t * 2349) + 135940); 5850 else if (t >= 50) 5851 corr = ((t * 964) + 29317); 5852 else /* < 50 */ 5853 corr = ((t * 301) + 1004); 5854 5855 corr = corr * ((150142 * state1) / 10000 - 78642); 5856 corr /= 100000; 5857 corr2 = (corr * dev_priv->ips.corr); 5858 5859 state2 = (corr2 * state1) / 10000; 5860 state2 /= 100; /* convert to mW */ 5861 5862 __i915_update_gfx_val(dev_priv); 5863 5864 return dev_priv->ips.gfx_power + state2; 5865 } 5866 5867 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 5868 { 5869 struct drm_device *dev = dev_priv->dev; 5870 unsigned long val; 5871 5872 if (INTEL_INFO(dev)->gen != 5) 5873 return 0; 5874 5875 spin_lock_irq(&mchdev_lock); 5876 5877 val = __i915_gfx_val(dev_priv); 5878 5879 spin_unlock_irq(&mchdev_lock); 5880 5881 return val; 5882 } 5883 5884 /** 5885 * i915_read_mch_val - return value for IPS use 5886 * 5887 * Calculate and return a value for the IPS driver to use when deciding whether 5888 * we have thermal and power headroom to increase CPU or GPU power budget. 5889 */ 5890 unsigned long i915_read_mch_val(void) 5891 { 5892 struct drm_i915_private *dev_priv; 5893 unsigned long chipset_val, graphics_val, ret = 0; 5894 5895 spin_lock_irq(&mchdev_lock); 5896 if (!i915_mch_dev) 5897 goto out_unlock; 5898 dev_priv = i915_mch_dev; 5899 5900 chipset_val = __i915_chipset_val(dev_priv); 5901 graphics_val = __i915_gfx_val(dev_priv); 5902 5903 ret = chipset_val + graphics_val; 5904 5905 out_unlock: 5906 spin_unlock_irq(&mchdev_lock); 5907 5908 return ret; 5909 } 5910 5911 /** 5912 * i915_gpu_raise - raise GPU frequency limit 5913 * 5914 * Raise the limit; IPS indicates we have thermal headroom. 5915 */ 5916 bool i915_gpu_raise(void) 5917 { 5918 struct drm_i915_private *dev_priv; 5919 bool ret = true; 5920 5921 spin_lock_irq(&mchdev_lock); 5922 if (!i915_mch_dev) { 5923 ret = false; 5924 goto out_unlock; 5925 } 5926 dev_priv = i915_mch_dev; 5927 5928 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 5929 dev_priv->ips.max_delay--; 5930 5931 out_unlock: 5932 spin_unlock_irq(&mchdev_lock); 5933 5934 return ret; 5935 } 5936 5937 /** 5938 * i915_gpu_lower - lower GPU frequency limit 5939 * 5940 * IPS indicates we're close to a thermal limit, so throttle back the GPU 5941 * frequency maximum. 5942 */ 5943 bool i915_gpu_lower(void) 5944 { 5945 struct drm_i915_private *dev_priv; 5946 bool ret = true; 5947 5948 spin_lock_irq(&mchdev_lock); 5949 if (!i915_mch_dev) { 5950 ret = false; 5951 goto out_unlock; 5952 } 5953 dev_priv = i915_mch_dev; 5954 5955 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 5956 dev_priv->ips.max_delay++; 5957 5958 out_unlock: 5959 spin_unlock_irq(&mchdev_lock); 5960 5961 return ret; 5962 } 5963 5964 /** 5965 * i915_gpu_busy - indicate GPU business to IPS 5966 * 5967 * Tell the IPS driver whether or not the GPU is busy. 5968 */ 5969 bool i915_gpu_busy(void) 5970 { 5971 struct drm_i915_private *dev_priv; 5972 struct intel_engine_cs *ring; 5973 bool ret = false; 5974 int i; 5975 5976 spin_lock_irq(&mchdev_lock); 5977 if (!i915_mch_dev) 5978 goto out_unlock; 5979 dev_priv = i915_mch_dev; 5980 5981 for_each_ring(ring, dev_priv, i) 5982 ret |= !list_empty(&ring->request_list); 5983 5984 out_unlock: 5985 spin_unlock_irq(&mchdev_lock); 5986 5987 return ret; 5988 } 5989 5990 /** 5991 * i915_gpu_turbo_disable - disable graphics turbo 5992 * 5993 * Disable graphics turbo by resetting the max frequency and setting the 5994 * current frequency to the default. 5995 */ 5996 bool i915_gpu_turbo_disable(void) 5997 { 5998 struct drm_i915_private *dev_priv; 5999 bool ret = true; 6000 6001 spin_lock_irq(&mchdev_lock); 6002 if (!i915_mch_dev) { 6003 ret = false; 6004 goto out_unlock; 6005 } 6006 dev_priv = i915_mch_dev; 6007 6008 dev_priv->ips.max_delay = dev_priv->ips.fstart; 6009 6010 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 6011 ret = false; 6012 6013 out_unlock: 6014 spin_unlock_irq(&mchdev_lock); 6015 6016 return ret; 6017 } 6018 6019 #if 0 6020 /** 6021 * Tells the intel_ips driver that the i915 driver is now loaded, if 6022 * IPS got loaded first. 6023 * 6024 * This awkward dance is so that neither module has to depend on the 6025 * other in order for IPS to do the appropriate communication of 6026 * GPU turbo limits to i915. 6027 */ 6028 static void 6029 ips_ping_for_i915_load(void) 6030 { 6031 void (*link)(void); 6032 6033 link = symbol_get(ips_link_to_i915_driver); 6034 if (link) { 6035 link(); 6036 symbol_put(ips_link_to_i915_driver); 6037 } 6038 } 6039 #endif 6040 6041 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 6042 { 6043 /* We only register the i915 ips part with intel-ips once everything is 6044 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 6045 spin_lock_irq(&mchdev_lock); 6046 i915_mch_dev = dev_priv; 6047 spin_unlock_irq(&mchdev_lock); 6048 6049 } 6050 6051 void intel_gpu_ips_teardown(void) 6052 { 6053 spin_lock_irq(&mchdev_lock); 6054 i915_mch_dev = NULL; 6055 spin_unlock_irq(&mchdev_lock); 6056 } 6057 6058 static void intel_init_emon(struct drm_device *dev) 6059 { 6060 struct drm_i915_private *dev_priv = dev->dev_private; 6061 u32 lcfuse; 6062 u8 pxw[16]; 6063 int i; 6064 6065 /* Disable to program */ 6066 I915_WRITE(ECR, 0); 6067 POSTING_READ(ECR); 6068 6069 /* Program energy weights for various events */ 6070 I915_WRITE(SDEW, 0x15040d00); 6071 I915_WRITE(CSIEW0, 0x007f0000); 6072 I915_WRITE(CSIEW1, 0x1e220004); 6073 I915_WRITE(CSIEW2, 0x04000004); 6074 6075 for (i = 0; i < 5; i++) 6076 I915_WRITE(PEW(i), 0); 6077 for (i = 0; i < 3; i++) 6078 I915_WRITE(DEW(i), 0); 6079 6080 /* Program P-state weights to account for frequency power adjustment */ 6081 for (i = 0; i < 16; i++) { 6082 u32 pxvidfreq = I915_READ(PXVFREQ(i)); 6083 unsigned long freq = intel_pxfreq(pxvidfreq); 6084 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 6085 PXVFREQ_PX_SHIFT; 6086 unsigned long val; 6087 6088 val = vid * vid; 6089 val *= (freq / 1000); 6090 val *= 255; 6091 val /= (127*127*900); 6092 if (val > 0xff) 6093 DRM_ERROR("bad pxval: %ld\n", val); 6094 pxw[i] = val; 6095 } 6096 /* Render standby states get 0 weight */ 6097 pxw[14] = 0; 6098 pxw[15] = 0; 6099 6100 for (i = 0; i < 4; i++) { 6101 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 6102 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 6103 I915_WRITE(PXW(i), val); 6104 } 6105 6106 /* Adjust magic regs to magic values (more experimental results) */ 6107 I915_WRITE(OGW0, 0); 6108 I915_WRITE(OGW1, 0); 6109 I915_WRITE(EG0, 0x00007f00); 6110 I915_WRITE(EG1, 0x0000000e); 6111 I915_WRITE(EG2, 0x000e0000); 6112 I915_WRITE(EG3, 0x68000300); 6113 I915_WRITE(EG4, 0x42000000); 6114 I915_WRITE(EG5, 0x00140031); 6115 I915_WRITE(EG6, 0); 6116 I915_WRITE(EG7, 0); 6117 6118 for (i = 0; i < 8; i++) 6119 I915_WRITE(PXWL(i), 0); 6120 6121 /* Enable PMON + select events */ 6122 I915_WRITE(ECR, 0x80000019); 6123 6124 lcfuse = I915_READ(LCFUSE02); 6125 6126 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 6127 } 6128 6129 void intel_init_gt_powersave(struct drm_device *dev) 6130 { 6131 struct drm_i915_private *dev_priv = dev->dev_private; 6132 6133 /* 6134 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a 6135 * requirement. 6136 */ 6137 if (!i915.enable_rc6) { 6138 DRM_INFO("RC6 disabled, disabling runtime PM support\n"); 6139 intel_runtime_pm_get(dev_priv); 6140 } 6141 6142 if (IS_CHERRYVIEW(dev)) 6143 cherryview_init_gt_powersave(dev); 6144 else if (IS_VALLEYVIEW(dev)) 6145 valleyview_init_gt_powersave(dev); 6146 } 6147 6148 void intel_cleanup_gt_powersave(struct drm_device *dev) 6149 { 6150 struct drm_i915_private *dev_priv = dev->dev_private; 6151 6152 if (IS_CHERRYVIEW(dev)) 6153 return; 6154 else if (IS_VALLEYVIEW(dev)) 6155 valleyview_cleanup_gt_powersave(dev); 6156 6157 if (!i915.enable_rc6) 6158 intel_runtime_pm_put(dev_priv); 6159 } 6160 6161 static void gen6_suspend_rps(struct drm_device *dev) 6162 { 6163 #if 0 6164 struct drm_i915_private *dev_priv = dev->dev_private; 6165 6166 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 6167 #endif 6168 6169 gen6_disable_rps_interrupts(dev); 6170 } 6171 6172 /** 6173 * intel_suspend_gt_powersave - suspend PM work and helper threads 6174 * @dev: drm device 6175 * 6176 * We don't want to disable RC6 or other features here, we just want 6177 * to make sure any work we've queued has finished and won't bother 6178 * us while we're suspended. 6179 */ 6180 void intel_suspend_gt_powersave(struct drm_device *dev) 6181 { 6182 struct drm_i915_private *dev_priv = dev->dev_private; 6183 6184 if (INTEL_INFO(dev)->gen < 6) 6185 return; 6186 6187 gen6_suspend_rps(dev); 6188 6189 /* Force GPU to min freq during suspend */ 6190 gen6_rps_idle(dev_priv); 6191 } 6192 6193 void intel_disable_gt_powersave(struct drm_device *dev) 6194 { 6195 struct drm_i915_private *dev_priv = dev->dev_private; 6196 6197 if (IS_IRONLAKE_M(dev)) { 6198 ironlake_disable_drps(dev); 6199 } else if (INTEL_INFO(dev)->gen >= 6) { 6200 intel_suspend_gt_powersave(dev); 6201 6202 mutex_lock(&dev_priv->rps.hw_lock); 6203 if (INTEL_INFO(dev)->gen >= 9) 6204 gen9_disable_rps(dev); 6205 else if (IS_CHERRYVIEW(dev)) 6206 cherryview_disable_rps(dev); 6207 else if (IS_VALLEYVIEW(dev)) 6208 valleyview_disable_rps(dev); 6209 else 6210 gen6_disable_rps(dev); 6211 6212 dev_priv->rps.enabled = false; 6213 mutex_unlock(&dev_priv->rps.hw_lock); 6214 } 6215 } 6216 6217 static void intel_gen6_powersave_work(struct work_struct *work) 6218 { 6219 struct drm_i915_private *dev_priv = 6220 container_of(work, struct drm_i915_private, 6221 rps.delayed_resume_work.work); 6222 struct drm_device *dev = dev_priv->dev; 6223 6224 mutex_lock(&dev_priv->rps.hw_lock); 6225 6226 gen6_reset_rps_interrupts(dev); 6227 6228 if (IS_CHERRYVIEW(dev)) { 6229 cherryview_enable_rps(dev); 6230 } else if (IS_VALLEYVIEW(dev)) { 6231 valleyview_enable_rps(dev); 6232 } else if (INTEL_INFO(dev)->gen >= 9) { 6233 gen9_enable_rc6(dev); 6234 gen9_enable_rps(dev); 6235 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) 6236 __gen6_update_ring_freq(dev); 6237 } else if (IS_BROADWELL(dev)) { 6238 gen8_enable_rps(dev); 6239 __gen6_update_ring_freq(dev); 6240 } else { 6241 gen6_enable_rps(dev); 6242 __gen6_update_ring_freq(dev); 6243 } 6244 6245 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); 6246 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); 6247 6248 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); 6249 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); 6250 6251 dev_priv->rps.enabled = true; 6252 6253 gen6_enable_rps_interrupts(dev); 6254 6255 mutex_unlock(&dev_priv->rps.hw_lock); 6256 6257 intel_runtime_pm_put(dev_priv); 6258 } 6259 6260 void intel_enable_gt_powersave(struct drm_device *dev) 6261 { 6262 struct drm_i915_private *dev_priv = dev->dev_private; 6263 6264 /* Powersaving is controlled by the host when inside a VM */ 6265 if (intel_vgpu_active(dev)) 6266 return; 6267 6268 if (IS_IRONLAKE_M(dev)) { 6269 ironlake_enable_drps(dev); 6270 mutex_lock(&dev->struct_mutex); 6271 intel_init_emon(dev); 6272 mutex_unlock(&dev->struct_mutex); 6273 } else if (INTEL_INFO(dev)->gen >= 6) { 6274 /* 6275 * PCU communication is slow and this doesn't need to be 6276 * done at any specific time, so do this out of our fast path 6277 * to make resume and init faster. 6278 * 6279 * We depend on the HW RC6 power context save/restore 6280 * mechanism when entering D3 through runtime PM suspend. So 6281 * disable RPM until RPS/RC6 is properly setup. We can only 6282 * get here via the driver load/system resume/runtime resume 6283 * paths, so the _noresume version is enough (and in case of 6284 * runtime resume it's necessary). 6285 */ 6286 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 6287 round_jiffies_up_relative(HZ))) 6288 intel_runtime_pm_get_noresume(dev_priv); 6289 } 6290 } 6291 6292 void intel_reset_gt_powersave(struct drm_device *dev) 6293 { 6294 struct drm_i915_private *dev_priv = dev->dev_private; 6295 6296 if (INTEL_INFO(dev)->gen < 6) 6297 return; 6298 6299 gen6_suspend_rps(dev); 6300 dev_priv->rps.enabled = false; 6301 } 6302 6303 static void ibx_init_clock_gating(struct drm_device *dev) 6304 { 6305 struct drm_i915_private *dev_priv = dev->dev_private; 6306 6307 /* 6308 * On Ibex Peak and Cougar Point, we need to disable clock 6309 * gating for the panel power sequencer or it will fail to 6310 * start up when no ports are active. 6311 */ 6312 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 6313 } 6314 6315 static void g4x_disable_trickle_feed(struct drm_device *dev) 6316 { 6317 struct drm_i915_private *dev_priv = dev->dev_private; 6318 enum i915_pipe pipe; 6319 6320 for_each_pipe(dev_priv, pipe) { 6321 I915_WRITE(DSPCNTR(pipe), 6322 I915_READ(DSPCNTR(pipe)) | 6323 DISPPLANE_TRICKLE_FEED_DISABLE); 6324 6325 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); 6326 POSTING_READ(DSPSURF(pipe)); 6327 } 6328 } 6329 6330 static void ilk_init_lp_watermarks(struct drm_device *dev) 6331 { 6332 struct drm_i915_private *dev_priv = dev->dev_private; 6333 6334 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); 6335 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); 6336 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); 6337 6338 /* 6339 * Don't touch WM1S_LP_EN here. 6340 * Doing so could cause underruns. 6341 */ 6342 } 6343 6344 static void ironlake_init_clock_gating(struct drm_device *dev) 6345 { 6346 struct drm_i915_private *dev_priv = dev->dev_private; 6347 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6348 6349 /* 6350 * Required for FBC 6351 * WaFbcDisableDpfcClockGating:ilk 6352 */ 6353 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 6354 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 6355 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 6356 6357 I915_WRITE(PCH_3DCGDIS0, 6358 MARIUNIT_CLOCK_GATE_DISABLE | 6359 SVSMUNIT_CLOCK_GATE_DISABLE); 6360 I915_WRITE(PCH_3DCGDIS1, 6361 VFMUNIT_CLOCK_GATE_DISABLE); 6362 6363 /* 6364 * According to the spec the following bits should be set in 6365 * order to enable memory self-refresh 6366 * The bit 22/21 of 0x42004 6367 * The bit 5 of 0x42020 6368 * The bit 15 of 0x45000 6369 */ 6370 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6371 (I915_READ(ILK_DISPLAY_CHICKEN2) | 6372 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 6373 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 6374 I915_WRITE(DISP_ARB_CTL, 6375 (I915_READ(DISP_ARB_CTL) | 6376 DISP_FBC_WM_DIS)); 6377 6378 ilk_init_lp_watermarks(dev); 6379 6380 /* 6381 * Based on the document from hardware guys the following bits 6382 * should be set unconditionally in order to enable FBC. 6383 * The bit 22 of 0x42000 6384 * The bit 22 of 0x42004 6385 * The bit 7,8,9 of 0x42020. 6386 */ 6387 if (IS_IRONLAKE_M(dev)) { 6388 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 6389 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6390 I915_READ(ILK_DISPLAY_CHICKEN1) | 6391 ILK_FBCQ_DIS); 6392 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6393 I915_READ(ILK_DISPLAY_CHICKEN2) | 6394 ILK_DPARB_GATE); 6395 } 6396 6397 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6398 6399 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6400 I915_READ(ILK_DISPLAY_CHICKEN2) | 6401 ILK_ELPIN_409_SELECT); 6402 I915_WRITE(_3D_CHICKEN2, 6403 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 6404 _3D_CHICKEN2_WM_READ_PIPELINED); 6405 6406 /* WaDisableRenderCachePipelinedFlush:ilk */ 6407 I915_WRITE(CACHE_MODE_0, 6408 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6409 6410 /* WaDisable_RenderCache_OperationalFlush:ilk */ 6411 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6412 6413 g4x_disable_trickle_feed(dev); 6414 6415 ibx_init_clock_gating(dev); 6416 } 6417 6418 static void cpt_init_clock_gating(struct drm_device *dev) 6419 { 6420 struct drm_i915_private *dev_priv = dev->dev_private; 6421 int pipe; 6422 uint32_t val; 6423 6424 /* 6425 * On Ibex Peak and Cougar Point, we need to disable clock 6426 * gating for the panel power sequencer or it will fail to 6427 * start up when no ports are active. 6428 */ 6429 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 6430 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 6431 PCH_CPUNIT_CLOCK_GATE_DISABLE); 6432 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 6433 DPLS_EDP_PPS_FIX_DIS); 6434 /* The below fixes the weird display corruption, a few pixels shifted 6435 * downward, on (only) LVDS of some HP laptops with IVY. 6436 */ 6437 for_each_pipe(dev_priv, pipe) { 6438 val = I915_READ(TRANS_CHICKEN2(pipe)); 6439 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 6440 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6441 if (dev_priv->vbt.fdi_rx_polarity_inverted) 6442 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6443 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 6444 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 6445 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 6446 I915_WRITE(TRANS_CHICKEN2(pipe), val); 6447 } 6448 /* WADP0ClockGatingDisable */ 6449 for_each_pipe(dev_priv, pipe) { 6450 I915_WRITE(TRANS_CHICKEN1(pipe), 6451 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6452 } 6453 } 6454 6455 static void gen6_check_mch_setup(struct drm_device *dev) 6456 { 6457 struct drm_i915_private *dev_priv = dev->dev_private; 6458 uint32_t tmp; 6459 6460 tmp = I915_READ(MCH_SSKPD); 6461 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) 6462 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 6463 tmp); 6464 } 6465 6466 static void gen6_init_clock_gating(struct drm_device *dev) 6467 { 6468 struct drm_i915_private *dev_priv = dev->dev_private; 6469 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6470 6471 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6472 6473 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6474 I915_READ(ILK_DISPLAY_CHICKEN2) | 6475 ILK_ELPIN_409_SELECT); 6476 6477 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 6478 I915_WRITE(_3D_CHICKEN, 6479 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 6480 6481 /* WaDisable_RenderCache_OperationalFlush:snb */ 6482 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6483 6484 /* 6485 * BSpec recoomends 8x4 when MSAA is used, 6486 * however in practice 16x4 seems fastest. 6487 * 6488 * Note that PS/WM thread counts depend on the WIZ hashing 6489 * disable bit, which we don't touch here, but it's good 6490 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6491 */ 6492 I915_WRITE(GEN6_GT_MODE, 6493 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6494 6495 ilk_init_lp_watermarks(dev); 6496 6497 I915_WRITE(CACHE_MODE_0, 6498 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 6499 6500 I915_WRITE(GEN6_UCGCTL1, 6501 I915_READ(GEN6_UCGCTL1) | 6502 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 6503 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6504 6505 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 6506 * gating disable must be set. Failure to set it results in 6507 * flickering pixels due to Z write ordering failures after 6508 * some amount of runtime in the Mesa "fire" demo, and Unigine 6509 * Sanctuary and Tropics, and apparently anything else with 6510 * alpha test or pixel discard. 6511 * 6512 * According to the spec, bit 11 (RCCUNIT) must also be set, 6513 * but we didn't debug actual testcases to find it out. 6514 * 6515 * WaDisableRCCUnitClockGating:snb 6516 * WaDisableRCPBUnitClockGating:snb 6517 */ 6518 I915_WRITE(GEN6_UCGCTL2, 6519 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 6520 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 6521 6522 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 6523 I915_WRITE(_3D_CHICKEN3, 6524 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); 6525 6526 /* 6527 * Bspec says: 6528 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and 6529 * 3DSTATE_SF number of SF output attributes is more than 16." 6530 */ 6531 I915_WRITE(_3D_CHICKEN3, 6532 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); 6533 6534 /* 6535 * According to the spec the following bits should be 6536 * set in order to enable memory self-refresh and fbc: 6537 * The bit21 and bit22 of 0x42000 6538 * The bit21 and bit22 of 0x42004 6539 * The bit5 and bit7 of 0x42020 6540 * The bit14 of 0x70180 6541 * The bit14 of 0x71180 6542 * 6543 * WaFbcAsynchFlipDisableFbcQueue:snb 6544 */ 6545 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6546 I915_READ(ILK_DISPLAY_CHICKEN1) | 6547 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 6548 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6549 I915_READ(ILK_DISPLAY_CHICKEN2) | 6550 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 6551 I915_WRITE(ILK_DSPCLK_GATE_D, 6552 I915_READ(ILK_DSPCLK_GATE_D) | 6553 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 6554 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 6555 6556 g4x_disable_trickle_feed(dev); 6557 6558 cpt_init_clock_gating(dev); 6559 6560 gen6_check_mch_setup(dev); 6561 } 6562 6563 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 6564 { 6565 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 6566 6567 /* 6568 * WaVSThreadDispatchOverride:ivb,vlv 6569 * 6570 * This actually overrides the dispatch 6571 * mode for all thread types. 6572 */ 6573 reg &= ~GEN7_FF_SCHED_MASK; 6574 reg |= GEN7_FF_TS_SCHED_HW; 6575 reg |= GEN7_FF_VS_SCHED_HW; 6576 reg |= GEN7_FF_DS_SCHED_HW; 6577 6578 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 6579 } 6580 6581 static void lpt_init_clock_gating(struct drm_device *dev) 6582 { 6583 struct drm_i915_private *dev_priv = dev->dev_private; 6584 6585 /* 6586 * TODO: this bit should only be enabled when really needed, then 6587 * disabled when not needed anymore in order to save power. 6588 */ 6589 if (HAS_PCH_LPT_LP(dev)) 6590 I915_WRITE(SOUTH_DSPCLK_GATE_D, 6591 I915_READ(SOUTH_DSPCLK_GATE_D) | 6592 PCH_LP_PARTITION_LEVEL_DISABLE); 6593 6594 /* WADPOClockGatingDisable:hsw */ 6595 I915_WRITE(TRANS_CHICKEN1(PIPE_A), 6596 I915_READ(TRANS_CHICKEN1(PIPE_A)) | 6597 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6598 } 6599 6600 static void lpt_suspend_hw(struct drm_device *dev) 6601 { 6602 struct drm_i915_private *dev_priv = dev->dev_private; 6603 6604 if (HAS_PCH_LPT_LP(dev)) { 6605 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); 6606 6607 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 6608 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 6609 } 6610 } 6611 6612 static void broadwell_init_clock_gating(struct drm_device *dev) 6613 { 6614 struct drm_i915_private *dev_priv = dev->dev_private; 6615 enum i915_pipe pipe; 6616 uint32_t misccpctl; 6617 6618 ilk_init_lp_watermarks(dev); 6619 6620 /* WaSwitchSolVfFArbitrationPriority:bdw */ 6621 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6622 6623 /* WaPsrDPAMaskVBlankInSRD:bdw */ 6624 I915_WRITE(CHICKEN_PAR1_1, 6625 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 6626 6627 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 6628 for_each_pipe(dev_priv, pipe) { 6629 I915_WRITE(CHICKEN_PIPESL_1(pipe), 6630 I915_READ(CHICKEN_PIPESL_1(pipe)) | 6631 BDW_DPRS_MASK_VBLANK_SRD); 6632 } 6633 6634 /* WaVSRefCountFullforceMissDisable:bdw */ 6635 /* WaDSRefCountFullforceMissDisable:bdw */ 6636 I915_WRITE(GEN7_FF_THREAD_MODE, 6637 I915_READ(GEN7_FF_THREAD_MODE) & 6638 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6639 6640 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6641 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6642 6643 /* WaDisableSDEUnitClockGating:bdw */ 6644 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6645 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6646 6647 /* 6648 * WaProgramL3SqcReg1Default:bdw 6649 * WaTempDisableDOPClkGating:bdw 6650 */ 6651 misccpctl = I915_READ(GEN7_MISCCPCTL); 6652 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 6653 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); 6654 /* 6655 * Wait at least 100 clocks before re-enabling clock gating. See 6656 * the definition of L3SQCREG1 in BSpec. 6657 */ 6658 POSTING_READ(GEN8_L3SQCREG1); 6659 udelay(1); 6660 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 6661 6662 /* 6663 * WaGttCachingOffByDefault:bdw 6664 * GTT cache may not work with big pages, so if those 6665 * are ever enabled GTT cache may need to be disabled. 6666 */ 6667 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6668 6669 lpt_init_clock_gating(dev); 6670 } 6671 6672 static void haswell_init_clock_gating(struct drm_device *dev) 6673 { 6674 struct drm_i915_private *dev_priv = dev->dev_private; 6675 6676 ilk_init_lp_watermarks(dev); 6677 6678 /* L3 caching of data atomics doesn't work -- disable it. */ 6679 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 6680 I915_WRITE(HSW_ROW_CHICKEN3, 6681 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); 6682 6683 /* This is required by WaCatErrorRejectionIssue:hsw */ 6684 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6685 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6686 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6687 6688 /* WaVSRefCountFullforceMissDisable:hsw */ 6689 I915_WRITE(GEN7_FF_THREAD_MODE, 6690 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); 6691 6692 /* WaDisable_RenderCache_OperationalFlush:hsw */ 6693 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6694 6695 /* enable HiZ Raw Stall Optimization */ 6696 I915_WRITE(CACHE_MODE_0_GEN7, 6697 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6698 6699 /* WaDisable4x2SubspanOptimization:hsw */ 6700 I915_WRITE(CACHE_MODE_1, 6701 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6702 6703 /* 6704 * BSpec recommends 8x4 when MSAA is used, 6705 * however in practice 16x4 seems fastest. 6706 * 6707 * Note that PS/WM thread counts depend on the WIZ hashing 6708 * disable bit, which we don't touch here, but it's good 6709 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6710 */ 6711 I915_WRITE(GEN7_GT_MODE, 6712 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6713 6714 /* WaSampleCChickenBitEnable:hsw */ 6715 I915_WRITE(HALF_SLICE_CHICKEN3, 6716 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); 6717 6718 /* WaSwitchSolVfFArbitrationPriority:hsw */ 6719 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6720 6721 /* WaRsPkgCStateDisplayPMReq:hsw */ 6722 I915_WRITE(CHICKEN_PAR1_1, 6723 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 6724 6725 lpt_init_clock_gating(dev); 6726 } 6727 6728 static void ivybridge_init_clock_gating(struct drm_device *dev) 6729 { 6730 struct drm_i915_private *dev_priv = dev->dev_private; 6731 uint32_t snpcr; 6732 6733 ilk_init_lp_watermarks(dev); 6734 6735 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 6736 6737 /* WaDisableEarlyCull:ivb */ 6738 I915_WRITE(_3D_CHICKEN3, 6739 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6740 6741 /* WaDisableBackToBackFlipFix:ivb */ 6742 I915_WRITE(IVB_CHICKEN3, 6743 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6744 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6745 6746 /* WaDisablePSDDualDispatchEnable:ivb */ 6747 if (IS_IVB_GT1(dev)) 6748 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6749 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6750 6751 /* WaDisable_RenderCache_OperationalFlush:ivb */ 6752 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6753 6754 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 6755 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 6756 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 6757 6758 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 6759 I915_WRITE(GEN7_L3CNTLREG1, 6760 GEN7_WA_FOR_GEN7_L3_CONTROL); 6761 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 6762 GEN7_WA_L3_CHICKEN_MODE); 6763 if (IS_IVB_GT1(dev)) 6764 I915_WRITE(GEN7_ROW_CHICKEN2, 6765 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6766 else { 6767 /* must write both registers */ 6768 I915_WRITE(GEN7_ROW_CHICKEN2, 6769 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6770 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 6771 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6772 } 6773 6774 /* WaForceL3Serialization:ivb */ 6775 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6776 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6777 6778 /* 6779 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6780 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 6781 */ 6782 I915_WRITE(GEN6_UCGCTL2, 6783 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6784 6785 /* This is required by WaCatErrorRejectionIssue:ivb */ 6786 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6787 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6788 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6789 6790 g4x_disable_trickle_feed(dev); 6791 6792 gen7_setup_fixed_func_scheduler(dev_priv); 6793 6794 if (0) { /* causes HiZ corruption on ivb:gt1 */ 6795 /* enable HiZ Raw Stall Optimization */ 6796 I915_WRITE(CACHE_MODE_0_GEN7, 6797 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6798 } 6799 6800 /* WaDisable4x2SubspanOptimization:ivb */ 6801 I915_WRITE(CACHE_MODE_1, 6802 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6803 6804 /* 6805 * BSpec recommends 8x4 when MSAA is used, 6806 * however in practice 16x4 seems fastest. 6807 * 6808 * Note that PS/WM thread counts depend on the WIZ hashing 6809 * disable bit, which we don't touch here, but it's good 6810 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6811 */ 6812 I915_WRITE(GEN7_GT_MODE, 6813 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6814 6815 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 6816 snpcr &= ~GEN6_MBC_SNPCR_MASK; 6817 snpcr |= GEN6_MBC_SNPCR_MED; 6818 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 6819 6820 if (!HAS_PCH_NOP(dev)) 6821 cpt_init_clock_gating(dev); 6822 6823 gen6_check_mch_setup(dev); 6824 } 6825 6826 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 6827 { 6828 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 6829 6830 /* 6831 * Disable trickle feed and enable pnd deadline calculation 6832 */ 6833 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 6834 I915_WRITE(CBR1_VLV, 0); 6835 } 6836 6837 static void valleyview_init_clock_gating(struct drm_device *dev) 6838 { 6839 struct drm_i915_private *dev_priv = dev->dev_private; 6840 6841 vlv_init_display_clock_gating(dev_priv); 6842 6843 /* WaDisableEarlyCull:vlv */ 6844 I915_WRITE(_3D_CHICKEN3, 6845 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6846 6847 /* WaDisableBackToBackFlipFix:vlv */ 6848 I915_WRITE(IVB_CHICKEN3, 6849 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6850 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6851 6852 /* WaPsdDispatchEnable:vlv */ 6853 /* WaDisablePSDDualDispatchEnable:vlv */ 6854 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6855 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 6856 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6857 6858 /* WaDisable_RenderCache_OperationalFlush:vlv */ 6859 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6860 6861 /* WaForceL3Serialization:vlv */ 6862 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6863 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6864 6865 /* WaDisableDopClockGating:vlv */ 6866 I915_WRITE(GEN7_ROW_CHICKEN2, 6867 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6868 6869 /* This is required by WaCatErrorRejectionIssue:vlv */ 6870 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6871 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6872 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6873 6874 gen7_setup_fixed_func_scheduler(dev_priv); 6875 6876 /* 6877 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6878 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 6879 */ 6880 I915_WRITE(GEN6_UCGCTL2, 6881 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6882 6883 /* WaDisableL3Bank2xClockGate:vlv 6884 * Disabling L3 clock gating- MMIO 940c[25] = 1 6885 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 6886 I915_WRITE(GEN7_UCGCTL4, 6887 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 6888 6889 /* 6890 * BSpec says this must be set, even though 6891 * WaDisable4x2SubspanOptimization isn't listed for VLV. 6892 */ 6893 I915_WRITE(CACHE_MODE_1, 6894 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6895 6896 /* 6897 * BSpec recommends 8x4 when MSAA is used, 6898 * however in practice 16x4 seems fastest. 6899 * 6900 * Note that PS/WM thread counts depend on the WIZ hashing 6901 * disable bit, which we don't touch here, but it's good 6902 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6903 */ 6904 I915_WRITE(GEN7_GT_MODE, 6905 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6906 6907 /* 6908 * WaIncreaseL3CreditsForVLVB0:vlv 6909 * This is the hardware default actually. 6910 */ 6911 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 6912 6913 /* 6914 * WaDisableVLVClockGating_VBIIssue:vlv 6915 * Disable clock gating on th GCFG unit to prevent a delay 6916 * in the reporting of vblank events. 6917 */ 6918 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 6919 } 6920 6921 static void cherryview_init_clock_gating(struct drm_device *dev) 6922 { 6923 struct drm_i915_private *dev_priv = dev->dev_private; 6924 6925 vlv_init_display_clock_gating(dev_priv); 6926 6927 /* WaVSRefCountFullforceMissDisable:chv */ 6928 /* WaDSRefCountFullforceMissDisable:chv */ 6929 I915_WRITE(GEN7_FF_THREAD_MODE, 6930 I915_READ(GEN7_FF_THREAD_MODE) & 6931 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6932 6933 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 6934 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6935 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6936 6937 /* WaDisableCSUnitClockGating:chv */ 6938 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | 6939 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6940 6941 /* WaDisableSDEUnitClockGating:chv */ 6942 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6943 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6944 6945 /* 6946 * GTT cache may not work with big pages, so if those 6947 * are ever enabled GTT cache may need to be disabled. 6948 */ 6949 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6950 } 6951 6952 static void g4x_init_clock_gating(struct drm_device *dev) 6953 { 6954 struct drm_i915_private *dev_priv = dev->dev_private; 6955 uint32_t dspclk_gate; 6956 6957 I915_WRITE(RENCLK_GATE_D1, 0); 6958 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 6959 GS_UNIT_CLOCK_GATE_DISABLE | 6960 CL_UNIT_CLOCK_GATE_DISABLE); 6961 I915_WRITE(RAMCLK_GATE_D, 0); 6962 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 6963 OVRUNIT_CLOCK_GATE_DISABLE | 6964 OVCUNIT_CLOCK_GATE_DISABLE; 6965 if (IS_GM45(dev)) 6966 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 6967 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 6968 6969 /* WaDisableRenderCachePipelinedFlush */ 6970 I915_WRITE(CACHE_MODE_0, 6971 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6972 6973 /* WaDisable_RenderCache_OperationalFlush:g4x */ 6974 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6975 6976 g4x_disable_trickle_feed(dev); 6977 } 6978 6979 static void crestline_init_clock_gating(struct drm_device *dev) 6980 { 6981 struct drm_i915_private *dev_priv = dev->dev_private; 6982 6983 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 6984 I915_WRITE(RENCLK_GATE_D2, 0); 6985 I915_WRITE(DSPCLK_GATE_D, 0); 6986 I915_WRITE(RAMCLK_GATE_D, 0); 6987 I915_WRITE16(DEUC, 0); 6988 I915_WRITE(MI_ARB_STATE, 6989 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 6990 6991 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 6992 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6993 } 6994 6995 static void broadwater_init_clock_gating(struct drm_device *dev) 6996 { 6997 struct drm_i915_private *dev_priv = dev->dev_private; 6998 6999 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 7000 I965_RCC_CLOCK_GATE_DISABLE | 7001 I965_RCPB_CLOCK_GATE_DISABLE | 7002 I965_ISC_CLOCK_GATE_DISABLE | 7003 I965_FBC_CLOCK_GATE_DISABLE); 7004 I915_WRITE(RENCLK_GATE_D2, 0); 7005 I915_WRITE(MI_ARB_STATE, 7006 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7007 7008 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7009 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7010 } 7011 7012 static void gen3_init_clock_gating(struct drm_device *dev) 7013 { 7014 struct drm_i915_private *dev_priv = dev->dev_private; 7015 u32 dstate = I915_READ(D_STATE); 7016 7017 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 7018 DSTATE_DOT_CLOCK_GATING; 7019 I915_WRITE(D_STATE, dstate); 7020 7021 if (IS_PINEVIEW(dev)) 7022 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 7023 7024 /* IIR "flip pending" means done if this bit is set */ 7025 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 7026 7027 /* interrupts should cause a wake up from C3 */ 7028 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); 7029 7030 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 7031 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 7032 7033 I915_WRITE(MI_ARB_STATE, 7034 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7035 } 7036 7037 static void i85x_init_clock_gating(struct drm_device *dev) 7038 { 7039 struct drm_i915_private *dev_priv = dev->dev_private; 7040 7041 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 7042 7043 /* interrupts should cause a wake up from C3 */ 7044 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 7045 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 7046 7047 I915_WRITE(MEM_MODE, 7048 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 7049 } 7050 7051 static void i830_init_clock_gating(struct drm_device *dev) 7052 { 7053 struct drm_i915_private *dev_priv = dev->dev_private; 7054 7055 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 7056 7057 I915_WRITE(MEM_MODE, 7058 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 7059 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 7060 } 7061 7062 void intel_init_clock_gating(struct drm_device *dev) 7063 { 7064 struct drm_i915_private *dev_priv = dev->dev_private; 7065 7066 if (dev_priv->display.init_clock_gating) 7067 dev_priv->display.init_clock_gating(dev); 7068 } 7069 7070 void intel_suspend_hw(struct drm_device *dev) 7071 { 7072 if (HAS_PCH_LPT(dev)) 7073 lpt_suspend_hw(dev); 7074 } 7075 7076 /* Set up chip specific power management-related functions */ 7077 void intel_init_pm(struct drm_device *dev) 7078 { 7079 struct drm_i915_private *dev_priv = dev->dev_private; 7080 7081 intel_fbc_init(dev_priv); 7082 7083 /* For cxsr */ 7084 if (IS_PINEVIEW(dev)) 7085 i915_pineview_get_mem_freq(dev); 7086 else if (IS_GEN5(dev)) 7087 i915_ironlake_get_mem_freq(dev); 7088 7089 /* For FIFO watermark updates */ 7090 if (INTEL_INFO(dev)->gen >= 9) { 7091 skl_setup_wm_latency(dev); 7092 7093 if (IS_BROXTON(dev)) 7094 dev_priv->display.init_clock_gating = 7095 bxt_init_clock_gating; 7096 dev_priv->display.update_wm = skl_update_wm; 7097 } else if (HAS_PCH_SPLIT(dev)) { 7098 ilk_setup_wm_latency(dev); 7099 7100 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && 7101 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 7102 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && 7103 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { 7104 dev_priv->display.update_wm = ilk_update_wm; 7105 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; 7106 dev_priv->display.program_watermarks = ilk_program_watermarks; 7107 } else { 7108 DRM_DEBUG_KMS("Failed to read display plane latency. " 7109 "Disable CxSR\n"); 7110 } 7111 7112 if (IS_GEN5(dev)) 7113 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 7114 else if (IS_GEN6(dev)) 7115 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 7116 else if (IS_IVYBRIDGE(dev)) 7117 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 7118 else if (IS_HASWELL(dev)) 7119 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 7120 else if (INTEL_INFO(dev)->gen == 8) 7121 dev_priv->display.init_clock_gating = broadwell_init_clock_gating; 7122 } else if (IS_CHERRYVIEW(dev)) { 7123 vlv_setup_wm_latency(dev); 7124 7125 dev_priv->display.update_wm = vlv_update_wm; 7126 dev_priv->display.init_clock_gating = 7127 cherryview_init_clock_gating; 7128 } else if (IS_VALLEYVIEW(dev)) { 7129 vlv_setup_wm_latency(dev); 7130 7131 dev_priv->display.update_wm = vlv_update_wm; 7132 dev_priv->display.init_clock_gating = 7133 valleyview_init_clock_gating; 7134 } else if (IS_PINEVIEW(dev)) { 7135 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 7136 dev_priv->is_ddr3, 7137 dev_priv->fsb_freq, 7138 dev_priv->mem_freq)) { 7139 DRM_INFO("failed to find known CxSR latency " 7140 "(found ddr%s fsb freq %d, mem freq %d), " 7141 "disabling CxSR\n", 7142 (dev_priv->is_ddr3 == 1) ? "3" : "2", 7143 dev_priv->fsb_freq, dev_priv->mem_freq); 7144 /* Disable CxSR and never update its watermark again */ 7145 intel_set_memory_cxsr(dev_priv, false); 7146 dev_priv->display.update_wm = NULL; 7147 } else 7148 dev_priv->display.update_wm = pineview_update_wm; 7149 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7150 } else if (IS_G4X(dev)) { 7151 dev_priv->display.update_wm = g4x_update_wm; 7152 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 7153 } else if (IS_GEN4(dev)) { 7154 dev_priv->display.update_wm = i965_update_wm; 7155 if (IS_CRESTLINE(dev)) 7156 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 7157 else if (IS_BROADWATER(dev)) 7158 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 7159 } else if (IS_GEN3(dev)) { 7160 dev_priv->display.update_wm = i9xx_update_wm; 7161 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 7162 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7163 } else if (IS_GEN2(dev)) { 7164 if (INTEL_INFO(dev)->num_pipes == 1) { 7165 dev_priv->display.update_wm = i845_update_wm; 7166 dev_priv->display.get_fifo_size = i845_get_fifo_size; 7167 } else { 7168 dev_priv->display.update_wm = i9xx_update_wm; 7169 dev_priv->display.get_fifo_size = i830_get_fifo_size; 7170 } 7171 7172 if (IS_I85X(dev) || IS_I865G(dev)) 7173 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 7174 else 7175 dev_priv->display.init_clock_gating = i830_init_clock_gating; 7176 } else { 7177 DRM_ERROR("unexpected fall-through in intel_init_pm\n"); 7178 } 7179 } 7180 7181 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) 7182 { 7183 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7184 7185 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7186 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 7187 return -EAGAIN; 7188 } 7189 7190 I915_WRITE(GEN6_PCODE_DATA, *val); 7191 I915_WRITE(GEN6_PCODE_DATA1, 0); 7192 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7193 7194 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7195 500)) { 7196 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 7197 return -ETIMEDOUT; 7198 } 7199 7200 *val = I915_READ(GEN6_PCODE_DATA); 7201 I915_WRITE(GEN6_PCODE_DATA, 0); 7202 7203 return 0; 7204 } 7205 7206 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) 7207 { 7208 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7209 7210 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7211 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 7212 return -EAGAIN; 7213 } 7214 7215 I915_WRITE(GEN6_PCODE_DATA, val); 7216 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7217 7218 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7219 500)) { 7220 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 7221 return -ETIMEDOUT; 7222 } 7223 7224 I915_WRITE(GEN6_PCODE_DATA, 0); 7225 7226 return 0; 7227 } 7228 7229 static int vlv_gpu_freq_div(unsigned int czclk_freq) 7230 { 7231 switch (czclk_freq) { 7232 case 200: 7233 return 10; 7234 case 267: 7235 return 12; 7236 case 320: 7237 case 333: 7238 return 16; 7239 case 400: 7240 return 20; 7241 default: 7242 return -1; 7243 } 7244 } 7245 7246 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) 7247 { 7248 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7249 7250 div = vlv_gpu_freq_div(czclk_freq); 7251 if (div < 0) 7252 return div; 7253 7254 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); 7255 } 7256 7257 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) 7258 { 7259 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7260 7261 mul = vlv_gpu_freq_div(czclk_freq); 7262 if (mul < 0) 7263 return mul; 7264 7265 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; 7266 } 7267 7268 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) 7269 { 7270 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7271 7272 div = vlv_gpu_freq_div(czclk_freq); 7273 if (div < 0) 7274 return div; 7275 div /= 2; 7276 7277 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; 7278 } 7279 7280 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) 7281 { 7282 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000); 7283 7284 mul = vlv_gpu_freq_div(czclk_freq); 7285 if (mul < 0) 7286 return mul; 7287 mul /= 2; 7288 7289 /* CHV needs even values */ 7290 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; 7291 } 7292 7293 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) 7294 { 7295 if (IS_GEN9(dev_priv->dev)) 7296 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, 7297 GEN9_FREQ_SCALER); 7298 else if (IS_CHERRYVIEW(dev_priv->dev)) 7299 return chv_gpu_freq(dev_priv, val); 7300 else if (IS_VALLEYVIEW(dev_priv->dev)) 7301 return byt_gpu_freq(dev_priv, val); 7302 else 7303 return val * GT_FREQUENCY_MULTIPLIER; 7304 } 7305 7306 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) 7307 { 7308 if (IS_GEN9(dev_priv->dev)) 7309 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, 7310 GT_FREQUENCY_MULTIPLIER); 7311 else if (IS_CHERRYVIEW(dev_priv->dev)) 7312 return chv_freq_opcode(dev_priv, val); 7313 else if (IS_VALLEYVIEW(dev_priv->dev)) 7314 return byt_freq_opcode(dev_priv, val); 7315 else 7316 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); 7317 } 7318 7319 struct request_boost { 7320 struct work_struct work; 7321 struct drm_i915_gem_request *req; 7322 }; 7323 7324 static void __intel_rps_boost_work(struct work_struct *work) 7325 { 7326 struct request_boost *boost = container_of(work, struct request_boost, work); 7327 struct drm_i915_gem_request *req = boost->req; 7328 7329 if (!i915_gem_request_completed(req, true)) 7330 gen6_rps_boost(to_i915(req->ring->dev), NULL, 7331 req->emitted_jiffies); 7332 7333 i915_gem_request_unreference__unlocked(req); 7334 kfree(boost); 7335 } 7336 7337 void intel_queue_rps_boost_for_request(struct drm_device *dev, 7338 struct drm_i915_gem_request *req) 7339 { 7340 struct request_boost *boost; 7341 7342 if (req == NULL || INTEL_INFO(dev)->gen < 6) 7343 return; 7344 7345 if (i915_gem_request_completed(req, true)) 7346 return; 7347 7348 boost = kmalloc(sizeof(*boost), M_DRM, M_NOWAIT); 7349 if (boost == NULL) 7350 return; 7351 7352 i915_gem_request_reference(req); 7353 boost->req = req; 7354 7355 INIT_WORK(&boost->work, __intel_rps_boost_work); 7356 queue_work(to_i915(dev)->wq, &boost->work); 7357 } 7358 7359 void intel_pm_setup(struct drm_device *dev) 7360 { 7361 struct drm_i915_private *dev_priv = dev->dev_private; 7362 7363 lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE); 7364 lockinit(&dev_priv->rps.client_lock, "i915rcl", 0, LK_CANRECURSE); 7365 7366 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 7367 intel_gen6_powersave_work); 7368 INIT_LIST_HEAD(&dev_priv->rps.clients); 7369 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); 7370 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); 7371 7372 dev_priv->pm.suspended = false; 7373 atomic_set(&dev_priv->pm.wakeref_count, 0); 7374 atomic_set(&dev_priv->pm.atomic_seq, 0); 7375 } 7376