1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <linux/module.h> 31 #include <machine/clock.h> 32 33 /** 34 * RC6 is a special power stage which allows the GPU to enter an very 35 * low-voltage mode when idle, using down to 0V while at this stage. This 36 * stage is entered automatically when the GPU is idle when RC6 support is 37 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 38 * 39 * There are different RC6 modes available in Intel GPU, which differentiate 40 * among each other with the latency required to enter and leave RC6 and 41 * voltage consumed by the GPU in different states. 42 * 43 * The combination of the following flags define which states GPU is allowed 44 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 45 * RC6pp is deepest RC6. Their support by hardware varies according to the 46 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 47 * which brings the most power savings; deeper states save more power, but 48 * require higher latency to switch to and wake up. 49 */ 50 #define INTEL_RC6_ENABLE (1<<0) 51 #define INTEL_RC6p_ENABLE (1<<1) 52 #define INTEL_RC6pp_ENABLE (1<<2) 53 54 static void gen9_init_clock_gating(struct drm_device *dev) 55 { 56 struct drm_i915_private *dev_priv = dev->dev_private; 57 58 /* WaEnableLbsSlaRetryTimerDecrement:skl */ 59 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | 60 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); 61 62 /* WaDisableKillLogic:bxt,skl */ 63 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | 64 ECOCHK_DIS_TLB); 65 } 66 67 static void skl_init_clock_gating(struct drm_device *dev) 68 { 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 71 gen9_init_clock_gating(dev); 72 73 if (INTEL_REVID(dev) <= SKL_REVID_B0) { 74 /* 75 * WaDisableSDEUnitClockGating:skl 76 * WaSetGAPSunitClckGateDisable:skl 77 */ 78 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 79 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE | 80 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 81 82 /* WaDisableVFUnitClockGating:skl */ 83 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) | 84 GEN6_VFUNIT_CLOCK_GATE_DISABLE); 85 } 86 87 if (INTEL_REVID(dev) <= SKL_REVID_D0) { 88 /* WaDisableHDCInvalidation:skl */ 89 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | 90 BDW_DISABLE_HDC_INVALIDATION); 91 92 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ 93 I915_WRITE(FF_SLICE_CS_CHICKEN2, 94 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); 95 } 96 97 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes 98 * involving this register should also be added to WA batch as required. 99 */ 100 if (INTEL_REVID(dev) <= SKL_REVID_E0) 101 /* WaDisableLSQCROPERFforOCL:skl */ 102 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | 103 GEN8_LQSC_RO_PERF_DIS); 104 105 /* WaEnableGapsTsvCreditFix:skl */ 106 if (IS_SKYLAKE(dev) && (INTEL_REVID(dev) >= SKL_REVID_C0)) { 107 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) | 108 GEN9_GAPS_TSV_CREDIT_DISABLE)); 109 } 110 } 111 112 static void bxt_init_clock_gating(struct drm_device *dev) 113 { 114 struct drm_i915_private *dev_priv = dev->dev_private; 115 116 gen9_init_clock_gating(dev); 117 118 /* 119 * FIXME: 120 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only. 121 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. 122 */ 123 /* WaDisableSDEUnitClockGating:bxt */ 124 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 125 GEN8_SDEUNIT_CLOCK_GATE_DISABLE | 126 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); 127 128 /* FIXME: apply on A0 only */ 129 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF); 130 } 131 132 static void i915_pineview_get_mem_freq(struct drm_device *dev) 133 { 134 struct drm_i915_private *dev_priv = dev->dev_private; 135 u32 tmp; 136 137 tmp = I915_READ(CLKCFG); 138 139 switch (tmp & CLKCFG_FSB_MASK) { 140 case CLKCFG_FSB_533: 141 dev_priv->fsb_freq = 533; /* 133*4 */ 142 break; 143 case CLKCFG_FSB_800: 144 dev_priv->fsb_freq = 800; /* 200*4 */ 145 break; 146 case CLKCFG_FSB_667: 147 dev_priv->fsb_freq = 667; /* 167*4 */ 148 break; 149 case CLKCFG_FSB_400: 150 dev_priv->fsb_freq = 400; /* 100*4 */ 151 break; 152 } 153 154 switch (tmp & CLKCFG_MEM_MASK) { 155 case CLKCFG_MEM_533: 156 dev_priv->mem_freq = 533; 157 break; 158 case CLKCFG_MEM_667: 159 dev_priv->mem_freq = 667; 160 break; 161 case CLKCFG_MEM_800: 162 dev_priv->mem_freq = 800; 163 break; 164 } 165 166 /* detect pineview DDR3 setting */ 167 tmp = I915_READ(CSHRDDR3CTL); 168 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; 169 } 170 171 static void i915_ironlake_get_mem_freq(struct drm_device *dev) 172 { 173 struct drm_i915_private *dev_priv = dev->dev_private; 174 u16 ddrpll, csipll; 175 176 ddrpll = I915_READ16(DDRMPLL1); 177 csipll = I915_READ16(CSIPLL0); 178 179 switch (ddrpll & 0xff) { 180 case 0xc: 181 dev_priv->mem_freq = 800; 182 break; 183 case 0x10: 184 dev_priv->mem_freq = 1066; 185 break; 186 case 0x14: 187 dev_priv->mem_freq = 1333; 188 break; 189 case 0x18: 190 dev_priv->mem_freq = 1600; 191 break; 192 default: 193 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", 194 ddrpll & 0xff); 195 dev_priv->mem_freq = 0; 196 break; 197 } 198 199 dev_priv->ips.r_t = dev_priv->mem_freq; 200 201 switch (csipll & 0x3ff) { 202 case 0x00c: 203 dev_priv->fsb_freq = 3200; 204 break; 205 case 0x00e: 206 dev_priv->fsb_freq = 3733; 207 break; 208 case 0x010: 209 dev_priv->fsb_freq = 4266; 210 break; 211 case 0x012: 212 dev_priv->fsb_freq = 4800; 213 break; 214 case 0x014: 215 dev_priv->fsb_freq = 5333; 216 break; 217 case 0x016: 218 dev_priv->fsb_freq = 5866; 219 break; 220 case 0x018: 221 dev_priv->fsb_freq = 6400; 222 break; 223 default: 224 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", 225 csipll & 0x3ff); 226 dev_priv->fsb_freq = 0; 227 break; 228 } 229 230 if (dev_priv->fsb_freq == 3200) { 231 dev_priv->ips.c_m = 0; 232 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { 233 dev_priv->ips.c_m = 1; 234 } else { 235 dev_priv->ips.c_m = 2; 236 } 237 } 238 239 static const struct cxsr_latency cxsr_latency_table[] = { 240 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ 241 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ 242 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ 243 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ 244 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ 245 246 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ 247 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ 248 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ 249 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ 250 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ 251 252 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ 253 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ 254 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ 255 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ 256 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ 257 258 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ 259 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ 260 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ 261 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ 262 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ 263 264 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ 265 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ 266 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ 267 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ 268 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ 269 270 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ 271 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ 272 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ 273 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ 274 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ 275 }; 276 277 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 278 int is_ddr3, 279 int fsb, 280 int mem) 281 { 282 const struct cxsr_latency *latency; 283 int i; 284 285 if (fsb == 0 || mem == 0) 286 return NULL; 287 288 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { 289 latency = &cxsr_latency_table[i]; 290 if (is_desktop == latency->is_desktop && 291 is_ddr3 == latency->is_ddr3 && 292 fsb == latency->fsb_freq && mem == latency->mem_freq) 293 return latency; 294 } 295 296 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 297 298 return NULL; 299 } 300 301 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) 302 { 303 u32 val; 304 305 mutex_lock(&dev_priv->rps.hw_lock); 306 307 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 308 if (enable) 309 val &= ~FORCE_DDR_HIGH_FREQ; 310 else 311 val |= FORCE_DDR_HIGH_FREQ; 312 val &= ~FORCE_DDR_LOW_FREQ; 313 val |= FORCE_DDR_FREQ_REQ_ACK; 314 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 315 316 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 317 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) 318 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); 319 320 mutex_unlock(&dev_priv->rps.hw_lock); 321 } 322 323 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) 324 { 325 u32 val; 326 327 mutex_lock(&dev_priv->rps.hw_lock); 328 329 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 330 if (enable) 331 val |= DSP_MAXFIFO_PM5_ENABLE; 332 else 333 val &= ~DSP_MAXFIFO_PM5_ENABLE; 334 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); 335 336 mutex_unlock(&dev_priv->rps.hw_lock); 337 } 338 339 #define FW_WM(value, plane) \ 340 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) 341 342 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) 343 { 344 struct drm_device *dev = dev_priv->dev; 345 u32 val; 346 347 if (IS_VALLEYVIEW(dev)) { 348 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); 349 POSTING_READ(FW_BLC_SELF_VLV); 350 dev_priv->wm.vlv.cxsr = enable; 351 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { 352 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); 353 POSTING_READ(FW_BLC_SELF); 354 } else if (IS_PINEVIEW(dev)) { 355 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; 356 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; 357 I915_WRITE(DSPFW3, val); 358 POSTING_READ(DSPFW3); 359 } else if (IS_I945G(dev) || IS_I945GM(dev)) { 360 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : 361 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); 362 I915_WRITE(FW_BLC_SELF, val); 363 POSTING_READ(FW_BLC_SELF); 364 } else if (IS_I915GM(dev)) { 365 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : 366 _MASKED_BIT_DISABLE(INSTPM_SELF_EN); 367 I915_WRITE(INSTPM, val); 368 POSTING_READ(INSTPM); 369 } else { 370 return; 371 } 372 373 DRM_DEBUG_KMS("memory self-refresh is %s\n", 374 enable ? "enabled" : "disabled"); 375 } 376 377 378 /* 379 * Latency for FIFO fetches is dependent on several factors: 380 * - memory configuration (speed, channels) 381 * - chipset 382 * - current MCH state 383 * It can be fairly high in some situations, so here we assume a fairly 384 * pessimal value. It's a tradeoff between extra memory fetches (if we 385 * set this value too high, the FIFO will fetch frequently to stay full) 386 * and power consumption (set it too low to save power and we might see 387 * FIFO underruns and display "flicker"). 388 * 389 * A value of 5us seems to be a good balance; safe for very low end 390 * platforms but not overly aggressive on lower latency configs. 391 */ 392 static const int pessimal_latency_ns = 5000; 393 394 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ 395 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) 396 397 static int vlv_get_fifo_size(struct drm_device *dev, 398 enum i915_pipe pipe, int plane) 399 { 400 struct drm_i915_private *dev_priv = dev->dev_private; 401 int sprite0_start, sprite1_start, size; 402 403 switch (pipe) { 404 uint32_t dsparb, dsparb2, dsparb3; 405 case PIPE_A: 406 dsparb = I915_READ(DSPARB); 407 dsparb2 = I915_READ(DSPARB2); 408 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); 409 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); 410 break; 411 case PIPE_B: 412 dsparb = I915_READ(DSPARB); 413 dsparb2 = I915_READ(DSPARB2); 414 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); 415 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); 416 break; 417 case PIPE_C: 418 dsparb2 = I915_READ(DSPARB2); 419 dsparb3 = I915_READ(DSPARB3); 420 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); 421 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); 422 break; 423 default: 424 return 0; 425 } 426 427 switch (plane) { 428 case 0: 429 size = sprite0_start; 430 break; 431 case 1: 432 size = sprite1_start - sprite0_start; 433 break; 434 case 2: 435 size = 512 - 1 - sprite1_start; 436 break; 437 default: 438 return 0; 439 } 440 441 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", 442 pipe_name(pipe), plane == 0 ? "primary" : "sprite", 443 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), 444 size); 445 446 return size; 447 } 448 449 static int i9xx_get_fifo_size(struct drm_device *dev, int plane) 450 { 451 struct drm_i915_private *dev_priv = dev->dev_private; 452 uint32_t dsparb = I915_READ(DSPARB); 453 int size; 454 455 size = dsparb & 0x7f; 456 if (plane) 457 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; 458 459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 460 plane ? "B" : "A", size); 461 462 return size; 463 } 464 465 static int i830_get_fifo_size(struct drm_device *dev, int plane) 466 { 467 struct drm_i915_private *dev_priv = dev->dev_private; 468 uint32_t dsparb = I915_READ(DSPARB); 469 int size; 470 471 size = dsparb & 0x1ff; 472 if (plane) 473 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; 474 size >>= 1; /* Convert to cachelines */ 475 476 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 477 plane ? "B" : "A", size); 478 479 return size; 480 } 481 482 static int i845_get_fifo_size(struct drm_device *dev, int plane) 483 { 484 struct drm_i915_private *dev_priv = dev->dev_private; 485 uint32_t dsparb = I915_READ(DSPARB); 486 int size; 487 488 size = dsparb & 0x7f; 489 size >>= 2; /* Convert to cachelines */ 490 491 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, 492 plane ? "B" : "A", 493 size); 494 495 return size; 496 } 497 498 /* Pineview has different values for various configs */ 499 static const struct intel_watermark_params pineview_display_wm = { 500 .fifo_size = PINEVIEW_DISPLAY_FIFO, 501 .max_wm = PINEVIEW_MAX_WM, 502 .default_wm = PINEVIEW_DFT_WM, 503 .guard_size = PINEVIEW_GUARD_WM, 504 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 505 }; 506 static const struct intel_watermark_params pineview_display_hplloff_wm = { 507 .fifo_size = PINEVIEW_DISPLAY_FIFO, 508 .max_wm = PINEVIEW_MAX_WM, 509 .default_wm = PINEVIEW_DFT_HPLLOFF_WM, 510 .guard_size = PINEVIEW_GUARD_WM, 511 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 512 }; 513 static const struct intel_watermark_params pineview_cursor_wm = { 514 .fifo_size = PINEVIEW_CURSOR_FIFO, 515 .max_wm = PINEVIEW_CURSOR_MAX_WM, 516 .default_wm = PINEVIEW_CURSOR_DFT_WM, 517 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 518 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 519 }; 520 static const struct intel_watermark_params pineview_cursor_hplloff_wm = { 521 .fifo_size = PINEVIEW_CURSOR_FIFO, 522 .max_wm = PINEVIEW_CURSOR_MAX_WM, 523 .default_wm = PINEVIEW_CURSOR_DFT_WM, 524 .guard_size = PINEVIEW_CURSOR_GUARD_WM, 525 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, 526 }; 527 static const struct intel_watermark_params g4x_wm_info = { 528 .fifo_size = G4X_FIFO_SIZE, 529 .max_wm = G4X_MAX_WM, 530 .default_wm = G4X_MAX_WM, 531 .guard_size = 2, 532 .cacheline_size = G4X_FIFO_LINE_SIZE, 533 }; 534 static const struct intel_watermark_params g4x_cursor_wm_info = { 535 .fifo_size = I965_CURSOR_FIFO, 536 .max_wm = I965_CURSOR_MAX_WM, 537 .default_wm = I965_CURSOR_DFT_WM, 538 .guard_size = 2, 539 .cacheline_size = G4X_FIFO_LINE_SIZE, 540 }; 541 static const struct intel_watermark_params valleyview_wm_info = { 542 .fifo_size = VALLEYVIEW_FIFO_SIZE, 543 .max_wm = VALLEYVIEW_MAX_WM, 544 .default_wm = VALLEYVIEW_MAX_WM, 545 .guard_size = 2, 546 .cacheline_size = G4X_FIFO_LINE_SIZE, 547 }; 548 static const struct intel_watermark_params valleyview_cursor_wm_info = { 549 .fifo_size = I965_CURSOR_FIFO, 550 .max_wm = VALLEYVIEW_CURSOR_MAX_WM, 551 .default_wm = I965_CURSOR_DFT_WM, 552 .guard_size = 2, 553 .cacheline_size = G4X_FIFO_LINE_SIZE, 554 }; 555 static const struct intel_watermark_params i965_cursor_wm_info = { 556 .fifo_size = I965_CURSOR_FIFO, 557 .max_wm = I965_CURSOR_MAX_WM, 558 .default_wm = I965_CURSOR_DFT_WM, 559 .guard_size = 2, 560 .cacheline_size = I915_FIFO_LINE_SIZE, 561 }; 562 static const struct intel_watermark_params i945_wm_info = { 563 .fifo_size = I945_FIFO_SIZE, 564 .max_wm = I915_MAX_WM, 565 .default_wm = 1, 566 .guard_size = 2, 567 .cacheline_size = I915_FIFO_LINE_SIZE, 568 }; 569 static const struct intel_watermark_params i915_wm_info = { 570 .fifo_size = I915_FIFO_SIZE, 571 .max_wm = I915_MAX_WM, 572 .default_wm = 1, 573 .guard_size = 2, 574 .cacheline_size = I915_FIFO_LINE_SIZE, 575 }; 576 static const struct intel_watermark_params i830_a_wm_info = { 577 .fifo_size = I855GM_FIFO_SIZE, 578 .max_wm = I915_MAX_WM, 579 .default_wm = 1, 580 .guard_size = 2, 581 .cacheline_size = I830_FIFO_LINE_SIZE, 582 }; 583 static const struct intel_watermark_params i830_bc_wm_info = { 584 .fifo_size = I855GM_FIFO_SIZE, 585 .max_wm = I915_MAX_WM/2, 586 .default_wm = 1, 587 .guard_size = 2, 588 .cacheline_size = I830_FIFO_LINE_SIZE, 589 }; 590 static const struct intel_watermark_params i845_wm_info = { 591 .fifo_size = I830_FIFO_SIZE, 592 .max_wm = I915_MAX_WM, 593 .default_wm = 1, 594 .guard_size = 2, 595 .cacheline_size = I830_FIFO_LINE_SIZE, 596 }; 597 598 /** 599 * intel_calculate_wm - calculate watermark level 600 * @clock_in_khz: pixel clock 601 * @wm: chip FIFO params 602 * @pixel_size: display pixel size 603 * @latency_ns: memory latency for the platform 604 * 605 * Calculate the watermark level (the level at which the display plane will 606 * start fetching from memory again). Each chip has a different display 607 * FIFO size and allocation, so the caller needs to figure that out and pass 608 * in the correct intel_watermark_params structure. 609 * 610 * As the pixel clock runs, the FIFO will be drained at a rate that depends 611 * on the pixel size. When it reaches the watermark level, it'll start 612 * fetching FIFO line sized based chunks from memory until the FIFO fills 613 * past the watermark point. If the FIFO drains completely, a FIFO underrun 614 * will occur, and a display engine hang could result. 615 */ 616 static unsigned long intel_calculate_wm(unsigned long clock_in_khz, 617 const struct intel_watermark_params *wm, 618 int fifo_size, 619 int pixel_size, 620 unsigned long latency_ns) 621 { 622 long entries_required, wm_size; 623 624 /* 625 * Note: we need to make sure we don't overflow for various clock & 626 * latency values. 627 * clocks go from a few thousand to several hundred thousand. 628 * latency is usually a few thousand 629 */ 630 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / 631 1000; 632 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); 633 634 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); 635 636 wm_size = fifo_size - (entries_required + wm->guard_size); 637 638 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); 639 640 /* Don't promote wm_size to unsigned... */ 641 if (wm_size > (long)wm->max_wm) 642 wm_size = wm->max_wm; 643 if (wm_size <= 0) 644 wm_size = wm->default_wm; 645 646 /* 647 * Bspec seems to indicate that the value shouldn't be lower than 648 * 'burst size + 1'. Certainly 830 is quite unhappy with low values. 649 * Lets go for 8 which is the burst size since certain platforms 650 * already use a hardcoded 8 (which is what the spec says should be 651 * done). 652 */ 653 if (wm_size <= 8) 654 wm_size = 8; 655 656 return wm_size; 657 } 658 659 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) 660 { 661 struct drm_crtc *crtc, *enabled = NULL; 662 663 for_each_crtc(dev, crtc) { 664 if (intel_crtc_active(crtc)) { 665 if (enabled) 666 return NULL; 667 enabled = crtc; 668 } 669 } 670 671 return enabled; 672 } 673 674 static void pineview_update_wm(struct drm_crtc *unused_crtc) 675 { 676 struct drm_device *dev = unused_crtc->dev; 677 struct drm_i915_private *dev_priv = dev->dev_private; 678 struct drm_crtc *crtc; 679 const struct cxsr_latency *latency; 680 u32 reg; 681 unsigned long wm; 682 683 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, 684 dev_priv->fsb_freq, dev_priv->mem_freq); 685 if (!latency) { 686 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); 687 intel_set_memory_cxsr(dev_priv, false); 688 return; 689 } 690 691 crtc = single_enabled_crtc(dev); 692 if (crtc) { 693 const struct drm_display_mode *adjusted_mode; 694 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 695 int clock; 696 697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 698 clock = adjusted_mode->crtc_clock; 699 700 /* Display SR */ 701 wm = intel_calculate_wm(clock, &pineview_display_wm, 702 pineview_display_wm.fifo_size, 703 pixel_size, latency->display_sr); 704 reg = I915_READ(DSPFW1); 705 reg &= ~DSPFW_SR_MASK; 706 reg |= FW_WM(wm, SR); 707 I915_WRITE(DSPFW1, reg); 708 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); 709 710 /* cursor SR */ 711 wm = intel_calculate_wm(clock, &pineview_cursor_wm, 712 pineview_display_wm.fifo_size, 713 pixel_size, latency->cursor_sr); 714 reg = I915_READ(DSPFW3); 715 reg &= ~DSPFW_CURSOR_SR_MASK; 716 reg |= FW_WM(wm, CURSOR_SR); 717 I915_WRITE(DSPFW3, reg); 718 719 /* Display HPLL off SR */ 720 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, 721 pineview_display_hplloff_wm.fifo_size, 722 pixel_size, latency->display_hpll_disable); 723 reg = I915_READ(DSPFW3); 724 reg &= ~DSPFW_HPLL_SR_MASK; 725 reg |= FW_WM(wm, HPLL_SR); 726 I915_WRITE(DSPFW3, reg); 727 728 /* cursor HPLL off SR */ 729 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, 730 pineview_display_hplloff_wm.fifo_size, 731 pixel_size, latency->cursor_hpll_disable); 732 reg = I915_READ(DSPFW3); 733 reg &= ~DSPFW_HPLL_CURSOR_MASK; 734 reg |= FW_WM(wm, HPLL_CURSOR); 735 I915_WRITE(DSPFW3, reg); 736 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); 737 738 intel_set_memory_cxsr(dev_priv, true); 739 } else { 740 intel_set_memory_cxsr(dev_priv, false); 741 } 742 } 743 744 static bool g4x_compute_wm0(struct drm_device *dev, 745 int plane, 746 const struct intel_watermark_params *display, 747 int display_latency_ns, 748 const struct intel_watermark_params *cursor, 749 int cursor_latency_ns, 750 int *plane_wm, 751 int *cursor_wm) 752 { 753 struct drm_crtc *crtc; 754 const struct drm_display_mode *adjusted_mode; 755 int htotal, hdisplay, clock, pixel_size; 756 int line_time_us, line_count; 757 int entries, tlb_miss; 758 759 crtc = intel_get_crtc_for_plane(dev, plane); 760 if (!intel_crtc_active(crtc)) { 761 *cursor_wm = cursor->guard_size; 762 *plane_wm = display->guard_size; 763 return false; 764 } 765 766 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 767 clock = adjusted_mode->crtc_clock; 768 htotal = adjusted_mode->crtc_htotal; 769 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 770 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 771 772 /* Use the small buffer method to calculate plane watermark */ 773 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; 774 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; 775 if (tlb_miss > 0) 776 entries += tlb_miss; 777 entries = DIV_ROUND_UP(entries, display->cacheline_size); 778 *plane_wm = entries + display->guard_size; 779 if (*plane_wm > (int)display->max_wm) 780 *plane_wm = display->max_wm; 781 782 /* Use the large buffer method to calculate cursor watermark */ 783 line_time_us = max(htotal * 1000 / clock, 1); 784 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 785 entries = line_count * crtc->cursor->state->crtc_w * pixel_size; 786 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 787 if (tlb_miss > 0) 788 entries += tlb_miss; 789 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 790 *cursor_wm = entries + cursor->guard_size; 791 if (*cursor_wm > (int)cursor->max_wm) 792 *cursor_wm = (int)cursor->max_wm; 793 794 return true; 795 } 796 797 /* 798 * Check the wm result. 799 * 800 * If any calculated watermark values is larger than the maximum value that 801 * can be programmed into the associated watermark register, that watermark 802 * must be disabled. 803 */ 804 static bool g4x_check_srwm(struct drm_device *dev, 805 int display_wm, int cursor_wm, 806 const struct intel_watermark_params *display, 807 const struct intel_watermark_params *cursor) 808 { 809 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", 810 display_wm, cursor_wm); 811 812 if (display_wm > display->max_wm) { 813 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", 814 display_wm, display->max_wm); 815 return false; 816 } 817 818 if (cursor_wm > cursor->max_wm) { 819 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", 820 cursor_wm, cursor->max_wm); 821 return false; 822 } 823 824 if (!(display_wm || cursor_wm)) { 825 DRM_DEBUG_KMS("SR latency is 0, disabling\n"); 826 return false; 827 } 828 829 return true; 830 } 831 832 static bool g4x_compute_srwm(struct drm_device *dev, 833 int plane, 834 int latency_ns, 835 const struct intel_watermark_params *display, 836 const struct intel_watermark_params *cursor, 837 int *display_wm, int *cursor_wm) 838 { 839 struct drm_crtc *crtc; 840 const struct drm_display_mode *adjusted_mode; 841 int hdisplay, htotal, pixel_size, clock; 842 unsigned long line_time_us; 843 int line_count, line_size; 844 int small, large; 845 int entries; 846 847 if (!latency_ns) { 848 *display_wm = *cursor_wm = 0; 849 return false; 850 } 851 852 crtc = intel_get_crtc_for_plane(dev, plane); 853 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 854 clock = adjusted_mode->crtc_clock; 855 htotal = adjusted_mode->crtc_htotal; 856 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 857 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 858 859 line_time_us = max(htotal * 1000 / clock, 1); 860 line_count = (latency_ns / line_time_us + 1000) / 1000; 861 line_size = hdisplay * pixel_size; 862 863 /* Use the minimum of the small and large buffer method for primary */ 864 small = ((clock * pixel_size / 1000) * latency_ns) / 1000; 865 large = line_count * line_size; 866 867 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); 868 *display_wm = entries + display->guard_size; 869 870 /* calculate the self-refresh watermark for display cursor */ 871 entries = line_count * pixel_size * crtc->cursor->state->crtc_w; 872 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); 873 *cursor_wm = entries + cursor->guard_size; 874 875 return g4x_check_srwm(dev, 876 *display_wm, *cursor_wm, 877 display, cursor); 878 } 879 880 #define FW_WM_VLV(value, plane) \ 881 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) 882 883 static void vlv_write_wm_values(struct intel_crtc *crtc, 884 const struct vlv_wm_values *wm) 885 { 886 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 887 enum i915_pipe pipe = crtc->pipe; 888 889 I915_WRITE(VLV_DDL(pipe), 890 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | 891 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | 892 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | 893 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); 894 895 I915_WRITE(DSPFW1, 896 FW_WM(wm->sr.plane, SR) | 897 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | 898 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | 899 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); 900 I915_WRITE(DSPFW2, 901 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | 902 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | 903 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); 904 I915_WRITE(DSPFW3, 905 FW_WM(wm->sr.cursor, CURSOR_SR)); 906 907 if (IS_CHERRYVIEW(dev_priv)) { 908 I915_WRITE(DSPFW7_CHV, 909 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 910 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 911 I915_WRITE(DSPFW8_CHV, 912 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | 913 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); 914 I915_WRITE(DSPFW9_CHV, 915 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | 916 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); 917 I915_WRITE(DSPHOWM, 918 FW_WM(wm->sr.plane >> 9, SR_HI) | 919 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | 920 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | 921 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | 922 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 923 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 924 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 925 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 926 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 927 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 928 } else { 929 I915_WRITE(DSPFW7, 930 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | 931 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); 932 I915_WRITE(DSPHOWM, 933 FW_WM(wm->sr.plane >> 9, SR_HI) | 934 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | 935 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | 936 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | 937 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | 938 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | 939 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); 940 } 941 942 /* zero (unused) WM1 watermarks */ 943 I915_WRITE(DSPFW4, 0); 944 I915_WRITE(DSPFW5, 0); 945 I915_WRITE(DSPFW6, 0); 946 I915_WRITE(DSPHOWM1, 0); 947 948 POSTING_READ(DSPFW1); 949 } 950 951 #undef FW_WM_VLV 952 953 enum vlv_wm_level { 954 VLV_WM_LEVEL_PM2, 955 VLV_WM_LEVEL_PM5, 956 VLV_WM_LEVEL_DDR_DVFS, 957 }; 958 959 /* latency must be in 0.1us units. */ 960 static unsigned int vlv_wm_method2(unsigned int pixel_rate, 961 unsigned int pipe_htotal, 962 unsigned int horiz_pixels, 963 unsigned int bytes_per_pixel, 964 unsigned int latency) 965 { 966 unsigned int ret; 967 968 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 969 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 970 ret = DIV_ROUND_UP(ret, 64); 971 972 return ret; 973 } 974 975 static void vlv_setup_wm_latency(struct drm_device *dev) 976 { 977 struct drm_i915_private *dev_priv = dev->dev_private; 978 979 /* all latencies in usec */ 980 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; 981 982 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; 983 984 if (IS_CHERRYVIEW(dev_priv)) { 985 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; 986 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; 987 988 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; 989 } 990 } 991 992 static uint16_t vlv_compute_wm_level(struct intel_plane *plane, 993 struct intel_crtc *crtc, 994 const struct intel_plane_state *state, 995 int level) 996 { 997 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 998 int clock, htotal, pixel_size, width, wm; 999 1000 if (dev_priv->wm.pri_latency[level] == 0) 1001 return USHRT_MAX; 1002 1003 if (!state->visible) 1004 return 0; 1005 1006 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1007 clock = crtc->config->base.adjusted_mode.crtc_clock; 1008 htotal = crtc->config->base.adjusted_mode.crtc_htotal; 1009 width = crtc->config->pipe_src_w; 1010 if (WARN_ON(htotal == 0)) 1011 htotal = 1; 1012 1013 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1014 /* 1015 * FIXME the formula gives values that are 1016 * too big for the cursor FIFO, and hence we 1017 * would never be able to use cursors. For 1018 * now just hardcode the watermark. 1019 */ 1020 wm = 63; 1021 } else { 1022 wm = vlv_wm_method2(clock, htotal, width, pixel_size, 1023 dev_priv->wm.pri_latency[level] * 10); 1024 } 1025 1026 return min_t(int, wm, USHRT_MAX); 1027 } 1028 1029 static void vlv_compute_fifo(struct intel_crtc *crtc) 1030 { 1031 struct drm_device *dev = crtc->base.dev; 1032 struct vlv_wm_state *wm_state = &crtc->wm_state; 1033 struct intel_plane *plane; 1034 unsigned int total_rate = 0; 1035 const int fifo_size = 512 - 1; 1036 int fifo_extra, fifo_left = fifo_size; 1037 1038 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1039 struct intel_plane_state *state = 1040 to_intel_plane_state(plane->base.state); 1041 1042 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1043 continue; 1044 1045 if (state->visible) { 1046 wm_state->num_active_planes++; 1047 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1048 } 1049 } 1050 1051 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1052 struct intel_plane_state *state = 1053 to_intel_plane_state(plane->base.state); 1054 unsigned int rate; 1055 1056 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1057 plane->wm.fifo_size = 63; 1058 continue; 1059 } 1060 1061 if (!state->visible) { 1062 plane->wm.fifo_size = 0; 1063 continue; 1064 } 1065 1066 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0); 1067 plane->wm.fifo_size = fifo_size * rate / total_rate; 1068 fifo_left -= plane->wm.fifo_size; 1069 } 1070 1071 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1); 1072 1073 /* spread the remainder evenly */ 1074 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1075 int plane_extra; 1076 1077 if (fifo_left == 0) 1078 break; 1079 1080 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) 1081 continue; 1082 1083 /* give it all to the first plane if none are active */ 1084 if (plane->wm.fifo_size == 0 && 1085 wm_state->num_active_planes) 1086 continue; 1087 1088 plane_extra = min(fifo_extra, fifo_left); 1089 plane->wm.fifo_size += plane_extra; 1090 fifo_left -= plane_extra; 1091 } 1092 1093 WARN_ON(fifo_left != 0); 1094 } 1095 1096 static void vlv_invert_wms(struct intel_crtc *crtc) 1097 { 1098 struct vlv_wm_state *wm_state = &crtc->wm_state; 1099 int level; 1100 1101 for (level = 0; level < wm_state->num_levels; level++) { 1102 struct drm_device *dev = crtc->base.dev; 1103 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1104 struct intel_plane *plane; 1105 1106 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane; 1107 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor; 1108 1109 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1110 switch (plane->base.type) { 1111 int sprite; 1112 case DRM_PLANE_TYPE_CURSOR: 1113 wm_state->wm[level].cursor = plane->wm.fifo_size - 1114 wm_state->wm[level].cursor; 1115 break; 1116 case DRM_PLANE_TYPE_PRIMARY: 1117 wm_state->wm[level].primary = plane->wm.fifo_size - 1118 wm_state->wm[level].primary; 1119 break; 1120 case DRM_PLANE_TYPE_OVERLAY: 1121 sprite = plane->plane; 1122 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size - 1123 wm_state->wm[level].sprite[sprite]; 1124 break; 1125 } 1126 } 1127 } 1128 } 1129 1130 static void vlv_compute_wm(struct intel_crtc *crtc) 1131 { 1132 struct drm_device *dev = crtc->base.dev; 1133 struct vlv_wm_state *wm_state = &crtc->wm_state; 1134 struct intel_plane *plane; 1135 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1; 1136 int level; 1137 1138 memset(wm_state, 0, sizeof(*wm_state)); 1139 1140 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed; 1141 wm_state->num_levels = to_i915(dev)->wm.max_level + 1; 1142 1143 wm_state->num_active_planes = 0; 1144 1145 vlv_compute_fifo(crtc); 1146 1147 if (wm_state->num_active_planes != 1) 1148 wm_state->cxsr = false; 1149 1150 if (wm_state->cxsr) { 1151 for (level = 0; level < wm_state->num_levels; level++) { 1152 wm_state->sr[level].plane = sr_fifo_size; 1153 wm_state->sr[level].cursor = 63; 1154 } 1155 } 1156 1157 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1158 struct intel_plane_state *state = 1159 to_intel_plane_state(plane->base.state); 1160 1161 if (!state->visible) 1162 continue; 1163 1164 /* normal watermarks */ 1165 for (level = 0; level < wm_state->num_levels; level++) { 1166 int wm = vlv_compute_wm_level(plane, crtc, state, level); 1167 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511; 1168 1169 /* hack */ 1170 if (WARN_ON(level == 0 && wm > max_wm)) 1171 wm = max_wm; 1172 1173 if (wm > plane->wm.fifo_size) 1174 break; 1175 1176 switch (plane->base.type) { 1177 int sprite; 1178 case DRM_PLANE_TYPE_CURSOR: 1179 wm_state->wm[level].cursor = wm; 1180 break; 1181 case DRM_PLANE_TYPE_PRIMARY: 1182 wm_state->wm[level].primary = wm; 1183 break; 1184 case DRM_PLANE_TYPE_OVERLAY: 1185 sprite = plane->plane; 1186 wm_state->wm[level].sprite[sprite] = wm; 1187 break; 1188 } 1189 } 1190 1191 wm_state->num_levels = level; 1192 1193 if (!wm_state->cxsr) 1194 continue; 1195 1196 /* maxfifo watermarks */ 1197 switch (plane->base.type) { 1198 int sprite, level; 1199 case DRM_PLANE_TYPE_CURSOR: 1200 for (level = 0; level < wm_state->num_levels; level++) 1201 wm_state->sr[level].cursor = 1202 wm_state->sr[level].cursor; 1203 break; 1204 case DRM_PLANE_TYPE_PRIMARY: 1205 for (level = 0; level < wm_state->num_levels; level++) 1206 wm_state->sr[level].plane = 1207 min(wm_state->sr[level].plane, 1208 wm_state->wm[level].primary); 1209 break; 1210 case DRM_PLANE_TYPE_OVERLAY: 1211 sprite = plane->plane; 1212 for (level = 0; level < wm_state->num_levels; level++) 1213 wm_state->sr[level].plane = 1214 min(wm_state->sr[level].plane, 1215 wm_state->wm[level].sprite[sprite]); 1216 break; 1217 } 1218 } 1219 1220 /* clear any (partially) filled invalid levels */ 1221 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) { 1222 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level])); 1223 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level])); 1224 } 1225 1226 vlv_invert_wms(crtc); 1227 } 1228 1229 #define VLV_FIFO(plane, value) \ 1230 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) 1231 1232 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) 1233 { 1234 struct drm_device *dev = crtc->base.dev; 1235 struct drm_i915_private *dev_priv = to_i915(dev); 1236 struct intel_plane *plane; 1237 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0; 1238 1239 for_each_intel_plane_on_crtc(dev, crtc, plane) { 1240 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) { 1241 WARN_ON(plane->wm.fifo_size != 63); 1242 continue; 1243 } 1244 1245 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) 1246 sprite0_start = plane->wm.fifo_size; 1247 else if (plane->plane == 0) 1248 sprite1_start = sprite0_start + plane->wm.fifo_size; 1249 else 1250 fifo_size = sprite1_start + plane->wm.fifo_size; 1251 } 1252 1253 WARN_ON(fifo_size != 512 - 1); 1254 1255 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n", 1256 pipe_name(crtc->pipe), sprite0_start, 1257 sprite1_start, fifo_size); 1258 1259 switch (crtc->pipe) { 1260 uint32_t dsparb, dsparb2, dsparb3; 1261 case PIPE_A: 1262 dsparb = I915_READ(DSPARB); 1263 dsparb2 = I915_READ(DSPARB2); 1264 1265 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | 1266 VLV_FIFO(SPRITEB, 0xff)); 1267 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | 1268 VLV_FIFO(SPRITEB, sprite1_start)); 1269 1270 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | 1271 VLV_FIFO(SPRITEB_HI, 0x1)); 1272 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | 1273 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); 1274 1275 I915_WRITE(DSPARB, dsparb); 1276 I915_WRITE(DSPARB2, dsparb2); 1277 break; 1278 case PIPE_B: 1279 dsparb = I915_READ(DSPARB); 1280 dsparb2 = I915_READ(DSPARB2); 1281 1282 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | 1283 VLV_FIFO(SPRITED, 0xff)); 1284 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | 1285 VLV_FIFO(SPRITED, sprite1_start)); 1286 1287 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | 1288 VLV_FIFO(SPRITED_HI, 0xff)); 1289 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | 1290 VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); 1291 1292 I915_WRITE(DSPARB, dsparb); 1293 I915_WRITE(DSPARB2, dsparb2); 1294 break; 1295 case PIPE_C: 1296 dsparb3 = I915_READ(DSPARB3); 1297 dsparb2 = I915_READ(DSPARB2); 1298 1299 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | 1300 VLV_FIFO(SPRITEF, 0xff)); 1301 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | 1302 VLV_FIFO(SPRITEF, sprite1_start)); 1303 1304 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | 1305 VLV_FIFO(SPRITEF_HI, 0xff)); 1306 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | 1307 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); 1308 1309 I915_WRITE(DSPARB3, dsparb3); 1310 I915_WRITE(DSPARB2, dsparb2); 1311 break; 1312 default: 1313 break; 1314 } 1315 } 1316 1317 #undef VLV_FIFO 1318 1319 static void vlv_merge_wm(struct drm_device *dev, 1320 struct vlv_wm_values *wm) 1321 { 1322 struct intel_crtc *crtc; 1323 int num_active_crtcs = 0; 1324 1325 wm->level = to_i915(dev)->wm.max_level; 1326 wm->cxsr = true; 1327 1328 for_each_intel_crtc(dev, crtc) { 1329 const struct vlv_wm_state *wm_state = &crtc->wm_state; 1330 1331 if (!crtc->active) 1332 continue; 1333 1334 if (!wm_state->cxsr) 1335 wm->cxsr = false; 1336 1337 num_active_crtcs++; 1338 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); 1339 } 1340 1341 if (num_active_crtcs != 1) 1342 wm->cxsr = false; 1343 1344 if (num_active_crtcs > 1) 1345 wm->level = VLV_WM_LEVEL_PM2; 1346 1347 for_each_intel_crtc(dev, crtc) { 1348 struct vlv_wm_state *wm_state = &crtc->wm_state; 1349 enum i915_pipe pipe = crtc->pipe; 1350 1351 if (!crtc->active) 1352 continue; 1353 1354 wm->pipe[pipe] = wm_state->wm[wm->level]; 1355 if (wm->cxsr) 1356 wm->sr = wm_state->sr[wm->level]; 1357 1358 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2; 1359 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2; 1360 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2; 1361 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2; 1362 } 1363 } 1364 1365 static void vlv_update_wm(struct drm_crtc *crtc) 1366 { 1367 struct drm_device *dev = crtc->dev; 1368 struct drm_i915_private *dev_priv = dev->dev_private; 1369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1370 enum i915_pipe pipe = intel_crtc->pipe; 1371 struct vlv_wm_values wm = {}; 1372 1373 vlv_compute_wm(intel_crtc); 1374 vlv_merge_wm(dev, &wm); 1375 1376 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) { 1377 /* FIXME should be part of crtc atomic commit */ 1378 vlv_pipe_set_fifo_size(intel_crtc); 1379 return; 1380 } 1381 1382 if (wm.level < VLV_WM_LEVEL_DDR_DVFS && 1383 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS) 1384 chv_set_memory_dvfs(dev_priv, false); 1385 1386 if (wm.level < VLV_WM_LEVEL_PM5 && 1387 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5) 1388 chv_set_memory_pm5(dev_priv, false); 1389 1390 if (!wm.cxsr && dev_priv->wm.vlv.cxsr) 1391 intel_set_memory_cxsr(dev_priv, false); 1392 1393 /* FIXME should be part of crtc atomic commit */ 1394 vlv_pipe_set_fifo_size(intel_crtc); 1395 1396 vlv_write_wm_values(intel_crtc, &wm); 1397 1398 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " 1399 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n", 1400 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor, 1401 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1], 1402 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr); 1403 1404 if (wm.cxsr && !dev_priv->wm.vlv.cxsr) 1405 intel_set_memory_cxsr(dev_priv, true); 1406 1407 if (wm.level >= VLV_WM_LEVEL_PM5 && 1408 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5) 1409 chv_set_memory_pm5(dev_priv, true); 1410 1411 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS && 1412 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS) 1413 chv_set_memory_dvfs(dev_priv, true); 1414 1415 dev_priv->wm.vlv = wm; 1416 } 1417 1418 #define single_plane_enabled(mask) is_power_of_2(mask) 1419 1420 static void g4x_update_wm(struct drm_crtc *crtc) 1421 { 1422 struct drm_device *dev = crtc->dev; 1423 static const int sr_latency_ns = 12000; 1424 struct drm_i915_private *dev_priv = dev->dev_private; 1425 int planea_wm, planeb_wm, cursora_wm, cursorb_wm; 1426 int plane_sr, cursor_sr; 1427 unsigned int enabled = 0; 1428 bool cxsr_enabled; 1429 1430 if (g4x_compute_wm0(dev, PIPE_A, 1431 &g4x_wm_info, pessimal_latency_ns, 1432 &g4x_cursor_wm_info, pessimal_latency_ns, 1433 &planea_wm, &cursora_wm)) 1434 enabled |= 1 << PIPE_A; 1435 1436 if (g4x_compute_wm0(dev, PIPE_B, 1437 &g4x_wm_info, pessimal_latency_ns, 1438 &g4x_cursor_wm_info, pessimal_latency_ns, 1439 &planeb_wm, &cursorb_wm)) 1440 enabled |= 1 << PIPE_B; 1441 1442 if (single_plane_enabled(enabled) && 1443 g4x_compute_srwm(dev, ffs(enabled) - 1, 1444 sr_latency_ns, 1445 &g4x_wm_info, 1446 &g4x_cursor_wm_info, 1447 &plane_sr, &cursor_sr)) { 1448 cxsr_enabled = true; 1449 } else { 1450 cxsr_enabled = false; 1451 intel_set_memory_cxsr(dev_priv, false); 1452 plane_sr = cursor_sr = 0; 1453 } 1454 1455 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " 1456 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", 1457 planea_wm, cursora_wm, 1458 planeb_wm, cursorb_wm, 1459 plane_sr, cursor_sr); 1460 1461 I915_WRITE(DSPFW1, 1462 FW_WM(plane_sr, SR) | 1463 FW_WM(cursorb_wm, CURSORB) | 1464 FW_WM(planeb_wm, PLANEB) | 1465 FW_WM(planea_wm, PLANEA)); 1466 I915_WRITE(DSPFW2, 1467 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | 1468 FW_WM(cursora_wm, CURSORA)); 1469 /* HPLL off in SR has some issues on G4x... disable it */ 1470 I915_WRITE(DSPFW3, 1471 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | 1472 FW_WM(cursor_sr, CURSOR_SR)); 1473 1474 if (cxsr_enabled) 1475 intel_set_memory_cxsr(dev_priv, true); 1476 } 1477 1478 static void i965_update_wm(struct drm_crtc *unused_crtc) 1479 { 1480 struct drm_device *dev = unused_crtc->dev; 1481 struct drm_i915_private *dev_priv = dev->dev_private; 1482 struct drm_crtc *crtc; 1483 int srwm = 1; 1484 int cursor_sr = 16; 1485 bool cxsr_enabled; 1486 1487 /* Calc sr entries for one plane configs */ 1488 crtc = single_enabled_crtc(dev); 1489 if (crtc) { 1490 /* self-refresh has much higher latency */ 1491 static const int sr_latency_ns = 12000; 1492 const struct drm_display_mode *adjusted_mode = 1493 &to_intel_crtc(crtc)->config->base.adjusted_mode; 1494 int clock = adjusted_mode->crtc_clock; 1495 int htotal = adjusted_mode->crtc_htotal; 1496 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; 1497 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; 1498 unsigned long line_time_us; 1499 int entries; 1500 1501 line_time_us = max(htotal * 1000 / clock, 1); 1502 1503 /* Use ns/us then divide to preserve precision */ 1504 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1505 pixel_size * hdisplay; 1506 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); 1507 srwm = I965_FIFO_SIZE - entries; 1508 if (srwm < 0) 1509 srwm = 1; 1510 srwm &= 0x1ff; 1511 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", 1512 entries, srwm); 1513 1514 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1515 pixel_size * crtc->cursor->state->crtc_w; 1516 entries = DIV_ROUND_UP(entries, 1517 i965_cursor_wm_info.cacheline_size); 1518 cursor_sr = i965_cursor_wm_info.fifo_size - 1519 (entries + i965_cursor_wm_info.guard_size); 1520 1521 if (cursor_sr > i965_cursor_wm_info.max_wm) 1522 cursor_sr = i965_cursor_wm_info.max_wm; 1523 1524 DRM_DEBUG_KMS("self-refresh watermark: display plane %d " 1525 "cursor %d\n", srwm, cursor_sr); 1526 1527 cxsr_enabled = true; 1528 } else { 1529 cxsr_enabled = false; 1530 /* Turn off self refresh if both pipes are enabled */ 1531 intel_set_memory_cxsr(dev_priv, false); 1532 } 1533 1534 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", 1535 srwm); 1536 1537 /* 965 has limitations... */ 1538 I915_WRITE(DSPFW1, FW_WM(srwm, SR) | 1539 FW_WM(8, CURSORB) | 1540 FW_WM(8, PLANEB) | 1541 FW_WM(8, PLANEA)); 1542 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | 1543 FW_WM(8, PLANEC_OLD)); 1544 /* update cursor SR watermark */ 1545 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); 1546 1547 if (cxsr_enabled) 1548 intel_set_memory_cxsr(dev_priv, true); 1549 } 1550 1551 #undef FW_WM 1552 1553 static void i9xx_update_wm(struct drm_crtc *unused_crtc) 1554 { 1555 struct drm_device *dev = unused_crtc->dev; 1556 struct drm_i915_private *dev_priv = dev->dev_private; 1557 const struct intel_watermark_params *wm_info; 1558 uint32_t fwater_lo; 1559 uint32_t fwater_hi; 1560 int cwm, srwm = 1; 1561 int fifo_size; 1562 int planea_wm, planeb_wm; 1563 struct drm_crtc *crtc, *enabled = NULL; 1564 1565 if (IS_I945GM(dev)) 1566 wm_info = &i945_wm_info; 1567 else if (!IS_GEN2(dev)) 1568 wm_info = &i915_wm_info; 1569 else 1570 wm_info = &i830_a_wm_info; 1571 1572 fifo_size = dev_priv->display.get_fifo_size(dev, 0); 1573 crtc = intel_get_crtc_for_plane(dev, 0); 1574 if (intel_crtc_active(crtc)) { 1575 const struct drm_display_mode *adjusted_mode; 1576 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1577 if (IS_GEN2(dev)) 1578 cpp = 4; 1579 1580 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1581 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1582 wm_info, fifo_size, cpp, 1583 pessimal_latency_ns); 1584 enabled = crtc; 1585 } else { 1586 planea_wm = fifo_size - wm_info->guard_size; 1587 if (planea_wm > (long)wm_info->max_wm) 1588 planea_wm = wm_info->max_wm; 1589 } 1590 1591 if (IS_GEN2(dev)) 1592 wm_info = &i830_bc_wm_info; 1593 1594 fifo_size = dev_priv->display.get_fifo_size(dev, 1); 1595 crtc = intel_get_crtc_for_plane(dev, 1); 1596 if (intel_crtc_active(crtc)) { 1597 const struct drm_display_mode *adjusted_mode; 1598 int cpp = crtc->primary->state->fb->bits_per_pixel / 8; 1599 if (IS_GEN2(dev)) 1600 cpp = 4; 1601 1602 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1603 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1604 wm_info, fifo_size, cpp, 1605 pessimal_latency_ns); 1606 if (enabled == NULL) 1607 enabled = crtc; 1608 else 1609 enabled = NULL; 1610 } else { 1611 planeb_wm = fifo_size - wm_info->guard_size; 1612 if (planeb_wm > (long)wm_info->max_wm) 1613 planeb_wm = wm_info->max_wm; 1614 } 1615 1616 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); 1617 1618 if (IS_I915GM(dev) && enabled) { 1619 struct drm_i915_gem_object *obj; 1620 1621 obj = intel_fb_obj(enabled->primary->state->fb); 1622 1623 /* self-refresh seems busted with untiled */ 1624 if (obj->tiling_mode == I915_TILING_NONE) 1625 enabled = NULL; 1626 } 1627 1628 /* 1629 * Overlay gets an aggressive default since video jitter is bad. 1630 */ 1631 cwm = 2; 1632 1633 /* Play safe and disable self-refresh before adjusting watermarks. */ 1634 intel_set_memory_cxsr(dev_priv, false); 1635 1636 /* Calc sr entries for one plane configs */ 1637 if (HAS_FW_BLC(dev) && enabled) { 1638 /* self-refresh has much higher latency */ 1639 static const int sr_latency_ns = 6000; 1640 const struct drm_display_mode *adjusted_mode = 1641 &to_intel_crtc(enabled)->config->base.adjusted_mode; 1642 int clock = adjusted_mode->crtc_clock; 1643 int htotal = adjusted_mode->crtc_htotal; 1644 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; 1645 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; 1646 unsigned long line_time_us; 1647 int entries; 1648 1649 line_time_us = max(htotal * 1000 / clock, 1); 1650 1651 /* Use ns/us then divide to preserve precision */ 1652 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1653 pixel_size * hdisplay; 1654 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); 1655 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); 1656 srwm = wm_info->fifo_size - entries; 1657 if (srwm < 0) 1658 srwm = 1; 1659 1660 if (IS_I945G(dev) || IS_I945GM(dev)) 1661 I915_WRITE(FW_BLC_SELF, 1662 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); 1663 else if (IS_I915GM(dev)) 1664 I915_WRITE(FW_BLC_SELF, srwm & 0x3f); 1665 } 1666 1667 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", 1668 planea_wm, planeb_wm, cwm, srwm); 1669 1670 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); 1671 fwater_hi = (cwm & 0x1f); 1672 1673 /* Set request length to 8 cachelines per fetch */ 1674 fwater_lo = fwater_lo | (1 << 24) | (1 << 8); 1675 fwater_hi = fwater_hi | (1 << 8); 1676 1677 I915_WRITE(FW_BLC, fwater_lo); 1678 I915_WRITE(FW_BLC2, fwater_hi); 1679 1680 if (enabled) 1681 intel_set_memory_cxsr(dev_priv, true); 1682 } 1683 1684 static void i845_update_wm(struct drm_crtc *unused_crtc) 1685 { 1686 struct drm_device *dev = unused_crtc->dev; 1687 struct drm_i915_private *dev_priv = dev->dev_private; 1688 struct drm_crtc *crtc; 1689 const struct drm_display_mode *adjusted_mode; 1690 uint32_t fwater_lo; 1691 int planea_wm; 1692 1693 crtc = single_enabled_crtc(dev); 1694 if (crtc == NULL) 1695 return; 1696 1697 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; 1698 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, 1699 &i845_wm_info, 1700 dev_priv->display.get_fifo_size(dev, 0), 1701 4, pessimal_latency_ns); 1702 fwater_lo = I915_READ(FW_BLC) & ~0xfff; 1703 fwater_lo |= (3<<8) | planea_wm; 1704 1705 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); 1706 1707 I915_WRITE(FW_BLC, fwater_lo); 1708 } 1709 1710 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) 1711 { 1712 uint32_t pixel_rate; 1713 1714 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; 1715 1716 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to 1717 * adjust the pixel_rate here. */ 1718 1719 if (pipe_config->pch_pfit.enabled) { 1720 uint64_t pipe_w, pipe_h, pfit_w, pfit_h; 1721 uint32_t pfit_size = pipe_config->pch_pfit.size; 1722 1723 pipe_w = pipe_config->pipe_src_w; 1724 pipe_h = pipe_config->pipe_src_h; 1725 1726 pfit_w = (pfit_size >> 16) & 0xFFFF; 1727 pfit_h = pfit_size & 0xFFFF; 1728 if (pipe_w < pfit_w) 1729 pipe_w = pfit_w; 1730 if (pipe_h < pfit_h) 1731 pipe_h = pfit_h; 1732 1733 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, 1734 pfit_w * pfit_h); 1735 } 1736 1737 return pixel_rate; 1738 } 1739 1740 /* latency must be in 0.1us units. */ 1741 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 1742 uint32_t latency) 1743 { 1744 uint64_t ret; 1745 1746 if (WARN(latency == 0, "Latency value missing\n")) 1747 return UINT_MAX; 1748 1749 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; 1750 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; 1751 1752 return ret; 1753 } 1754 1755 /* latency must be in 0.1us units. */ 1756 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 1757 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 1758 uint32_t latency) 1759 { 1760 uint32_t ret; 1761 1762 if (WARN(latency == 0, "Latency value missing\n")) 1763 return UINT_MAX; 1764 1765 ret = (latency * pixel_rate) / (pipe_htotal * 10000); 1766 ret = (ret + 1) * horiz_pixels * bytes_per_pixel; 1767 ret = DIV_ROUND_UP(ret, 64) + 2; 1768 return ret; 1769 } 1770 1771 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, 1772 uint8_t bytes_per_pixel) 1773 { 1774 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; 1775 } 1776 1777 struct skl_pipe_wm_parameters { 1778 bool active; 1779 uint32_t pipe_htotal; 1780 uint32_t pixel_rate; /* in KHz */ 1781 struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; 1782 struct intel_plane_wm_parameters cursor; 1783 }; 1784 1785 struct ilk_pipe_wm_parameters { 1786 bool active; 1787 uint32_t pipe_htotal; 1788 uint32_t pixel_rate; 1789 struct intel_plane_wm_parameters pri; 1790 struct intel_plane_wm_parameters spr; 1791 struct intel_plane_wm_parameters cur; 1792 }; 1793 1794 struct ilk_wm_maximums { 1795 uint16_t pri; 1796 uint16_t spr; 1797 uint16_t cur; 1798 uint16_t fbc; 1799 }; 1800 1801 /* used in computing the new watermarks state */ 1802 struct intel_wm_config { 1803 unsigned int num_pipes_active; 1804 bool sprites_enabled; 1805 bool sprites_scaled; 1806 }; 1807 1808 /* 1809 * For both WM_PIPE and WM_LP. 1810 * mem_value must be in 0.1us units. 1811 */ 1812 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, 1813 uint32_t mem_value, 1814 bool is_lp) 1815 { 1816 uint32_t method1, method2; 1817 1818 if (!params->active || !params->pri.enabled) 1819 return 0; 1820 1821 method1 = ilk_wm_method1(params->pixel_rate, 1822 params->pri.bytes_per_pixel, 1823 mem_value); 1824 1825 if (!is_lp) 1826 return method1; 1827 1828 method2 = ilk_wm_method2(params->pixel_rate, 1829 params->pipe_htotal, 1830 params->pri.horiz_pixels, 1831 params->pri.bytes_per_pixel, 1832 mem_value); 1833 1834 return min(method1, method2); 1835 } 1836 1837 /* 1838 * For both WM_PIPE and WM_LP. 1839 * mem_value must be in 0.1us units. 1840 */ 1841 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, 1842 uint32_t mem_value) 1843 { 1844 uint32_t method1, method2; 1845 1846 if (!params->active || !params->spr.enabled) 1847 return 0; 1848 1849 method1 = ilk_wm_method1(params->pixel_rate, 1850 params->spr.bytes_per_pixel, 1851 mem_value); 1852 method2 = ilk_wm_method2(params->pixel_rate, 1853 params->pipe_htotal, 1854 params->spr.horiz_pixels, 1855 params->spr.bytes_per_pixel, 1856 mem_value); 1857 return min(method1, method2); 1858 } 1859 1860 /* 1861 * For both WM_PIPE and WM_LP. 1862 * mem_value must be in 0.1us units. 1863 */ 1864 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, 1865 uint32_t mem_value) 1866 { 1867 if (!params->active || !params->cur.enabled) 1868 return 0; 1869 1870 return ilk_wm_method2(params->pixel_rate, 1871 params->pipe_htotal, 1872 params->cur.horiz_pixels, 1873 params->cur.bytes_per_pixel, 1874 mem_value); 1875 } 1876 1877 /* Only for WM_LP. */ 1878 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, 1879 uint32_t pri_val) 1880 { 1881 if (!params->active || !params->pri.enabled) 1882 return 0; 1883 1884 return ilk_wm_fbc(pri_val, 1885 params->pri.horiz_pixels, 1886 params->pri.bytes_per_pixel); 1887 } 1888 1889 static unsigned int ilk_display_fifo_size(const struct drm_device *dev) 1890 { 1891 if (INTEL_INFO(dev)->gen >= 8) 1892 return 3072; 1893 else if (INTEL_INFO(dev)->gen >= 7) 1894 return 768; 1895 else 1896 return 512; 1897 } 1898 1899 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, 1900 int level, bool is_sprite) 1901 { 1902 if (INTEL_INFO(dev)->gen >= 8) 1903 /* BDW primary/sprite plane watermarks */ 1904 return level == 0 ? 255 : 2047; 1905 else if (INTEL_INFO(dev)->gen >= 7) 1906 /* IVB/HSW primary/sprite plane watermarks */ 1907 return level == 0 ? 127 : 1023; 1908 else if (!is_sprite) 1909 /* ILK/SNB primary plane watermarks */ 1910 return level == 0 ? 127 : 511; 1911 else 1912 /* ILK/SNB sprite plane watermarks */ 1913 return level == 0 ? 63 : 255; 1914 } 1915 1916 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, 1917 int level) 1918 { 1919 if (INTEL_INFO(dev)->gen >= 7) 1920 return level == 0 ? 63 : 255; 1921 else 1922 return level == 0 ? 31 : 63; 1923 } 1924 1925 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) 1926 { 1927 if (INTEL_INFO(dev)->gen >= 8) 1928 return 31; 1929 else 1930 return 15; 1931 } 1932 1933 /* Calculate the maximum primary/sprite plane watermark */ 1934 static unsigned int ilk_plane_wm_max(const struct drm_device *dev, 1935 int level, 1936 const struct intel_wm_config *config, 1937 enum intel_ddb_partitioning ddb_partitioning, 1938 bool is_sprite) 1939 { 1940 unsigned int fifo_size = ilk_display_fifo_size(dev); 1941 1942 /* if sprites aren't enabled, sprites get nothing */ 1943 if (is_sprite && !config->sprites_enabled) 1944 return 0; 1945 1946 /* HSW allows LP1+ watermarks even with multiple pipes */ 1947 if (level == 0 || config->num_pipes_active > 1) { 1948 fifo_size /= INTEL_INFO(dev)->num_pipes; 1949 1950 /* 1951 * For some reason the non self refresh 1952 * FIFO size is only half of the self 1953 * refresh FIFO size on ILK/SNB. 1954 */ 1955 if (INTEL_INFO(dev)->gen <= 6) 1956 fifo_size /= 2; 1957 } 1958 1959 if (config->sprites_enabled) { 1960 /* level 0 is always calculated with 1:1 split */ 1961 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { 1962 if (is_sprite) 1963 fifo_size *= 5; 1964 fifo_size /= 6; 1965 } else { 1966 fifo_size /= 2; 1967 } 1968 } 1969 1970 /* clamp to max that the registers can hold */ 1971 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); 1972 } 1973 1974 /* Calculate the maximum cursor plane watermark */ 1975 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, 1976 int level, 1977 const struct intel_wm_config *config) 1978 { 1979 /* HSW LP1+ watermarks w/ multiple pipes */ 1980 if (level > 0 && config->num_pipes_active > 1) 1981 return 64; 1982 1983 /* otherwise just report max that registers can hold */ 1984 return ilk_cursor_wm_reg_max(dev, level); 1985 } 1986 1987 static void ilk_compute_wm_maximums(const struct drm_device *dev, 1988 int level, 1989 const struct intel_wm_config *config, 1990 enum intel_ddb_partitioning ddb_partitioning, 1991 struct ilk_wm_maximums *max) 1992 { 1993 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); 1994 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); 1995 max->cur = ilk_cursor_wm_max(dev, level, config); 1996 max->fbc = ilk_fbc_wm_reg_max(dev); 1997 } 1998 1999 static void ilk_compute_wm_reg_maximums(struct drm_device *dev, 2000 int level, 2001 struct ilk_wm_maximums *max) 2002 { 2003 max->pri = ilk_plane_wm_reg_max(dev, level, false); 2004 max->spr = ilk_plane_wm_reg_max(dev, level, true); 2005 max->cur = ilk_cursor_wm_reg_max(dev, level); 2006 max->fbc = ilk_fbc_wm_reg_max(dev); 2007 } 2008 2009 static bool ilk_validate_wm_level(int level, 2010 const struct ilk_wm_maximums *max, 2011 struct intel_wm_level *result) 2012 { 2013 bool ret; 2014 2015 /* already determined to be invalid? */ 2016 if (!result->enable) 2017 return false; 2018 2019 result->enable = result->pri_val <= max->pri && 2020 result->spr_val <= max->spr && 2021 result->cur_val <= max->cur; 2022 2023 ret = result->enable; 2024 2025 /* 2026 * HACK until we can pre-compute everything, 2027 * and thus fail gracefully if LP0 watermarks 2028 * are exceeded... 2029 */ 2030 if (level == 0 && !result->enable) { 2031 if (result->pri_val > max->pri) 2032 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", 2033 level, result->pri_val, max->pri); 2034 if (result->spr_val > max->spr) 2035 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", 2036 level, result->spr_val, max->spr); 2037 if (result->cur_val > max->cur) 2038 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", 2039 level, result->cur_val, max->cur); 2040 2041 result->pri_val = min_t(uint32_t, result->pri_val, max->pri); 2042 result->spr_val = min_t(uint32_t, result->spr_val, max->spr); 2043 result->cur_val = min_t(uint32_t, result->cur_val, max->cur); 2044 result->enable = true; 2045 } 2046 2047 return ret; 2048 } 2049 2050 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, 2051 int level, 2052 const struct ilk_pipe_wm_parameters *p, 2053 struct intel_wm_level *result) 2054 { 2055 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; 2056 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; 2057 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; 2058 2059 /* WM1+ latency values stored in 0.5us units */ 2060 if (level > 0) { 2061 pri_latency *= 5; 2062 spr_latency *= 5; 2063 cur_latency *= 5; 2064 } 2065 2066 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); 2067 result->spr_val = ilk_compute_spr_wm(p, spr_latency); 2068 result->cur_val = ilk_compute_cur_wm(p, cur_latency); 2069 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); 2070 result->enable = true; 2071 } 2072 2073 static uint32_t 2074 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) 2075 { 2076 struct drm_i915_private *dev_priv = dev->dev_private; 2077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2078 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; 2079 u32 linetime, ips_linetime; 2080 2081 if (!intel_crtc->active) 2082 return 0; 2083 2084 /* The WM are computed with base on how long it takes to fill a single 2085 * row at the given clock rate, multiplied by 8. 2086 * */ 2087 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, 2088 mode->crtc_clock); 2089 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, 2090 dev_priv->cdclk_freq); 2091 2092 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | 2093 PIPE_WM_LINETIME_TIME(linetime); 2094 } 2095 2096 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) 2097 { 2098 struct drm_i915_private *dev_priv = dev->dev_private; 2099 2100 if (IS_GEN9(dev)) { 2101 uint32_t val; 2102 int ret, i; 2103 int level, max_level = ilk_wm_max_level(dev); 2104 2105 /* read the first set of memory latencies[0:3] */ 2106 val = 0; /* data0 to be programmed to 0 for first set */ 2107 mutex_lock(&dev_priv->rps.hw_lock); 2108 ret = sandybridge_pcode_read(dev_priv, 2109 GEN9_PCODE_READ_MEM_LATENCY, 2110 &val); 2111 mutex_unlock(&dev_priv->rps.hw_lock); 2112 2113 if (ret) { 2114 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2115 return; 2116 } 2117 2118 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2119 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2120 GEN9_MEM_LATENCY_LEVEL_MASK; 2121 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2122 GEN9_MEM_LATENCY_LEVEL_MASK; 2123 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2124 GEN9_MEM_LATENCY_LEVEL_MASK; 2125 2126 /* read the second set of memory latencies[4:7] */ 2127 val = 1; /* data0 to be programmed to 1 for second set */ 2128 mutex_lock(&dev_priv->rps.hw_lock); 2129 ret = sandybridge_pcode_read(dev_priv, 2130 GEN9_PCODE_READ_MEM_LATENCY, 2131 &val); 2132 mutex_unlock(&dev_priv->rps.hw_lock); 2133 if (ret) { 2134 DRM_ERROR("SKL Mailbox read error = %d\n", ret); 2135 return; 2136 } 2137 2138 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; 2139 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & 2140 GEN9_MEM_LATENCY_LEVEL_MASK; 2141 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & 2142 GEN9_MEM_LATENCY_LEVEL_MASK; 2143 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & 2144 GEN9_MEM_LATENCY_LEVEL_MASK; 2145 2146 /* 2147 * WaWmMemoryReadLatency:skl 2148 * 2149 * punit doesn't take into account the read latency so we need 2150 * to add 2us to the various latency levels we retrieve from 2151 * the punit. 2152 * - W0 is a bit special in that it's the only level that 2153 * can't be disabled if we want to have display working, so 2154 * we always add 2us there. 2155 * - For levels >=1, punit returns 0us latency when they are 2156 * disabled, so we respect that and don't add 2us then 2157 * 2158 * Additionally, if a level n (n > 1) has a 0us latency, all 2159 * levels m (m >= n) need to be disabled. We make sure to 2160 * sanitize the values out of the punit to satisfy this 2161 * requirement. 2162 */ 2163 wm[0] += 2; 2164 for (level = 1; level <= max_level; level++) 2165 if (wm[level] != 0) 2166 wm[level] += 2; 2167 else { 2168 for (i = level + 1; i <= max_level; i++) 2169 wm[i] = 0; 2170 2171 break; 2172 } 2173 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2174 uint64_t sskpd = I915_READ64(MCH_SSKPD); 2175 2176 wm[0] = (sskpd >> 56) & 0xFF; 2177 if (wm[0] == 0) 2178 wm[0] = sskpd & 0xF; 2179 wm[1] = (sskpd >> 4) & 0xFF; 2180 wm[2] = (sskpd >> 12) & 0xFF; 2181 wm[3] = (sskpd >> 20) & 0x1FF; 2182 wm[4] = (sskpd >> 32) & 0x1FF; 2183 } else if (INTEL_INFO(dev)->gen >= 6) { 2184 uint32_t sskpd = I915_READ(MCH_SSKPD); 2185 2186 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; 2187 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; 2188 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; 2189 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; 2190 } else if (INTEL_INFO(dev)->gen >= 5) { 2191 uint32_t mltr = I915_READ(MLTR_ILK); 2192 2193 /* ILK primary LP0 latency is 700 ns */ 2194 wm[0] = 7; 2195 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; 2196 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; 2197 } 2198 } 2199 2200 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2201 { 2202 /* ILK sprite LP0 latency is 1300 ns */ 2203 if (INTEL_INFO(dev)->gen == 5) 2204 wm[0] = 13; 2205 } 2206 2207 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) 2208 { 2209 /* ILK cursor LP0 latency is 1300 ns */ 2210 if (INTEL_INFO(dev)->gen == 5) 2211 wm[0] = 13; 2212 2213 /* WaDoubleCursorLP3Latency:ivb */ 2214 if (IS_IVYBRIDGE(dev)) 2215 wm[3] *= 2; 2216 } 2217 2218 int ilk_wm_max_level(const struct drm_device *dev) 2219 { 2220 /* how many WM levels are we expecting */ 2221 if (INTEL_INFO(dev)->gen >= 9) 2222 return 7; 2223 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2224 return 4; 2225 else if (INTEL_INFO(dev)->gen >= 6) 2226 return 3; 2227 else 2228 return 2; 2229 } 2230 2231 static void intel_print_wm_latency(struct drm_device *dev, 2232 const char *name, 2233 const uint16_t wm[8]) 2234 { 2235 int level, max_level = ilk_wm_max_level(dev); 2236 2237 for (level = 0; level <= max_level; level++) { 2238 unsigned int latency = wm[level]; 2239 2240 if (latency == 0) { 2241 DRM_ERROR("%s WM%d latency not provided\n", 2242 name, level); 2243 continue; 2244 } 2245 2246 /* 2247 * - latencies are in us on gen9. 2248 * - before then, WM1+ latency values are in 0.5us units 2249 */ 2250 if (IS_GEN9(dev)) 2251 latency *= 10; 2252 else if (level > 0) 2253 latency *= 5; 2254 2255 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", 2256 name, level, wm[level], 2257 latency / 10, latency % 10); 2258 } 2259 } 2260 2261 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, 2262 uint16_t wm[5], uint16_t min) 2263 { 2264 int level, max_level = ilk_wm_max_level(dev_priv->dev); 2265 2266 if (wm[0] >= min) 2267 return false; 2268 2269 wm[0] = max(wm[0], min); 2270 for (level = 1; level <= max_level; level++) 2271 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); 2272 2273 return true; 2274 } 2275 2276 static void snb_wm_latency_quirk(struct drm_device *dev) 2277 { 2278 struct drm_i915_private *dev_priv = dev->dev_private; 2279 bool changed; 2280 2281 /* 2282 * The BIOS provided WM memory latency values are often 2283 * inadequate for high resolution displays. Adjust them. 2284 */ 2285 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | 2286 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | 2287 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); 2288 2289 if (!changed) 2290 return; 2291 2292 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); 2293 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2294 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2295 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2296 } 2297 2298 static void ilk_setup_wm_latency(struct drm_device *dev) 2299 { 2300 struct drm_i915_private *dev_priv = dev->dev_private; 2301 2302 intel_read_wm_latency(dev, dev_priv->wm.pri_latency); 2303 2304 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, 2305 sizeof(dev_priv->wm.pri_latency)); 2306 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, 2307 sizeof(dev_priv->wm.pri_latency)); 2308 2309 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); 2310 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); 2311 2312 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); 2313 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); 2314 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); 2315 2316 if (IS_GEN6(dev)) 2317 snb_wm_latency_quirk(dev); 2318 } 2319 2320 static void skl_setup_wm_latency(struct drm_device *dev) 2321 { 2322 struct drm_i915_private *dev_priv = dev->dev_private; 2323 2324 intel_read_wm_latency(dev, dev_priv->wm.skl_latency); 2325 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); 2326 } 2327 2328 static void ilk_compute_wm_parameters(struct drm_crtc *crtc, 2329 struct ilk_pipe_wm_parameters *p) 2330 { 2331 struct drm_device *dev = crtc->dev; 2332 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2333 enum i915_pipe pipe = intel_crtc->pipe; 2334 struct drm_plane *plane; 2335 2336 if (!intel_crtc->active) 2337 return; 2338 2339 p->active = true; 2340 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; 2341 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config); 2342 2343 if (crtc->primary->state->fb) 2344 p->pri.bytes_per_pixel = 2345 crtc->primary->state->fb->bits_per_pixel / 8; 2346 else 2347 p->pri.bytes_per_pixel = 4; 2348 2349 p->cur.bytes_per_pixel = 4; 2350 /* 2351 * TODO: for now, assume primary and cursor planes are always enabled. 2352 * Setting them to false makes the screen flicker. 2353 */ 2354 p->pri.enabled = true; 2355 p->cur.enabled = true; 2356 2357 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w; 2358 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w; 2359 2360 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { 2361 struct intel_plane *intel_plane = to_intel_plane(plane); 2362 2363 if (intel_plane->pipe == pipe) { 2364 p->spr = intel_plane->wm; 2365 break; 2366 } 2367 } 2368 } 2369 2370 static void ilk_compute_wm_config(struct drm_device *dev, 2371 struct intel_wm_config *config) 2372 { 2373 struct intel_crtc *intel_crtc; 2374 2375 /* Compute the currently _active_ config */ 2376 for_each_intel_crtc(dev, intel_crtc) { 2377 const struct intel_pipe_wm *wm = &intel_crtc->wm.active; 2378 2379 if (!wm->pipe_enabled) 2380 continue; 2381 2382 config->sprites_enabled |= wm->sprites_enabled; 2383 config->sprites_scaled |= wm->sprites_scaled; 2384 config->num_pipes_active++; 2385 } 2386 } 2387 2388 /* Compute new watermarks for the pipe */ 2389 static bool intel_compute_pipe_wm(struct drm_crtc *crtc, 2390 const struct ilk_pipe_wm_parameters *params, 2391 struct intel_pipe_wm *pipe_wm) 2392 { 2393 struct drm_device *dev = crtc->dev; 2394 const struct drm_i915_private *dev_priv = dev->dev_private; 2395 int level, max_level = ilk_wm_max_level(dev); 2396 /* LP0 watermark maximums depend on this pipe alone */ 2397 struct intel_wm_config config = { 2398 .num_pipes_active = 1, 2399 .sprites_enabled = params->spr.enabled, 2400 .sprites_scaled = params->spr.scaled, 2401 }; 2402 struct ilk_wm_maximums max; 2403 2404 pipe_wm->pipe_enabled = params->active; 2405 pipe_wm->sprites_enabled = params->spr.enabled; 2406 pipe_wm->sprites_scaled = params->spr.scaled; 2407 2408 /* ILK/SNB: LP2+ watermarks only w/o sprites */ 2409 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) 2410 max_level = 1; 2411 2412 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ 2413 if (params->spr.scaled) 2414 max_level = 0; 2415 2416 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); 2417 2418 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2419 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); 2420 2421 /* LP0 watermarks always use 1/2 DDB partitioning */ 2422 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); 2423 2424 /* At least LP0 must be valid */ 2425 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) 2426 return false; 2427 2428 ilk_compute_wm_reg_maximums(dev, 1, &max); 2429 2430 for (level = 1; level <= max_level; level++) { 2431 struct intel_wm_level wm = {}; 2432 2433 ilk_compute_wm_level(dev_priv, level, params, &wm); 2434 2435 /* 2436 * Disable any watermark level that exceeds the 2437 * register maximums since such watermarks are 2438 * always invalid. 2439 */ 2440 if (!ilk_validate_wm_level(level, &max, &wm)) 2441 break; 2442 2443 pipe_wm->wm[level] = wm; 2444 } 2445 2446 return true; 2447 } 2448 2449 /* 2450 * Merge the watermarks from all active pipes for a specific level. 2451 */ 2452 static void ilk_merge_wm_level(struct drm_device *dev, 2453 int level, 2454 struct intel_wm_level *ret_wm) 2455 { 2456 struct intel_crtc *intel_crtc; 2457 2458 ret_wm->enable = true; 2459 2460 for_each_intel_crtc(dev, intel_crtc) { 2461 const struct intel_pipe_wm *active = &intel_crtc->wm.active; 2462 const struct intel_wm_level *wm = &active->wm[level]; 2463 2464 if (!active->pipe_enabled) 2465 continue; 2466 2467 /* 2468 * The watermark values may have been used in the past, 2469 * so we must maintain them in the registers for some 2470 * time even if the level is now disabled. 2471 */ 2472 if (!wm->enable) 2473 ret_wm->enable = false; 2474 2475 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); 2476 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); 2477 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); 2478 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); 2479 } 2480 } 2481 2482 /* 2483 * Merge all low power watermarks for all active pipes. 2484 */ 2485 static void ilk_wm_merge(struct drm_device *dev, 2486 const struct intel_wm_config *config, 2487 const struct ilk_wm_maximums *max, 2488 struct intel_pipe_wm *merged) 2489 { 2490 struct drm_i915_private *dev_priv = dev->dev_private; 2491 int level, max_level = ilk_wm_max_level(dev); 2492 int last_enabled_level = max_level; 2493 2494 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ 2495 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && 2496 config->num_pipes_active > 1) 2497 return; 2498 2499 /* ILK: FBC WM must be disabled always */ 2500 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; 2501 2502 /* merge each WM1+ level */ 2503 for (level = 1; level <= max_level; level++) { 2504 struct intel_wm_level *wm = &merged->wm[level]; 2505 2506 ilk_merge_wm_level(dev, level, wm); 2507 2508 if (level > last_enabled_level) 2509 wm->enable = false; 2510 else if (!ilk_validate_wm_level(level, max, wm)) 2511 /* make sure all following levels get disabled */ 2512 last_enabled_level = level - 1; 2513 2514 /* 2515 * The spec says it is preferred to disable 2516 * FBC WMs instead of disabling a WM level. 2517 */ 2518 if (wm->fbc_val > max->fbc) { 2519 if (wm->enable) 2520 merged->fbc_wm_enabled = false; 2521 wm->fbc_val = 0; 2522 } 2523 } 2524 2525 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ 2526 /* 2527 * FIXME this is racy. FBC might get enabled later. 2528 * What we should check here is whether FBC can be 2529 * enabled sometime later. 2530 */ 2531 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && 2532 intel_fbc_enabled(dev_priv)) { 2533 for (level = 2; level <= max_level; level++) { 2534 struct intel_wm_level *wm = &merged->wm[level]; 2535 2536 wm->enable = false; 2537 } 2538 } 2539 } 2540 2541 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) 2542 { 2543 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ 2544 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); 2545 } 2546 2547 /* The value we need to program into the WM_LPx latency field */ 2548 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) 2549 { 2550 struct drm_i915_private *dev_priv = dev->dev_private; 2551 2552 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 2553 return 2 * level; 2554 else 2555 return dev_priv->wm.pri_latency[level]; 2556 } 2557 2558 static void ilk_compute_wm_results(struct drm_device *dev, 2559 const struct intel_pipe_wm *merged, 2560 enum intel_ddb_partitioning partitioning, 2561 struct ilk_wm_values *results) 2562 { 2563 struct intel_crtc *intel_crtc; 2564 int level, wm_lp; 2565 2566 results->enable_fbc_wm = merged->fbc_wm_enabled; 2567 results->partitioning = partitioning; 2568 2569 /* LP1+ register values */ 2570 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2571 const struct intel_wm_level *r; 2572 2573 level = ilk_wm_lp_to_level(wm_lp, merged); 2574 2575 r = &merged->wm[level]; 2576 2577 /* 2578 * Maintain the watermark values even if the level is 2579 * disabled. Doing otherwise could cause underruns. 2580 */ 2581 results->wm_lp[wm_lp - 1] = 2582 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | 2583 (r->pri_val << WM1_LP_SR_SHIFT) | 2584 r->cur_val; 2585 2586 if (r->enable) 2587 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; 2588 2589 if (INTEL_INFO(dev)->gen >= 8) 2590 results->wm_lp[wm_lp - 1] |= 2591 r->fbc_val << WM1_LP_FBC_SHIFT_BDW; 2592 else 2593 results->wm_lp[wm_lp - 1] |= 2594 r->fbc_val << WM1_LP_FBC_SHIFT; 2595 2596 /* 2597 * Always set WM1S_LP_EN when spr_val != 0, even if the 2598 * level is disabled. Doing otherwise could cause underruns. 2599 */ 2600 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { 2601 WARN_ON(wm_lp != 1); 2602 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; 2603 } else 2604 results->wm_lp_spr[wm_lp - 1] = r->spr_val; 2605 } 2606 2607 /* LP0 register values */ 2608 for_each_intel_crtc(dev, intel_crtc) { 2609 enum i915_pipe pipe = intel_crtc->pipe; 2610 const struct intel_wm_level *r = 2611 &intel_crtc->wm.active.wm[0]; 2612 2613 if (WARN_ON(!r->enable)) 2614 continue; 2615 2616 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; 2617 2618 results->wm_pipe[pipe] = 2619 (r->pri_val << WM0_PIPE_PLANE_SHIFT) | 2620 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | 2621 r->cur_val; 2622 } 2623 } 2624 2625 /* Find the result with the highest level enabled. Check for enable_fbc_wm in 2626 * case both are at the same level. Prefer r1 in case they're the same. */ 2627 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, 2628 struct intel_pipe_wm *r1, 2629 struct intel_pipe_wm *r2) 2630 { 2631 int level, max_level = ilk_wm_max_level(dev); 2632 int level1 = 0, level2 = 0; 2633 2634 for (level = 1; level <= max_level; level++) { 2635 if (r1->wm[level].enable) 2636 level1 = level; 2637 if (r2->wm[level].enable) 2638 level2 = level; 2639 } 2640 2641 if (level1 == level2) { 2642 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) 2643 return r2; 2644 else 2645 return r1; 2646 } else if (level1 > level2) { 2647 return r1; 2648 } else { 2649 return r2; 2650 } 2651 } 2652 2653 /* dirty bits used to track which watermarks need changes */ 2654 #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) 2655 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) 2656 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) 2657 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) 2658 #define WM_DIRTY_FBC (1 << 24) 2659 #define WM_DIRTY_DDB (1 << 25) 2660 2661 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, 2662 const struct ilk_wm_values *old, 2663 const struct ilk_wm_values *new) 2664 { 2665 unsigned int dirty = 0; 2666 enum i915_pipe pipe; 2667 int wm_lp; 2668 2669 for_each_pipe(dev_priv, pipe) { 2670 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { 2671 dirty |= WM_DIRTY_LINETIME(pipe); 2672 /* Must disable LP1+ watermarks too */ 2673 dirty |= WM_DIRTY_LP_ALL; 2674 } 2675 2676 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { 2677 dirty |= WM_DIRTY_PIPE(pipe); 2678 /* Must disable LP1+ watermarks too */ 2679 dirty |= WM_DIRTY_LP_ALL; 2680 } 2681 } 2682 2683 if (old->enable_fbc_wm != new->enable_fbc_wm) { 2684 dirty |= WM_DIRTY_FBC; 2685 /* Must disable LP1+ watermarks too */ 2686 dirty |= WM_DIRTY_LP_ALL; 2687 } 2688 2689 if (old->partitioning != new->partitioning) { 2690 dirty |= WM_DIRTY_DDB; 2691 /* Must disable LP1+ watermarks too */ 2692 dirty |= WM_DIRTY_LP_ALL; 2693 } 2694 2695 /* LP1+ watermarks already deemed dirty, no need to continue */ 2696 if (dirty & WM_DIRTY_LP_ALL) 2697 return dirty; 2698 2699 /* Find the lowest numbered LP1+ watermark in need of an update... */ 2700 for (wm_lp = 1; wm_lp <= 3; wm_lp++) { 2701 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || 2702 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) 2703 break; 2704 } 2705 2706 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ 2707 for (; wm_lp <= 3; wm_lp++) 2708 dirty |= WM_DIRTY_LP(wm_lp); 2709 2710 return dirty; 2711 } 2712 2713 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, 2714 unsigned int dirty) 2715 { 2716 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2717 bool changed = false; 2718 2719 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { 2720 previous->wm_lp[2] &= ~WM1_LP_SR_EN; 2721 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); 2722 changed = true; 2723 } 2724 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { 2725 previous->wm_lp[1] &= ~WM1_LP_SR_EN; 2726 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); 2727 changed = true; 2728 } 2729 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { 2730 previous->wm_lp[0] &= ~WM1_LP_SR_EN; 2731 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); 2732 changed = true; 2733 } 2734 2735 /* 2736 * Don't touch WM1S_LP_EN here. 2737 * Doing so could cause underruns. 2738 */ 2739 2740 return changed; 2741 } 2742 2743 /* 2744 * The spec says we shouldn't write when we don't need, because every write 2745 * causes WMs to be re-evaluated, expending some power. 2746 */ 2747 static void ilk_write_wm_values(struct drm_i915_private *dev_priv, 2748 struct ilk_wm_values *results) 2749 { 2750 struct drm_device *dev = dev_priv->dev; 2751 struct ilk_wm_values *previous = &dev_priv->wm.hw; 2752 unsigned int dirty; 2753 uint32_t val; 2754 2755 dirty = ilk_compute_wm_dirty(dev_priv, previous, results); 2756 if (!dirty) 2757 return; 2758 2759 _ilk_disable_lp_wm(dev_priv, dirty); 2760 2761 if (dirty & WM_DIRTY_PIPE(PIPE_A)) 2762 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); 2763 if (dirty & WM_DIRTY_PIPE(PIPE_B)) 2764 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); 2765 if (dirty & WM_DIRTY_PIPE(PIPE_C)) 2766 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); 2767 2768 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) 2769 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); 2770 if (dirty & WM_DIRTY_LINETIME(PIPE_B)) 2771 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); 2772 if (dirty & WM_DIRTY_LINETIME(PIPE_C)) 2773 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); 2774 2775 if (dirty & WM_DIRTY_DDB) { 2776 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { 2777 val = I915_READ(WM_MISC); 2778 if (results->partitioning == INTEL_DDB_PART_1_2) 2779 val &= ~WM_MISC_DATA_PARTITION_5_6; 2780 else 2781 val |= WM_MISC_DATA_PARTITION_5_6; 2782 I915_WRITE(WM_MISC, val); 2783 } else { 2784 val = I915_READ(DISP_ARB_CTL2); 2785 if (results->partitioning == INTEL_DDB_PART_1_2) 2786 val &= ~DISP_DATA_PARTITION_5_6; 2787 else 2788 val |= DISP_DATA_PARTITION_5_6; 2789 I915_WRITE(DISP_ARB_CTL2, val); 2790 } 2791 } 2792 2793 if (dirty & WM_DIRTY_FBC) { 2794 val = I915_READ(DISP_ARB_CTL); 2795 if (results->enable_fbc_wm) 2796 val &= ~DISP_FBC_WM_DIS; 2797 else 2798 val |= DISP_FBC_WM_DIS; 2799 I915_WRITE(DISP_ARB_CTL, val); 2800 } 2801 2802 if (dirty & WM_DIRTY_LP(1) && 2803 previous->wm_lp_spr[0] != results->wm_lp_spr[0]) 2804 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); 2805 2806 if (INTEL_INFO(dev)->gen >= 7) { 2807 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) 2808 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); 2809 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) 2810 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); 2811 } 2812 2813 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) 2814 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); 2815 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) 2816 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); 2817 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) 2818 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); 2819 2820 dev_priv->wm.hw = *results; 2821 } 2822 2823 static bool ilk_disable_lp_wm(struct drm_device *dev) 2824 { 2825 struct drm_i915_private *dev_priv = dev->dev_private; 2826 2827 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); 2828 } 2829 2830 /* 2831 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the 2832 * different active planes. 2833 */ 2834 2835 #define SKL_DDB_SIZE 896 /* in blocks */ 2836 #define BXT_DDB_SIZE 512 2837 2838 static void 2839 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, 2840 struct drm_crtc *for_crtc, 2841 const struct intel_wm_config *config, 2842 const struct skl_pipe_wm_parameters *params, 2843 struct skl_ddb_entry *alloc /* out */) 2844 { 2845 struct drm_crtc *crtc; 2846 unsigned int pipe_size, ddb_size; 2847 int nth_active_pipe; 2848 2849 if (!params->active) { 2850 alloc->start = 0; 2851 alloc->end = 0; 2852 return; 2853 } 2854 2855 if (IS_BROXTON(dev)) 2856 ddb_size = BXT_DDB_SIZE; 2857 else 2858 ddb_size = SKL_DDB_SIZE; 2859 2860 ddb_size -= 4; /* 4 blocks for bypass path allocation */ 2861 2862 nth_active_pipe = 0; 2863 for_each_crtc(dev, crtc) { 2864 if (!to_intel_crtc(crtc)->active) 2865 continue; 2866 2867 if (crtc == for_crtc) 2868 break; 2869 2870 nth_active_pipe++; 2871 } 2872 2873 pipe_size = ddb_size / config->num_pipes_active; 2874 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; 2875 alloc->end = alloc->start + pipe_size; 2876 } 2877 2878 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) 2879 { 2880 if (config->num_pipes_active == 1) 2881 return 32; 2882 2883 return 8; 2884 } 2885 2886 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) 2887 { 2888 entry->start = reg & 0x3ff; 2889 entry->end = (reg >> 16) & 0x3ff; 2890 if (entry->end) 2891 entry->end += 1; 2892 } 2893 2894 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 2895 struct skl_ddb_allocation *ddb /* out */) 2896 { 2897 enum i915_pipe pipe; 2898 int plane; 2899 u32 val; 2900 2901 for_each_pipe(dev_priv, pipe) { 2902 for_each_plane(dev_priv, pipe, plane) { 2903 val = I915_READ(PLANE_BUF_CFG(pipe, plane)); 2904 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], 2905 val); 2906 } 2907 2908 val = I915_READ(CUR_BUF_CFG(pipe)); 2909 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val); 2910 } 2911 } 2912 2913 static unsigned int 2914 skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y) 2915 { 2916 2917 /* for planar format */ 2918 if (p->y_bytes_per_pixel) { 2919 if (y) /* y-plane data rate */ 2920 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel; 2921 else /* uv-plane data rate */ 2922 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel; 2923 } 2924 2925 /* for packed formats */ 2926 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; 2927 } 2928 2929 /* 2930 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching 2931 * a 8192x4096@32bpp framebuffer: 2932 * 3 * 4096 * 8192 * 4 < 2^32 2933 */ 2934 static unsigned int 2935 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, 2936 const struct skl_pipe_wm_parameters *params) 2937 { 2938 unsigned int total_data_rate = 0; 2939 int plane; 2940 2941 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 2942 const struct intel_plane_wm_parameters *p; 2943 2944 p = ¶ms->plane[plane]; 2945 if (!p->enabled) 2946 continue; 2947 2948 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */ 2949 if (p->y_bytes_per_pixel) { 2950 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */ 2951 } 2952 } 2953 2954 return total_data_rate; 2955 } 2956 2957 static void 2958 skl_allocate_pipe_ddb(struct drm_crtc *crtc, 2959 const struct intel_wm_config *config, 2960 const struct skl_pipe_wm_parameters *params, 2961 struct skl_ddb_allocation *ddb /* out */) 2962 { 2963 struct drm_device *dev = crtc->dev; 2964 struct drm_i915_private *dev_priv = dev->dev_private; 2965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2966 enum i915_pipe pipe = intel_crtc->pipe; 2967 struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; 2968 uint16_t alloc_size, start, cursor_blocks; 2969 uint16_t minimum[I915_MAX_PLANES]; 2970 uint16_t y_minimum[I915_MAX_PLANES]; 2971 unsigned int total_data_rate; 2972 int plane; 2973 2974 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); 2975 alloc_size = skl_ddb_entry_size(alloc); 2976 if (alloc_size == 0) { 2977 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); 2978 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe])); 2979 return; 2980 } 2981 2982 cursor_blocks = skl_cursor_allocation(config); 2983 ddb->cursor[pipe].start = alloc->end - cursor_blocks; 2984 ddb->cursor[pipe].end = alloc->end; 2985 2986 alloc_size -= cursor_blocks; 2987 alloc->end -= cursor_blocks; 2988 2989 /* 1. Allocate the mininum required blocks for each active plane */ 2990 for_each_plane(dev_priv, pipe, plane) { 2991 const struct intel_plane_wm_parameters *p; 2992 2993 p = ¶ms->plane[plane]; 2994 if (!p->enabled) 2995 continue; 2996 2997 minimum[plane] = 8; 2998 alloc_size -= minimum[plane]; 2999 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0; 3000 alloc_size -= y_minimum[plane]; 3001 } 3002 3003 /* 3004 * 2. Distribute the remaining space in proportion to the amount of 3005 * data each plane needs to fetch from memory. 3006 * 3007 * FIXME: we may not allocate every single block here. 3008 */ 3009 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); 3010 3011 start = alloc->start; 3012 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { 3013 const struct intel_plane_wm_parameters *p; 3014 unsigned int data_rate, y_data_rate; 3015 uint16_t plane_blocks, y_plane_blocks = 0; 3016 3017 p = ¶ms->plane[plane]; 3018 if (!p->enabled) 3019 continue; 3020 3021 data_rate = skl_plane_relative_data_rate(p, 0); 3022 3023 /* 3024 * allocation for (packed formats) or (uv-plane part of planar format): 3025 * promote the expression to 64 bits to avoid overflowing, the 3026 * result is < available as data_rate / total_data_rate < 1 3027 */ 3028 plane_blocks = minimum[plane]; 3029 plane_blocks += div_u64((uint64_t)alloc_size * data_rate, 3030 total_data_rate); 3031 3032 ddb->plane[pipe][plane].start = start; 3033 ddb->plane[pipe][plane].end = start + plane_blocks; 3034 3035 start += plane_blocks; 3036 3037 /* 3038 * allocation for y_plane part of planar format: 3039 */ 3040 if (p->y_bytes_per_pixel) { 3041 y_data_rate = skl_plane_relative_data_rate(p, 1); 3042 y_plane_blocks = y_minimum[plane]; 3043 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, 3044 total_data_rate); 3045 3046 ddb->y_plane[pipe][plane].start = start; 3047 ddb->y_plane[pipe][plane].end = start + y_plane_blocks; 3048 3049 start += y_plane_blocks; 3050 } 3051 3052 } 3053 3054 } 3055 3056 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) 3057 { 3058 /* TODO: Take into account the scalers once we support them */ 3059 return config->base.adjusted_mode.crtc_clock; 3060 } 3061 3062 /* 3063 * The max latency should be 257 (max the punit can code is 255 and we add 2us 3064 * for the read latency) and bytes_per_pixel should always be <= 8, so that 3065 * should allow pixel_rate up to ~2 GHz which seems sufficient since max 3066 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. 3067 */ 3068 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, 3069 uint32_t latency) 3070 { 3071 uint32_t wm_intermediate_val, ret; 3072 3073 if (latency == 0) 3074 return UINT_MAX; 3075 3076 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; 3077 ret = DIV_ROUND_UP(wm_intermediate_val, 1000); 3078 3079 return ret; 3080 } 3081 3082 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, 3083 uint32_t horiz_pixels, uint8_t bytes_per_pixel, 3084 uint64_t tiling, uint32_t latency) 3085 { 3086 uint32_t ret; 3087 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3088 uint32_t wm_intermediate_val; 3089 3090 if (latency == 0) 3091 return UINT_MAX; 3092 3093 plane_bytes_per_line = horiz_pixels * bytes_per_pixel; 3094 3095 if (tiling == I915_FORMAT_MOD_Y_TILED || 3096 tiling == I915_FORMAT_MOD_Yf_TILED) { 3097 plane_bytes_per_line *= 4; 3098 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3099 plane_blocks_per_line /= 4; 3100 } else { 3101 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3102 } 3103 3104 wm_intermediate_val = latency * pixel_rate; 3105 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * 3106 plane_blocks_per_line; 3107 3108 return ret; 3109 } 3110 3111 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, 3112 const struct intel_crtc *intel_crtc) 3113 { 3114 struct drm_device *dev = intel_crtc->base.dev; 3115 struct drm_i915_private *dev_priv = dev->dev_private; 3116 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; 3117 enum i915_pipe pipe = intel_crtc->pipe; 3118 3119 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], 3120 sizeof(new_ddb->plane[pipe]))) 3121 return true; 3122 3123 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe], 3124 sizeof(new_ddb->cursor[pipe]))) 3125 return true; 3126 3127 return false; 3128 } 3129 3130 static void skl_compute_wm_global_parameters(struct drm_device *dev, 3131 struct intel_wm_config *config) 3132 { 3133 struct drm_crtc *crtc; 3134 struct drm_plane *plane; 3135 3136 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3137 config->num_pipes_active += to_intel_crtc(crtc)->active; 3138 3139 /* FIXME: I don't think we need those two global parameters on SKL */ 3140 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3141 struct intel_plane *intel_plane = to_intel_plane(plane); 3142 3143 config->sprites_enabled |= intel_plane->wm.enabled; 3144 config->sprites_scaled |= intel_plane->wm.scaled; 3145 } 3146 } 3147 3148 static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, 3149 struct skl_pipe_wm_parameters *p) 3150 { 3151 struct drm_device *dev = crtc->dev; 3152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3153 enum i915_pipe pipe = intel_crtc->pipe; 3154 struct drm_plane *plane; 3155 struct drm_framebuffer *fb; 3156 int i = 1; /* Index for sprite planes start */ 3157 3158 p->active = intel_crtc->active; 3159 if (p->active) { 3160 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; 3161 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); 3162 3163 fb = crtc->primary->state->fb; 3164 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */ 3165 if (fb) { 3166 p->plane[0].enabled = true; 3167 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3168 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8; 3169 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ? 3170 drm_format_plane_cpp(fb->pixel_format, 0) : 0; 3171 p->plane[0].tiling = fb->modifier[0]; 3172 } else { 3173 p->plane[0].enabled = false; 3174 p->plane[0].bytes_per_pixel = 0; 3175 p->plane[0].y_bytes_per_pixel = 0; 3176 p->plane[0].tiling = DRM_FORMAT_MOD_NONE; 3177 } 3178 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; 3179 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; 3180 p->plane[0].rotation = crtc->primary->state->rotation; 3181 3182 fb = crtc->cursor->state->fb; 3183 p->cursor.y_bytes_per_pixel = 0; 3184 if (fb) { 3185 p->cursor.enabled = true; 3186 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8; 3187 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w; 3188 p->cursor.vert_pixels = crtc->cursor->state->crtc_h; 3189 } else { 3190 p->cursor.enabled = false; 3191 p->cursor.bytes_per_pixel = 0; 3192 p->cursor.horiz_pixels = 64; 3193 p->cursor.vert_pixels = 64; 3194 } 3195 } 3196 3197 list_for_each_entry(plane, &dev->mode_config.plane_list, head) { 3198 struct intel_plane *intel_plane = to_intel_plane(plane); 3199 3200 if (intel_plane->pipe == pipe && 3201 plane->type == DRM_PLANE_TYPE_OVERLAY) 3202 p->plane[i++] = intel_plane->wm; 3203 } 3204 } 3205 3206 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, 3207 struct skl_pipe_wm_parameters *p, 3208 struct intel_plane_wm_parameters *p_params, 3209 uint16_t ddb_allocation, 3210 int level, 3211 uint16_t *out_blocks, /* out */ 3212 uint8_t *out_lines /* out */) 3213 { 3214 uint32_t latency = dev_priv->wm.skl_latency[level]; 3215 uint32_t method1, method2; 3216 uint32_t plane_bytes_per_line, plane_blocks_per_line; 3217 uint32_t res_blocks, res_lines; 3218 uint32_t selected_result; 3219 uint8_t bytes_per_pixel; 3220 3221 if (latency == 0 || !p->active || !p_params->enabled) 3222 return false; 3223 3224 bytes_per_pixel = p_params->y_bytes_per_pixel ? 3225 p_params->y_bytes_per_pixel : 3226 p_params->bytes_per_pixel; 3227 method1 = skl_wm_method1(p->pixel_rate, 3228 bytes_per_pixel, 3229 latency); 3230 method2 = skl_wm_method2(p->pixel_rate, 3231 p->pipe_htotal, 3232 p_params->horiz_pixels, 3233 bytes_per_pixel, 3234 p_params->tiling, 3235 latency); 3236 3237 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel; 3238 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); 3239 3240 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3241 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { 3242 uint32_t min_scanlines = 4; 3243 uint32_t y_tile_minimum; 3244 if (intel_rotation_90_or_270(p_params->rotation)) { 3245 switch (p_params->bytes_per_pixel) { 3246 case 1: 3247 min_scanlines = 16; 3248 break; 3249 case 2: 3250 min_scanlines = 8; 3251 break; 3252 case 8: 3253 WARN(1, "Unsupported pixel depth for rotation"); 3254 } 3255 } 3256 y_tile_minimum = plane_blocks_per_line * min_scanlines; 3257 selected_result = max(method2, y_tile_minimum); 3258 } else { 3259 if ((ddb_allocation / plane_blocks_per_line) >= 1) 3260 selected_result = min(method1, method2); 3261 else 3262 selected_result = method1; 3263 } 3264 3265 res_blocks = selected_result + 1; 3266 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); 3267 3268 if (level >= 1 && level <= 7) { 3269 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || 3270 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) 3271 res_lines += 4; 3272 else 3273 res_blocks++; 3274 } 3275 3276 if (res_blocks >= ddb_allocation || res_lines > 31) 3277 return false; 3278 3279 *out_blocks = res_blocks; 3280 *out_lines = res_lines; 3281 3282 return true; 3283 } 3284 3285 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, 3286 struct skl_ddb_allocation *ddb, 3287 struct skl_pipe_wm_parameters *p, 3288 enum i915_pipe pipe, 3289 int level, 3290 int num_planes, 3291 struct skl_wm_level *result) 3292 { 3293 uint16_t ddb_blocks; 3294 int i; 3295 3296 for (i = 0; i < num_planes; i++) { 3297 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); 3298 3299 result->plane_en[i] = skl_compute_plane_wm(dev_priv, 3300 p, &p->plane[i], 3301 ddb_blocks, 3302 level, 3303 &result->plane_res_b[i], 3304 &result->plane_res_l[i]); 3305 } 3306 3307 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]); 3308 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor, 3309 ddb_blocks, level, 3310 &result->cursor_res_b, 3311 &result->cursor_res_l); 3312 } 3313 3314 static uint32_t 3315 skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) 3316 { 3317 if (!to_intel_crtc(crtc)->active) 3318 return 0; 3319 3320 if (WARN_ON(p->pixel_rate == 0)) 3321 return 0; 3322 3323 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); 3324 } 3325 3326 static void skl_compute_transition_wm(struct drm_crtc *crtc, 3327 struct skl_pipe_wm_parameters *params, 3328 struct skl_wm_level *trans_wm /* out */) 3329 { 3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3331 int i; 3332 3333 if (!params->active) 3334 return; 3335 3336 /* Until we know more, just disable transition WMs */ 3337 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3338 trans_wm->plane_en[i] = false; 3339 trans_wm->cursor_en = false; 3340 } 3341 3342 static void skl_compute_pipe_wm(struct drm_crtc *crtc, 3343 struct skl_ddb_allocation *ddb, 3344 struct skl_pipe_wm_parameters *params, 3345 struct skl_pipe_wm *pipe_wm) 3346 { 3347 struct drm_device *dev = crtc->dev; 3348 const struct drm_i915_private *dev_priv = dev->dev_private; 3349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3350 int level, max_level = ilk_wm_max_level(dev); 3351 3352 for (level = 0; level <= max_level; level++) { 3353 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, 3354 level, intel_num_planes(intel_crtc), 3355 &pipe_wm->wm[level]); 3356 } 3357 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); 3358 3359 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); 3360 } 3361 3362 static void skl_compute_wm_results(struct drm_device *dev, 3363 struct skl_pipe_wm_parameters *p, 3364 struct skl_pipe_wm *p_wm, 3365 struct skl_wm_values *r, 3366 struct intel_crtc *intel_crtc) 3367 { 3368 int level, max_level = ilk_wm_max_level(dev); 3369 enum i915_pipe pipe = intel_crtc->pipe; 3370 uint32_t temp; 3371 int i; 3372 3373 for (level = 0; level <= max_level; level++) { 3374 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3375 temp = 0; 3376 3377 temp |= p_wm->wm[level].plane_res_l[i] << 3378 PLANE_WM_LINES_SHIFT; 3379 temp |= p_wm->wm[level].plane_res_b[i]; 3380 if (p_wm->wm[level].plane_en[i]) 3381 temp |= PLANE_WM_EN; 3382 3383 r->plane[pipe][i][level] = temp; 3384 } 3385 3386 temp = 0; 3387 3388 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT; 3389 temp |= p_wm->wm[level].cursor_res_b; 3390 3391 if (p_wm->wm[level].cursor_en) 3392 temp |= PLANE_WM_EN; 3393 3394 r->cursor[pipe][level] = temp; 3395 3396 } 3397 3398 /* transition WMs */ 3399 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3400 temp = 0; 3401 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; 3402 temp |= p_wm->trans_wm.plane_res_b[i]; 3403 if (p_wm->trans_wm.plane_en[i]) 3404 temp |= PLANE_WM_EN; 3405 3406 r->plane_trans[pipe][i] = temp; 3407 } 3408 3409 temp = 0; 3410 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT; 3411 temp |= p_wm->trans_wm.cursor_res_b; 3412 if (p_wm->trans_wm.cursor_en) 3413 temp |= PLANE_WM_EN; 3414 3415 r->cursor_trans[pipe] = temp; 3416 3417 r->wm_linetime[pipe] = p_wm->linetime; 3418 } 3419 3420 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, 3421 const struct skl_ddb_entry *entry) 3422 { 3423 if (entry->end) 3424 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); 3425 else 3426 I915_WRITE(reg, 0); 3427 } 3428 3429 static void skl_write_wm_values(struct drm_i915_private *dev_priv, 3430 const struct skl_wm_values *new) 3431 { 3432 struct drm_device *dev = dev_priv->dev; 3433 struct intel_crtc *crtc; 3434 3435 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 3436 int i, level, max_level = ilk_wm_max_level(dev); 3437 enum i915_pipe pipe = crtc->pipe; 3438 3439 if (!new->dirty[pipe]) 3440 continue; 3441 3442 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); 3443 3444 for (level = 0; level <= max_level; level++) { 3445 for (i = 0; i < intel_num_planes(crtc); i++) 3446 I915_WRITE(PLANE_WM(pipe, i, level), 3447 new->plane[pipe][i][level]); 3448 I915_WRITE(CUR_WM(pipe, level), 3449 new->cursor[pipe][level]); 3450 } 3451 for (i = 0; i < intel_num_planes(crtc); i++) 3452 I915_WRITE(PLANE_WM_TRANS(pipe, i), 3453 new->plane_trans[pipe][i]); 3454 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); 3455 3456 for (i = 0; i < intel_num_planes(crtc); i++) { 3457 skl_ddb_entry_write(dev_priv, 3458 PLANE_BUF_CFG(pipe, i), 3459 &new->ddb.plane[pipe][i]); 3460 skl_ddb_entry_write(dev_priv, 3461 PLANE_NV12_BUF_CFG(pipe, i), 3462 &new->ddb.y_plane[pipe][i]); 3463 } 3464 3465 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), 3466 &new->ddb.cursor[pipe]); 3467 } 3468 } 3469 3470 /* 3471 * When setting up a new DDB allocation arrangement, we need to correctly 3472 * sequence the times at which the new allocations for the pipes are taken into 3473 * account or we'll have pipes fetching from space previously allocated to 3474 * another pipe. 3475 * 3476 * Roughly the sequence looks like: 3477 * 1. re-allocate the pipe(s) with the allocation being reduced and not 3478 * overlapping with a previous light-up pipe (another way to put it is: 3479 * pipes with their new allocation strickly included into their old ones). 3480 * 2. re-allocate the other pipes that get their allocation reduced 3481 * 3. allocate the pipes having their allocation increased 3482 * 3483 * Steps 1. and 2. are here to take care of the following case: 3484 * - Initially DDB looks like this: 3485 * | B | C | 3486 * - enable pipe A. 3487 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C 3488 * allocation 3489 * | A | B | C | 3490 * 3491 * We need to sequence the re-allocation: C, B, A (and not B, C, A). 3492 */ 3493 3494 static void 3495 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, int pass) 3496 { 3497 int plane; 3498 3499 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); 3500 3501 for_each_plane(dev_priv, pipe, plane) { 3502 I915_WRITE(PLANE_SURF(pipe, plane), 3503 I915_READ(PLANE_SURF(pipe, plane))); 3504 } 3505 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); 3506 } 3507 3508 static bool 3509 skl_ddb_allocation_included(const struct skl_ddb_allocation *old, 3510 const struct skl_ddb_allocation *new, 3511 enum i915_pipe pipe) 3512 { 3513 uint16_t old_size, new_size; 3514 3515 old_size = skl_ddb_entry_size(&old->pipe[pipe]); 3516 new_size = skl_ddb_entry_size(&new->pipe[pipe]); 3517 3518 return old_size != new_size && 3519 new->pipe[pipe].start >= old->pipe[pipe].start && 3520 new->pipe[pipe].end <= old->pipe[pipe].end; 3521 } 3522 3523 static void skl_flush_wm_values(struct drm_i915_private *dev_priv, 3524 struct skl_wm_values *new_values) 3525 { 3526 struct drm_device *dev = dev_priv->dev; 3527 struct skl_ddb_allocation *cur_ddb, *new_ddb; 3528 bool reallocated[I915_MAX_PIPES] = {}; 3529 struct intel_crtc *crtc; 3530 enum i915_pipe pipe; 3531 3532 new_ddb = &new_values->ddb; 3533 cur_ddb = &dev_priv->wm.skl_hw.ddb; 3534 3535 /* 3536 * First pass: flush the pipes with the new allocation contained into 3537 * the old space. 3538 * 3539 * We'll wait for the vblank on those pipes to ensure we can safely 3540 * re-allocate the freed space without this pipe fetching from it. 3541 */ 3542 for_each_intel_crtc(dev, crtc) { 3543 if (!crtc->active) 3544 continue; 3545 3546 pipe = crtc->pipe; 3547 3548 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) 3549 continue; 3550 3551 skl_wm_flush_pipe(dev_priv, pipe, 1); 3552 intel_wait_for_vblank(dev, pipe); 3553 3554 reallocated[pipe] = true; 3555 } 3556 3557 3558 /* 3559 * Second pass: flush the pipes that are having their allocation 3560 * reduced, but overlapping with a previous allocation. 3561 * 3562 * Here as well we need to wait for the vblank to make sure the freed 3563 * space is not used anymore. 3564 */ 3565 for_each_intel_crtc(dev, crtc) { 3566 if (!crtc->active) 3567 continue; 3568 3569 pipe = crtc->pipe; 3570 3571 if (reallocated[pipe]) 3572 continue; 3573 3574 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < 3575 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { 3576 skl_wm_flush_pipe(dev_priv, pipe, 2); 3577 intel_wait_for_vblank(dev, pipe); 3578 reallocated[pipe] = true; 3579 } 3580 } 3581 3582 /* 3583 * Third pass: flush the pipes that got more space allocated. 3584 * 3585 * We don't need to actively wait for the update here, next vblank 3586 * will just get more DDB space with the correct WM values. 3587 */ 3588 for_each_intel_crtc(dev, crtc) { 3589 if (!crtc->active) 3590 continue; 3591 3592 pipe = crtc->pipe; 3593 3594 /* 3595 * At this point, only the pipes more space than before are 3596 * left to re-allocate. 3597 */ 3598 if (reallocated[pipe]) 3599 continue; 3600 3601 skl_wm_flush_pipe(dev_priv, pipe, 3); 3602 } 3603 } 3604 3605 static bool skl_update_pipe_wm(struct drm_crtc *crtc, 3606 struct skl_pipe_wm_parameters *params, 3607 struct intel_wm_config *config, 3608 struct skl_ddb_allocation *ddb, /* out */ 3609 struct skl_pipe_wm *pipe_wm /* out */) 3610 { 3611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3612 3613 skl_compute_wm_pipe_parameters(crtc, params); 3614 skl_allocate_pipe_ddb(crtc, config, params, ddb); 3615 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); 3616 3617 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) 3618 return false; 3619 3620 intel_crtc->wm.skl_active = *pipe_wm; 3621 3622 return true; 3623 } 3624 3625 static void skl_update_other_pipe_wm(struct drm_device *dev, 3626 struct drm_crtc *crtc, 3627 struct intel_wm_config *config, 3628 struct skl_wm_values *r) 3629 { 3630 struct intel_crtc *intel_crtc; 3631 struct intel_crtc *this_crtc = to_intel_crtc(crtc); 3632 3633 /* 3634 * If the WM update hasn't changed the allocation for this_crtc (the 3635 * crtc we are currently computing the new WM values for), other 3636 * enabled crtcs will keep the same allocation and we don't need to 3637 * recompute anything for them. 3638 */ 3639 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) 3640 return; 3641 3642 /* 3643 * Otherwise, because of this_crtc being freshly enabled/disabled, the 3644 * other active pipes need new DDB allocation and WM values. 3645 */ 3646 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 3647 base.head) { 3648 struct skl_pipe_wm_parameters params = {}; 3649 struct skl_pipe_wm pipe_wm = {}; 3650 bool wm_changed; 3651 3652 if (this_crtc->pipe == intel_crtc->pipe) 3653 continue; 3654 3655 if (!intel_crtc->active) 3656 continue; 3657 3658 wm_changed = skl_update_pipe_wm(&intel_crtc->base, 3659 ¶ms, config, 3660 &r->ddb, &pipe_wm); 3661 3662 /* 3663 * If we end up re-computing the other pipe WM values, it's 3664 * because it was really needed, so we expect the WM values to 3665 * be different. 3666 */ 3667 WARN_ON(!wm_changed); 3668 3669 skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); 3670 r->dirty[intel_crtc->pipe] = true; 3671 } 3672 } 3673 3674 static void skl_update_wm(struct drm_crtc *crtc) 3675 { 3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3677 struct drm_device *dev = crtc->dev; 3678 struct drm_i915_private *dev_priv = dev->dev_private; 3679 struct skl_pipe_wm_parameters params = {}; 3680 struct skl_wm_values *results = &dev_priv->wm.skl_results; 3681 struct skl_pipe_wm pipe_wm = {}; 3682 struct intel_wm_config config = {}; 3683 3684 memset(results, 0, sizeof(*results)); 3685 3686 skl_compute_wm_global_parameters(dev, &config); 3687 3688 if (!skl_update_pipe_wm(crtc, ¶ms, &config, 3689 &results->ddb, &pipe_wm)) 3690 return; 3691 3692 skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); 3693 results->dirty[intel_crtc->pipe] = true; 3694 3695 skl_update_other_pipe_wm(dev, crtc, &config, results); 3696 skl_write_wm_values(dev_priv, results); 3697 skl_flush_wm_values(dev_priv, results); 3698 3699 /* store the new configuration */ 3700 dev_priv->wm.skl_hw = *results; 3701 } 3702 3703 static void 3704 skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, 3705 uint32_t sprite_width, uint32_t sprite_height, 3706 int pixel_size, bool enabled, bool scaled) 3707 { 3708 struct intel_plane *intel_plane = to_intel_plane(plane); 3709 struct drm_framebuffer *fb = plane->state->fb; 3710 3711 intel_plane->wm.enabled = enabled; 3712 intel_plane->wm.scaled = scaled; 3713 intel_plane->wm.horiz_pixels = sprite_width; 3714 intel_plane->wm.vert_pixels = sprite_height; 3715 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; 3716 3717 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */ 3718 intel_plane->wm.bytes_per_pixel = 3719 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3720 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size; 3721 intel_plane->wm.y_bytes_per_pixel = 3722 (fb && fb->pixel_format == DRM_FORMAT_NV12) ? 3723 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0; 3724 3725 /* 3726 * Framebuffer can be NULL on plane disable, but it does not 3727 * matter for watermarks if we assume no tiling in that case. 3728 */ 3729 if (fb) 3730 intel_plane->wm.tiling = fb->modifier[0]; 3731 intel_plane->wm.rotation = plane->state->rotation; 3732 3733 skl_update_wm(crtc); 3734 } 3735 3736 static void ilk_update_wm(struct drm_crtc *crtc) 3737 { 3738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3739 struct drm_device *dev = crtc->dev; 3740 struct drm_i915_private *dev_priv = dev->dev_private; 3741 struct ilk_wm_maximums max; 3742 struct ilk_pipe_wm_parameters params = {}; 3743 struct ilk_wm_values results = {}; 3744 enum intel_ddb_partitioning partitioning; 3745 struct intel_pipe_wm pipe_wm = {}; 3746 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; 3747 struct intel_wm_config config = {}; 3748 3749 ilk_compute_wm_parameters(crtc, ¶ms); 3750 3751 intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); 3752 3753 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) 3754 return; 3755 3756 intel_crtc->wm.active = pipe_wm; 3757 3758 ilk_compute_wm_config(dev, &config); 3759 3760 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); 3761 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); 3762 3763 /* 5/6 split only in single pipe config on IVB+ */ 3764 if (INTEL_INFO(dev)->gen >= 7 && 3765 config.num_pipes_active == 1 && config.sprites_enabled) { 3766 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); 3767 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); 3768 3769 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); 3770 } else { 3771 best_lp_wm = &lp_wm_1_2; 3772 } 3773 3774 partitioning = (best_lp_wm == &lp_wm_1_2) ? 3775 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; 3776 3777 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); 3778 3779 ilk_write_wm_values(dev_priv, &results); 3780 } 3781 3782 static void 3783 ilk_update_sprite_wm(struct drm_plane *plane, 3784 struct drm_crtc *crtc, 3785 uint32_t sprite_width, uint32_t sprite_height, 3786 int pixel_size, bool enabled, bool scaled) 3787 { 3788 struct drm_device *dev = plane->dev; 3789 struct intel_plane *intel_plane = to_intel_plane(plane); 3790 3791 intel_plane->wm.enabled = enabled; 3792 intel_plane->wm.scaled = scaled; 3793 intel_plane->wm.horiz_pixels = sprite_width; 3794 intel_plane->wm.vert_pixels = sprite_width; 3795 intel_plane->wm.bytes_per_pixel = pixel_size; 3796 3797 /* 3798 * IVB workaround: must disable low power watermarks for at least 3799 * one frame before enabling scaling. LP watermarks can be re-enabled 3800 * when scaling is disabled. 3801 * 3802 * WaCxSRDisabledForSpriteScaling:ivb 3803 */ 3804 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) 3805 intel_wait_for_vblank(dev, intel_plane->pipe); 3806 3807 ilk_update_wm(crtc); 3808 } 3809 3810 static void skl_pipe_wm_active_state(uint32_t val, 3811 struct skl_pipe_wm *active, 3812 bool is_transwm, 3813 bool is_cursor, 3814 int i, 3815 int level) 3816 { 3817 bool is_enabled = (val & PLANE_WM_EN) != 0; 3818 3819 if (!is_transwm) { 3820 if (!is_cursor) { 3821 active->wm[level].plane_en[i] = is_enabled; 3822 active->wm[level].plane_res_b[i] = 3823 val & PLANE_WM_BLOCKS_MASK; 3824 active->wm[level].plane_res_l[i] = 3825 (val >> PLANE_WM_LINES_SHIFT) & 3826 PLANE_WM_LINES_MASK; 3827 } else { 3828 active->wm[level].cursor_en = is_enabled; 3829 active->wm[level].cursor_res_b = 3830 val & PLANE_WM_BLOCKS_MASK; 3831 active->wm[level].cursor_res_l = 3832 (val >> PLANE_WM_LINES_SHIFT) & 3833 PLANE_WM_LINES_MASK; 3834 } 3835 } else { 3836 if (!is_cursor) { 3837 active->trans_wm.plane_en[i] = is_enabled; 3838 active->trans_wm.plane_res_b[i] = 3839 val & PLANE_WM_BLOCKS_MASK; 3840 active->trans_wm.plane_res_l[i] = 3841 (val >> PLANE_WM_LINES_SHIFT) & 3842 PLANE_WM_LINES_MASK; 3843 } else { 3844 active->trans_wm.cursor_en = is_enabled; 3845 active->trans_wm.cursor_res_b = 3846 val & PLANE_WM_BLOCKS_MASK; 3847 active->trans_wm.cursor_res_l = 3848 (val >> PLANE_WM_LINES_SHIFT) & 3849 PLANE_WM_LINES_MASK; 3850 } 3851 } 3852 } 3853 3854 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3855 { 3856 struct drm_device *dev = crtc->dev; 3857 struct drm_i915_private *dev_priv = dev->dev_private; 3858 struct skl_wm_values *hw = &dev_priv->wm.skl_hw; 3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3860 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; 3861 enum i915_pipe pipe = intel_crtc->pipe; 3862 int level, i, max_level; 3863 uint32_t temp; 3864 3865 max_level = ilk_wm_max_level(dev); 3866 3867 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3868 3869 for (level = 0; level <= max_level; level++) { 3870 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3871 hw->plane[pipe][i][level] = 3872 I915_READ(PLANE_WM(pipe, i, level)); 3873 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level)); 3874 } 3875 3876 for (i = 0; i < intel_num_planes(intel_crtc); i++) 3877 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); 3878 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe)); 3879 3880 if (!intel_crtc->active) 3881 return; 3882 3883 hw->dirty[pipe] = true; 3884 3885 active->linetime = hw->wm_linetime[pipe]; 3886 3887 for (level = 0; level <= max_level; level++) { 3888 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3889 temp = hw->plane[pipe][i][level]; 3890 skl_pipe_wm_active_state(temp, active, false, 3891 false, i, level); 3892 } 3893 temp = hw->cursor[pipe][level]; 3894 skl_pipe_wm_active_state(temp, active, false, true, i, level); 3895 } 3896 3897 for (i = 0; i < intel_num_planes(intel_crtc); i++) { 3898 temp = hw->plane_trans[pipe][i]; 3899 skl_pipe_wm_active_state(temp, active, true, false, i, 0); 3900 } 3901 3902 temp = hw->cursor_trans[pipe]; 3903 skl_pipe_wm_active_state(temp, active, true, true, i, 0); 3904 } 3905 3906 void skl_wm_get_hw_state(struct drm_device *dev) 3907 { 3908 struct drm_i915_private *dev_priv = dev->dev_private; 3909 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; 3910 struct drm_crtc *crtc; 3911 3912 skl_ddb_get_hw_state(dev_priv, ddb); 3913 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 3914 skl_pipe_wm_get_hw_state(crtc); 3915 } 3916 3917 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) 3918 { 3919 struct drm_device *dev = crtc->dev; 3920 struct drm_i915_private *dev_priv = dev->dev_private; 3921 struct ilk_wm_values *hw = &dev_priv->wm.hw; 3922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3923 struct intel_pipe_wm *active = &intel_crtc->wm.active; 3924 enum i915_pipe pipe = intel_crtc->pipe; 3925 static const unsigned int wm0_pipe_reg[] = { 3926 [PIPE_A] = WM0_PIPEA_ILK, 3927 [PIPE_B] = WM0_PIPEB_ILK, 3928 [PIPE_C] = WM0_PIPEC_IVB, 3929 }; 3930 3931 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); 3932 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 3933 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); 3934 3935 active->pipe_enabled = intel_crtc->active; 3936 3937 if (active->pipe_enabled) { 3938 u32 tmp = hw->wm_pipe[pipe]; 3939 3940 /* 3941 * For active pipes LP0 watermark is marked as 3942 * enabled, and LP1+ watermaks as disabled since 3943 * we can't really reverse compute them in case 3944 * multiple pipes are active. 3945 */ 3946 active->wm[0].enable = true; 3947 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; 3948 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; 3949 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; 3950 active->linetime = hw->wm_linetime[pipe]; 3951 } else { 3952 int level, max_level = ilk_wm_max_level(dev); 3953 3954 /* 3955 * For inactive pipes, all watermark levels 3956 * should be marked as enabled but zeroed, 3957 * which is what we'd compute them to. 3958 */ 3959 for (level = 0; level <= max_level; level++) 3960 active->wm[level].enable = true; 3961 } 3962 } 3963 3964 #define _FW_WM(value, plane) \ 3965 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) 3966 #define _FW_WM_VLV(value, plane) \ 3967 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) 3968 3969 static void vlv_read_wm_values(struct drm_i915_private *dev_priv, 3970 struct vlv_wm_values *wm) 3971 { 3972 enum i915_pipe pipe; 3973 uint32_t tmp; 3974 3975 for_each_pipe(dev_priv, pipe) { 3976 tmp = I915_READ(VLV_DDL(pipe)); 3977 3978 wm->ddl[pipe].primary = 3979 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3980 wm->ddl[pipe].cursor = 3981 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3982 wm->ddl[pipe].sprite[0] = 3983 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3984 wm->ddl[pipe].sprite[1] = 3985 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); 3986 } 3987 3988 tmp = I915_READ(DSPFW1); 3989 wm->sr.plane = _FW_WM(tmp, SR); 3990 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB); 3991 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB); 3992 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA); 3993 3994 tmp = I915_READ(DSPFW2); 3995 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB); 3996 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA); 3997 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA); 3998 3999 tmp = I915_READ(DSPFW3); 4000 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); 4001 4002 if (IS_CHERRYVIEW(dev_priv)) { 4003 tmp = I915_READ(DSPFW7_CHV); 4004 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 4005 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 4006 4007 tmp = I915_READ(DSPFW8_CHV); 4008 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF); 4009 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE); 4010 4011 tmp = I915_READ(DSPFW9_CHV); 4012 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC); 4013 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC); 4014 4015 tmp = I915_READ(DSPHOWM); 4016 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 4017 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8; 4018 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8; 4019 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8; 4020 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 4021 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 4022 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 4023 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 4024 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 4025 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 4026 } else { 4027 tmp = I915_READ(DSPFW7); 4028 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED); 4029 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC); 4030 4031 tmp = I915_READ(DSPHOWM); 4032 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; 4033 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8; 4034 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8; 4035 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8; 4036 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8; 4037 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8; 4038 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8; 4039 } 4040 } 4041 4042 #undef _FW_WM 4043 #undef _FW_WM_VLV 4044 4045 void vlv_wm_get_hw_state(struct drm_device *dev) 4046 { 4047 struct drm_i915_private *dev_priv = to_i915(dev); 4048 struct vlv_wm_values *wm = &dev_priv->wm.vlv; 4049 struct intel_plane *plane; 4050 enum i915_pipe pipe; 4051 u32 val; 4052 4053 vlv_read_wm_values(dev_priv, wm); 4054 4055 for_each_intel_plane(dev, plane) { 4056 switch (plane->base.type) { 4057 int sprite; 4058 case DRM_PLANE_TYPE_CURSOR: 4059 plane->wm.fifo_size = 63; 4060 break; 4061 case DRM_PLANE_TYPE_PRIMARY: 4062 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0); 4063 break; 4064 case DRM_PLANE_TYPE_OVERLAY: 4065 sprite = plane->plane; 4066 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1); 4067 break; 4068 } 4069 } 4070 4071 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; 4072 wm->level = VLV_WM_LEVEL_PM2; 4073 4074 if (IS_CHERRYVIEW(dev_priv)) { 4075 mutex_lock(&dev_priv->rps.hw_lock); 4076 4077 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); 4078 if (val & DSP_MAXFIFO_PM5_ENABLE) 4079 wm->level = VLV_WM_LEVEL_PM5; 4080 4081 /* 4082 * If DDR DVFS is disabled in the BIOS, Punit 4083 * will never ack the request. So if that happens 4084 * assume we don't have to enable/disable DDR DVFS 4085 * dynamically. To test that just set the REQ_ACK 4086 * bit to poke the Punit, but don't change the 4087 * HIGH/LOW bits so that we don't actually change 4088 * the current state. 4089 */ 4090 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4091 val |= FORCE_DDR_FREQ_REQ_ACK; 4092 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); 4093 4094 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & 4095 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { 4096 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " 4097 "assuming DDR DVFS is disabled\n"); 4098 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; 4099 } else { 4100 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); 4101 if ((val & FORCE_DDR_HIGH_FREQ) == 0) 4102 wm->level = VLV_WM_LEVEL_DDR_DVFS; 4103 } 4104 4105 mutex_unlock(&dev_priv->rps.hw_lock); 4106 } 4107 4108 for_each_pipe(dev_priv, pipe) 4109 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", 4110 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor, 4111 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]); 4112 4113 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", 4114 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); 4115 } 4116 4117 void ilk_wm_get_hw_state(struct drm_device *dev) 4118 { 4119 struct drm_i915_private *dev_priv = dev->dev_private; 4120 struct ilk_wm_values *hw = &dev_priv->wm.hw; 4121 struct drm_crtc *crtc; 4122 4123 for_each_crtc(dev, crtc) 4124 ilk_pipe_wm_get_hw_state(crtc); 4125 4126 hw->wm_lp[0] = I915_READ(WM1_LP_ILK); 4127 hw->wm_lp[1] = I915_READ(WM2_LP_ILK); 4128 hw->wm_lp[2] = I915_READ(WM3_LP_ILK); 4129 4130 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); 4131 if (INTEL_INFO(dev)->gen >= 7) { 4132 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); 4133 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); 4134 } 4135 4136 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4137 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? 4138 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4139 else if (IS_IVYBRIDGE(dev)) 4140 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? 4141 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; 4142 4143 hw->enable_fbc_wm = 4144 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); 4145 } 4146 4147 /** 4148 * intel_update_watermarks - update FIFO watermark values based on current modes 4149 * 4150 * Calculate watermark values for the various WM regs based on current mode 4151 * and plane configuration. 4152 * 4153 * There are several cases to deal with here: 4154 * - normal (i.e. non-self-refresh) 4155 * - self-refresh (SR) mode 4156 * - lines are large relative to FIFO size (buffer can hold up to 2) 4157 * - lines are small relative to FIFO size (buffer can hold more than 2 4158 * lines), so need to account for TLB latency 4159 * 4160 * The normal calculation is: 4161 * watermark = dotclock * bytes per pixel * latency 4162 * where latency is platform & configuration dependent (we assume pessimal 4163 * values here). 4164 * 4165 * The SR calculation is: 4166 * watermark = (trunc(latency/line time)+1) * surface width * 4167 * bytes per pixel 4168 * where 4169 * line time = htotal / dotclock 4170 * surface width = hdisplay for normal plane and 64 for cursor 4171 * and latency is assumed to be high, as above. 4172 * 4173 * The final value programmed to the register should always be rounded up, 4174 * and include an extra 2 entries to account for clock crossings. 4175 * 4176 * We don't use the sprite, so we can ignore that. And on Crestline we have 4177 * to set the non-SR watermarks to 8. 4178 */ 4179 void intel_update_watermarks(struct drm_crtc *crtc) 4180 { 4181 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 4182 4183 if (dev_priv->display.update_wm) 4184 dev_priv->display.update_wm(crtc); 4185 } 4186 4187 void intel_update_sprite_watermarks(struct drm_plane *plane, 4188 struct drm_crtc *crtc, 4189 uint32_t sprite_width, 4190 uint32_t sprite_height, 4191 int pixel_size, 4192 bool enabled, bool scaled) 4193 { 4194 struct drm_i915_private *dev_priv = plane->dev->dev_private; 4195 4196 if (dev_priv->display.update_sprite_wm) 4197 dev_priv->display.update_sprite_wm(plane, crtc, 4198 sprite_width, sprite_height, 4199 pixel_size, enabled, scaled); 4200 } 4201 4202 /** 4203 * Lock protecting IPS related data structures 4204 */ 4205 struct lock mchdev_lock; 4206 LOCK_SYSINIT(mchdev, &mchdev_lock, "mchdev", LK_CANRECURSE); 4207 4208 /* Global for IPS driver to get at the current i915 device. Protected by 4209 * mchdev_lock. */ 4210 static struct drm_i915_private *i915_mch_dev; 4211 4212 bool ironlake_set_drps(struct drm_device *dev, u8 val) 4213 { 4214 struct drm_i915_private *dev_priv = dev->dev_private; 4215 u16 rgvswctl; 4216 4217 assert_spin_locked(&mchdev_lock); 4218 4219 rgvswctl = I915_READ16(MEMSWCTL); 4220 if (rgvswctl & MEMCTL_CMD_STS) { 4221 DRM_DEBUG("gpu busy, RCS change rejected\n"); 4222 return false; /* still busy with another command */ 4223 } 4224 4225 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | 4226 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; 4227 I915_WRITE16(MEMSWCTL, rgvswctl); 4228 POSTING_READ16(MEMSWCTL); 4229 4230 rgvswctl |= MEMCTL_CMD_STS; 4231 I915_WRITE16(MEMSWCTL, rgvswctl); 4232 4233 return true; 4234 } 4235 4236 static void ironlake_enable_drps(struct drm_device *dev) 4237 { 4238 struct drm_i915_private *dev_priv = dev->dev_private; 4239 u32 rgvmodectl = I915_READ(MEMMODECTL); 4240 u8 fmax, fmin, fstart, vstart; 4241 4242 spin_lock_irq(&mchdev_lock); 4243 4244 /* Enable temp reporting */ 4245 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); 4246 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); 4247 4248 /* 100ms RC evaluation intervals */ 4249 I915_WRITE(RCUPEI, 100000); 4250 I915_WRITE(RCDNEI, 100000); 4251 4252 /* Set max/min thresholds to 90ms and 80ms respectively */ 4253 I915_WRITE(RCBMAXAVG, 90000); 4254 I915_WRITE(RCBMINAVG, 80000); 4255 4256 I915_WRITE(MEMIHYST, 1); 4257 4258 /* Set up min, max, and cur for interrupt handling */ 4259 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; 4260 fmin = (rgvmodectl & MEMMODE_FMIN_MASK); 4261 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> 4262 MEMMODE_FSTART_SHIFT; 4263 4264 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> 4265 PXVFREQ_PX_SHIFT; 4266 4267 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ 4268 dev_priv->ips.fstart = fstart; 4269 4270 dev_priv->ips.max_delay = fstart; 4271 dev_priv->ips.min_delay = fmin; 4272 dev_priv->ips.cur_delay = fstart; 4273 4274 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", 4275 fmax, fmin, fstart); 4276 4277 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); 4278 4279 /* 4280 * Interrupts will be enabled in ironlake_irq_postinstall 4281 */ 4282 4283 I915_WRITE(VIDSTART, vstart); 4284 POSTING_READ(VIDSTART); 4285 4286 rgvmodectl |= MEMMODE_SWMODE_EN; 4287 I915_WRITE(MEMMODECTL, rgvmodectl); 4288 4289 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) 4290 DRM_ERROR("stuck trying to change perf mode\n"); 4291 mdelay(1); 4292 4293 ironlake_set_drps(dev, fstart); 4294 4295 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + 4296 I915_READ(0x112e0); 4297 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); 4298 dev_priv->ips.last_count2 = I915_READ(0x112f4); 4299 dev_priv->ips.last_time2 = ktime_get_raw_ns(); 4300 4301 spin_unlock_irq(&mchdev_lock); 4302 } 4303 4304 static void ironlake_disable_drps(struct drm_device *dev) 4305 { 4306 struct drm_i915_private *dev_priv = dev->dev_private; 4307 u16 rgvswctl; 4308 4309 spin_lock_irq(&mchdev_lock); 4310 4311 rgvswctl = I915_READ16(MEMSWCTL); 4312 4313 /* Ack interrupts, disable EFC interrupt */ 4314 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); 4315 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); 4316 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); 4317 I915_WRITE(DEIIR, DE_PCU_EVENT); 4318 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); 4319 4320 /* Go back to the starting frequency */ 4321 ironlake_set_drps(dev, dev_priv->ips.fstart); 4322 mdelay(1); 4323 rgvswctl |= MEMCTL_CMD_STS; 4324 I915_WRITE(MEMSWCTL, rgvswctl); 4325 mdelay(1); 4326 4327 spin_unlock_irq(&mchdev_lock); 4328 } 4329 4330 /* There's a funny hw issue where the hw returns all 0 when reading from 4331 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value 4332 * ourselves, instead of doing a rmw cycle (which might result in us clearing 4333 * all limits and the gpu stuck at whatever frequency it is at atm). 4334 */ 4335 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) 4336 { 4337 u32 limits; 4338 4339 /* Only set the down limit when we've reached the lowest level to avoid 4340 * getting more interrupts, otherwise leave this clear. This prevents a 4341 * race in the hw when coming out of rc6: There's a tiny window where 4342 * the hw runs at the minimal clock before selecting the desired 4343 * frequency, if the down threshold expires in that window we will not 4344 * receive a down interrupt. */ 4345 if (IS_GEN9(dev_priv->dev)) { 4346 limits = (dev_priv->rps.max_freq_softlimit) << 23; 4347 if (val <= dev_priv->rps.min_freq_softlimit) 4348 limits |= (dev_priv->rps.min_freq_softlimit) << 14; 4349 } else { 4350 limits = dev_priv->rps.max_freq_softlimit << 24; 4351 if (val <= dev_priv->rps.min_freq_softlimit) 4352 limits |= dev_priv->rps.min_freq_softlimit << 16; 4353 } 4354 4355 return limits; 4356 } 4357 4358 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) 4359 { 4360 int new_power; 4361 u32 threshold_up = 0, threshold_down = 0; /* in % */ 4362 u32 ei_up = 0, ei_down = 0; 4363 4364 new_power = dev_priv->rps.power; 4365 switch (dev_priv->rps.power) { 4366 case LOW_POWER: 4367 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) 4368 new_power = BETWEEN; 4369 break; 4370 4371 case BETWEEN: 4372 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) 4373 new_power = LOW_POWER; 4374 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) 4375 new_power = HIGH_POWER; 4376 break; 4377 4378 case HIGH_POWER: 4379 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) 4380 new_power = BETWEEN; 4381 break; 4382 } 4383 /* Max/min bins are special */ 4384 if (val <= dev_priv->rps.min_freq_softlimit) 4385 new_power = LOW_POWER; 4386 if (val >= dev_priv->rps.max_freq_softlimit) 4387 new_power = HIGH_POWER; 4388 if (new_power == dev_priv->rps.power) 4389 return; 4390 4391 /* Note the units here are not exactly 1us, but 1280ns. */ 4392 switch (new_power) { 4393 case LOW_POWER: 4394 /* Upclock if more than 95% busy over 16ms */ 4395 ei_up = 16000; 4396 threshold_up = 95; 4397 4398 /* Downclock if less than 85% busy over 32ms */ 4399 ei_down = 32000; 4400 threshold_down = 85; 4401 break; 4402 4403 case BETWEEN: 4404 /* Upclock if more than 90% busy over 13ms */ 4405 ei_up = 13000; 4406 threshold_up = 90; 4407 4408 /* Downclock if less than 75% busy over 32ms */ 4409 ei_down = 32000; 4410 threshold_down = 75; 4411 break; 4412 4413 case HIGH_POWER: 4414 /* Upclock if more than 85% busy over 10ms */ 4415 ei_up = 10000; 4416 threshold_up = 85; 4417 4418 /* Downclock if less than 60% busy over 32ms */ 4419 ei_down = 32000; 4420 threshold_down = 60; 4421 break; 4422 } 4423 4424 I915_WRITE(GEN6_RP_UP_EI, 4425 GT_INTERVAL_FROM_US(dev_priv, ei_up)); 4426 I915_WRITE(GEN6_RP_UP_THRESHOLD, 4427 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100))); 4428 4429 I915_WRITE(GEN6_RP_DOWN_EI, 4430 GT_INTERVAL_FROM_US(dev_priv, ei_down)); 4431 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 4432 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100))); 4433 4434 I915_WRITE(GEN6_RP_CONTROL, 4435 GEN6_RP_MEDIA_TURBO | 4436 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4437 GEN6_RP_MEDIA_IS_GFX | 4438 GEN6_RP_ENABLE | 4439 GEN6_RP_UP_BUSY_AVG | 4440 GEN6_RP_DOWN_IDLE_AVG); 4441 4442 dev_priv->rps.power = new_power; 4443 dev_priv->rps.up_threshold = threshold_up; 4444 dev_priv->rps.down_threshold = threshold_down; 4445 dev_priv->rps.last_adj = 0; 4446 } 4447 4448 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) 4449 { 4450 u32 mask = 0; 4451 4452 if (val > dev_priv->rps.min_freq_softlimit) 4453 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; 4454 if (val < dev_priv->rps.max_freq_softlimit) 4455 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; 4456 4457 mask &= dev_priv->pm_rps_events; 4458 4459 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); 4460 } 4461 4462 /* gen6_set_rps is called to update the frequency request, but should also be 4463 * called when the range (min_delay and max_delay) is modified so that we can 4464 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ 4465 static void gen6_set_rps(struct drm_device *dev, u8 val) 4466 { 4467 struct drm_i915_private *dev_priv = dev->dev_private; 4468 4469 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4470 WARN_ON(val > dev_priv->rps.max_freq); 4471 WARN_ON(val < dev_priv->rps.min_freq); 4472 4473 /* min/max delay may still have been modified so be sure to 4474 * write the limits value. 4475 */ 4476 if (val != dev_priv->rps.cur_freq) { 4477 gen6_set_rps_thresholds(dev_priv, val); 4478 4479 if (IS_GEN9(dev)) 4480 I915_WRITE(GEN6_RPNSWREQ, 4481 GEN9_FREQUENCY(val)); 4482 else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4483 I915_WRITE(GEN6_RPNSWREQ, 4484 HSW_FREQUENCY(val)); 4485 else 4486 I915_WRITE(GEN6_RPNSWREQ, 4487 GEN6_FREQUENCY(val) | 4488 GEN6_OFFSET(0) | 4489 GEN6_AGGRESSIVE_TURBO); 4490 } 4491 4492 /* Make sure we continue to get interrupts 4493 * until we hit the minimum or maximum frequencies. 4494 */ 4495 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); 4496 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4497 4498 POSTING_READ(GEN6_RPNSWREQ); 4499 4500 dev_priv->rps.cur_freq = val; 4501 trace_intel_gpu_freq_change(val * 50); 4502 } 4503 4504 static void valleyview_set_rps(struct drm_device *dev, u8 val) 4505 { 4506 struct drm_i915_private *dev_priv = dev->dev_private; 4507 4508 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4509 WARN_ON(val > dev_priv->rps.max_freq); 4510 WARN_ON(val < dev_priv->rps.min_freq); 4511 4512 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), 4513 "Odd GPU freq value\n")) 4514 val &= ~1; 4515 4516 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); 4517 4518 if (val != dev_priv->rps.cur_freq) { 4519 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); 4520 if (!IS_CHERRYVIEW(dev_priv)) 4521 gen6_set_rps_thresholds(dev_priv, val); 4522 } 4523 4524 dev_priv->rps.cur_freq = val; 4525 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); 4526 } 4527 4528 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down 4529 * 4530 * * If Gfx is Idle, then 4531 * 1. Forcewake Media well. 4532 * 2. Request idle freq. 4533 * 3. Release Forcewake of Media well. 4534 */ 4535 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) 4536 { 4537 u32 val = dev_priv->rps.idle_freq; 4538 4539 if (dev_priv->rps.cur_freq <= val) 4540 return; 4541 4542 /* Wake up the media well, as that takes a lot less 4543 * power than the Render well. */ 4544 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); 4545 valleyview_set_rps(dev_priv->dev, val); 4546 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); 4547 } 4548 4549 void gen6_rps_busy(struct drm_i915_private *dev_priv) 4550 { 4551 mutex_lock(&dev_priv->rps.hw_lock); 4552 if (dev_priv->rps.enabled) { 4553 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) 4554 gen6_rps_reset_ei(dev_priv); 4555 I915_WRITE(GEN6_PMINTRMSK, 4556 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); 4557 } 4558 mutex_unlock(&dev_priv->rps.hw_lock); 4559 } 4560 4561 void gen6_rps_idle(struct drm_i915_private *dev_priv) 4562 { 4563 struct drm_device *dev = dev_priv->dev; 4564 4565 mutex_lock(&dev_priv->rps.hw_lock); 4566 if (dev_priv->rps.enabled) { 4567 if (IS_VALLEYVIEW(dev)) 4568 vlv_set_rps_idle(dev_priv); 4569 else 4570 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4571 dev_priv->rps.last_adj = 0; 4572 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); 4573 } 4574 mutex_unlock(&dev_priv->rps.hw_lock); 4575 4576 lockmgr(&dev_priv->rps.client_lock, LK_EXCLUSIVE); 4577 while (!list_empty(&dev_priv->rps.clients)) 4578 list_del_init(dev_priv->rps.clients.next); 4579 lockmgr(&dev_priv->rps.client_lock, LK_RELEASE); 4580 } 4581 4582 void gen6_rps_boost(struct drm_i915_private *dev_priv, 4583 struct intel_rps_client *rps, 4584 unsigned long submitted) 4585 { 4586 /* This is intentionally racy! We peek at the state here, then 4587 * validate inside the RPS worker. 4588 */ 4589 if (!(dev_priv->mm.busy && 4590 dev_priv->rps.enabled && 4591 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)) 4592 return; 4593 4594 /* Force a RPS boost (and don't count it against the client) if 4595 * the GPU is severely congested. 4596 */ 4597 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) 4598 rps = NULL; 4599 4600 lockmgr(&dev_priv->rps.client_lock, LK_EXCLUSIVE); 4601 if (rps == NULL || list_empty(&rps->link)) { 4602 spin_lock_irq(&dev_priv->irq_lock); 4603 if (dev_priv->rps.interrupts_enabled) { 4604 dev_priv->rps.client_boost = true; 4605 queue_work(dev_priv->wq, &dev_priv->rps.work); 4606 } 4607 spin_unlock_irq(&dev_priv->irq_lock); 4608 4609 if (rps != NULL) { 4610 list_add(&rps->link, &dev_priv->rps.clients); 4611 rps->boosts++; 4612 } else 4613 dev_priv->rps.boosts++; 4614 } 4615 lockmgr(&dev_priv->rps.client_lock, LK_RELEASE); 4616 } 4617 4618 void intel_set_rps(struct drm_device *dev, u8 val) 4619 { 4620 if (IS_VALLEYVIEW(dev)) 4621 valleyview_set_rps(dev, val); 4622 else 4623 gen6_set_rps(dev, val); 4624 } 4625 4626 static void gen9_disable_rps(struct drm_device *dev) 4627 { 4628 struct drm_i915_private *dev_priv = dev->dev_private; 4629 4630 I915_WRITE(GEN6_RC_CONTROL, 0); 4631 I915_WRITE(GEN9_PG_ENABLE, 0); 4632 } 4633 4634 static void gen6_disable_rps(struct drm_device *dev) 4635 { 4636 struct drm_i915_private *dev_priv = dev->dev_private; 4637 4638 I915_WRITE(GEN6_RC_CONTROL, 0); 4639 I915_WRITE(GEN6_RPNSWREQ, 1 << 31); 4640 } 4641 4642 static void cherryview_disable_rps(struct drm_device *dev) 4643 { 4644 struct drm_i915_private *dev_priv = dev->dev_private; 4645 4646 I915_WRITE(GEN6_RC_CONTROL, 0); 4647 } 4648 4649 static void valleyview_disable_rps(struct drm_device *dev) 4650 { 4651 struct drm_i915_private *dev_priv = dev->dev_private; 4652 4653 /* we're doing forcewake before Disabling RC6, 4654 * This what the BIOS expects when going into suspend */ 4655 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4656 4657 I915_WRITE(GEN6_RC_CONTROL, 0); 4658 4659 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4660 } 4661 4662 static void intel_print_rc6_info(struct drm_device *dev, u32 mode) 4663 { 4664 if (IS_VALLEYVIEW(dev)) { 4665 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) 4666 mode = GEN6_RC_CTL_RC6_ENABLE; 4667 else 4668 mode = 0; 4669 } 4670 if (HAS_RC6p(dev)) 4671 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", 4672 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", 4673 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", 4674 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); 4675 4676 else 4677 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", 4678 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); 4679 } 4680 4681 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) 4682 { 4683 /* No RC6 before Ironlake and code is gone for ilk. */ 4684 if (INTEL_INFO(dev)->gen < 6) 4685 return 0; 4686 4687 /* Respect the kernel parameter if it is set */ 4688 if (enable_rc6 >= 0) { 4689 int mask; 4690 4691 if (HAS_RC6p(dev)) 4692 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | 4693 INTEL_RC6pp_ENABLE; 4694 else 4695 mask = INTEL_RC6_ENABLE; 4696 4697 if ((enable_rc6 & mask) != enable_rc6) 4698 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", 4699 enable_rc6 & mask, enable_rc6, mask); 4700 4701 return enable_rc6 & mask; 4702 } 4703 4704 if (IS_IVYBRIDGE(dev)) 4705 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); 4706 4707 return INTEL_RC6_ENABLE; 4708 } 4709 4710 int intel_enable_rc6(const struct drm_device *dev) 4711 { 4712 return i915.enable_rc6; 4713 } 4714 4715 static void gen6_init_rps_frequencies(struct drm_device *dev) 4716 { 4717 struct drm_i915_private *dev_priv = dev->dev_private; 4718 uint32_t rp_state_cap; 4719 u32 ddcc_status = 0; 4720 int ret; 4721 4722 /* All of these values are in units of 50MHz */ 4723 dev_priv->rps.cur_freq = 0; 4724 /* static values from HW: RP0 > RP1 > RPn (min_freq) */ 4725 if (IS_BROXTON(dev)) { 4726 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); 4727 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; 4728 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4729 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; 4730 } else { 4731 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 4732 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; 4733 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; 4734 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; 4735 } 4736 4737 /* hw_max = RP0 until we check for overclocking */ 4738 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; 4739 4740 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; 4741 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) { 4742 ret = sandybridge_pcode_read(dev_priv, 4743 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, 4744 &ddcc_status); 4745 if (0 == ret) 4746 dev_priv->rps.efficient_freq = 4747 clamp_t(u8, 4748 ((ddcc_status >> 8) & 0xff), 4749 dev_priv->rps.min_freq, 4750 dev_priv->rps.max_freq); 4751 } 4752 4753 if (IS_SKYLAKE(dev)) { 4754 /* Store the frequency values in 16.66 MHZ units, which is 4755 the natural hardware unit for SKL */ 4756 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; 4757 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; 4758 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; 4759 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; 4760 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; 4761 } 4762 4763 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 4764 4765 /* Preserve min/max settings in case of re-init */ 4766 if (dev_priv->rps.max_freq_softlimit == 0) 4767 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 4768 4769 if (dev_priv->rps.min_freq_softlimit == 0) { 4770 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 4771 dev_priv->rps.min_freq_softlimit = 4772 max_t(int, dev_priv->rps.efficient_freq, 4773 intel_freq_opcode(dev_priv, 450)); 4774 else 4775 dev_priv->rps.min_freq_softlimit = 4776 dev_priv->rps.min_freq; 4777 } 4778 } 4779 4780 /* See the Gen9_GT_PM_Programming_Guide doc for the below */ 4781 static void gen9_enable_rps(struct drm_device *dev) 4782 { 4783 struct drm_i915_private *dev_priv = dev->dev_private; 4784 4785 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4786 4787 gen6_init_rps_frequencies(dev); 4788 4789 /* Program defaults and thresholds for RPS*/ 4790 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4791 GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); 4792 4793 /* 1 second timeout*/ 4794 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 4795 GT_INTERVAL_FROM_US(dev_priv, 1000000)); 4796 4797 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); 4798 4799 /* Leaning on the below call to gen6_set_rps to program/setup the 4800 * Up/Down EI & threshold registers, as well as the RP_CONTROL, 4801 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ 4802 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4803 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); 4804 4805 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4806 } 4807 4808 static void gen9_enable_rc6(struct drm_device *dev) 4809 { 4810 struct drm_i915_private *dev_priv = dev->dev_private; 4811 struct intel_engine_cs *ring; 4812 uint32_t rc6_mask = 0; 4813 int unused; 4814 4815 /* 1a: Software RC state - RC0 */ 4816 I915_WRITE(GEN6_RC_STATE, 0); 4817 4818 /* 1b: Get forcewake during program sequence. Although the driver 4819 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4820 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4821 4822 /* 2a: Disable RC states. */ 4823 I915_WRITE(GEN6_RC_CONTROL, 0); 4824 4825 /* 2b: Program RC6 thresholds.*/ 4826 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 4827 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4828 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4829 for_each_ring(ring, dev_priv, unused) 4830 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4831 I915_WRITE(GEN6_RC_SLEEP, 0); 4832 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ 4833 4834 /* 2c: Program Coarse Power Gating Policies. */ 4835 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); 4836 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); 4837 4838 /* 3a: Enable RC6 */ 4839 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4840 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4841 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4842 "on" : "off"); 4843 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4844 GEN6_RC_CTL_EI_MODE(1) | 4845 rc6_mask); 4846 4847 /* 4848 * 3b: Enable Coarse Power Gating only when RC6 is enabled. 4849 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6. 4850 */ 4851 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4852 GEN9_MEDIA_PG_ENABLE : 0); 4853 4854 4855 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4856 4857 } 4858 4859 static void gen8_enable_rps(struct drm_device *dev) 4860 { 4861 struct drm_i915_private *dev_priv = dev->dev_private; 4862 struct intel_engine_cs *ring; 4863 uint32_t rc6_mask = 0; 4864 int unused; 4865 4866 /* 1a: Software RC state - RC0 */ 4867 I915_WRITE(GEN6_RC_STATE, 0); 4868 4869 /* 1c & 1d: Get forcewake during program sequence. Although the driver 4870 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 4871 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4872 4873 /* 2a: Disable RC states. */ 4874 I915_WRITE(GEN6_RC_CONTROL, 0); 4875 4876 /* Initialize rps frequencies */ 4877 gen6_init_rps_frequencies(dev); 4878 4879 /* 2b: Program RC6 thresholds.*/ 4880 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 4881 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 4882 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 4883 for_each_ring(ring, dev_priv, unused) 4884 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4885 I915_WRITE(GEN6_RC_SLEEP, 0); 4886 if (IS_BROADWELL(dev)) 4887 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ 4888 else 4889 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ 4890 4891 /* 3: Enable RC6 */ 4892 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4893 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 4894 intel_print_rc6_info(dev, rc6_mask); 4895 if (IS_BROADWELL(dev)) 4896 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4897 GEN7_RC_CTL_TO_MODE | 4898 rc6_mask); 4899 else 4900 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 4901 GEN6_RC_CTL_EI_MODE(1) | 4902 rc6_mask); 4903 4904 /* 4 Program defaults and thresholds for RPS*/ 4905 I915_WRITE(GEN6_RPNSWREQ, 4906 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4907 I915_WRITE(GEN6_RC_VIDEO_FREQ, 4908 HSW_FREQUENCY(dev_priv->rps.rp1_freq)); 4909 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ 4910 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ 4911 4912 /* Docs recommend 900MHz, and 300 MHz respectively */ 4913 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 4914 dev_priv->rps.max_freq_softlimit << 24 | 4915 dev_priv->rps.min_freq_softlimit << 16); 4916 4917 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ 4918 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ 4919 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ 4920 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ 4921 4922 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 4923 4924 /* 5: Enable RPS */ 4925 I915_WRITE(GEN6_RP_CONTROL, 4926 GEN6_RP_MEDIA_TURBO | 4927 GEN6_RP_MEDIA_HW_NORMAL_MODE | 4928 GEN6_RP_MEDIA_IS_GFX | 4929 GEN6_RP_ENABLE | 4930 GEN6_RP_UP_BUSY_AVG | 4931 GEN6_RP_DOWN_IDLE_AVG); 4932 4933 /* 6: Ring frequency + overclocking (our driver does this later */ 4934 4935 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 4936 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 4937 4938 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 4939 } 4940 4941 static void gen6_enable_rps(struct drm_device *dev) 4942 { 4943 struct drm_i915_private *dev_priv = dev->dev_private; 4944 struct intel_engine_cs *ring; 4945 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; 4946 u32 gtfifodbg; 4947 int rc6_mode; 4948 int i, ret; 4949 4950 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 4951 4952 /* Here begins a magic sequence of register writes to enable 4953 * auto-downclocking. 4954 * 4955 * Perhaps there might be some value in exposing these to 4956 * userspace... 4957 */ 4958 I915_WRITE(GEN6_RC_STATE, 0); 4959 4960 /* Clear the DBG now so we don't confuse earlier errors */ 4961 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 4962 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); 4963 I915_WRITE(GTFIFODBG, gtfifodbg); 4964 } 4965 4966 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 4967 4968 /* Initialize rps frequencies */ 4969 gen6_init_rps_frequencies(dev); 4970 4971 /* disable the counters and set deterministic thresholds */ 4972 I915_WRITE(GEN6_RC_CONTROL, 0); 4973 4974 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); 4975 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); 4976 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); 4977 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 4978 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 4979 4980 for_each_ring(ring, dev_priv, i) 4981 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4982 4983 I915_WRITE(GEN6_RC_SLEEP, 0); 4984 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); 4985 if (IS_IVYBRIDGE(dev)) 4986 I915_WRITE(GEN6_RC6_THRESHOLD, 125000); 4987 else 4988 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); 4989 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); 4990 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ 4991 4992 /* Check if we are enabling RC6 */ 4993 rc6_mode = intel_enable_rc6(dev_priv->dev); 4994 if (rc6_mode & INTEL_RC6_ENABLE) 4995 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; 4996 4997 /* We don't use those on Haswell */ 4998 if (!IS_HASWELL(dev)) { 4999 if (rc6_mode & INTEL_RC6p_ENABLE) 5000 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; 5001 5002 if (rc6_mode & INTEL_RC6pp_ENABLE) 5003 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; 5004 } 5005 5006 intel_print_rc6_info(dev, rc6_mask); 5007 5008 I915_WRITE(GEN6_RC_CONTROL, 5009 rc6_mask | 5010 GEN6_RC_CTL_EI_MODE(1) | 5011 GEN6_RC_CTL_HW_ENABLE); 5012 5013 /* Power down if completely idle for over 50ms */ 5014 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); 5015 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5016 5017 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); 5018 if (ret) 5019 DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); 5020 5021 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); 5022 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ 5023 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", 5024 (dev_priv->rps.max_freq_softlimit & 0xff) * 50, 5025 (pcu_mbox & 0xff) * 50); 5026 dev_priv->rps.max_freq = pcu_mbox & 0xff; 5027 } 5028 5029 dev_priv->rps.power = HIGH_POWER; /* force a reset */ 5030 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq); 5031 5032 rc6vids = 0; 5033 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); 5034 if (IS_GEN6(dev) && ret) { 5035 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); 5036 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { 5037 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", 5038 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); 5039 rc6vids &= 0xffff00; 5040 rc6vids |= GEN6_ENCODE_RC6_VID(450); 5041 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); 5042 if (ret) 5043 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 5044 } 5045 5046 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5047 } 5048 5049 static void __gen6_update_ring_freq(struct drm_device *dev) 5050 { 5051 struct drm_i915_private *dev_priv = dev->dev_private; 5052 int min_freq = 15; 5053 unsigned int gpu_freq; 5054 unsigned int max_ia_freq, min_ring_freq; 5055 unsigned int max_gpu_freq, min_gpu_freq; 5056 int scaling_factor = 180; 5057 5058 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5059 5060 #if 0 5061 policy = cpufreq_cpu_get(0); 5062 if (policy) { 5063 max_ia_freq = policy->cpuinfo.max_freq; 5064 cpufreq_cpu_put(policy); 5065 } else { 5066 /* 5067 * Default to measured freq if none found, PCU will ensure we 5068 * don't go over 5069 */ 5070 max_ia_freq = tsc_khz; 5071 } 5072 #else 5073 max_ia_freq = tsc_frequency / 1000; 5074 #endif 5075 5076 /* Convert from kHz to MHz */ 5077 max_ia_freq /= 1000; 5078 5079 min_ring_freq = I915_READ(DCLK) & 0xf; 5080 /* convert DDR frequency from units of 266.6MHz to bandwidth */ 5081 min_ring_freq = mult_frac(min_ring_freq, 8, 3); 5082 5083 if (IS_SKYLAKE(dev)) { 5084 /* Convert GT frequency to 50 HZ units */ 5085 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; 5086 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; 5087 } else { 5088 min_gpu_freq = dev_priv->rps.min_freq; 5089 max_gpu_freq = dev_priv->rps.max_freq; 5090 } 5091 5092 /* 5093 * For each potential GPU frequency, load a ring frequency we'd like 5094 * to use for memory access. We do this by specifying the IA frequency 5095 * the PCU should use as a reference to determine the ring frequency. 5096 */ 5097 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { 5098 int diff = max_gpu_freq - gpu_freq; 5099 unsigned int ia_freq = 0, ring_freq = 0; 5100 5101 if (IS_SKYLAKE(dev)) { 5102 /* 5103 * ring_freq = 2 * GT. ring_freq is in 100MHz units 5104 * No floor required for ring frequency on SKL. 5105 */ 5106 ring_freq = gpu_freq; 5107 } else if (INTEL_INFO(dev)->gen >= 8) { 5108 /* max(2 * GT, DDR). NB: GT is 50MHz units */ 5109 ring_freq = max(min_ring_freq, gpu_freq); 5110 } else if (IS_HASWELL(dev)) { 5111 ring_freq = mult_frac(gpu_freq, 5, 4); 5112 ring_freq = max(min_ring_freq, ring_freq); 5113 /* leave ia_freq as the default, chosen by cpufreq */ 5114 } else { 5115 /* On older processors, there is no separate ring 5116 * clock domain, so in order to boost the bandwidth 5117 * of the ring, we need to upclock the CPU (ia_freq). 5118 * 5119 * For GPU frequencies less than 750MHz, 5120 * just use the lowest ring freq. 5121 */ 5122 if (gpu_freq < min_freq) 5123 ia_freq = 800; 5124 else 5125 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); 5126 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); 5127 } 5128 5129 sandybridge_pcode_write(dev_priv, 5130 GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 5131 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | 5132 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | 5133 gpu_freq); 5134 } 5135 } 5136 5137 void gen6_update_ring_freq(struct drm_device *dev) 5138 { 5139 struct drm_i915_private *dev_priv = dev->dev_private; 5140 5141 if (!HAS_CORE_RING_FREQ(dev)) 5142 return; 5143 5144 mutex_lock(&dev_priv->rps.hw_lock); 5145 __gen6_update_ring_freq(dev); 5146 mutex_unlock(&dev_priv->rps.hw_lock); 5147 } 5148 5149 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) 5150 { 5151 struct drm_device *dev = dev_priv->dev; 5152 u32 val, rp0; 5153 5154 if (dev->pdev->revision >= 0x20) { 5155 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5156 5157 switch (INTEL_INFO(dev)->eu_total) { 5158 case 8: 5159 /* (2 * 4) config */ 5160 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); 5161 break; 5162 case 12: 5163 /* (2 * 6) config */ 5164 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); 5165 break; 5166 case 16: 5167 /* (2 * 8) config */ 5168 default: 5169 /* Setting (2 * 8) Min RP0 for any other combination */ 5170 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); 5171 break; 5172 } 5173 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); 5174 } else { 5175 /* For pre-production hardware */ 5176 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); 5177 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & 5178 PUNIT_GPU_STATUS_MAX_FREQ_MASK; 5179 } 5180 return rp0; 5181 } 5182 5183 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5184 { 5185 u32 val, rpe; 5186 5187 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); 5188 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; 5189 5190 return rpe; 5191 } 5192 5193 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) 5194 { 5195 struct drm_device *dev = dev_priv->dev; 5196 u32 val, rp1; 5197 5198 if (dev->pdev->revision >= 0x20) { 5199 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); 5200 rp1 = (val & FB_GFX_FREQ_FUSE_MASK); 5201 } else { 5202 /* For pre-production hardware */ 5203 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5204 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & 5205 PUNIT_GPU_STATUS_MAX_FREQ_MASK); 5206 } 5207 return rp1; 5208 } 5209 5210 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) 5211 { 5212 u32 val, rp1; 5213 5214 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5215 5216 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; 5217 5218 return rp1; 5219 } 5220 5221 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) 5222 { 5223 u32 val, rp0; 5224 5225 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); 5226 5227 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; 5228 /* Clamp to max */ 5229 rp0 = min_t(u32, rp0, 0xea); 5230 5231 return rp0; 5232 } 5233 5234 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) 5235 { 5236 u32 val, rpe; 5237 5238 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); 5239 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; 5240 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); 5241 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; 5242 5243 return rpe; 5244 } 5245 5246 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) 5247 { 5248 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; 5249 } 5250 5251 /* Check that the pctx buffer wasn't move under us. */ 5252 static void valleyview_check_pctx(struct drm_i915_private *dev_priv) 5253 { 5254 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5255 5256 /* DragonFly - if EDID fails vlv_pctx can wind up NULL */ 5257 if (WARN_ON(!dev_priv->vlv_pctx)) 5258 return; 5259 5260 WARN_ON(pctx_addr != dev_priv->mm.stolen_base + 5261 dev_priv->vlv_pctx->stolen->start); 5262 } 5263 5264 5265 /* Check that the pcbr address is not empty. */ 5266 static void cherryview_check_pctx(struct drm_i915_private *dev_priv) 5267 { 5268 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; 5269 5270 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); 5271 } 5272 5273 static void cherryview_setup_pctx(struct drm_device *dev) 5274 { 5275 struct drm_i915_private *dev_priv = dev->dev_private; 5276 unsigned long pctx_paddr, paddr; 5277 struct i915_gtt *gtt = &dev_priv->gtt; 5278 u32 pcbr; 5279 int pctx_size = 32*1024; 5280 5281 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5282 5283 pcbr = I915_READ(VLV_PCBR); 5284 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { 5285 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5286 paddr = (dev_priv->mm.stolen_base + 5287 (gtt->stolen_size - pctx_size)); 5288 5289 pctx_paddr = (paddr & (~4095)); 5290 I915_WRITE(VLV_PCBR, pctx_paddr); 5291 } 5292 5293 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5294 } 5295 5296 static void valleyview_setup_pctx(struct drm_device *dev) 5297 { 5298 struct drm_i915_private *dev_priv = dev->dev_private; 5299 struct drm_i915_gem_object *pctx; 5300 unsigned long pctx_paddr; 5301 u32 pcbr; 5302 int pctx_size = 24*1024; 5303 5304 WARN_ON(!mutex_is_locked(&dev->struct_mutex)); 5305 5306 pcbr = I915_READ(VLV_PCBR); 5307 if (pcbr) { 5308 /* BIOS set it up already, grab the pre-alloc'd space */ 5309 int pcbr_offset; 5310 5311 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; 5312 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, 5313 pcbr_offset, 5314 I915_GTT_OFFSET_NONE, 5315 pctx_size); 5316 goto out; 5317 } 5318 5319 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); 5320 5321 /* 5322 * From the Gunit register HAS: 5323 * The Gfx driver is expected to program this register and ensure 5324 * proper allocation within Gfx stolen memory. For example, this 5325 * register should be programmed such than the PCBR range does not 5326 * overlap with other ranges, such as the frame buffer, protected 5327 * memory, or any other relevant ranges. 5328 */ 5329 pctx = i915_gem_object_create_stolen(dev, pctx_size); 5330 if (!pctx) { 5331 DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); 5332 return; 5333 } 5334 5335 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; 5336 I915_WRITE(VLV_PCBR, pctx_paddr); 5337 5338 out: 5339 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); 5340 dev_priv->vlv_pctx = pctx; 5341 } 5342 5343 static void valleyview_cleanup_pctx(struct drm_device *dev) 5344 { 5345 struct drm_i915_private *dev_priv = dev->dev_private; 5346 5347 if (WARN_ON(!dev_priv->vlv_pctx)) 5348 return; 5349 5350 drm_gem_object_unreference(&dev_priv->vlv_pctx->base); 5351 dev_priv->vlv_pctx = NULL; 5352 } 5353 5354 static void valleyview_init_gt_powersave(struct drm_device *dev) 5355 { 5356 struct drm_i915_private *dev_priv = dev->dev_private; 5357 u32 val; 5358 5359 valleyview_setup_pctx(dev); 5360 5361 mutex_lock(&dev_priv->rps.hw_lock); 5362 5363 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5364 switch ((val >> 6) & 3) { 5365 case 0: 5366 case 1: 5367 dev_priv->mem_freq = 800; 5368 break; 5369 case 2: 5370 dev_priv->mem_freq = 1066; 5371 break; 5372 case 3: 5373 dev_priv->mem_freq = 1333; 5374 break; 5375 } 5376 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5377 5378 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); 5379 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5380 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5381 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5382 dev_priv->rps.max_freq); 5383 5384 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); 5385 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5386 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5387 dev_priv->rps.efficient_freq); 5388 5389 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); 5390 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", 5391 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5392 dev_priv->rps.rp1_freq); 5393 5394 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); 5395 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5396 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5397 dev_priv->rps.min_freq); 5398 5399 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5400 5401 /* Preserve min/max settings in case of re-init */ 5402 if (dev_priv->rps.max_freq_softlimit == 0) 5403 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5404 5405 if (dev_priv->rps.min_freq_softlimit == 0) 5406 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5407 5408 mutex_unlock(&dev_priv->rps.hw_lock); 5409 } 5410 5411 static void cherryview_init_gt_powersave(struct drm_device *dev) 5412 { 5413 struct drm_i915_private *dev_priv = dev->dev_private; 5414 u32 val; 5415 5416 cherryview_setup_pctx(dev); 5417 5418 mutex_lock(&dev_priv->rps.hw_lock); 5419 5420 mutex_lock(&dev_priv->sb_lock); 5421 val = vlv_cck_read(dev_priv, CCK_FUSE_REG); 5422 mutex_unlock(&dev_priv->sb_lock); 5423 5424 switch ((val >> 2) & 0x7) { 5425 case 0: 5426 case 1: 5427 dev_priv->rps.cz_freq = 200; 5428 dev_priv->mem_freq = 1600; 5429 break; 5430 case 2: 5431 dev_priv->rps.cz_freq = 267; 5432 dev_priv->mem_freq = 1600; 5433 break; 5434 case 3: 5435 dev_priv->rps.cz_freq = 333; 5436 dev_priv->mem_freq = 2000; 5437 break; 5438 case 4: 5439 dev_priv->rps.cz_freq = 320; 5440 dev_priv->mem_freq = 1600; 5441 break; 5442 case 5: 5443 dev_priv->rps.cz_freq = 400; 5444 dev_priv->mem_freq = 1600; 5445 break; 5446 } 5447 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); 5448 5449 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); 5450 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; 5451 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 5452 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), 5453 dev_priv->rps.max_freq); 5454 5455 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); 5456 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 5457 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5458 dev_priv->rps.efficient_freq); 5459 5460 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); 5461 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", 5462 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), 5463 dev_priv->rps.rp1_freq); 5464 5465 /* PUnit validated range is only [RPe, RP0] */ 5466 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq; 5467 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 5468 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), 5469 dev_priv->rps.min_freq); 5470 5471 WARN_ONCE((dev_priv->rps.max_freq | 5472 dev_priv->rps.efficient_freq | 5473 dev_priv->rps.rp1_freq | 5474 dev_priv->rps.min_freq) & 1, 5475 "Odd GPU freq values\n"); 5476 5477 dev_priv->rps.idle_freq = dev_priv->rps.min_freq; 5478 5479 /* Preserve min/max settings in case of re-init */ 5480 if (dev_priv->rps.max_freq_softlimit == 0) 5481 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; 5482 5483 if (dev_priv->rps.min_freq_softlimit == 0) 5484 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; 5485 5486 mutex_unlock(&dev_priv->rps.hw_lock); 5487 } 5488 5489 static void valleyview_cleanup_gt_powersave(struct drm_device *dev) 5490 { 5491 valleyview_cleanup_pctx(dev); 5492 } 5493 5494 static void cherryview_enable_rps(struct drm_device *dev) 5495 { 5496 struct drm_i915_private *dev_priv = dev->dev_private; 5497 struct intel_engine_cs *ring; 5498 u32 gtfifodbg, val, rc6_mode = 0, pcbr; 5499 int i; 5500 5501 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5502 5503 gtfifodbg = I915_READ(GTFIFODBG); 5504 if (gtfifodbg) { 5505 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5506 gtfifodbg); 5507 I915_WRITE(GTFIFODBG, gtfifodbg); 5508 } 5509 5510 cherryview_check_pctx(dev_priv); 5511 5512 /* 1a & 1b: Get forcewake during program sequence. Although the driver 5513 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 5514 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5515 5516 /* Disable RC states. */ 5517 I915_WRITE(GEN6_RC_CONTROL, 0); 5518 5519 /* 2a: Program RC6 thresholds.*/ 5520 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); 5521 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ 5522 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ 5523 5524 for_each_ring(ring, dev_priv, i) 5525 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5526 I915_WRITE(GEN6_RC_SLEEP, 0); 5527 5528 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ 5529 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); 5530 5531 /* allows RC6 residency counter to work */ 5532 I915_WRITE(VLV_COUNTER_CONTROL, 5533 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | 5534 VLV_MEDIA_RC6_COUNT_EN | 5535 VLV_RENDER_RC6_COUNT_EN)); 5536 5537 /* For now we assume BIOS is allocating and populating the PCBR */ 5538 pcbr = I915_READ(VLV_PCBR); 5539 5540 /* 3: Enable RC6 */ 5541 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && 5542 (pcbr >> VLV_PCBR_ADDR_SHIFT)) 5543 rc6_mode = GEN7_RC_CTL_TO_MODE; 5544 5545 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5546 5547 /* 4 Program defaults and thresholds for RPS*/ 5548 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5549 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5550 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5551 I915_WRITE(GEN6_RP_UP_EI, 66000); 5552 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5553 5554 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5555 5556 /* 5: Enable RPS */ 5557 I915_WRITE(GEN6_RP_CONTROL, 5558 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5559 GEN6_RP_MEDIA_IS_GFX | 5560 GEN6_RP_ENABLE | 5561 GEN6_RP_UP_BUSY_AVG | 5562 GEN6_RP_DOWN_IDLE_AVG); 5563 5564 /* Setting Fixed Bias */ 5565 val = VLV_OVERRIDE_EN | 5566 VLV_SOC_TDP_EN | 5567 CHV_BIAS_CPU_50_SOC_50; 5568 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5569 5570 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5571 5572 /* RPS code assumes GPLL is used */ 5573 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5574 5575 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); 5576 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5577 5578 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5579 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5580 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5581 dev_priv->rps.cur_freq); 5582 5583 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5584 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5585 dev_priv->rps.efficient_freq); 5586 5587 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5588 5589 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5590 } 5591 5592 static void valleyview_enable_rps(struct drm_device *dev) 5593 { 5594 struct drm_i915_private *dev_priv = dev->dev_private; 5595 struct intel_engine_cs *ring; 5596 u32 gtfifodbg, val, rc6_mode = 0; 5597 int i; 5598 5599 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 5600 5601 valleyview_check_pctx(dev_priv); 5602 5603 if ((gtfifodbg = I915_READ(GTFIFODBG))) { 5604 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", 5605 gtfifodbg); 5606 I915_WRITE(GTFIFODBG, gtfifodbg); 5607 } 5608 5609 /* If VLV, Forcewake all wells, else re-direct to regular path */ 5610 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); 5611 5612 /* Disable RC states. */ 5613 I915_WRITE(GEN6_RC_CONTROL, 0); 5614 5615 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); 5616 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 5617 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 5618 I915_WRITE(GEN6_RP_UP_EI, 66000); 5619 I915_WRITE(GEN6_RP_DOWN_EI, 350000); 5620 5621 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); 5622 5623 I915_WRITE(GEN6_RP_CONTROL, 5624 GEN6_RP_MEDIA_TURBO | 5625 GEN6_RP_MEDIA_HW_NORMAL_MODE | 5626 GEN6_RP_MEDIA_IS_GFX | 5627 GEN6_RP_ENABLE | 5628 GEN6_RP_UP_BUSY_AVG | 5629 GEN6_RP_DOWN_IDLE_CONT); 5630 5631 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); 5632 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); 5633 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); 5634 5635 for_each_ring(ring, dev_priv, i) 5636 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 5637 5638 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); 5639 5640 /* allows RC6 residency counter to work */ 5641 I915_WRITE(VLV_COUNTER_CONTROL, 5642 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | 5643 VLV_RENDER_RC0_COUNT_EN | 5644 VLV_MEDIA_RC6_COUNT_EN | 5645 VLV_RENDER_RC6_COUNT_EN)); 5646 5647 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 5648 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; 5649 5650 intel_print_rc6_info(dev, rc6_mode); 5651 5652 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 5653 5654 /* Setting Fixed Bias */ 5655 val = VLV_OVERRIDE_EN | 5656 VLV_SOC_TDP_EN | 5657 VLV_BIAS_CPU_125_SOC_875; 5658 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); 5659 5660 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 5661 5662 /* RPS code assumes GPLL is used */ 5663 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); 5664 5665 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); 5666 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 5667 5668 dev_priv->rps.cur_freq = (val >> 8) & 0xff; 5669 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 5670 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), 5671 dev_priv->rps.cur_freq); 5672 5673 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 5674 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), 5675 dev_priv->rps.efficient_freq); 5676 5677 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); 5678 5679 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); 5680 } 5681 5682 static unsigned long intel_pxfreq(u32 vidfreq) 5683 { 5684 unsigned long freq; 5685 int div = (vidfreq & 0x3f0000) >> 16; 5686 int post = (vidfreq & 0x3000) >> 12; 5687 int pre = (vidfreq & 0x7); 5688 5689 if (!pre) 5690 return 0; 5691 5692 freq = ((div * 133333) / ((1<<post) * pre)); 5693 5694 return freq; 5695 } 5696 5697 static const struct cparams { 5698 u16 i; 5699 u16 t; 5700 u16 m; 5701 u16 c; 5702 } cparams[] = { 5703 { 1, 1333, 301, 28664 }, 5704 { 1, 1066, 294, 24460 }, 5705 { 1, 800, 294, 25192 }, 5706 { 0, 1333, 276, 27605 }, 5707 { 0, 1066, 276, 27605 }, 5708 { 0, 800, 231, 23784 }, 5709 }; 5710 5711 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) 5712 { 5713 u64 total_count, diff, ret; 5714 u32 count1, count2, count3, m = 0, c = 0; 5715 unsigned long now = jiffies_to_msecs(jiffies), diff1; 5716 int i; 5717 5718 assert_spin_locked(&mchdev_lock); 5719 5720 diff1 = now - dev_priv->ips.last_time1; 5721 5722 /* Prevent division-by-zero if we are asking too fast. 5723 * Also, we don't get interesting results if we are polling 5724 * faster than once in 10ms, so just return the saved value 5725 * in such cases. 5726 */ 5727 if (diff1 <= 10) 5728 return dev_priv->ips.chipset_power; 5729 5730 count1 = I915_READ(DMIEC); 5731 count2 = I915_READ(DDREC); 5732 count3 = I915_READ(CSIEC); 5733 5734 total_count = count1 + count2 + count3; 5735 5736 /* FIXME: handle per-counter overflow */ 5737 if (total_count < dev_priv->ips.last_count1) { 5738 diff = ~0UL - dev_priv->ips.last_count1; 5739 diff += total_count; 5740 } else { 5741 diff = total_count - dev_priv->ips.last_count1; 5742 } 5743 5744 for (i = 0; i < ARRAY_SIZE(cparams); i++) { 5745 if (cparams[i].i == dev_priv->ips.c_m && 5746 cparams[i].t == dev_priv->ips.r_t) { 5747 m = cparams[i].m; 5748 c = cparams[i].c; 5749 break; 5750 } 5751 } 5752 5753 diff = div_u64(diff, diff1); 5754 ret = ((m * diff) + c); 5755 ret = div_u64(ret, 10); 5756 5757 dev_priv->ips.last_count1 = total_count; 5758 dev_priv->ips.last_time1 = now; 5759 5760 dev_priv->ips.chipset_power = ret; 5761 5762 return ret; 5763 } 5764 5765 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) 5766 { 5767 struct drm_device *dev = dev_priv->dev; 5768 unsigned long val; 5769 5770 if (INTEL_INFO(dev)->gen != 5) 5771 return 0; 5772 5773 spin_lock_irq(&mchdev_lock); 5774 5775 val = __i915_chipset_val(dev_priv); 5776 5777 spin_unlock_irq(&mchdev_lock); 5778 5779 return val; 5780 } 5781 5782 unsigned long i915_mch_val(struct drm_i915_private *dev_priv) 5783 { 5784 unsigned long m, x, b; 5785 u32 tsfs; 5786 5787 tsfs = I915_READ(TSFS); 5788 5789 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); 5790 x = I915_READ8(TR1); 5791 5792 b = tsfs & TSFS_INTR_MASK; 5793 5794 return ((m * x) / 127) - b; 5795 } 5796 5797 static int _pxvid_to_vd(u8 pxvid) 5798 { 5799 if (pxvid == 0) 5800 return 0; 5801 5802 if (pxvid >= 8 && pxvid < 31) 5803 pxvid = 31; 5804 5805 return (pxvid + 2) * 125; 5806 } 5807 5808 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) 5809 { 5810 struct drm_device *dev = dev_priv->dev; 5811 const int vd = _pxvid_to_vd(pxvid); 5812 const int vm = vd - 1125; 5813 5814 if (INTEL_INFO(dev)->is_mobile) 5815 return vm > 0 ? vm : 0; 5816 5817 return vd; 5818 } 5819 5820 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) 5821 { 5822 u64 now, diff, diffms; 5823 u32 count; 5824 5825 assert_spin_locked(&mchdev_lock); 5826 5827 now = ktime_get_raw_ns(); 5828 diffms = now - dev_priv->ips.last_time2; 5829 do_div(diffms, NSEC_PER_MSEC); 5830 5831 /* Don't divide by 0 */ 5832 if (!diffms) 5833 return; 5834 5835 count = I915_READ(GFXEC); 5836 5837 if (count < dev_priv->ips.last_count2) { 5838 diff = ~0UL - dev_priv->ips.last_count2; 5839 diff += count; 5840 } else { 5841 diff = count - dev_priv->ips.last_count2; 5842 } 5843 5844 dev_priv->ips.last_count2 = count; 5845 dev_priv->ips.last_time2 = now; 5846 5847 /* More magic constants... */ 5848 diff = diff * 1181; 5849 diff = div_u64(diff, diffms * 10); 5850 dev_priv->ips.gfx_power = diff; 5851 } 5852 5853 void i915_update_gfx_val(struct drm_i915_private *dev_priv) 5854 { 5855 struct drm_device *dev = dev_priv->dev; 5856 5857 if (INTEL_INFO(dev)->gen != 5) 5858 return; 5859 5860 spin_lock_irq(&mchdev_lock); 5861 5862 __i915_update_gfx_val(dev_priv); 5863 5864 spin_unlock_irq(&mchdev_lock); 5865 } 5866 5867 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) 5868 { 5869 unsigned long t, corr, state1, corr2, state2; 5870 u32 pxvid, ext_v; 5871 5872 assert_spin_locked(&mchdev_lock); 5873 5874 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); 5875 pxvid = (pxvid >> 24) & 0x7f; 5876 ext_v = pvid_to_extvid(dev_priv, pxvid); 5877 5878 state1 = ext_v; 5879 5880 t = i915_mch_val(dev_priv); 5881 5882 /* Revel in the empirically derived constants */ 5883 5884 /* Correction factor in 1/100000 units */ 5885 if (t > 80) 5886 corr = ((t * 2349) + 135940); 5887 else if (t >= 50) 5888 corr = ((t * 964) + 29317); 5889 else /* < 50 */ 5890 corr = ((t * 301) + 1004); 5891 5892 corr = corr * ((150142 * state1) / 10000 - 78642); 5893 corr /= 100000; 5894 corr2 = (corr * dev_priv->ips.corr); 5895 5896 state2 = (corr2 * state1) / 10000; 5897 state2 /= 100; /* convert to mW */ 5898 5899 __i915_update_gfx_val(dev_priv); 5900 5901 return dev_priv->ips.gfx_power + state2; 5902 } 5903 5904 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) 5905 { 5906 struct drm_device *dev = dev_priv->dev; 5907 unsigned long val; 5908 5909 if (INTEL_INFO(dev)->gen != 5) 5910 return 0; 5911 5912 spin_lock_irq(&mchdev_lock); 5913 5914 val = __i915_gfx_val(dev_priv); 5915 5916 spin_unlock_irq(&mchdev_lock); 5917 5918 return val; 5919 } 5920 5921 /** 5922 * i915_read_mch_val - return value for IPS use 5923 * 5924 * Calculate and return a value for the IPS driver to use when deciding whether 5925 * we have thermal and power headroom to increase CPU or GPU power budget. 5926 */ 5927 unsigned long i915_read_mch_val(void) 5928 { 5929 struct drm_i915_private *dev_priv; 5930 unsigned long chipset_val, graphics_val, ret = 0; 5931 5932 spin_lock_irq(&mchdev_lock); 5933 if (!i915_mch_dev) 5934 goto out_unlock; 5935 dev_priv = i915_mch_dev; 5936 5937 chipset_val = __i915_chipset_val(dev_priv); 5938 graphics_val = __i915_gfx_val(dev_priv); 5939 5940 ret = chipset_val + graphics_val; 5941 5942 out_unlock: 5943 spin_unlock_irq(&mchdev_lock); 5944 5945 return ret; 5946 } 5947 5948 /** 5949 * i915_gpu_raise - raise GPU frequency limit 5950 * 5951 * Raise the limit; IPS indicates we have thermal headroom. 5952 */ 5953 bool i915_gpu_raise(void) 5954 { 5955 struct drm_i915_private *dev_priv; 5956 bool ret = true; 5957 5958 spin_lock_irq(&mchdev_lock); 5959 if (!i915_mch_dev) { 5960 ret = false; 5961 goto out_unlock; 5962 } 5963 dev_priv = i915_mch_dev; 5964 5965 if (dev_priv->ips.max_delay > dev_priv->ips.fmax) 5966 dev_priv->ips.max_delay--; 5967 5968 out_unlock: 5969 spin_unlock_irq(&mchdev_lock); 5970 5971 return ret; 5972 } 5973 5974 /** 5975 * i915_gpu_lower - lower GPU frequency limit 5976 * 5977 * IPS indicates we're close to a thermal limit, so throttle back the GPU 5978 * frequency maximum. 5979 */ 5980 bool i915_gpu_lower(void) 5981 { 5982 struct drm_i915_private *dev_priv; 5983 bool ret = true; 5984 5985 spin_lock_irq(&mchdev_lock); 5986 if (!i915_mch_dev) { 5987 ret = false; 5988 goto out_unlock; 5989 } 5990 dev_priv = i915_mch_dev; 5991 5992 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) 5993 dev_priv->ips.max_delay++; 5994 5995 out_unlock: 5996 spin_unlock_irq(&mchdev_lock); 5997 5998 return ret; 5999 } 6000 6001 /** 6002 * i915_gpu_busy - indicate GPU business to IPS 6003 * 6004 * Tell the IPS driver whether or not the GPU is busy. 6005 */ 6006 bool i915_gpu_busy(void) 6007 { 6008 struct drm_i915_private *dev_priv; 6009 struct intel_engine_cs *ring; 6010 bool ret = false; 6011 int i; 6012 6013 spin_lock_irq(&mchdev_lock); 6014 if (!i915_mch_dev) 6015 goto out_unlock; 6016 dev_priv = i915_mch_dev; 6017 6018 for_each_ring(ring, dev_priv, i) 6019 ret |= !list_empty(&ring->request_list); 6020 6021 out_unlock: 6022 spin_unlock_irq(&mchdev_lock); 6023 6024 return ret; 6025 } 6026 6027 /** 6028 * i915_gpu_turbo_disable - disable graphics turbo 6029 * 6030 * Disable graphics turbo by resetting the max frequency and setting the 6031 * current frequency to the default. 6032 */ 6033 bool i915_gpu_turbo_disable(void) 6034 { 6035 struct drm_i915_private *dev_priv; 6036 bool ret = true; 6037 6038 spin_lock_irq(&mchdev_lock); 6039 if (!i915_mch_dev) { 6040 ret = false; 6041 goto out_unlock; 6042 } 6043 dev_priv = i915_mch_dev; 6044 6045 dev_priv->ips.max_delay = dev_priv->ips.fstart; 6046 6047 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) 6048 ret = false; 6049 6050 out_unlock: 6051 spin_unlock_irq(&mchdev_lock); 6052 6053 return ret; 6054 } 6055 6056 #if 0 6057 /** 6058 * Tells the intel_ips driver that the i915 driver is now loaded, if 6059 * IPS got loaded first. 6060 * 6061 * This awkward dance is so that neither module has to depend on the 6062 * other in order for IPS to do the appropriate communication of 6063 * GPU turbo limits to i915. 6064 */ 6065 static void 6066 ips_ping_for_i915_load(void) 6067 { 6068 void (*link)(void); 6069 6070 link = symbol_get(ips_link_to_i915_driver); 6071 if (link) { 6072 link(); 6073 symbol_put(ips_link_to_i915_driver); 6074 } 6075 } 6076 #endif 6077 6078 void intel_gpu_ips_init(struct drm_i915_private *dev_priv) 6079 { 6080 /* We only register the i915 ips part with intel-ips once everything is 6081 * set up, to avoid intel-ips sneaking in and reading bogus values. */ 6082 spin_lock_irq(&mchdev_lock); 6083 i915_mch_dev = dev_priv; 6084 spin_unlock_irq(&mchdev_lock); 6085 } 6086 6087 void intel_gpu_ips_teardown(void) 6088 { 6089 spin_lock_irq(&mchdev_lock); 6090 i915_mch_dev = NULL; 6091 spin_unlock_irq(&mchdev_lock); 6092 } 6093 6094 static void intel_init_emon(struct drm_device *dev) 6095 { 6096 struct drm_i915_private *dev_priv = dev->dev_private; 6097 u32 lcfuse; 6098 u8 pxw[16]; 6099 int i; 6100 6101 /* Disable to program */ 6102 I915_WRITE(ECR, 0); 6103 POSTING_READ(ECR); 6104 6105 /* Program energy weights for various events */ 6106 I915_WRITE(SDEW, 0x15040d00); 6107 I915_WRITE(CSIEW0, 0x007f0000); 6108 I915_WRITE(CSIEW1, 0x1e220004); 6109 I915_WRITE(CSIEW2, 0x04000004); 6110 6111 for (i = 0; i < 5; i++) 6112 I915_WRITE(PEW + (i * 4), 0); 6113 for (i = 0; i < 3; i++) 6114 I915_WRITE(DEW + (i * 4), 0); 6115 6116 /* Program P-state weights to account for frequency power adjustment */ 6117 for (i = 0; i < 16; i++) { 6118 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); 6119 unsigned long freq = intel_pxfreq(pxvidfreq); 6120 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> 6121 PXVFREQ_PX_SHIFT; 6122 unsigned long val; 6123 6124 val = vid * vid; 6125 val *= (freq / 1000); 6126 val *= 255; 6127 val /= (127*127*900); 6128 if (val > 0xff) 6129 DRM_ERROR("bad pxval: %ld\n", val); 6130 pxw[i] = val; 6131 } 6132 /* Render standby states get 0 weight */ 6133 pxw[14] = 0; 6134 pxw[15] = 0; 6135 6136 for (i = 0; i < 4; i++) { 6137 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | 6138 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); 6139 I915_WRITE(PXW + (i * 4), val); 6140 } 6141 6142 /* Adjust magic regs to magic values (more experimental results) */ 6143 I915_WRITE(OGW0, 0); 6144 I915_WRITE(OGW1, 0); 6145 I915_WRITE(EG0, 0x00007f00); 6146 I915_WRITE(EG1, 0x0000000e); 6147 I915_WRITE(EG2, 0x000e0000); 6148 I915_WRITE(EG3, 0x68000300); 6149 I915_WRITE(EG4, 0x42000000); 6150 I915_WRITE(EG5, 0x00140031); 6151 I915_WRITE(EG6, 0); 6152 I915_WRITE(EG7, 0); 6153 6154 for (i = 0; i < 8; i++) 6155 I915_WRITE(PXWL + (i * 4), 0); 6156 6157 /* Enable PMON + select events */ 6158 I915_WRITE(ECR, 0x80000019); 6159 6160 lcfuse = I915_READ(LCFUSE02); 6161 6162 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); 6163 } 6164 6165 void intel_init_gt_powersave(struct drm_device *dev) 6166 { 6167 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); 6168 6169 if (IS_CHERRYVIEW(dev)) 6170 cherryview_init_gt_powersave(dev); 6171 else if (IS_VALLEYVIEW(dev)) 6172 valleyview_init_gt_powersave(dev); 6173 } 6174 6175 void intel_cleanup_gt_powersave(struct drm_device *dev) 6176 { 6177 if (IS_CHERRYVIEW(dev)) 6178 return; 6179 else if (IS_VALLEYVIEW(dev)) 6180 valleyview_cleanup_gt_powersave(dev); 6181 } 6182 6183 static void gen6_suspend_rps(struct drm_device *dev) 6184 { 6185 #if 0 6186 struct drm_i915_private *dev_priv = dev->dev_private; 6187 6188 flush_delayed_work(&dev_priv->rps.delayed_resume_work); 6189 #endif 6190 6191 gen6_disable_rps_interrupts(dev); 6192 } 6193 6194 /** 6195 * intel_suspend_gt_powersave - suspend PM work and helper threads 6196 * @dev: drm device 6197 * 6198 * We don't want to disable RC6 or other features here, we just want 6199 * to make sure any work we've queued has finished and won't bother 6200 * us while we're suspended. 6201 */ 6202 void intel_suspend_gt_powersave(struct drm_device *dev) 6203 { 6204 struct drm_i915_private *dev_priv = dev->dev_private; 6205 6206 if (INTEL_INFO(dev)->gen < 6) 6207 return; 6208 6209 gen6_suspend_rps(dev); 6210 6211 /* Force GPU to min freq during suspend */ 6212 gen6_rps_idle(dev_priv); 6213 } 6214 6215 void intel_disable_gt_powersave(struct drm_device *dev) 6216 { 6217 struct drm_i915_private *dev_priv = dev->dev_private; 6218 6219 if (IS_IRONLAKE_M(dev)) { 6220 ironlake_disable_drps(dev); 6221 } else if (INTEL_INFO(dev)->gen >= 6) { 6222 intel_suspend_gt_powersave(dev); 6223 6224 mutex_lock(&dev_priv->rps.hw_lock); 6225 if (INTEL_INFO(dev)->gen >= 9) 6226 gen9_disable_rps(dev); 6227 else if (IS_CHERRYVIEW(dev)) 6228 cherryview_disable_rps(dev); 6229 else if (IS_VALLEYVIEW(dev)) 6230 valleyview_disable_rps(dev); 6231 else 6232 gen6_disable_rps(dev); 6233 6234 dev_priv->rps.enabled = false; 6235 mutex_unlock(&dev_priv->rps.hw_lock); 6236 } 6237 } 6238 6239 static void intel_gen6_powersave_work(struct work_struct *work) 6240 { 6241 struct drm_i915_private *dev_priv = 6242 container_of(work, struct drm_i915_private, 6243 rps.delayed_resume_work.work); 6244 struct drm_device *dev = dev_priv->dev; 6245 6246 mutex_lock(&dev_priv->rps.hw_lock); 6247 6248 gen6_reset_rps_interrupts(dev); 6249 6250 if (IS_CHERRYVIEW(dev)) { 6251 cherryview_enable_rps(dev); 6252 } else if (IS_VALLEYVIEW(dev)) { 6253 valleyview_enable_rps(dev); 6254 } else if (INTEL_INFO(dev)->gen >= 9) { 6255 gen9_enable_rc6(dev); 6256 gen9_enable_rps(dev); 6257 if (IS_SKYLAKE(dev)) 6258 __gen6_update_ring_freq(dev); 6259 } else if (IS_BROADWELL(dev)) { 6260 gen8_enable_rps(dev); 6261 __gen6_update_ring_freq(dev); 6262 } else { 6263 gen6_enable_rps(dev); 6264 __gen6_update_ring_freq(dev); 6265 } 6266 6267 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); 6268 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); 6269 6270 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); 6271 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); 6272 6273 dev_priv->rps.enabled = true; 6274 6275 gen6_enable_rps_interrupts(dev); 6276 6277 mutex_unlock(&dev_priv->rps.hw_lock); 6278 6279 intel_runtime_pm_put(dev_priv); 6280 } 6281 6282 void intel_enable_gt_powersave(struct drm_device *dev) 6283 { 6284 struct drm_i915_private *dev_priv = dev->dev_private; 6285 6286 /* Powersaving is controlled by the host when inside a VM */ 6287 if (intel_vgpu_active(dev)) 6288 return; 6289 6290 if (IS_IRONLAKE_M(dev)) { 6291 mutex_lock(&dev->struct_mutex); 6292 ironlake_enable_drps(dev); 6293 intel_init_emon(dev); 6294 mutex_unlock(&dev->struct_mutex); 6295 } else if (INTEL_INFO(dev)->gen >= 6) { 6296 /* 6297 * PCU communication is slow and this doesn't need to be 6298 * done at any specific time, so do this out of our fast path 6299 * to make resume and init faster. 6300 * 6301 * We depend on the HW RC6 power context save/restore 6302 * mechanism when entering D3 through runtime PM suspend. So 6303 * disable RPM until RPS/RC6 is properly setup. We can only 6304 * get here via the driver load/system resume/runtime resume 6305 * paths, so the _noresume version is enough (and in case of 6306 * runtime resume it's necessary). 6307 */ 6308 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, 6309 round_jiffies_up_relative(HZ))) 6310 intel_runtime_pm_get_noresume(dev_priv); 6311 } 6312 } 6313 6314 void intel_reset_gt_powersave(struct drm_device *dev) 6315 { 6316 struct drm_i915_private *dev_priv = dev->dev_private; 6317 6318 if (INTEL_INFO(dev)->gen < 6) 6319 return; 6320 6321 gen6_suspend_rps(dev); 6322 dev_priv->rps.enabled = false; 6323 } 6324 6325 static void ibx_init_clock_gating(struct drm_device *dev) 6326 { 6327 struct drm_i915_private *dev_priv = dev->dev_private; 6328 6329 /* 6330 * On Ibex Peak and Cougar Point, we need to disable clock 6331 * gating for the panel power sequencer or it will fail to 6332 * start up when no ports are active. 6333 */ 6334 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 6335 } 6336 6337 static void g4x_disable_trickle_feed(struct drm_device *dev) 6338 { 6339 struct drm_i915_private *dev_priv = dev->dev_private; 6340 enum i915_pipe pipe; 6341 6342 for_each_pipe(dev_priv, pipe) { 6343 I915_WRITE(DSPCNTR(pipe), 6344 I915_READ(DSPCNTR(pipe)) | 6345 DISPPLANE_TRICKLE_FEED_DISABLE); 6346 6347 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); 6348 POSTING_READ(DSPSURF(pipe)); 6349 } 6350 } 6351 6352 static void ilk_init_lp_watermarks(struct drm_device *dev) 6353 { 6354 struct drm_i915_private *dev_priv = dev->dev_private; 6355 6356 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); 6357 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); 6358 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); 6359 6360 /* 6361 * Don't touch WM1S_LP_EN here. 6362 * Doing so could cause underruns. 6363 */ 6364 } 6365 6366 static void ironlake_init_clock_gating(struct drm_device *dev) 6367 { 6368 struct drm_i915_private *dev_priv = dev->dev_private; 6369 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6370 6371 /* 6372 * Required for FBC 6373 * WaFbcDisableDpfcClockGating:ilk 6374 */ 6375 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | 6376 ILK_DPFCUNIT_CLOCK_GATE_DISABLE | 6377 ILK_DPFDUNIT_CLOCK_GATE_ENABLE; 6378 6379 I915_WRITE(PCH_3DCGDIS0, 6380 MARIUNIT_CLOCK_GATE_DISABLE | 6381 SVSMUNIT_CLOCK_GATE_DISABLE); 6382 I915_WRITE(PCH_3DCGDIS1, 6383 VFMUNIT_CLOCK_GATE_DISABLE); 6384 6385 /* 6386 * According to the spec the following bits should be set in 6387 * order to enable memory self-refresh 6388 * The bit 22/21 of 0x42004 6389 * The bit 5 of 0x42020 6390 * The bit 15 of 0x45000 6391 */ 6392 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6393 (I915_READ(ILK_DISPLAY_CHICKEN2) | 6394 ILK_DPARB_GATE | ILK_VSDPFD_FULL)); 6395 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; 6396 I915_WRITE(DISP_ARB_CTL, 6397 (I915_READ(DISP_ARB_CTL) | 6398 DISP_FBC_WM_DIS)); 6399 6400 ilk_init_lp_watermarks(dev); 6401 6402 /* 6403 * Based on the document from hardware guys the following bits 6404 * should be set unconditionally in order to enable FBC. 6405 * The bit 22 of 0x42000 6406 * The bit 22 of 0x42004 6407 * The bit 7,8,9 of 0x42020. 6408 */ 6409 if (IS_IRONLAKE_M(dev)) { 6410 /* WaFbcAsynchFlipDisableFbcQueue:ilk */ 6411 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6412 I915_READ(ILK_DISPLAY_CHICKEN1) | 6413 ILK_FBCQ_DIS); 6414 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6415 I915_READ(ILK_DISPLAY_CHICKEN2) | 6416 ILK_DPARB_GATE); 6417 } 6418 6419 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6420 6421 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6422 I915_READ(ILK_DISPLAY_CHICKEN2) | 6423 ILK_ELPIN_409_SELECT); 6424 I915_WRITE(_3D_CHICKEN2, 6425 _3D_CHICKEN2_WM_READ_PIPELINED << 16 | 6426 _3D_CHICKEN2_WM_READ_PIPELINED); 6427 6428 /* WaDisableRenderCachePipelinedFlush:ilk */ 6429 I915_WRITE(CACHE_MODE_0, 6430 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6431 6432 /* WaDisable_RenderCache_OperationalFlush:ilk */ 6433 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6434 6435 g4x_disable_trickle_feed(dev); 6436 6437 ibx_init_clock_gating(dev); 6438 } 6439 6440 static void cpt_init_clock_gating(struct drm_device *dev) 6441 { 6442 struct drm_i915_private *dev_priv = dev->dev_private; 6443 int pipe; 6444 uint32_t val; 6445 6446 /* 6447 * On Ibex Peak and Cougar Point, we need to disable clock 6448 * gating for the panel power sequencer or it will fail to 6449 * start up when no ports are active. 6450 */ 6451 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 6452 PCH_DPLUNIT_CLOCK_GATE_DISABLE | 6453 PCH_CPUNIT_CLOCK_GATE_DISABLE); 6454 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | 6455 DPLS_EDP_PPS_FIX_DIS); 6456 /* The below fixes the weird display corruption, a few pixels shifted 6457 * downward, on (only) LVDS of some HP laptops with IVY. 6458 */ 6459 for_each_pipe(dev_priv, pipe) { 6460 val = I915_READ(TRANS_CHICKEN2(pipe)); 6461 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 6462 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6463 if (dev_priv->vbt.fdi_rx_polarity_inverted) 6464 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; 6465 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; 6466 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; 6467 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; 6468 I915_WRITE(TRANS_CHICKEN2(pipe), val); 6469 } 6470 /* WADP0ClockGatingDisable */ 6471 for_each_pipe(dev_priv, pipe) { 6472 I915_WRITE(TRANS_CHICKEN1(pipe), 6473 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6474 } 6475 } 6476 6477 static void gen6_check_mch_setup(struct drm_device *dev) 6478 { 6479 struct drm_i915_private *dev_priv = dev->dev_private; 6480 uint32_t tmp; 6481 6482 tmp = I915_READ(MCH_SSKPD); 6483 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) 6484 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", 6485 tmp); 6486 } 6487 6488 static void gen6_init_clock_gating(struct drm_device *dev) 6489 { 6490 struct drm_i915_private *dev_priv = dev->dev_private; 6491 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; 6492 6493 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); 6494 6495 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6496 I915_READ(ILK_DISPLAY_CHICKEN2) | 6497 ILK_ELPIN_409_SELECT); 6498 6499 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ 6500 I915_WRITE(_3D_CHICKEN, 6501 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); 6502 6503 /* WaDisable_RenderCache_OperationalFlush:snb */ 6504 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6505 6506 /* 6507 * BSpec recoomends 8x4 when MSAA is used, 6508 * however in practice 16x4 seems fastest. 6509 * 6510 * Note that PS/WM thread counts depend on the WIZ hashing 6511 * disable bit, which we don't touch here, but it's good 6512 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6513 */ 6514 I915_WRITE(GEN6_GT_MODE, 6515 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6516 6517 ilk_init_lp_watermarks(dev); 6518 6519 I915_WRITE(CACHE_MODE_0, 6520 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); 6521 6522 I915_WRITE(GEN6_UCGCTL1, 6523 I915_READ(GEN6_UCGCTL1) | 6524 GEN6_BLBUNIT_CLOCK_GATE_DISABLE | 6525 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6526 6527 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock 6528 * gating disable must be set. Failure to set it results in 6529 * flickering pixels due to Z write ordering failures after 6530 * some amount of runtime in the Mesa "fire" demo, and Unigine 6531 * Sanctuary and Tropics, and apparently anything else with 6532 * alpha test or pixel discard. 6533 * 6534 * According to the spec, bit 11 (RCCUNIT) must also be set, 6535 * but we didn't debug actual testcases to find it out. 6536 * 6537 * WaDisableRCCUnitClockGating:snb 6538 * WaDisableRCPBUnitClockGating:snb 6539 */ 6540 I915_WRITE(GEN6_UCGCTL2, 6541 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | 6542 GEN6_RCCUNIT_CLOCK_GATE_DISABLE); 6543 6544 /* WaStripsFansDisableFastClipPerformanceFix:snb */ 6545 I915_WRITE(_3D_CHICKEN3, 6546 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); 6547 6548 /* 6549 * Bspec says: 6550 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and 6551 * 3DSTATE_SF number of SF output attributes is more than 16." 6552 */ 6553 I915_WRITE(_3D_CHICKEN3, 6554 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); 6555 6556 /* 6557 * According to the spec the following bits should be 6558 * set in order to enable memory self-refresh and fbc: 6559 * The bit21 and bit22 of 0x42000 6560 * The bit21 and bit22 of 0x42004 6561 * The bit5 and bit7 of 0x42020 6562 * The bit14 of 0x70180 6563 * The bit14 of 0x71180 6564 * 6565 * WaFbcAsynchFlipDisableFbcQueue:snb 6566 */ 6567 I915_WRITE(ILK_DISPLAY_CHICKEN1, 6568 I915_READ(ILK_DISPLAY_CHICKEN1) | 6569 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); 6570 I915_WRITE(ILK_DISPLAY_CHICKEN2, 6571 I915_READ(ILK_DISPLAY_CHICKEN2) | 6572 ILK_DPARB_GATE | ILK_VSDPFD_FULL); 6573 I915_WRITE(ILK_DSPCLK_GATE_D, 6574 I915_READ(ILK_DSPCLK_GATE_D) | 6575 ILK_DPARBUNIT_CLOCK_GATE_ENABLE | 6576 ILK_DPFDUNIT_CLOCK_GATE_ENABLE); 6577 6578 g4x_disable_trickle_feed(dev); 6579 6580 cpt_init_clock_gating(dev); 6581 6582 gen6_check_mch_setup(dev); 6583 } 6584 6585 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) 6586 { 6587 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); 6588 6589 /* 6590 * WaVSThreadDispatchOverride:ivb,vlv 6591 * 6592 * This actually overrides the dispatch 6593 * mode for all thread types. 6594 */ 6595 reg &= ~GEN7_FF_SCHED_MASK; 6596 reg |= GEN7_FF_TS_SCHED_HW; 6597 reg |= GEN7_FF_VS_SCHED_HW; 6598 reg |= GEN7_FF_DS_SCHED_HW; 6599 6600 I915_WRITE(GEN7_FF_THREAD_MODE, reg); 6601 } 6602 6603 static void lpt_init_clock_gating(struct drm_device *dev) 6604 { 6605 struct drm_i915_private *dev_priv = dev->dev_private; 6606 6607 /* 6608 * TODO: this bit should only be enabled when really needed, then 6609 * disabled when not needed anymore in order to save power. 6610 */ 6611 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) 6612 I915_WRITE(SOUTH_DSPCLK_GATE_D, 6613 I915_READ(SOUTH_DSPCLK_GATE_D) | 6614 PCH_LP_PARTITION_LEVEL_DISABLE); 6615 6616 /* WADPOClockGatingDisable:hsw */ 6617 I915_WRITE(_TRANSA_CHICKEN1, 6618 I915_READ(_TRANSA_CHICKEN1) | 6619 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); 6620 } 6621 6622 static void lpt_suspend_hw(struct drm_device *dev) 6623 { 6624 struct drm_i915_private *dev_priv = dev->dev_private; 6625 6626 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { 6627 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); 6628 6629 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; 6630 I915_WRITE(SOUTH_DSPCLK_GATE_D, val); 6631 } 6632 } 6633 6634 static void broadwell_init_clock_gating(struct drm_device *dev) 6635 { 6636 struct drm_i915_private *dev_priv = dev->dev_private; 6637 enum i915_pipe pipe; 6638 uint32_t misccpctl; 6639 6640 ilk_init_lp_watermarks(dev); 6641 6642 /* WaSwitchSolVfFArbitrationPriority:bdw */ 6643 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6644 6645 /* WaPsrDPAMaskVBlankInSRD:bdw */ 6646 I915_WRITE(CHICKEN_PAR1_1, 6647 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); 6648 6649 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ 6650 for_each_pipe(dev_priv, pipe) { 6651 I915_WRITE(CHICKEN_PIPESL_1(pipe), 6652 I915_READ(CHICKEN_PIPESL_1(pipe)) | 6653 BDW_DPRS_MASK_VBLANK_SRD); 6654 } 6655 6656 /* WaVSRefCountFullforceMissDisable:bdw */ 6657 /* WaDSRefCountFullforceMissDisable:bdw */ 6658 I915_WRITE(GEN7_FF_THREAD_MODE, 6659 I915_READ(GEN7_FF_THREAD_MODE) & 6660 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6661 6662 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6663 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6664 6665 /* WaDisableSDEUnitClockGating:bdw */ 6666 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6667 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6668 6669 /* 6670 * WaProgramL3SqcReg1Default:bdw 6671 * WaTempDisableDOPClkGating:bdw 6672 */ 6673 misccpctl = I915_READ(GEN7_MISCCPCTL); 6674 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 6675 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT); 6676 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 6677 6678 /* 6679 * WaGttCachingOffByDefault:bdw 6680 * GTT cache may not work with big pages, so if those 6681 * are ever enabled GTT cache may need to be disabled. 6682 */ 6683 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6684 6685 lpt_init_clock_gating(dev); 6686 } 6687 6688 static void haswell_init_clock_gating(struct drm_device *dev) 6689 { 6690 struct drm_i915_private *dev_priv = dev->dev_private; 6691 6692 ilk_init_lp_watermarks(dev); 6693 6694 /* L3 caching of data atomics doesn't work -- disable it. */ 6695 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); 6696 I915_WRITE(HSW_ROW_CHICKEN3, 6697 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); 6698 6699 /* This is required by WaCatErrorRejectionIssue:hsw */ 6700 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6701 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6702 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6703 6704 /* WaVSRefCountFullforceMissDisable:hsw */ 6705 I915_WRITE(GEN7_FF_THREAD_MODE, 6706 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); 6707 6708 /* WaDisable_RenderCache_OperationalFlush:hsw */ 6709 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6710 6711 /* enable HiZ Raw Stall Optimization */ 6712 I915_WRITE(CACHE_MODE_0_GEN7, 6713 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6714 6715 /* WaDisable4x2SubspanOptimization:hsw */ 6716 I915_WRITE(CACHE_MODE_1, 6717 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6718 6719 /* 6720 * BSpec recommends 8x4 when MSAA is used, 6721 * however in practice 16x4 seems fastest. 6722 * 6723 * Note that PS/WM thread counts depend on the WIZ hashing 6724 * disable bit, which we don't touch here, but it's good 6725 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6726 */ 6727 I915_WRITE(GEN7_GT_MODE, 6728 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6729 6730 /* WaSampleCChickenBitEnable:hsw */ 6731 I915_WRITE(HALF_SLICE_CHICKEN3, 6732 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); 6733 6734 /* WaSwitchSolVfFArbitrationPriority:hsw */ 6735 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); 6736 6737 /* WaRsPkgCStateDisplayPMReq:hsw */ 6738 I915_WRITE(CHICKEN_PAR1_1, 6739 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); 6740 6741 lpt_init_clock_gating(dev); 6742 } 6743 6744 static void ivybridge_init_clock_gating(struct drm_device *dev) 6745 { 6746 struct drm_i915_private *dev_priv = dev->dev_private; 6747 uint32_t snpcr; 6748 6749 ilk_init_lp_watermarks(dev); 6750 6751 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); 6752 6753 /* WaDisableEarlyCull:ivb */ 6754 I915_WRITE(_3D_CHICKEN3, 6755 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6756 6757 /* WaDisableBackToBackFlipFix:ivb */ 6758 I915_WRITE(IVB_CHICKEN3, 6759 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6760 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6761 6762 /* WaDisablePSDDualDispatchEnable:ivb */ 6763 if (IS_IVB_GT1(dev)) 6764 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6765 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6766 6767 /* WaDisable_RenderCache_OperationalFlush:ivb */ 6768 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6769 6770 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ 6771 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, 6772 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); 6773 6774 /* WaApplyL3ControlAndL3ChickenMode:ivb */ 6775 I915_WRITE(GEN7_L3CNTLREG1, 6776 GEN7_WA_FOR_GEN7_L3_CONTROL); 6777 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, 6778 GEN7_WA_L3_CHICKEN_MODE); 6779 if (IS_IVB_GT1(dev)) 6780 I915_WRITE(GEN7_ROW_CHICKEN2, 6781 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6782 else { 6783 /* must write both registers */ 6784 I915_WRITE(GEN7_ROW_CHICKEN2, 6785 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6786 I915_WRITE(GEN7_ROW_CHICKEN2_GT2, 6787 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6788 } 6789 6790 /* WaForceL3Serialization:ivb */ 6791 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6792 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6793 6794 /* 6795 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6796 * This implements the WaDisableRCZUnitClockGating:ivb workaround. 6797 */ 6798 I915_WRITE(GEN6_UCGCTL2, 6799 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6800 6801 /* This is required by WaCatErrorRejectionIssue:ivb */ 6802 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6803 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6804 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6805 6806 g4x_disable_trickle_feed(dev); 6807 6808 gen7_setup_fixed_func_scheduler(dev_priv); 6809 6810 if (0) { /* causes HiZ corruption on ivb:gt1 */ 6811 /* enable HiZ Raw Stall Optimization */ 6812 I915_WRITE(CACHE_MODE_0_GEN7, 6813 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); 6814 } 6815 6816 /* WaDisable4x2SubspanOptimization:ivb */ 6817 I915_WRITE(CACHE_MODE_1, 6818 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6819 6820 /* 6821 * BSpec recommends 8x4 when MSAA is used, 6822 * however in practice 16x4 seems fastest. 6823 * 6824 * Note that PS/WM thread counts depend on the WIZ hashing 6825 * disable bit, which we don't touch here, but it's good 6826 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6827 */ 6828 I915_WRITE(GEN7_GT_MODE, 6829 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6830 6831 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); 6832 snpcr &= ~GEN6_MBC_SNPCR_MASK; 6833 snpcr |= GEN6_MBC_SNPCR_MED; 6834 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); 6835 6836 if (!HAS_PCH_NOP(dev)) 6837 cpt_init_clock_gating(dev); 6838 6839 gen6_check_mch_setup(dev); 6840 } 6841 6842 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) 6843 { 6844 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 6845 6846 /* 6847 * Disable trickle feed and enable pnd deadline calculation 6848 */ 6849 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 6850 I915_WRITE(CBR1_VLV, 0); 6851 } 6852 6853 static void valleyview_init_clock_gating(struct drm_device *dev) 6854 { 6855 struct drm_i915_private *dev_priv = dev->dev_private; 6856 6857 vlv_init_display_clock_gating(dev_priv); 6858 6859 /* WaDisableEarlyCull:vlv */ 6860 I915_WRITE(_3D_CHICKEN3, 6861 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); 6862 6863 /* WaDisableBackToBackFlipFix:vlv */ 6864 I915_WRITE(IVB_CHICKEN3, 6865 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | 6866 CHICKEN3_DGMG_DONE_FIX_DISABLE); 6867 6868 /* WaPsdDispatchEnable:vlv */ 6869 /* WaDisablePSDDualDispatchEnable:vlv */ 6870 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, 6871 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | 6872 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); 6873 6874 /* WaDisable_RenderCache_OperationalFlush:vlv */ 6875 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6876 6877 /* WaForceL3Serialization:vlv */ 6878 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & 6879 ~L3SQ_URB_READ_CAM_MATCH_DISABLE); 6880 6881 /* WaDisableDopClockGating:vlv */ 6882 I915_WRITE(GEN7_ROW_CHICKEN2, 6883 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); 6884 6885 /* This is required by WaCatErrorRejectionIssue:vlv */ 6886 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 6887 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | 6888 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); 6889 6890 gen7_setup_fixed_func_scheduler(dev_priv); 6891 6892 /* 6893 * According to the spec, bit 13 (RCZUNIT) must be set on IVB. 6894 * This implements the WaDisableRCZUnitClockGating:vlv workaround. 6895 */ 6896 I915_WRITE(GEN6_UCGCTL2, 6897 GEN6_RCZUNIT_CLOCK_GATE_DISABLE); 6898 6899 /* WaDisableL3Bank2xClockGate:vlv 6900 * Disabling L3 clock gating- MMIO 940c[25] = 1 6901 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ 6902 I915_WRITE(GEN7_UCGCTL4, 6903 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); 6904 6905 /* 6906 * BSpec says this must be set, even though 6907 * WaDisable4x2SubspanOptimization isn't listed for VLV. 6908 */ 6909 I915_WRITE(CACHE_MODE_1, 6910 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); 6911 6912 /* 6913 * BSpec recommends 8x4 when MSAA is used, 6914 * however in practice 16x4 seems fastest. 6915 * 6916 * Note that PS/WM thread counts depend on the WIZ hashing 6917 * disable bit, which we don't touch here, but it's good 6918 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). 6919 */ 6920 I915_WRITE(GEN7_GT_MODE, 6921 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); 6922 6923 /* 6924 * WaIncreaseL3CreditsForVLVB0:vlv 6925 * This is the hardware default actually. 6926 */ 6927 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); 6928 6929 /* 6930 * WaDisableVLVClockGating_VBIIssue:vlv 6931 * Disable clock gating on th GCFG unit to prevent a delay 6932 * in the reporting of vblank events. 6933 */ 6934 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); 6935 } 6936 6937 static void cherryview_init_clock_gating(struct drm_device *dev) 6938 { 6939 struct drm_i915_private *dev_priv = dev->dev_private; 6940 6941 vlv_init_display_clock_gating(dev_priv); 6942 6943 /* WaVSRefCountFullforceMissDisable:chv */ 6944 /* WaDSRefCountFullforceMissDisable:chv */ 6945 I915_WRITE(GEN7_FF_THREAD_MODE, 6946 I915_READ(GEN7_FF_THREAD_MODE) & 6947 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); 6948 6949 /* WaDisableSemaphoreAndSyncFlipWait:chv */ 6950 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, 6951 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); 6952 6953 /* WaDisableCSUnitClockGating:chv */ 6954 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | 6955 GEN6_CSUNIT_CLOCK_GATE_DISABLE); 6956 6957 /* WaDisableSDEUnitClockGating:chv */ 6958 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | 6959 GEN8_SDEUNIT_CLOCK_GATE_DISABLE); 6960 6961 /* 6962 * GTT cache may not work with big pages, so if those 6963 * are ever enabled GTT cache may need to be disabled. 6964 */ 6965 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); 6966 } 6967 6968 static void g4x_init_clock_gating(struct drm_device *dev) 6969 { 6970 struct drm_i915_private *dev_priv = dev->dev_private; 6971 uint32_t dspclk_gate; 6972 6973 I915_WRITE(RENCLK_GATE_D1, 0); 6974 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 6975 GS_UNIT_CLOCK_GATE_DISABLE | 6976 CL_UNIT_CLOCK_GATE_DISABLE); 6977 I915_WRITE(RAMCLK_GATE_D, 0); 6978 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | 6979 OVRUNIT_CLOCK_GATE_DISABLE | 6980 OVCUNIT_CLOCK_GATE_DISABLE; 6981 if (IS_GM45(dev)) 6982 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; 6983 I915_WRITE(DSPCLK_GATE_D, dspclk_gate); 6984 6985 /* WaDisableRenderCachePipelinedFlush */ 6986 I915_WRITE(CACHE_MODE_0, 6987 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); 6988 6989 /* WaDisable_RenderCache_OperationalFlush:g4x */ 6990 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 6991 6992 g4x_disable_trickle_feed(dev); 6993 } 6994 6995 static void crestline_init_clock_gating(struct drm_device *dev) 6996 { 6997 struct drm_i915_private *dev_priv = dev->dev_private; 6998 6999 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); 7000 I915_WRITE(RENCLK_GATE_D2, 0); 7001 I915_WRITE(DSPCLK_GATE_D, 0); 7002 I915_WRITE(RAMCLK_GATE_D, 0); 7003 I915_WRITE16(DEUC, 0); 7004 I915_WRITE(MI_ARB_STATE, 7005 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7006 7007 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7008 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7009 } 7010 7011 static void broadwater_init_clock_gating(struct drm_device *dev) 7012 { 7013 struct drm_i915_private *dev_priv = dev->dev_private; 7014 7015 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | 7016 I965_RCC_CLOCK_GATE_DISABLE | 7017 I965_RCPB_CLOCK_GATE_DISABLE | 7018 I965_ISC_CLOCK_GATE_DISABLE | 7019 I965_FBC_CLOCK_GATE_DISABLE); 7020 I915_WRITE(RENCLK_GATE_D2, 0); 7021 I915_WRITE(MI_ARB_STATE, 7022 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7023 7024 /* WaDisable_RenderCache_OperationalFlush:gen4 */ 7025 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); 7026 } 7027 7028 static void gen3_init_clock_gating(struct drm_device *dev) 7029 { 7030 struct drm_i915_private *dev_priv = dev->dev_private; 7031 u32 dstate = I915_READ(D_STATE); 7032 7033 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | 7034 DSTATE_DOT_CLOCK_GATING; 7035 I915_WRITE(D_STATE, dstate); 7036 7037 if (IS_PINEVIEW(dev)) 7038 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); 7039 7040 /* IIR "flip pending" means done if this bit is set */ 7041 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); 7042 7043 /* interrupts should cause a wake up from C3 */ 7044 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); 7045 7046 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ 7047 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); 7048 7049 I915_WRITE(MI_ARB_STATE, 7050 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); 7051 } 7052 7053 static void i85x_init_clock_gating(struct drm_device *dev) 7054 { 7055 struct drm_i915_private *dev_priv = dev->dev_private; 7056 7057 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); 7058 7059 /* interrupts should cause a wake up from C3 */ 7060 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | 7061 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); 7062 7063 I915_WRITE(MEM_MODE, 7064 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); 7065 } 7066 7067 static void i830_init_clock_gating(struct drm_device *dev) 7068 { 7069 struct drm_i915_private *dev_priv = dev->dev_private; 7070 7071 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 7072 7073 I915_WRITE(MEM_MODE, 7074 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | 7075 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); 7076 } 7077 7078 void intel_init_clock_gating(struct drm_device *dev) 7079 { 7080 struct drm_i915_private *dev_priv = dev->dev_private; 7081 7082 if (dev_priv->display.init_clock_gating) 7083 dev_priv->display.init_clock_gating(dev); 7084 } 7085 7086 void intel_suspend_hw(struct drm_device *dev) 7087 { 7088 if (HAS_PCH_LPT(dev)) 7089 lpt_suspend_hw(dev); 7090 } 7091 7092 /* Set up chip specific power management-related functions */ 7093 void intel_init_pm(struct drm_device *dev) 7094 { 7095 struct drm_i915_private *dev_priv = dev->dev_private; 7096 7097 intel_fbc_init(dev_priv); 7098 7099 /* For cxsr */ 7100 if (IS_PINEVIEW(dev)) 7101 i915_pineview_get_mem_freq(dev); 7102 else if (IS_GEN5(dev)) 7103 i915_ironlake_get_mem_freq(dev); 7104 7105 /* For FIFO watermark updates */ 7106 if (INTEL_INFO(dev)->gen >= 9) { 7107 skl_setup_wm_latency(dev); 7108 7109 if (IS_BROXTON(dev)) 7110 dev_priv->display.init_clock_gating = 7111 bxt_init_clock_gating; 7112 else if (IS_SKYLAKE(dev)) 7113 dev_priv->display.init_clock_gating = 7114 skl_init_clock_gating; 7115 dev_priv->display.update_wm = skl_update_wm; 7116 dev_priv->display.update_sprite_wm = skl_update_sprite_wm; 7117 } else if (HAS_PCH_SPLIT(dev)) { 7118 ilk_setup_wm_latency(dev); 7119 7120 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && 7121 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || 7122 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && 7123 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { 7124 dev_priv->display.update_wm = ilk_update_wm; 7125 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; 7126 } else { 7127 DRM_DEBUG_KMS("Failed to read display plane latency. " 7128 "Disable CxSR\n"); 7129 } 7130 7131 if (IS_GEN5(dev)) 7132 dev_priv->display.init_clock_gating = ironlake_init_clock_gating; 7133 else if (IS_GEN6(dev)) 7134 dev_priv->display.init_clock_gating = gen6_init_clock_gating; 7135 else if (IS_IVYBRIDGE(dev)) 7136 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; 7137 else if (IS_HASWELL(dev)) 7138 dev_priv->display.init_clock_gating = haswell_init_clock_gating; 7139 else if (INTEL_INFO(dev)->gen == 8) 7140 dev_priv->display.init_clock_gating = broadwell_init_clock_gating; 7141 } else if (IS_CHERRYVIEW(dev)) { 7142 vlv_setup_wm_latency(dev); 7143 7144 dev_priv->display.update_wm = vlv_update_wm; 7145 dev_priv->display.init_clock_gating = 7146 cherryview_init_clock_gating; 7147 } else if (IS_VALLEYVIEW(dev)) { 7148 vlv_setup_wm_latency(dev); 7149 7150 dev_priv->display.update_wm = vlv_update_wm; 7151 dev_priv->display.init_clock_gating = 7152 valleyview_init_clock_gating; 7153 } else if (IS_PINEVIEW(dev)) { 7154 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), 7155 dev_priv->is_ddr3, 7156 dev_priv->fsb_freq, 7157 dev_priv->mem_freq)) { 7158 DRM_INFO("failed to find known CxSR latency " 7159 "(found ddr%s fsb freq %d, mem freq %d), " 7160 "disabling CxSR\n", 7161 (dev_priv->is_ddr3 == 1) ? "3" : "2", 7162 dev_priv->fsb_freq, dev_priv->mem_freq); 7163 /* Disable CxSR and never update its watermark again */ 7164 intel_set_memory_cxsr(dev_priv, false); 7165 dev_priv->display.update_wm = NULL; 7166 } else 7167 dev_priv->display.update_wm = pineview_update_wm; 7168 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7169 } else if (IS_G4X(dev)) { 7170 dev_priv->display.update_wm = g4x_update_wm; 7171 dev_priv->display.init_clock_gating = g4x_init_clock_gating; 7172 } else if (IS_GEN4(dev)) { 7173 dev_priv->display.update_wm = i965_update_wm; 7174 if (IS_CRESTLINE(dev)) 7175 dev_priv->display.init_clock_gating = crestline_init_clock_gating; 7176 else if (IS_BROADWATER(dev)) 7177 dev_priv->display.init_clock_gating = broadwater_init_clock_gating; 7178 } else if (IS_GEN3(dev)) { 7179 dev_priv->display.update_wm = i9xx_update_wm; 7180 dev_priv->display.get_fifo_size = i9xx_get_fifo_size; 7181 dev_priv->display.init_clock_gating = gen3_init_clock_gating; 7182 } else if (IS_GEN2(dev)) { 7183 if (INTEL_INFO(dev)->num_pipes == 1) { 7184 dev_priv->display.update_wm = i845_update_wm; 7185 dev_priv->display.get_fifo_size = i845_get_fifo_size; 7186 } else { 7187 dev_priv->display.update_wm = i9xx_update_wm; 7188 dev_priv->display.get_fifo_size = i830_get_fifo_size; 7189 } 7190 7191 if (IS_I85X(dev) || IS_I865G(dev)) 7192 dev_priv->display.init_clock_gating = i85x_init_clock_gating; 7193 else 7194 dev_priv->display.init_clock_gating = i830_init_clock_gating; 7195 } else { 7196 DRM_ERROR("unexpected fall-through in intel_init_pm\n"); 7197 } 7198 } 7199 7200 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) 7201 { 7202 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7203 7204 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7205 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); 7206 return -EAGAIN; 7207 } 7208 7209 I915_WRITE(GEN6_PCODE_DATA, *val); 7210 I915_WRITE(GEN6_PCODE_DATA1, 0); 7211 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7212 7213 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7214 500)) { 7215 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); 7216 return -ETIMEDOUT; 7217 } 7218 7219 *val = I915_READ(GEN6_PCODE_DATA); 7220 I915_WRITE(GEN6_PCODE_DATA, 0); 7221 7222 return 0; 7223 } 7224 7225 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) 7226 { 7227 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 7228 7229 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { 7230 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); 7231 return -EAGAIN; 7232 } 7233 7234 I915_WRITE(GEN6_PCODE_DATA, val); 7235 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); 7236 7237 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, 7238 500)) { 7239 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); 7240 return -ETIMEDOUT; 7241 } 7242 7243 I915_WRITE(GEN6_PCODE_DATA, 0); 7244 7245 return 0; 7246 } 7247 7248 static int vlv_gpu_freq_div(unsigned int czclk_freq) 7249 { 7250 switch (czclk_freq) { 7251 case 200: 7252 return 10; 7253 case 267: 7254 return 12; 7255 case 320: 7256 case 333: 7257 return 16; 7258 case 400: 7259 return 20; 7260 default: 7261 return -1; 7262 } 7263 } 7264 7265 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) 7266 { 7267 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); 7268 7269 div = vlv_gpu_freq_div(czclk_freq); 7270 if (div < 0) 7271 return div; 7272 7273 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); 7274 } 7275 7276 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) 7277 { 7278 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); 7279 7280 mul = vlv_gpu_freq_div(czclk_freq); 7281 if (mul < 0) 7282 return mul; 7283 7284 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; 7285 } 7286 7287 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) 7288 { 7289 int div, czclk_freq = dev_priv->rps.cz_freq; 7290 7291 div = vlv_gpu_freq_div(czclk_freq) / 2; 7292 if (div < 0) 7293 return div; 7294 7295 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; 7296 } 7297 7298 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) 7299 { 7300 int mul, czclk_freq = dev_priv->rps.cz_freq; 7301 7302 mul = vlv_gpu_freq_div(czclk_freq) / 2; 7303 if (mul < 0) 7304 return mul; 7305 7306 /* CHV needs even values */ 7307 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; 7308 } 7309 7310 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) 7311 { 7312 if (IS_GEN9(dev_priv->dev)) 7313 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER; 7314 else if (IS_CHERRYVIEW(dev_priv->dev)) 7315 return chv_gpu_freq(dev_priv, val); 7316 else if (IS_VALLEYVIEW(dev_priv->dev)) 7317 return byt_gpu_freq(dev_priv, val); 7318 else 7319 return val * GT_FREQUENCY_MULTIPLIER; 7320 } 7321 7322 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) 7323 { 7324 if (IS_GEN9(dev_priv->dev)) 7325 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER; 7326 else if (IS_CHERRYVIEW(dev_priv->dev)) 7327 return chv_freq_opcode(dev_priv, val); 7328 else if (IS_VALLEYVIEW(dev_priv->dev)) 7329 return byt_freq_opcode(dev_priv, val); 7330 else 7331 return val / GT_FREQUENCY_MULTIPLIER; 7332 } 7333 7334 struct request_boost { 7335 struct work_struct work; 7336 struct drm_i915_gem_request *req; 7337 }; 7338 7339 static void __intel_rps_boost_work(struct work_struct *work) 7340 { 7341 struct request_boost *boost = container_of(work, struct request_boost, work); 7342 struct drm_i915_gem_request *req = boost->req; 7343 7344 if (!i915_gem_request_completed(req, true)) 7345 gen6_rps_boost(to_i915(req->ring->dev), NULL, 7346 req->emitted_jiffies); 7347 7348 i915_gem_request_unreference__unlocked(req); 7349 kfree(boost); 7350 } 7351 7352 void intel_queue_rps_boost_for_request(struct drm_device *dev, 7353 struct drm_i915_gem_request *req) 7354 { 7355 struct request_boost *boost; 7356 7357 if (req == NULL || INTEL_INFO(dev)->gen < 6) 7358 return; 7359 7360 if (i915_gem_request_completed(req, true)) 7361 return; 7362 7363 boost = kmalloc(sizeof(*boost), M_DRM, M_NOWAIT); 7364 if (boost == NULL) 7365 return; 7366 7367 i915_gem_request_reference(req); 7368 boost->req = req; 7369 7370 INIT_WORK(&boost->work, __intel_rps_boost_work); 7371 queue_work(to_i915(dev)->wq, &boost->work); 7372 } 7373 7374 void intel_pm_setup(struct drm_device *dev) 7375 { 7376 struct drm_i915_private *dev_priv = dev->dev_private; 7377 7378 lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE); 7379 lockinit(&dev_priv->rps.client_lock, "i915rcl", 0, LK_CANRECURSE); 7380 7381 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, 7382 intel_gen6_powersave_work); 7383 INIT_LIST_HEAD(&dev_priv->rps.clients); 7384 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link); 7385 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link); 7386 7387 dev_priv->pm.suspended = false; 7388 } 7389