1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Ben Widawsky <ben@bwidawsk.net> 25 * Michel Thierry <michel.thierry@intel.com> 26 * Thomas Daniel <thomas.daniel@intel.com> 27 * Oscar Mateo <oscar.mateo@intel.com> 28 * 29 */ 30 31 /** 32 * DOC: Logical Rings, Logical Ring Contexts and Execlists 33 * 34 * Motivation: 35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". 36 * These expanded contexts enable a number of new abilities, especially 37 * "Execlists" (also implemented in this file). 38 * 39 * One of the main differences with the legacy HW contexts is that logical 40 * ring contexts incorporate many more things to the context's state, like 41 * PDPs or ringbuffer control registers: 42 * 43 * The reason why PDPs are included in the context is straightforward: as 44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs 45 * contained there mean you don't need to do a ppgtt->switch_mm yourself, 46 * instead, the GPU will do it for you on the context switch. 47 * 48 * But, what about the ringbuffer control registers (head, tail, etc..)? 49 * shouldn't we just need a set of those per engine command streamer? This is 50 * where the name "Logical Rings" starts to make sense: by virtualizing the 51 * rings, the engine cs shifts to a new "ring buffer" with every context 52 * switch. When you want to submit a workload to the GPU you: A) choose your 53 * context, B) find its appropriate virtualized ring, C) write commands to it 54 * and then, finally, D) tell the GPU to switch to that context. 55 * 56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch 57 * to a contexts is via a context execution list, ergo "Execlists". 58 * 59 * LRC implementation: 60 * Regarding the creation of contexts, we have: 61 * 62 * - One global default context. 63 * - One local default context for each opened fd. 64 * - One local extra context for each context create ioctl call. 65 * 66 * Now that ringbuffers belong per-context (and not per-engine, like before) 67 * and that contexts are uniquely tied to a given engine (and not reusable, 68 * like before) we need: 69 * 70 * - One ringbuffer per-engine inside each context. 71 * - One backing object per-engine inside each context. 72 * 73 * The global default context starts its life with these new objects fully 74 * allocated and populated. The local default context for each opened fd is 75 * more complex, because we don't know at creation time which engine is going 76 * to use them. To handle this, we have implemented a deferred creation of LR 77 * contexts: 78 * 79 * The local context starts its life as a hollow or blank holder, that only 80 * gets populated for a given engine once we receive an execbuffer. If later 81 * on we receive another execbuffer ioctl for the same context but a different 82 * engine, we allocate/populate a new ringbuffer and context backing object and 83 * so on. 84 * 85 * Finally, regarding local contexts created using the ioctl call: as they are 86 * only allowed with the render ring, we can allocate & populate them right 87 * away (no need to defer anything, at least for now). 88 * 89 * Execlists implementation: 90 * Execlists are the new method by which, on gen8+ hardware, workloads are 91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method). 92 * This method works as follows: 93 * 94 * When a request is committed, its commands (the BB start and any leading or 95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer 96 * for the appropriate context. The tail pointer in the hardware context is not 97 * updated at this time, but instead, kept by the driver in the ringbuffer 98 * structure. A structure representing this request is added to a request queue 99 * for the appropriate engine: this structure contains a copy of the context's 100 * tail after the request was written to the ring buffer and a pointer to the 101 * context itself. 102 * 103 * If the engine's request queue was empty before the request was added, the 104 * queue is processed immediately. Otherwise the queue will be processed during 105 * a context switch interrupt. In any case, elements on the queue will get sent 106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a 107 * globally unique 20-bits submission ID. 108 * 109 * When execution of a request completes, the GPU updates the context status 110 * buffer with a context complete event and generates a context switch interrupt. 111 * During the interrupt handling, the driver examines the events in the buffer: 112 * for each context complete event, if the announced ID matches that on the head 113 * of the request queue, then that request is retired and removed from the queue. 114 * 115 * After processing, if any requests were retired and the queue is not empty 116 * then a new execution list can be submitted. The two requests at the front of 117 * the queue are next to be submitted but since a context may not occur twice in 118 * an execution list, if subsequent requests have the same ID as the first then 119 * the two requests must be combined. This is done simply by discarding requests 120 * at the head of the queue until either only one requests is left (in which case 121 * we use a NULL second context) or the first two requests have unique IDs. 122 * 123 * By always executing the first two requests in the queue the driver ensures 124 * that the GPU is kept as busy as possible. In the case where a single context 125 * completes but a second context is still executing, the request for this second 126 * context will be at the head of the queue when we remove the first one. This 127 * request will then be resubmitted along with a new request for a different context, 128 * which will cause the hardware to continue executing the second request and queue 129 * the new request (the GPU detects the condition of a context getting preempted 130 * with the same context and optimizes the context switch flow by not doing 131 * preemption, but just sampling the new tail pointer). 132 * 133 */ 134 135 #include <drm/drmP.h> 136 #include <drm/i915_drm.h> 137 #include "i915_drv.h" 138 #include "intel_drv.h" 139 140 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) 141 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) 142 #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) 143 144 #define RING_EXECLIST_QFULL (1 << 0x2) 145 #define RING_EXECLIST1_VALID (1 << 0x3) 146 #define RING_EXECLIST0_VALID (1 << 0x4) 147 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) 148 #define RING_EXECLIST1_ACTIVE (1 << 0x11) 149 #define RING_EXECLIST0_ACTIVE (1 << 0x12) 150 151 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) 152 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) 153 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) 154 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) 155 #define GEN8_CTX_STATUS_COMPLETE (1 << 4) 156 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) 157 158 #define CTX_LRI_HEADER_0 0x01 159 #define CTX_CONTEXT_CONTROL 0x02 160 #define CTX_RING_HEAD 0x04 161 #define CTX_RING_TAIL 0x06 162 #define CTX_RING_BUFFER_START 0x08 163 #define CTX_RING_BUFFER_CONTROL 0x0a 164 #define CTX_BB_HEAD_U 0x0c 165 #define CTX_BB_HEAD_L 0x0e 166 #define CTX_BB_STATE 0x10 167 #define CTX_SECOND_BB_HEAD_U 0x12 168 #define CTX_SECOND_BB_HEAD_L 0x14 169 #define CTX_SECOND_BB_STATE 0x16 170 #define CTX_BB_PER_CTX_PTR 0x18 171 #define CTX_RCS_INDIRECT_CTX 0x1a 172 #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c 173 #define CTX_LRI_HEADER_1 0x21 174 #define CTX_CTX_TIMESTAMP 0x22 175 #define CTX_PDP3_UDW 0x24 176 #define CTX_PDP3_LDW 0x26 177 #define CTX_PDP2_UDW 0x28 178 #define CTX_PDP2_LDW 0x2a 179 #define CTX_PDP1_UDW 0x2c 180 #define CTX_PDP1_LDW 0x2e 181 #define CTX_PDP0_UDW 0x30 182 #define CTX_PDP0_LDW 0x32 183 #define CTX_LRI_HEADER_2 0x41 184 #define CTX_R_PWR_CLK_STATE 0x42 185 #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 186 187 #define GEN8_CTX_VALID (1<<0) 188 #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) 189 #define GEN8_CTX_FORCE_RESTORE (1<<2) 190 #define GEN8_CTX_L3LLC_COHERENT (1<<5) 191 #define GEN8_CTX_PRIVILEGE (1<<8) 192 193 #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ 194 const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \ 195 ppgtt->pdp.page_directory[n]->daddr : \ 196 ppgtt->scratch_pd->daddr; \ 197 reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ 198 reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ 199 } 200 201 enum { 202 ADVANCED_CONTEXT = 0, 203 LEGACY_CONTEXT, 204 ADVANCED_AD_CONTEXT, 205 LEGACY_64B_CONTEXT 206 }; 207 #define GEN8_CTX_MODE_SHIFT 3 208 enum { 209 FAULT_AND_HANG = 0, 210 FAULT_AND_HALT, /* Debug only */ 211 FAULT_AND_STREAM, 212 FAULT_AND_CONTINUE /* Unsupported */ 213 }; 214 #define GEN8_CTX_ID_SHIFT 32 215 216 static int intel_lr_context_pin(struct intel_engine_cs *ring, 217 struct intel_context *ctx); 218 219 /** 220 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists 221 * @dev: DRM device. 222 * @enable_execlists: value of i915.enable_execlists module parameter. 223 * 224 * Only certain platforms support Execlists (the prerequisites being 225 * support for Logical Ring Contexts and Aliasing PPGTT or better). 226 * 227 * Return: 1 if Execlists is supported and has to be enabled. 228 */ 229 int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) 230 { 231 WARN_ON(i915.enable_ppgtt == -1); 232 233 if (INTEL_INFO(dev)->gen >= 9) 234 return 1; 235 236 if (enable_execlists == 0) 237 return 0; 238 239 if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && 240 i915.use_mmio_flip >= 0) 241 return 1; 242 243 return 0; 244 } 245 246 /** 247 * intel_execlists_ctx_id() - get the Execlists Context ID 248 * @ctx_obj: Logical Ring Context backing object. 249 * 250 * Do not confuse with ctx->id! Unfortunately we have a name overload 251 * here: the old context ID we pass to userspace as a handler so that 252 * they can refer to a context, and the new context ID we pass to the 253 * ELSP so that the GPU can inform us of the context status via 254 * interrupts. 255 * 256 * Return: 20-bits globally unique context ID. 257 */ 258 u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) 259 { 260 u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj); 261 262 /* LRCA is required to be 4K aligned so the more significant 20 bits 263 * are globally unique */ 264 return lrca >> 12; 265 } 266 267 static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring, 268 struct drm_i915_gem_object *ctx_obj) 269 { 270 struct drm_device *dev = ring->dev; 271 uint64_t desc; 272 uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj); 273 274 WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); 275 276 desc = GEN8_CTX_VALID; 277 desc |= LEGACY_CONTEXT << GEN8_CTX_MODE_SHIFT; 278 if (IS_GEN8(ctx_obj->base.dev)) 279 desc |= GEN8_CTX_L3LLC_COHERENT; 280 desc |= GEN8_CTX_PRIVILEGE; 281 desc |= lrca; 282 desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; 283 284 /* TODO: WaDisableLiteRestore when we start using semaphore 285 * signalling between Command Streamers */ 286 /* desc |= GEN8_CTX_FORCE_RESTORE; */ 287 288 /* WaEnableForceRestoreInCtxtDescForVCS:skl */ 289 if (IS_GEN9(dev) && 290 INTEL_REVID(dev) <= SKL_REVID_B0 && 291 (ring->id == BCS || ring->id == VCS || 292 ring->id == VECS || ring->id == VCS2)) 293 desc |= GEN8_CTX_FORCE_RESTORE; 294 295 return desc; 296 } 297 298 static void execlists_elsp_write(struct intel_engine_cs *ring, 299 struct drm_i915_gem_object *ctx_obj0, 300 struct drm_i915_gem_object *ctx_obj1) 301 { 302 struct drm_device *dev = ring->dev; 303 struct drm_i915_private *dev_priv = dev->dev_private; 304 uint64_t temp = 0; 305 uint32_t desc[4]; 306 307 /* XXX: You must always write both descriptors in the order below. */ 308 if (ctx_obj1) 309 temp = execlists_ctx_descriptor(ring, ctx_obj1); 310 else 311 temp = 0; 312 desc[1] = (u32)(temp >> 32); 313 desc[0] = (u32)temp; 314 315 temp = execlists_ctx_descriptor(ring, ctx_obj0); 316 desc[3] = (u32)(temp >> 32); 317 desc[2] = (u32)temp; 318 319 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 320 intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); 321 I915_WRITE_FW(RING_ELSP(ring), desc[1]); 322 I915_WRITE_FW(RING_ELSP(ring), desc[0]); 323 I915_WRITE_FW(RING_ELSP(ring), desc[3]); 324 325 /* The context is automatically loaded after the following */ 326 I915_WRITE_FW(RING_ELSP(ring), desc[2]); 327 328 /* ELSP is a wo register, so use another nearby reg for posting instead */ 329 POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); 330 intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); 331 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 332 } 333 334 static int execlists_update_context(struct drm_i915_gem_object *ctx_obj, 335 struct drm_i915_gem_object *ring_obj, 336 struct i915_hw_ppgtt *ppgtt, 337 u32 tail) 338 { 339 struct vm_page *page; 340 uint32_t *reg_state; 341 342 page = i915_gem_object_get_page(ctx_obj, 1); 343 reg_state = kmap_atomic(page); 344 345 reg_state[CTX_RING_TAIL+1] = tail; 346 reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(ring_obj); 347 348 /* True PPGTT with dynamic page allocation: update PDP registers and 349 * point the unallocated PDPs to the scratch page 350 */ 351 if (ppgtt) { 352 ASSIGN_CTX_PDP(ppgtt, reg_state, 3); 353 ASSIGN_CTX_PDP(ppgtt, reg_state, 2); 354 ASSIGN_CTX_PDP(ppgtt, reg_state, 1); 355 ASSIGN_CTX_PDP(ppgtt, reg_state, 0); 356 } 357 358 kunmap_atomic(reg_state); 359 360 return 0; 361 } 362 363 static void execlists_submit_contexts(struct intel_engine_cs *ring, 364 struct intel_context *to0, u32 tail0, 365 struct intel_context *to1, u32 tail1) 366 { 367 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state; 368 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf; 369 struct drm_i915_gem_object *ctx_obj1 = NULL; 370 struct intel_ringbuffer *ringbuf1 = NULL; 371 372 BUG_ON(!ctx_obj0); 373 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); 374 WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj)); 375 376 execlists_update_context(ctx_obj0, ringbuf0->obj, to0->ppgtt, tail0); 377 378 if (to1) { 379 ringbuf1 = to1->engine[ring->id].ringbuf; 380 ctx_obj1 = to1->engine[ring->id].state; 381 BUG_ON(!ctx_obj1); 382 WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); 383 WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj)); 384 385 execlists_update_context(ctx_obj1, ringbuf1->obj, to1->ppgtt, tail1); 386 } 387 388 execlists_elsp_write(ring, ctx_obj0, ctx_obj1); 389 } 390 391 static void execlists_context_unqueue(struct intel_engine_cs *ring) 392 { 393 struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; 394 struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; 395 396 assert_spin_locked(&ring->execlist_lock); 397 398 /* 399 * If irqs are not active generate a warning as batches that finish 400 * without the irqs may get lost and a GPU Hang may occur. 401 */ 402 WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); 403 404 if (list_empty(&ring->execlist_queue)) 405 return; 406 407 /* Try to read in pairs */ 408 list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, 409 execlist_link) { 410 if (!req0) { 411 req0 = cursor; 412 } else if (req0->ctx == cursor->ctx) { 413 /* Same ctx: ignore first request, as second request 414 * will update tail past first request's workload */ 415 cursor->elsp_submitted = req0->elsp_submitted; 416 list_del(&req0->execlist_link); 417 list_add_tail(&req0->execlist_link, 418 &ring->execlist_retired_req_list); 419 req0 = cursor; 420 } else { 421 req1 = cursor; 422 break; 423 } 424 } 425 426 if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { 427 /* 428 * WaIdleLiteRestore: make sure we never cause a lite 429 * restore with HEAD==TAIL 430 */ 431 if (req0->elsp_submitted) { 432 /* 433 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL 434 * as we resubmit the request. See gen8_emit_request() 435 * for where we prepare the padding after the end of the 436 * request. 437 */ 438 struct intel_ringbuffer *ringbuf; 439 440 ringbuf = req0->ctx->engine[ring->id].ringbuf; 441 req0->tail += 8; 442 req0->tail &= ringbuf->size - 1; 443 } 444 } 445 446 WARN_ON(req1 && req1->elsp_submitted); 447 448 execlists_submit_contexts(ring, req0->ctx, req0->tail, 449 req1 ? req1->ctx : NULL, 450 req1 ? req1->tail : 0); 451 452 req0->elsp_submitted++; 453 if (req1) 454 req1->elsp_submitted++; 455 } 456 457 static bool execlists_check_remove_request(struct intel_engine_cs *ring, 458 u32 request_id) 459 { 460 struct drm_i915_gem_request *head_req; 461 462 assert_spin_locked(&ring->execlist_lock); 463 464 head_req = list_first_entry_or_null(&ring->execlist_queue, 465 struct drm_i915_gem_request, 466 execlist_link); 467 468 if (head_req != NULL) { 469 struct drm_i915_gem_object *ctx_obj = 470 head_req->ctx->engine[ring->id].state; 471 if (intel_execlists_ctx_id(ctx_obj) == request_id) { 472 WARN(head_req->elsp_submitted == 0, 473 "Never submitted head request\n"); 474 475 if (--head_req->elsp_submitted <= 0) { 476 list_del(&head_req->execlist_link); 477 list_add_tail(&head_req->execlist_link, 478 &ring->execlist_retired_req_list); 479 return true; 480 } 481 } 482 } 483 484 return false; 485 } 486 487 /** 488 * intel_lrc_irq_handler() - handle Context Switch interrupts 489 * @ring: Engine Command Streamer to handle. 490 * 491 * Check the unread Context Status Buffers and manage the submission of new 492 * contexts to the ELSP accordingly. 493 */ 494 void intel_lrc_irq_handler(struct intel_engine_cs *ring) 495 { 496 struct drm_i915_private *dev_priv = ring->dev->dev_private; 497 u32 status_pointer; 498 u8 read_pointer; 499 u8 write_pointer; 500 u32 status; 501 u32 status_id; 502 u32 submit_contexts = 0; 503 504 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); 505 506 read_pointer = ring->next_context_status_buffer; 507 write_pointer = status_pointer & 0x07; 508 if (read_pointer > write_pointer) 509 write_pointer += 6; 510 511 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 512 513 while (read_pointer < write_pointer) { 514 read_pointer++; 515 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 516 (read_pointer % 6) * 8); 517 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 518 (read_pointer % 6) * 8 + 4); 519 520 if (status & GEN8_CTX_STATUS_PREEMPTED) { 521 if (status & GEN8_CTX_STATUS_LITE_RESTORE) { 522 if (execlists_check_remove_request(ring, status_id)) 523 WARN(1, "Lite Restored request removed from queue\n"); 524 } else 525 WARN(1, "Preemption without Lite Restore\n"); 526 } 527 528 if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || 529 (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { 530 if (execlists_check_remove_request(ring, status_id)) 531 submit_contexts++; 532 } 533 } 534 535 if (submit_contexts != 0) 536 execlists_context_unqueue(ring); 537 538 lockmgr(&ring->execlist_lock, LK_RELEASE); 539 540 WARN(submit_contexts > 2, "More than two context complete events?\n"); 541 ring->next_context_status_buffer = write_pointer % 6; 542 543 I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), 544 ((u32)ring->next_context_status_buffer & 0x07) << 8); 545 } 546 547 static int execlists_context_queue(struct intel_engine_cs *ring, 548 struct intel_context *to, 549 u32 tail, 550 struct drm_i915_gem_request *request) 551 { 552 struct drm_i915_gem_request *cursor; 553 int num_elements = 0; 554 555 if (to != ring->default_context) 556 intel_lr_context_pin(ring, to); 557 558 if (!request) { 559 /* 560 * If there isn't a request associated with this submission, 561 * create one as a temporary holder. 562 */ 563 request = kzalloc(sizeof(*request), GFP_KERNEL); 564 if (request == NULL) 565 return -ENOMEM; 566 request->ring = ring; 567 request->ctx = to; 568 kref_init(&request->ref); 569 i915_gem_context_reference(request->ctx); 570 } else { 571 i915_gem_request_reference(request); 572 WARN_ON(to != request->ctx); 573 } 574 request->tail = tail; 575 576 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 577 578 list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) 579 if (++num_elements > 2) 580 break; 581 582 if (num_elements > 2) { 583 struct drm_i915_gem_request *tail_req; 584 585 tail_req = list_last_entry(&ring->execlist_queue, 586 struct drm_i915_gem_request, 587 execlist_link); 588 589 if (to == tail_req->ctx) { 590 WARN(tail_req->elsp_submitted != 0, 591 "More than 2 already-submitted reqs queued\n"); 592 list_del(&tail_req->execlist_link); 593 list_add_tail(&tail_req->execlist_link, 594 &ring->execlist_retired_req_list); 595 } 596 } 597 598 list_add_tail(&request->execlist_link, &ring->execlist_queue); 599 if (num_elements == 0) 600 execlists_context_unqueue(ring); 601 602 lockmgr(&ring->execlist_lock, LK_RELEASE); 603 604 return 0; 605 } 606 607 static int logical_ring_invalidate_all_caches(struct intel_ringbuffer *ringbuf, 608 struct intel_context *ctx) 609 { 610 struct intel_engine_cs *ring = ringbuf->ring; 611 uint32_t flush_domains; 612 int ret; 613 614 flush_domains = 0; 615 if (ring->gpu_caches_dirty) 616 flush_domains = I915_GEM_GPU_DOMAINS; 617 618 ret = ring->emit_flush(ringbuf, ctx, 619 I915_GEM_GPU_DOMAINS, flush_domains); 620 if (ret) 621 return ret; 622 623 ring->gpu_caches_dirty = false; 624 return 0; 625 } 626 627 static int execlists_move_to_gpu(struct intel_ringbuffer *ringbuf, 628 struct intel_context *ctx, 629 struct list_head *vmas) 630 { 631 struct intel_engine_cs *ring = ringbuf->ring; 632 const unsigned other_rings = ~intel_ring_flag(ring); 633 struct i915_vma *vma; 634 uint32_t flush_domains = 0; 635 bool flush_chipset = false; 636 int ret; 637 638 list_for_each_entry(vma, vmas, exec_list) { 639 struct drm_i915_gem_object *obj = vma->obj; 640 641 if (obj->active & other_rings) { 642 ret = i915_gem_object_sync(obj, ring); 643 if (ret) 644 return ret; 645 } 646 647 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) 648 flush_chipset |= i915_gem_clflush_object(obj, false); 649 650 flush_domains |= obj->base.write_domain; 651 } 652 653 if (flush_domains & I915_GEM_DOMAIN_GTT) 654 wmb(); 655 656 /* Unconditionally invalidate gpu caches and ensure that we do flush 657 * any residual writes from the previous batch. 658 */ 659 return logical_ring_invalidate_all_caches(ringbuf, ctx); 660 } 661 662 int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request, 663 struct intel_context *ctx) 664 { 665 int ret; 666 667 if (ctx != request->ring->default_context) { 668 ret = intel_lr_context_pin(request->ring, ctx); 669 if (ret) 670 return ret; 671 } 672 673 request->ringbuf = ctx->engine[request->ring->id].ringbuf; 674 request->ctx = ctx; 675 i915_gem_context_reference(request->ctx); 676 677 return 0; 678 } 679 680 static int logical_ring_wait_for_space(struct intel_ringbuffer *ringbuf, 681 struct intel_context *ctx, 682 int bytes) 683 { 684 struct intel_engine_cs *ring = ringbuf->ring; 685 struct drm_i915_gem_request *request; 686 unsigned space; 687 int ret; 688 689 if (intel_ring_space(ringbuf) >= bytes) 690 return 0; 691 692 list_for_each_entry(request, &ring->request_list, list) { 693 /* 694 * The request queue is per-engine, so can contain requests 695 * from multiple ringbuffers. Here, we must ignore any that 696 * aren't from the ringbuffer we're considering. 697 */ 698 if (request->ringbuf != ringbuf) 699 continue; 700 701 /* Would completion of this request free enough space? */ 702 space = __intel_ring_space(request->postfix, ringbuf->tail, 703 ringbuf->size); 704 if (space >= bytes) 705 break; 706 } 707 708 if (WARN_ON(&request->list == &ring->request_list)) 709 return -ENOSPC; 710 711 ret = i915_wait_request(request); 712 if (ret) 713 return ret; 714 715 ringbuf->space = space; 716 return 0; 717 } 718 719 /* 720 * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload 721 * @ringbuf: Logical Ringbuffer to advance. 722 * 723 * The tail is updated in our logical ringbuffer struct, not in the actual context. What 724 * really happens during submission is that the context and current tail will be placed 725 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that 726 * point, the tail *inside* the context is updated and the ELSP written to. 727 */ 728 static void 729 intel_logical_ring_advance_and_submit(struct intel_ringbuffer *ringbuf, 730 struct intel_context *ctx, 731 struct drm_i915_gem_request *request) 732 { 733 struct intel_engine_cs *ring = ringbuf->ring; 734 735 intel_logical_ring_advance(ringbuf); 736 737 if (intel_ring_stopped(ring)) 738 return; 739 740 execlists_context_queue(ring, ctx, ringbuf->tail, request); 741 } 742 743 static int logical_ring_wrap_buffer(struct intel_ringbuffer *ringbuf, 744 struct intel_context *ctx) 745 { 746 uint32_t __iomem *virt; 747 int rem = ringbuf->size - ringbuf->tail; 748 749 if (ringbuf->space < rem) { 750 int ret = logical_ring_wait_for_space(ringbuf, ctx, rem); 751 752 if (ret) 753 return ret; 754 } 755 756 virt = (uint32_t *)(ringbuf->virtual_start + ringbuf->tail); 757 rem /= 4; 758 while (rem--) 759 iowrite32(MI_NOOP, virt++); 760 761 ringbuf->tail = 0; 762 intel_ring_update_space(ringbuf); 763 764 return 0; 765 } 766 767 static int logical_ring_prepare(struct intel_ringbuffer *ringbuf, 768 struct intel_context *ctx, int bytes) 769 { 770 int ret; 771 772 if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { 773 ret = logical_ring_wrap_buffer(ringbuf, ctx); 774 if (unlikely(ret)) 775 return ret; 776 } 777 778 if (unlikely(ringbuf->space < bytes)) { 779 ret = logical_ring_wait_for_space(ringbuf, ctx, bytes); 780 if (unlikely(ret)) 781 return ret; 782 } 783 784 return 0; 785 } 786 787 /** 788 * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands 789 * 790 * @ringbuf: Logical ringbuffer. 791 * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. 792 * 793 * The ringbuffer might not be ready to accept the commands right away (maybe it needs to 794 * be wrapped, or wait a bit for the tail to be updated). This function takes care of that 795 * and also preallocates a request (every workload submission is still mediated through 796 * requests, same as it did with legacy ringbuffer submission). 797 * 798 * Return: non-zero if the ringbuffer is not ready to be written to. 799 */ 800 static int intel_logical_ring_begin(struct intel_ringbuffer *ringbuf, 801 struct intel_context *ctx, int num_dwords) 802 { 803 struct intel_engine_cs *ring = ringbuf->ring; 804 struct drm_device *dev = ring->dev; 805 struct drm_i915_private *dev_priv = dev->dev_private; 806 int ret; 807 808 ret = i915_gem_check_wedge(&dev_priv->gpu_error, 809 dev_priv->mm.interruptible); 810 if (ret) 811 return ret; 812 813 ret = logical_ring_prepare(ringbuf, ctx, num_dwords * sizeof(uint32_t)); 814 if (ret) 815 return ret; 816 817 /* Preallocate the olr before touching the ring */ 818 ret = i915_gem_request_alloc(ring, ctx); 819 if (ret) 820 return ret; 821 822 ringbuf->space -= num_dwords * sizeof(uint32_t); 823 return 0; 824 } 825 826 /** 827 * execlists_submission() - submit a batchbuffer for execution, Execlists style 828 * @dev: DRM device. 829 * @file: DRM file. 830 * @ring: Engine Command Streamer to submit to. 831 * @ctx: Context to employ for this submission. 832 * @args: execbuffer call arguments. 833 * @vmas: list of vmas. 834 * @batch_obj: the batchbuffer to submit. 835 * @exec_start: batchbuffer start virtual address pointer. 836 * @dispatch_flags: translated execbuffer call flags. 837 * 838 * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts 839 * away the submission details of the execbuffer ioctl call. 840 * 841 * Return: non-zero if the submission fails. 842 */ 843 int intel_execlists_submission(struct drm_device *dev, struct drm_file *file, 844 struct intel_engine_cs *ring, 845 struct intel_context *ctx, 846 struct drm_i915_gem_execbuffer2 *args, 847 struct list_head *vmas, 848 struct drm_i915_gem_object *batch_obj, 849 u64 exec_start, u32 dispatch_flags) 850 { 851 struct drm_i915_private *dev_priv = dev->dev_private; 852 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 853 int instp_mode; 854 u32 instp_mask; 855 int ret; 856 857 instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; 858 instp_mask = I915_EXEC_CONSTANTS_MASK; 859 switch (instp_mode) { 860 case I915_EXEC_CONSTANTS_REL_GENERAL: 861 case I915_EXEC_CONSTANTS_ABSOLUTE: 862 case I915_EXEC_CONSTANTS_REL_SURFACE: 863 if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { 864 DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); 865 return -EINVAL; 866 } 867 868 if (instp_mode != dev_priv->relative_constants_mode) { 869 if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { 870 DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); 871 return -EINVAL; 872 } 873 874 /* The HW changed the meaning on this bit on gen6 */ 875 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; 876 } 877 break; 878 default: 879 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); 880 return -EINVAL; 881 } 882 883 if (args->num_cliprects != 0) { 884 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); 885 return -EINVAL; 886 } else { 887 if (args->DR4 == 0xffffffff) { 888 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); 889 args->DR4 = 0; 890 } 891 892 if (args->DR1 || args->DR4 || args->cliprects_ptr) { 893 DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); 894 return -EINVAL; 895 } 896 } 897 898 if (args->flags & I915_EXEC_GEN7_SOL_RESET) { 899 DRM_DEBUG("sol reset is gen7 only\n"); 900 return -EINVAL; 901 } 902 903 ret = execlists_move_to_gpu(ringbuf, ctx, vmas); 904 if (ret) 905 return ret; 906 907 if (ring == &dev_priv->ring[RCS] && 908 instp_mode != dev_priv->relative_constants_mode) { 909 ret = intel_logical_ring_begin(ringbuf, ctx, 4); 910 if (ret) 911 return ret; 912 913 intel_logical_ring_emit(ringbuf, MI_NOOP); 914 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); 915 intel_logical_ring_emit(ringbuf, INSTPM); 916 intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); 917 intel_logical_ring_advance(ringbuf); 918 919 dev_priv->relative_constants_mode = instp_mode; 920 } 921 922 ret = ring->emit_bb_start(ringbuf, ctx, exec_start, dispatch_flags); 923 if (ret) 924 return ret; 925 926 trace_i915_gem_ring_dispatch(intel_ring_get_request(ring), dispatch_flags); 927 928 i915_gem_execbuffer_move_to_active(vmas, ring); 929 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj); 930 931 return 0; 932 } 933 934 void intel_execlists_retire_requests(struct intel_engine_cs *ring) 935 { 936 struct drm_i915_gem_request *req, *tmp; 937 struct list_head retired_list; 938 939 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 940 if (list_empty(&ring->execlist_retired_req_list)) 941 return; 942 943 INIT_LIST_HEAD(&retired_list); 944 lockmgr(&ring->execlist_lock, LK_EXCLUSIVE); 945 list_replace_init(&ring->execlist_retired_req_list, &retired_list); 946 lockmgr(&ring->execlist_lock, LK_RELEASE); 947 948 list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { 949 struct intel_context *ctx = req->ctx; 950 struct drm_i915_gem_object *ctx_obj = 951 ctx->engine[ring->id].state; 952 953 if (ctx_obj && (ctx != ring->default_context)) 954 intel_lr_context_unpin(ring, ctx); 955 list_del(&req->execlist_link); 956 i915_gem_request_unreference(req); 957 } 958 } 959 960 void intel_logical_ring_stop(struct intel_engine_cs *ring) 961 { 962 struct drm_i915_private *dev_priv = ring->dev->dev_private; 963 int ret; 964 965 if (!intel_ring_initialized(ring)) 966 return; 967 968 ret = intel_ring_idle(ring); 969 if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) 970 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", 971 ring->name, ret); 972 973 /* TODO: Is this correct with Execlists enabled? */ 974 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); 975 if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { 976 DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); 977 return; 978 } 979 I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); 980 } 981 982 int logical_ring_flush_all_caches(struct intel_ringbuffer *ringbuf, 983 struct intel_context *ctx) 984 { 985 struct intel_engine_cs *ring = ringbuf->ring; 986 int ret; 987 988 if (!ring->gpu_caches_dirty) 989 return 0; 990 991 ret = ring->emit_flush(ringbuf, ctx, 0, I915_GEM_GPU_DOMAINS); 992 if (ret) 993 return ret; 994 995 ring->gpu_caches_dirty = false; 996 return 0; 997 } 998 999 static int intel_lr_context_pin(struct intel_engine_cs *ring, 1000 struct intel_context *ctx) 1001 { 1002 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; 1003 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 1004 int ret = 0; 1005 1006 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 1007 if (ctx->engine[ring->id].pin_count++ == 0) { 1008 ret = i915_gem_obj_ggtt_pin(ctx_obj, 1009 GEN8_LR_CONTEXT_ALIGN, 0); 1010 if (ret) 1011 goto reset_pin_count; 1012 1013 ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); 1014 if (ret) 1015 goto unpin_ctx_obj; 1016 1017 ctx_obj->dirty = true; 1018 } 1019 1020 return ret; 1021 1022 unpin_ctx_obj: 1023 i915_gem_object_ggtt_unpin(ctx_obj); 1024 reset_pin_count: 1025 ctx->engine[ring->id].pin_count = 0; 1026 1027 return ret; 1028 } 1029 1030 void intel_lr_context_unpin(struct intel_engine_cs *ring, 1031 struct intel_context *ctx) 1032 { 1033 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; 1034 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 1035 1036 if (ctx_obj) { 1037 WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); 1038 if (--ctx->engine[ring->id].pin_count == 0) { 1039 intel_unpin_ringbuffer_obj(ringbuf); 1040 i915_gem_object_ggtt_unpin(ctx_obj); 1041 } 1042 } 1043 } 1044 1045 static int intel_logical_ring_workarounds_emit(struct intel_engine_cs *ring, 1046 struct intel_context *ctx) 1047 { 1048 int ret, i; 1049 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 1050 struct drm_device *dev = ring->dev; 1051 struct drm_i915_private *dev_priv = dev->dev_private; 1052 struct i915_workarounds *w = &dev_priv->workarounds; 1053 1054 if (WARN_ON_ONCE(w->count == 0)) 1055 return 0; 1056 1057 ring->gpu_caches_dirty = true; 1058 ret = logical_ring_flush_all_caches(ringbuf, ctx); 1059 if (ret) 1060 return ret; 1061 1062 ret = intel_logical_ring_begin(ringbuf, ctx, w->count * 2 + 2); 1063 if (ret) 1064 return ret; 1065 1066 intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); 1067 for (i = 0; i < w->count; i++) { 1068 intel_logical_ring_emit(ringbuf, w->reg[i].addr); 1069 intel_logical_ring_emit(ringbuf, w->reg[i].value); 1070 } 1071 intel_logical_ring_emit(ringbuf, MI_NOOP); 1072 1073 intel_logical_ring_advance(ringbuf); 1074 1075 ring->gpu_caches_dirty = true; 1076 ret = logical_ring_flush_all_caches(ringbuf, ctx); 1077 if (ret) 1078 return ret; 1079 1080 return 0; 1081 } 1082 1083 static int gen8_init_common_ring(struct intel_engine_cs *ring) 1084 { 1085 struct drm_device *dev = ring->dev; 1086 struct drm_i915_private *dev_priv = dev->dev_private; 1087 1088 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); 1089 I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); 1090 1091 if (ring->status_page.obj) { 1092 I915_WRITE(RING_HWS_PGA(ring->mmio_base), 1093 (u32)ring->status_page.gfx_addr); 1094 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); 1095 } 1096 1097 I915_WRITE(RING_MODE_GEN7(ring), 1098 _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | 1099 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); 1100 POSTING_READ(RING_MODE_GEN7(ring)); 1101 ring->next_context_status_buffer = 0; 1102 DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); 1103 1104 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); 1105 1106 return 0; 1107 } 1108 1109 static int gen8_init_render_ring(struct intel_engine_cs *ring) 1110 { 1111 struct drm_device *dev = ring->dev; 1112 struct drm_i915_private *dev_priv = dev->dev_private; 1113 int ret; 1114 1115 ret = gen8_init_common_ring(ring); 1116 if (ret) 1117 return ret; 1118 1119 /* We need to disable the AsyncFlip performance optimisations in order 1120 * to use MI_WAIT_FOR_EVENT within the CS. It should already be 1121 * programmed to '1' on all products. 1122 * 1123 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv 1124 */ 1125 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); 1126 1127 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); 1128 1129 return init_workarounds_ring(ring); 1130 } 1131 1132 static int gen9_init_render_ring(struct intel_engine_cs *ring) 1133 { 1134 int ret; 1135 1136 ret = gen8_init_common_ring(ring); 1137 if (ret) 1138 return ret; 1139 1140 return init_workarounds_ring(ring); 1141 } 1142 1143 static int gen8_emit_bb_start(struct intel_ringbuffer *ringbuf, 1144 struct intel_context *ctx, 1145 u64 offset, unsigned dispatch_flags) 1146 { 1147 bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); 1148 int ret; 1149 1150 ret = intel_logical_ring_begin(ringbuf, ctx, 4); 1151 if (ret) 1152 return ret; 1153 1154 /* FIXME(BDW): Address space and security selectors. */ 1155 intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); 1156 intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); 1157 intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); 1158 intel_logical_ring_emit(ringbuf, MI_NOOP); 1159 intel_logical_ring_advance(ringbuf); 1160 1161 return 0; 1162 } 1163 1164 static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) 1165 { 1166 struct drm_device *dev = ring->dev; 1167 struct drm_i915_private *dev_priv = dev->dev_private; 1168 1169 if (WARN_ON(!intel_irqs_enabled(dev_priv))) 1170 return false; 1171 1172 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1173 if (ring->irq_refcount++ == 0) { 1174 I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); 1175 POSTING_READ(RING_IMR(ring->mmio_base)); 1176 } 1177 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1178 1179 return true; 1180 } 1181 1182 static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) 1183 { 1184 struct drm_device *dev = ring->dev; 1185 struct drm_i915_private *dev_priv = dev->dev_private; 1186 1187 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1188 if (--ring->irq_refcount == 0) { 1189 I915_WRITE_IMR(ring, ~ring->irq_keep_mask); 1190 POSTING_READ(RING_IMR(ring->mmio_base)); 1191 } 1192 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1193 } 1194 1195 static int gen8_emit_flush(struct intel_ringbuffer *ringbuf, 1196 struct intel_context *ctx, 1197 u32 invalidate_domains, 1198 u32 unused) 1199 { 1200 struct intel_engine_cs *ring = ringbuf->ring; 1201 struct drm_device *dev = ring->dev; 1202 struct drm_i915_private *dev_priv = dev->dev_private; 1203 uint32_t cmd; 1204 int ret; 1205 1206 ret = intel_logical_ring_begin(ringbuf, ctx, 4); 1207 if (ret) 1208 return ret; 1209 1210 cmd = MI_FLUSH_DW + 1; 1211 1212 /* We always require a command barrier so that subsequent 1213 * commands, such as breadcrumb interrupts, are strictly ordered 1214 * wrt the contents of the write cache being flushed to memory 1215 * (and thus being coherent from the CPU). 1216 */ 1217 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; 1218 1219 if (invalidate_domains & I915_GEM_GPU_DOMAINS) { 1220 cmd |= MI_INVALIDATE_TLB; 1221 if (ring == &dev_priv->ring[VCS]) 1222 cmd |= MI_INVALIDATE_BSD; 1223 } 1224 1225 intel_logical_ring_emit(ringbuf, cmd); 1226 intel_logical_ring_emit(ringbuf, 1227 I915_GEM_HWS_SCRATCH_ADDR | 1228 MI_FLUSH_DW_USE_GTT); 1229 intel_logical_ring_emit(ringbuf, 0); /* upper addr */ 1230 intel_logical_ring_emit(ringbuf, 0); /* value */ 1231 intel_logical_ring_advance(ringbuf); 1232 1233 return 0; 1234 } 1235 1236 static int gen8_emit_flush_render(struct intel_ringbuffer *ringbuf, 1237 struct intel_context *ctx, 1238 u32 invalidate_domains, 1239 u32 flush_domains) 1240 { 1241 struct intel_engine_cs *ring = ringbuf->ring; 1242 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; 1243 bool vf_flush_wa; 1244 u32 flags = 0; 1245 int ret; 1246 1247 flags |= PIPE_CONTROL_CS_STALL; 1248 1249 if (flush_domains) { 1250 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 1251 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 1252 flags |= PIPE_CONTROL_FLUSH_ENABLE; 1253 } 1254 1255 if (invalidate_domains) { 1256 flags |= PIPE_CONTROL_TLB_INVALIDATE; 1257 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 1258 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 1259 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 1260 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 1261 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; 1262 flags |= PIPE_CONTROL_QW_WRITE; 1263 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; 1264 } 1265 1266 /* 1267 * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe 1268 * control. 1269 */ 1270 vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && 1271 flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; 1272 1273 ret = intel_logical_ring_begin(ringbuf, ctx, vf_flush_wa ? 12 : 6); 1274 if (ret) 1275 return ret; 1276 1277 if (vf_flush_wa) { 1278 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); 1279 intel_logical_ring_emit(ringbuf, 0); 1280 intel_logical_ring_emit(ringbuf, 0); 1281 intel_logical_ring_emit(ringbuf, 0); 1282 intel_logical_ring_emit(ringbuf, 0); 1283 intel_logical_ring_emit(ringbuf, 0); 1284 } 1285 1286 intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); 1287 intel_logical_ring_emit(ringbuf, flags); 1288 intel_logical_ring_emit(ringbuf, scratch_addr); 1289 intel_logical_ring_emit(ringbuf, 0); 1290 intel_logical_ring_emit(ringbuf, 0); 1291 intel_logical_ring_emit(ringbuf, 0); 1292 intel_logical_ring_advance(ringbuf); 1293 1294 return 0; 1295 } 1296 1297 static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) 1298 { 1299 return intel_read_status_page(ring, I915_GEM_HWS_INDEX); 1300 } 1301 1302 static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) 1303 { 1304 intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); 1305 } 1306 1307 static int gen8_emit_request(struct intel_ringbuffer *ringbuf, 1308 struct drm_i915_gem_request *request) 1309 { 1310 struct intel_engine_cs *ring = ringbuf->ring; 1311 u32 cmd; 1312 int ret; 1313 1314 /* 1315 * Reserve space for 2 NOOPs at the end of each request to be 1316 * used as a workaround for not being allowed to do lite 1317 * restore with HEAD==TAIL (WaIdleLiteRestore). 1318 */ 1319 ret = intel_logical_ring_begin(ringbuf, request->ctx, 8); 1320 if (ret) 1321 return ret; 1322 1323 cmd = MI_STORE_DWORD_IMM_GEN4; 1324 cmd |= MI_GLOBAL_GTT; 1325 1326 intel_logical_ring_emit(ringbuf, cmd); 1327 intel_logical_ring_emit(ringbuf, 1328 (ring->status_page.gfx_addr + 1329 (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); 1330 intel_logical_ring_emit(ringbuf, 0); 1331 intel_logical_ring_emit(ringbuf, 1332 i915_gem_request_get_seqno(ring->outstanding_lazy_request)); 1333 intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); 1334 intel_logical_ring_emit(ringbuf, MI_NOOP); 1335 intel_logical_ring_advance_and_submit(ringbuf, request->ctx, request); 1336 1337 /* 1338 * Here we add two extra NOOPs as padding to avoid 1339 * lite restore of a context with HEAD==TAIL. 1340 */ 1341 intel_logical_ring_emit(ringbuf, MI_NOOP); 1342 intel_logical_ring_emit(ringbuf, MI_NOOP); 1343 intel_logical_ring_advance(ringbuf); 1344 1345 return 0; 1346 } 1347 1348 static int intel_lr_context_render_state_init(struct intel_engine_cs *ring, 1349 struct intel_context *ctx) 1350 { 1351 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; 1352 struct render_state so; 1353 struct drm_i915_file_private *file_priv = ctx->file_priv; 1354 struct drm_file *file = file_priv ? file_priv->file : NULL; 1355 int ret; 1356 1357 ret = i915_gem_render_state_prepare(ring, &so); 1358 if (ret) 1359 return ret; 1360 1361 if (so.rodata == NULL) 1362 return 0; 1363 1364 ret = ring->emit_bb_start(ringbuf, 1365 ctx, 1366 so.ggtt_offset, 1367 I915_DISPATCH_SECURE); 1368 if (ret) 1369 goto out; 1370 1371 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); 1372 1373 ret = __i915_add_request(ring, file, so.obj); 1374 /* intel_logical_ring_add_request moves object to inactive if it 1375 * fails */ 1376 out: 1377 i915_gem_render_state_fini(&so); 1378 return ret; 1379 } 1380 1381 static int gen8_init_rcs_context(struct intel_engine_cs *ring, 1382 struct intel_context *ctx) 1383 { 1384 int ret; 1385 1386 ret = intel_logical_ring_workarounds_emit(ring, ctx); 1387 if (ret) 1388 return ret; 1389 1390 return intel_lr_context_render_state_init(ring, ctx); 1391 } 1392 1393 /** 1394 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer 1395 * 1396 * @ring: Engine Command Streamer. 1397 * 1398 */ 1399 void intel_logical_ring_cleanup(struct intel_engine_cs *ring) 1400 { 1401 struct drm_i915_private *dev_priv; 1402 1403 if (!intel_ring_initialized(ring)) 1404 return; 1405 1406 dev_priv = ring->dev->dev_private; 1407 1408 intel_logical_ring_stop(ring); 1409 WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); 1410 i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); 1411 1412 if (ring->cleanup) 1413 ring->cleanup(ring); 1414 1415 i915_cmd_parser_fini_ring(ring); 1416 i915_gem_batch_pool_fini(&ring->batch_pool); 1417 1418 if (ring->status_page.obj) { 1419 kunmap(sg_page(ring->status_page.obj->pages->sgl)); 1420 ring->status_page.obj = NULL; 1421 } 1422 } 1423 1424 static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) 1425 { 1426 int ret; 1427 1428 /* Intentionally left blank. */ 1429 ring->buffer = NULL; 1430 1431 ring->dev = dev; 1432 INIT_LIST_HEAD(&ring->active_list); 1433 INIT_LIST_HEAD(&ring->request_list); 1434 i915_gem_batch_pool_init(dev, &ring->batch_pool); 1435 init_waitqueue_head(&ring->irq_queue); 1436 1437 INIT_LIST_HEAD(&ring->execlist_queue); 1438 INIT_LIST_HEAD(&ring->execlist_retired_req_list); 1439 lockinit(&ring->execlist_lock, "i915el", 0, LK_CANRECURSE); 1440 1441 ret = i915_cmd_parser_init_ring(ring); 1442 if (ret) 1443 return ret; 1444 1445 ret = intel_lr_context_deferred_create(ring->default_context, ring); 1446 1447 return ret; 1448 } 1449 1450 static int logical_render_ring_init(struct drm_device *dev) 1451 { 1452 struct drm_i915_private *dev_priv = dev->dev_private; 1453 struct intel_engine_cs *ring = &dev_priv->ring[RCS]; 1454 int ret; 1455 1456 ring->name = "render ring"; 1457 ring->id = RCS; 1458 ring->mmio_base = RENDER_RING_BASE; 1459 ring->irq_enable_mask = 1460 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; 1461 ring->irq_keep_mask = 1462 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; 1463 if (HAS_L3_DPF(dev)) 1464 ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; 1465 1466 if (INTEL_INFO(dev)->gen >= 9) 1467 ring->init_hw = gen9_init_render_ring; 1468 else 1469 ring->init_hw = gen8_init_render_ring; 1470 ring->init_context = gen8_init_rcs_context; 1471 ring->cleanup = intel_fini_pipe_control; 1472 ring->get_seqno = gen8_get_seqno; 1473 ring->set_seqno = gen8_set_seqno; 1474 ring->emit_request = gen8_emit_request; 1475 ring->emit_flush = gen8_emit_flush_render; 1476 ring->irq_get = gen8_logical_ring_get_irq; 1477 ring->irq_put = gen8_logical_ring_put_irq; 1478 ring->emit_bb_start = gen8_emit_bb_start; 1479 1480 ring->dev = dev; 1481 ret = logical_ring_init(dev, ring); 1482 if (ret) 1483 return ret; 1484 1485 return intel_init_pipe_control(ring); 1486 } 1487 1488 static int logical_bsd_ring_init(struct drm_device *dev) 1489 { 1490 struct drm_i915_private *dev_priv = dev->dev_private; 1491 struct intel_engine_cs *ring = &dev_priv->ring[VCS]; 1492 1493 ring->name = "bsd ring"; 1494 ring->id = VCS; 1495 ring->mmio_base = GEN6_BSD_RING_BASE; 1496 ring->irq_enable_mask = 1497 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 1498 ring->irq_keep_mask = 1499 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; 1500 1501 ring->init_hw = gen8_init_common_ring; 1502 ring->get_seqno = gen8_get_seqno; 1503 ring->set_seqno = gen8_set_seqno; 1504 ring->emit_request = gen8_emit_request; 1505 ring->emit_flush = gen8_emit_flush; 1506 ring->irq_get = gen8_logical_ring_get_irq; 1507 ring->irq_put = gen8_logical_ring_put_irq; 1508 ring->emit_bb_start = gen8_emit_bb_start; 1509 1510 return logical_ring_init(dev, ring); 1511 } 1512 1513 static int logical_bsd2_ring_init(struct drm_device *dev) 1514 { 1515 struct drm_i915_private *dev_priv = dev->dev_private; 1516 struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; 1517 1518 ring->name = "bds2 ring"; 1519 ring->id = VCS2; 1520 ring->mmio_base = GEN8_BSD2_RING_BASE; 1521 ring->irq_enable_mask = 1522 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 1523 ring->irq_keep_mask = 1524 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; 1525 1526 ring->init_hw = gen8_init_common_ring; 1527 ring->get_seqno = gen8_get_seqno; 1528 ring->set_seqno = gen8_set_seqno; 1529 ring->emit_request = gen8_emit_request; 1530 ring->emit_flush = gen8_emit_flush; 1531 ring->irq_get = gen8_logical_ring_get_irq; 1532 ring->irq_put = gen8_logical_ring_put_irq; 1533 ring->emit_bb_start = gen8_emit_bb_start; 1534 1535 return logical_ring_init(dev, ring); 1536 } 1537 1538 static int logical_blt_ring_init(struct drm_device *dev) 1539 { 1540 struct drm_i915_private *dev_priv = dev->dev_private; 1541 struct intel_engine_cs *ring = &dev_priv->ring[BCS]; 1542 1543 ring->name = "blitter ring"; 1544 ring->id = BCS; 1545 ring->mmio_base = BLT_RING_BASE; 1546 ring->irq_enable_mask = 1547 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1548 ring->irq_keep_mask = 1549 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; 1550 1551 ring->init_hw = gen8_init_common_ring; 1552 ring->get_seqno = gen8_get_seqno; 1553 ring->set_seqno = gen8_set_seqno; 1554 ring->emit_request = gen8_emit_request; 1555 ring->emit_flush = gen8_emit_flush; 1556 ring->irq_get = gen8_logical_ring_get_irq; 1557 ring->irq_put = gen8_logical_ring_put_irq; 1558 ring->emit_bb_start = gen8_emit_bb_start; 1559 1560 return logical_ring_init(dev, ring); 1561 } 1562 1563 static int logical_vebox_ring_init(struct drm_device *dev) 1564 { 1565 struct drm_i915_private *dev_priv = dev->dev_private; 1566 struct intel_engine_cs *ring = &dev_priv->ring[VECS]; 1567 1568 ring->name = "video enhancement ring"; 1569 ring->id = VECS; 1570 ring->mmio_base = VEBOX_RING_BASE; 1571 ring->irq_enable_mask = 1572 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 1573 ring->irq_keep_mask = 1574 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; 1575 1576 ring->init_hw = gen8_init_common_ring; 1577 ring->get_seqno = gen8_get_seqno; 1578 ring->set_seqno = gen8_set_seqno; 1579 ring->emit_request = gen8_emit_request; 1580 ring->emit_flush = gen8_emit_flush; 1581 ring->irq_get = gen8_logical_ring_get_irq; 1582 ring->irq_put = gen8_logical_ring_put_irq; 1583 ring->emit_bb_start = gen8_emit_bb_start; 1584 1585 return logical_ring_init(dev, ring); 1586 } 1587 1588 /** 1589 * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers 1590 * @dev: DRM device. 1591 * 1592 * This function inits the engines for an Execlists submission style (the equivalent in the 1593 * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for 1594 * those engines that are present in the hardware. 1595 * 1596 * Return: non-zero if the initialization failed. 1597 */ 1598 int intel_logical_rings_init(struct drm_device *dev) 1599 { 1600 struct drm_i915_private *dev_priv = dev->dev_private; 1601 int ret; 1602 1603 ret = logical_render_ring_init(dev); 1604 if (ret) 1605 return ret; 1606 1607 if (HAS_BSD(dev)) { 1608 ret = logical_bsd_ring_init(dev); 1609 if (ret) 1610 goto cleanup_render_ring; 1611 } 1612 1613 if (HAS_BLT(dev)) { 1614 ret = logical_blt_ring_init(dev); 1615 if (ret) 1616 goto cleanup_bsd_ring; 1617 } 1618 1619 if (HAS_VEBOX(dev)) { 1620 ret = logical_vebox_ring_init(dev); 1621 if (ret) 1622 goto cleanup_blt_ring; 1623 } 1624 1625 if (HAS_BSD2(dev)) { 1626 ret = logical_bsd2_ring_init(dev); 1627 if (ret) 1628 goto cleanup_vebox_ring; 1629 } 1630 1631 ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); 1632 if (ret) 1633 goto cleanup_bsd2_ring; 1634 1635 return 0; 1636 1637 cleanup_bsd2_ring: 1638 intel_logical_ring_cleanup(&dev_priv->ring[VCS2]); 1639 cleanup_vebox_ring: 1640 intel_logical_ring_cleanup(&dev_priv->ring[VECS]); 1641 cleanup_blt_ring: 1642 intel_logical_ring_cleanup(&dev_priv->ring[BCS]); 1643 cleanup_bsd_ring: 1644 intel_logical_ring_cleanup(&dev_priv->ring[VCS]); 1645 cleanup_render_ring: 1646 intel_logical_ring_cleanup(&dev_priv->ring[RCS]); 1647 1648 return ret; 1649 } 1650 1651 static u32 1652 make_rpcs(struct drm_device *dev) 1653 { 1654 u32 rpcs = 0; 1655 1656 /* 1657 * No explicit RPCS request is needed to ensure full 1658 * slice/subslice/EU enablement prior to Gen9. 1659 */ 1660 if (INTEL_INFO(dev)->gen < 9) 1661 return 0; 1662 1663 /* 1664 * Starting in Gen9, render power gating can leave 1665 * slice/subslice/EU in a partially enabled state. We 1666 * must make an explicit request through RPCS for full 1667 * enablement. 1668 */ 1669 if (INTEL_INFO(dev)->has_slice_pg) { 1670 rpcs |= GEN8_RPCS_S_CNT_ENABLE; 1671 rpcs |= INTEL_INFO(dev)->slice_total << 1672 GEN8_RPCS_S_CNT_SHIFT; 1673 rpcs |= GEN8_RPCS_ENABLE; 1674 } 1675 1676 if (INTEL_INFO(dev)->has_subslice_pg) { 1677 rpcs |= GEN8_RPCS_SS_CNT_ENABLE; 1678 rpcs |= INTEL_INFO(dev)->subslice_per_slice << 1679 GEN8_RPCS_SS_CNT_SHIFT; 1680 rpcs |= GEN8_RPCS_ENABLE; 1681 } 1682 1683 if (INTEL_INFO(dev)->has_eu_pg) { 1684 rpcs |= INTEL_INFO(dev)->eu_per_subslice << 1685 GEN8_RPCS_EU_MIN_SHIFT; 1686 rpcs |= INTEL_INFO(dev)->eu_per_subslice << 1687 GEN8_RPCS_EU_MAX_SHIFT; 1688 rpcs |= GEN8_RPCS_ENABLE; 1689 } 1690 1691 return rpcs; 1692 } 1693 1694 static int 1695 populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, 1696 struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) 1697 { 1698 struct drm_device *dev = ring->dev; 1699 struct drm_i915_private *dev_priv = dev->dev_private; 1700 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; 1701 struct vm_page *page; 1702 uint32_t *reg_state; 1703 int ret; 1704 1705 if (!ppgtt) 1706 ppgtt = dev_priv->mm.aliasing_ppgtt; 1707 1708 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); 1709 if (ret) { 1710 DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); 1711 return ret; 1712 } 1713 1714 ret = i915_gem_object_get_pages(ctx_obj); 1715 if (ret) { 1716 DRM_DEBUG_DRIVER("Could not get object pages\n"); 1717 return ret; 1718 } 1719 1720 i915_gem_object_pin_pages(ctx_obj); 1721 1722 /* The second page of the context object contains some fields which must 1723 * be set up prior to the first execution. */ 1724 page = i915_gem_object_get_page(ctx_obj, 1); 1725 reg_state = kmap_atomic(page); 1726 1727 /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM 1728 * commands followed by (reg, value) pairs. The values we are setting here are 1729 * only for the first context restore: on a subsequent save, the GPU will 1730 * recreate this batchbuffer with new values (including all the missing 1731 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ 1732 if (ring->id == RCS) 1733 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); 1734 else 1735 reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); 1736 reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; 1737 reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); 1738 reg_state[CTX_CONTEXT_CONTROL+1] = 1739 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | 1740 CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); 1741 reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); 1742 reg_state[CTX_RING_HEAD+1] = 0; 1743 reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); 1744 reg_state[CTX_RING_TAIL+1] = 0; 1745 reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); 1746 /* Ring buffer start address is not known until the buffer is pinned. 1747 * It is written to the context image in execlists_update_context() 1748 */ 1749 reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); 1750 reg_state[CTX_RING_BUFFER_CONTROL+1] = 1751 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; 1752 reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; 1753 reg_state[CTX_BB_HEAD_U+1] = 0; 1754 reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; 1755 reg_state[CTX_BB_HEAD_L+1] = 0; 1756 reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; 1757 reg_state[CTX_BB_STATE+1] = (1<<5); 1758 reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; 1759 reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; 1760 reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; 1761 reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; 1762 reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; 1763 reg_state[CTX_SECOND_BB_STATE+1] = 0; 1764 if (ring->id == RCS) { 1765 /* TODO: according to BSpec, the register state context 1766 * for CHV does not have these. OTOH, these registers do 1767 * exist in CHV. I'm waiting for a clarification */ 1768 reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; 1769 reg_state[CTX_BB_PER_CTX_PTR+1] = 0; 1770 reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; 1771 reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; 1772 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; 1773 reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; 1774 } 1775 reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); 1776 reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; 1777 reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; 1778 reg_state[CTX_CTX_TIMESTAMP+1] = 0; 1779 reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); 1780 reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); 1781 reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); 1782 reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); 1783 reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); 1784 reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); 1785 reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); 1786 reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); 1787 1788 /* With dynamic page allocation, PDPs may not be allocated at this point, 1789 * Point the unallocated PDPs to the scratch page 1790 */ 1791 ASSIGN_CTX_PDP(ppgtt, reg_state, 3); 1792 ASSIGN_CTX_PDP(ppgtt, reg_state, 2); 1793 ASSIGN_CTX_PDP(ppgtt, reg_state, 1); 1794 ASSIGN_CTX_PDP(ppgtt, reg_state, 0); 1795 if (ring->id == RCS) { 1796 reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); 1797 reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; 1798 reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); 1799 } 1800 1801 kunmap_atomic(reg_state); 1802 1803 ctx_obj->dirty = 1; 1804 set_page_dirty(page); 1805 i915_gem_object_unpin_pages(ctx_obj); 1806 1807 return 0; 1808 } 1809 1810 /** 1811 * intel_lr_context_free() - free the LRC specific bits of a context 1812 * @ctx: the LR context to free. 1813 * 1814 * The real context freeing is done in i915_gem_context_free: this only 1815 * takes care of the bits that are LRC related: the per-engine backing 1816 * objects and the logical ringbuffer. 1817 */ 1818 void intel_lr_context_free(struct intel_context *ctx) 1819 { 1820 int i; 1821 1822 for (i = 0; i < I915_NUM_RINGS; i++) { 1823 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; 1824 1825 if (ctx_obj) { 1826 struct intel_ringbuffer *ringbuf = 1827 ctx->engine[i].ringbuf; 1828 struct intel_engine_cs *ring = ringbuf->ring; 1829 1830 if (ctx == ring->default_context) { 1831 intel_unpin_ringbuffer_obj(ringbuf); 1832 i915_gem_object_ggtt_unpin(ctx_obj); 1833 } 1834 WARN_ON(ctx->engine[ring->id].pin_count); 1835 intel_destroy_ringbuffer_obj(ringbuf); 1836 kfree(ringbuf); 1837 drm_gem_object_unreference(&ctx_obj->base); 1838 } 1839 } 1840 } 1841 1842 static uint32_t get_lr_context_size(struct intel_engine_cs *ring) 1843 { 1844 int ret = 0; 1845 1846 WARN_ON(INTEL_INFO(ring->dev)->gen < 8); 1847 1848 switch (ring->id) { 1849 case RCS: 1850 if (INTEL_INFO(ring->dev)->gen >= 9) 1851 ret = GEN9_LR_CONTEXT_RENDER_SIZE; 1852 else 1853 ret = GEN8_LR_CONTEXT_RENDER_SIZE; 1854 break; 1855 case VCS: 1856 case BCS: 1857 case VECS: 1858 case VCS2: 1859 ret = GEN8_LR_CONTEXT_OTHER_SIZE; 1860 break; 1861 } 1862 1863 return ret; 1864 } 1865 1866 static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, 1867 struct drm_i915_gem_object *default_ctx_obj) 1868 { 1869 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1870 1871 /* The status page is offset 0 from the default context object 1872 * in LRC mode. */ 1873 ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj); 1874 ring->status_page.page_addr = 1875 kmap(sg_page(default_ctx_obj->pages->sgl)); 1876 ring->status_page.obj = default_ctx_obj; 1877 1878 I915_WRITE(RING_HWS_PGA(ring->mmio_base), 1879 (u32)ring->status_page.gfx_addr); 1880 POSTING_READ(RING_HWS_PGA(ring->mmio_base)); 1881 } 1882 1883 /** 1884 * intel_lr_context_deferred_create() - create the LRC specific bits of a context 1885 * @ctx: LR context to create. 1886 * @ring: engine to be used with the context. 1887 * 1888 * This function can be called more than once, with different engines, if we plan 1889 * to use the context with them. The context backing objects and the ringbuffers 1890 * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why 1891 * the creation is a deferred call: it's better to make sure first that we need to use 1892 * a given ring with the context. 1893 * 1894 * Return: non-zero on error. 1895 */ 1896 int intel_lr_context_deferred_create(struct intel_context *ctx, 1897 struct intel_engine_cs *ring) 1898 { 1899 const bool is_global_default_ctx = (ctx == ring->default_context); 1900 struct drm_device *dev = ring->dev; 1901 struct drm_i915_gem_object *ctx_obj; 1902 uint32_t context_size; 1903 struct intel_ringbuffer *ringbuf; 1904 int ret; 1905 1906 WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); 1907 WARN_ON(ctx->engine[ring->id].state); 1908 1909 context_size = round_up(get_lr_context_size(ring), 4096); 1910 1911 ctx_obj = i915_gem_alloc_object(dev, context_size); 1912 if (!ctx_obj) { 1913 DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); 1914 return -ENOMEM; 1915 } 1916 1917 if (is_global_default_ctx) { 1918 ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, 0); 1919 if (ret) { 1920 DRM_DEBUG_DRIVER("Pin LRC backing obj failed: %d\n", 1921 ret); 1922 drm_gem_object_unreference(&ctx_obj->base); 1923 return ret; 1924 } 1925 } 1926 1927 ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); 1928 if (!ringbuf) { 1929 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n", 1930 ring->name); 1931 ret = -ENOMEM; 1932 goto error_unpin_ctx; 1933 } 1934 1935 ringbuf->ring = ring; 1936 1937 ringbuf->size = 32 * PAGE_SIZE; 1938 ringbuf->effective_size = ringbuf->size; 1939 ringbuf->head = 0; 1940 ringbuf->tail = 0; 1941 ringbuf->last_retired_head = -1; 1942 intel_ring_update_space(ringbuf); 1943 1944 if (ringbuf->obj == NULL) { 1945 ret = intel_alloc_ringbuffer_obj(dev, ringbuf); 1946 if (ret) { 1947 DRM_DEBUG_DRIVER( 1948 "Failed to allocate ringbuffer obj %s: %d\n", 1949 ring->name, ret); 1950 goto error_free_rbuf; 1951 } 1952 1953 if (is_global_default_ctx) { 1954 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); 1955 if (ret) { 1956 DRM_ERROR( 1957 "Failed to pin and map ringbuffer %s: %d\n", 1958 ring->name, ret); 1959 goto error_destroy_rbuf; 1960 } 1961 } 1962 1963 } 1964 1965 ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); 1966 if (ret) { 1967 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); 1968 goto error; 1969 } 1970 1971 ctx->engine[ring->id].ringbuf = ringbuf; 1972 ctx->engine[ring->id].state = ctx_obj; 1973 1974 if (ctx == ring->default_context) 1975 lrc_setup_hardware_status_page(ring, ctx_obj); 1976 else if (ring->id == RCS && !ctx->rcs_initialized) { 1977 if (ring->init_context) { 1978 ret = ring->init_context(ring, ctx); 1979 if (ret) { 1980 DRM_ERROR("ring init context: %d\n", ret); 1981 ctx->engine[ring->id].ringbuf = NULL; 1982 ctx->engine[ring->id].state = NULL; 1983 goto error; 1984 } 1985 } 1986 1987 ctx->rcs_initialized = true; 1988 } 1989 1990 return 0; 1991 1992 error: 1993 if (is_global_default_ctx) 1994 intel_unpin_ringbuffer_obj(ringbuf); 1995 error_destroy_rbuf: 1996 intel_destroy_ringbuffer_obj(ringbuf); 1997 error_free_rbuf: 1998 kfree(ringbuf); 1999 error_unpin_ctx: 2000 if (is_global_default_ctx) 2001 i915_gem_object_ggtt_unpin(ctx_obj); 2002 drm_gem_object_unreference(&ctx_obj->base); 2003 return ret; 2004 } 2005 2006 void intel_lr_context_reset(struct drm_device *dev, 2007 struct intel_context *ctx) 2008 { 2009 struct drm_i915_private *dev_priv = dev->dev_private; 2010 struct intel_engine_cs *ring; 2011 int i; 2012 2013 for_each_ring(ring, dev_priv, i) { 2014 struct drm_i915_gem_object *ctx_obj = 2015 ctx->engine[ring->id].state; 2016 struct intel_ringbuffer *ringbuf = 2017 ctx->engine[ring->id].ringbuf; 2018 uint32_t *reg_state; 2019 struct vm_page *page; 2020 2021 if (!ctx_obj) 2022 continue; 2023 2024 if (i915_gem_object_get_pages(ctx_obj)) { 2025 WARN(1, "Failed get_pages for context obj\n"); 2026 continue; 2027 } 2028 page = i915_gem_object_get_page(ctx_obj, 1); 2029 reg_state = kmap_atomic(page); 2030 2031 reg_state[CTX_RING_HEAD+1] = 0; 2032 reg_state[CTX_RING_TAIL+1] = 0; 2033 2034 kunmap_atomic(reg_state); 2035 2036 ringbuf->head = 0; 2037 ringbuf->tail = 0; 2038 } 2039 } 2040