1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2008,2010 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Chris Wilson <chris@chris-wilson.co.uk> 28 * 29 * Copyright (c) 2011 The FreeBSD Foundation 30 * All rights reserved. 31 * 32 * This software was developed by Konstantin Belousov under sponsorship from 33 * the FreeBSD Foundation. 34 * 35 * Redistribution and use in source and binary forms, with or without 36 * modification, are permitted provided that the following conditions 37 * are met: 38 * 1. Redistributions of source code must retain the above copyright 39 * notice, this list of conditions and the following disclaimer. 40 * 2. Redistributions in binary form must reproduce the above copyright 41 * notice, this list of conditions and the following disclaimer in the 42 * documentation and/or other materials provided with the distribution. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 54 * SUCH DAMAGE. 55 * 56 * $FreeBSD: head/sys/dev/drm2/i915/intel_iic.c 249041 2013-04-03 08:27:35Z dumbbell $ 57 */ 58 59 #include <sys/mplock2.h> 60 61 #include <drm/drmP.h> 62 #include <drm/i915_drm.h> 63 #include "i915_drv.h" 64 #include "intel_drv.h" 65 #include <bus/iicbus/iic.h> 66 #include <bus/iicbus/iiconf.h> 67 #include <bus/iicbus/iicbus.h> 68 #include "iicbus_if.h" 69 #include "iicbb_if.h" 70 71 static int intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs); 72 static void intel_teardown_gmbus_m(struct drm_device *dev, int m); 73 74 /* Intel GPIO access functions */ 75 76 #define I2C_RISEFALL_TIME 10 77 78 struct intel_iic_softc { 79 struct drm_device *drm_dev; 80 device_t iic_dev; 81 bool force_bit_dev; 82 char name[32]; 83 uint32_t reg; 84 uint32_t reg0; 85 }; 86 87 static void 88 intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable) 89 { 90 u32 val; 91 92 /* When using bit bashing for I2C, this bit needs to be set to 1 */ 93 if (!IS_PINEVIEW(dev_priv->dev)) 94 return; 95 96 val = I915_READ(DSPCLK_GATE_D); 97 if (enable) 98 val |= DPCUNIT_CLOCK_GATE_DISABLE; 99 else 100 val &= ~DPCUNIT_CLOCK_GATE_DISABLE; 101 I915_WRITE(DSPCLK_GATE_D, val); 102 } 103 104 static u32 105 intel_iic_get_reserved(device_t idev) 106 { 107 struct intel_iic_softc *sc; 108 struct drm_device *dev; 109 struct drm_i915_private *dev_priv; 110 u32 reserved; 111 112 sc = device_get_softc(idev); 113 dev = sc->drm_dev; 114 dev_priv = dev->dev_private; 115 116 if (!IS_I830(dev) && !IS_845G(dev)) { 117 reserved = I915_READ_NOTRACE(sc->reg) & 118 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); 119 } else { 120 reserved = 0; 121 } 122 123 return (reserved); 124 } 125 126 void 127 intel_iic_reset(struct drm_device *dev) 128 { 129 struct drm_i915_private *dev_priv; 130 131 dev_priv = dev->dev_private; 132 if (HAS_PCH_SPLIT(dev)) 133 I915_WRITE(PCH_GMBUS0, 0); 134 else 135 I915_WRITE(GMBUS0, 0); 136 } 137 138 static int 139 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr) 140 { 141 struct intel_iic_softc *sc; 142 struct drm_device *dev; 143 144 sc = device_get_softc(idev); 145 dev = sc->drm_dev; 146 147 intel_iic_reset(dev); 148 return (0); 149 } 150 151 static void 152 intel_iicbb_setsda(device_t idev, int val) 153 { 154 struct intel_iic_softc *sc; 155 struct drm_i915_private *dev_priv; 156 u32 reserved; 157 u32 data_bits; 158 159 sc = device_get_softc(idev); 160 dev_priv = sc->drm_dev->dev_private; 161 162 reserved = intel_iic_get_reserved(idev); 163 if (val) 164 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK; 165 else 166 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | 167 GPIO_DATA_VAL_MASK; 168 169 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits); 170 POSTING_READ(sc->reg); 171 } 172 173 static void 174 intel_iicbb_setscl(device_t idev, int val) 175 { 176 struct intel_iic_softc *sc; 177 struct drm_i915_private *dev_priv; 178 u32 clock_bits, reserved; 179 180 sc = device_get_softc(idev); 181 dev_priv = sc->drm_dev->dev_private; 182 183 reserved = intel_iic_get_reserved(idev); 184 if (val) 185 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK; 186 else 187 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | 188 GPIO_CLOCK_VAL_MASK; 189 190 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits); 191 POSTING_READ(sc->reg); 192 } 193 194 static int 195 intel_iicbb_getsda(device_t idev) 196 { 197 struct intel_iic_softc *sc; 198 struct drm_i915_private *dev_priv; 199 u32 reserved; 200 201 sc = device_get_softc(idev); 202 dev_priv = sc->drm_dev->dev_private; 203 204 reserved = intel_iic_get_reserved(idev); 205 206 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK); 207 I915_WRITE_NOTRACE(sc->reg, reserved); 208 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0); 209 } 210 211 static int 212 intel_iicbb_getscl(device_t idev) 213 { 214 struct intel_iic_softc *sc; 215 struct drm_i915_private *dev_priv; 216 u32 reserved; 217 218 sc = device_get_softc(idev); 219 dev_priv = sc->drm_dev->dev_private; 220 221 reserved = intel_iic_get_reserved(idev); 222 223 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK); 224 I915_WRITE_NOTRACE(sc->reg, reserved); 225 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0); 226 } 227 228 static int 229 intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs) 230 { 231 struct intel_iic_softc *sc; 232 struct drm_i915_private *dev_priv; 233 u8 *buf; 234 int error, i, reg_offset, unit; 235 u32 val, loop; 236 u16 len; 237 238 sc = device_get_softc(idev); 239 dev_priv = sc->drm_dev->dev_private; 240 unit = device_get_unit(idev); 241 242 lockmgr(&dev_priv->gmbus_lock, LK_EXCLUSIVE); 243 if (sc->force_bit_dev) { 244 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs); 245 goto out; 246 } 247 248 reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; 249 250 I915_WRITE(GMBUS0 + reg_offset, sc->reg0); 251 252 for (i = 0; i < nmsgs; i++) { 253 len = msgs[i].len; 254 buf = msgs[i].buf; 255 256 if ((msgs[i].flags & IIC_M_RD) != 0) { 257 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT | 258 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) | 259 (len << GMBUS_BYTE_COUNT_SHIFT) | 260 (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 261 GMBUS_SLAVE_READ | GMBUS_SW_RDY); 262 POSTING_READ(GMBUS2 + reg_offset); 263 do { 264 loop = 0; 265 266 if (_intel_wait_for(sc->drm_dev, 267 (I915_READ(GMBUS2 + reg_offset) & 268 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0, 269 50, 1, "915gbr")) 270 goto timeout; 271 if ((I915_READ(GMBUS2 + reg_offset) & 272 GMBUS_SATOER) != 0) 273 goto clear_err; 274 275 val = I915_READ(GMBUS3 + reg_offset); 276 do { 277 *buf++ = val & 0xff; 278 val >>= 8; 279 } while (--len != 0 && ++loop < 4); 280 } while (len != 0); 281 } else { 282 val = loop = 0; 283 do { 284 val |= *buf++ << (8 * loop); 285 } while (--len != 0 && ++loop < 4); 286 287 I915_WRITE(GMBUS3 + reg_offset, val); 288 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_WAIT | 289 (i + 1 == nmsgs ? GMBUS_CYCLE_STOP : 0) | 290 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | 291 (msgs[i].slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) | 292 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); 293 POSTING_READ(GMBUS2+reg_offset); 294 295 while (len != 0) { 296 if (_intel_wait_for(sc->drm_dev, 297 (I915_READ(GMBUS2 + reg_offset) & 298 (GMBUS_SATOER | GMBUS_HW_RDY)) != 0, 299 50, 1, "915gbw")) 300 goto timeout; 301 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) 302 goto clear_err; 303 304 val = loop = 0; 305 do { 306 val |= *buf++ << (8 * loop); 307 } while (--len != 0 && ++loop < 4); 308 309 I915_WRITE(GMBUS3 + reg_offset, val); 310 POSTING_READ(GMBUS2 + reg_offset); 311 } 312 } 313 314 if (i + 1 < nmsgs && _intel_wait_for(sc->drm_dev, 315 (I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | 316 GMBUS_HW_WAIT_PHASE)) != 0, 317 50, 1, "915gbh")) 318 goto timeout; 319 if ((I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER) != 0) 320 goto clear_err; 321 } 322 323 error = 0; 324 done: 325 /* Mark the GMBUS interface as disabled after waiting for idle. 326 * We will re-enable it at the start of the next xfer, 327 * till then let it sleep. 328 */ 329 if (_intel_wait_for(dev, 330 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 331 10, 1, "915gbu")) 332 DRM_INFO("GMBUS timed out waiting for idle\n"); 333 I915_WRITE(GMBUS0 + reg_offset, 0); 334 out: 335 lockmgr(&dev_priv->gmbus_lock, LK_RELEASE); 336 return (error); 337 338 clear_err: 339 /* Toggle the Software Clear Interrupt bit. This has the effect 340 * of resetting the GMBUS controller and so clearing the 341 * BUS_ERROR raised by the slave's NAK. 342 */ 343 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); 344 I915_WRITE(GMBUS1 + reg_offset, 0); 345 error = EIO; 346 goto done; 347 348 timeout: 349 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", 350 sc->reg0 & 0xff, sc->name); 351 I915_WRITE(GMBUS0 + reg_offset, 0); 352 353 /* 354 * Hardware may not support GMBUS over these pins? 355 * Try GPIO bitbanging instead. 356 */ 357 sc->force_bit_dev = true; 358 359 error = intel_iic_quirk_xfer(dev_priv->bbbus[unit], msgs, nmsgs); 360 goto out; 361 } 362 363 void 364 intel_gmbus_set_speed(device_t idev, int speed) 365 { 366 struct intel_iic_softc *sc; 367 368 sc = device_get_softc(device_get_parent(idev)); 369 370 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed; 371 } 372 373 void 374 intel_gmbus_force_bit(device_t idev, bool force_bit) 375 { 376 struct intel_iic_softc *sc; 377 378 sc = device_get_softc(device_get_parent(idev)); 379 sc->force_bit_dev = force_bit; 380 } 381 382 static int 383 intel_iic_quirk_xfer(device_t idev, struct iic_msg *msgs, int nmsgs) 384 { 385 device_t bridge_dev; 386 struct intel_iic_softc *sc; 387 struct drm_i915_private *dev_priv; 388 int ret; 389 int i; 390 391 bridge_dev = device_get_parent(device_get_parent(idev)); 392 sc = device_get_softc(bridge_dev); 393 dev_priv = sc->drm_dev->dev_private; 394 395 intel_iic_reset(sc->drm_dev); 396 intel_iic_quirk_set(dev_priv, true); 397 IICBB_SETSDA(bridge_dev, 1); 398 IICBB_SETSCL(bridge_dev, 1); 399 DELAY(I2C_RISEFALL_TIME); 400 401 for (i = 0; i < nmsgs - 1; i++) { 402 /* force use of repeated start instead of default stop+start */ 403 msgs[i].flags |= IIC_M_NOSTOP; 404 } 405 ret = iicbus_transfer(idev, msgs, nmsgs); 406 IICBB_SETSDA(bridge_dev, 1); 407 IICBB_SETSCL(bridge_dev, 1); 408 intel_iic_quirk_set(dev_priv, false); 409 410 return (ret); 411 } 412 413 static const char *gpio_names[GMBUS_NUM_PORTS] = { 414 "ssc", 415 "vga", 416 "panel", 417 "dpc", 418 "dpb", 419 "dpd", 420 }; 421 422 static int 423 intel_gmbus_probe(device_t dev) 424 { 425 426 return (BUS_PROBE_SPECIFIC); 427 } 428 429 static int 430 intel_gmbus_attach(device_t idev) 431 { 432 struct drm_i915_private *dev_priv; 433 struct intel_iic_softc *sc; 434 int pin; 435 436 sc = device_get_softc(idev); 437 sc->drm_dev = device_get_softc(device_get_parent(idev)); 438 dev_priv = sc->drm_dev->dev_private; 439 pin = device_get_unit(idev); 440 441 ksnprintf(sc->name, sizeof(sc->name), "gmbus bus %s", gpio_names[pin]); 442 device_set_desc(idev, sc->name); 443 444 /* By default use a conservative clock rate */ 445 sc->reg0 = pin | GMBUS_RATE_100KHZ; 446 447 /* XXX force bit banging until GMBUS is fully debugged */ 448 if (IS_GEN2(sc->drm_dev)) { 449 sc->force_bit_dev = true; 450 } 451 452 /* add bus interface device */ 453 sc->iic_dev = device_add_child(idev, "iicbus", -1); 454 if (sc->iic_dev == NULL) 455 return (ENXIO); 456 device_quiet(sc->iic_dev); 457 bus_generic_attach(idev); 458 459 return (0); 460 } 461 462 static int 463 intel_gmbus_detach(device_t idev) 464 { 465 struct intel_iic_softc *sc; 466 struct drm_i915_private *dev_priv; 467 device_t child; 468 int u; 469 470 sc = device_get_softc(idev); 471 u = device_get_unit(idev); 472 dev_priv = sc->drm_dev->dev_private; 473 474 child = sc->iic_dev; 475 bus_generic_detach(idev); 476 if (child != NULL) 477 device_delete_child(idev, child); 478 479 return (0); 480 } 481 482 static int 483 intel_iicbb_probe(device_t dev) 484 { 485 486 return (BUS_PROBE_DEFAULT); 487 } 488 489 static int 490 intel_iicbb_attach(device_t idev) 491 { 492 static const int map_pin_to_reg[] = { 493 0, 494 GPIOB, 495 GPIOA, 496 GPIOC, 497 GPIOD, 498 GPIOE, 499 0, 500 GPIOF 501 }; 502 503 struct intel_iic_softc *sc; 504 struct drm_i915_private *dev_priv; 505 int pin; 506 507 sc = device_get_softc(idev); 508 sc->drm_dev = device_get_softc(device_get_parent(idev)); 509 dev_priv = sc->drm_dev->dev_private; 510 pin = device_get_unit(idev); 511 512 ksnprintf(sc->name, sizeof(sc->name), "i915 iicbb %s", gpio_names[pin]); 513 device_set_desc(idev, sc->name); 514 515 sc->reg0 = pin | GMBUS_RATE_100KHZ; 516 sc->reg = map_pin_to_reg[pin]; 517 if (HAS_PCH_SPLIT(dev_priv->dev)) 518 sc->reg += PCH_GPIOA - GPIOA; 519 520 /* add generic bit-banging code */ 521 sc->iic_dev = device_add_child(idev, "iicbb", -1); 522 if (sc->iic_dev == NULL) 523 return (ENXIO); 524 device_quiet(sc->iic_dev); 525 bus_generic_attach(idev); 526 527 return (0); 528 } 529 530 static int 531 intel_iicbb_detach(device_t idev) 532 { 533 struct intel_iic_softc *sc; 534 device_t child; 535 536 sc = device_get_softc(idev); 537 child = sc->iic_dev; 538 bus_generic_detach(idev); 539 if (child) 540 device_delete_child(idev, child); 541 return (0); 542 } 543 544 static device_method_t intel_gmbus_methods[] = { 545 DEVMETHOD(device_probe, intel_gmbus_probe), 546 DEVMETHOD(device_attach, intel_gmbus_attach), 547 DEVMETHOD(device_detach, intel_gmbus_detach), 548 DEVMETHOD(iicbus_reset, intel_iicbus_reset), 549 DEVMETHOD(iicbus_transfer, intel_gmbus_transfer), 550 DEVMETHOD_END 551 }; 552 static driver_t intel_gmbus_driver = { 553 "intel_gmbus", 554 intel_gmbus_methods, 555 sizeof(struct intel_iic_softc) 556 }; 557 static devclass_t intel_gmbus_devclass; 558 DRIVER_MODULE_ORDERED(intel_gmbus, drm, intel_gmbus_driver, 559 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST); 560 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0); 561 562 static device_method_t intel_iicbb_methods[] = { 563 DEVMETHOD(device_probe, intel_iicbb_probe), 564 DEVMETHOD(device_attach, intel_iicbb_attach), 565 DEVMETHOD(device_detach, intel_iicbb_detach), 566 567 DEVMETHOD(bus_add_child, bus_generic_add_child), 568 DEVMETHOD(bus_print_child, bus_generic_print_child), 569 570 DEVMETHOD(iicbb_callback, iicbus_null_callback), 571 DEVMETHOD(iicbb_reset, intel_iicbus_reset), 572 DEVMETHOD(iicbb_setsda, intel_iicbb_setsda), 573 DEVMETHOD(iicbb_setscl, intel_iicbb_setscl), 574 DEVMETHOD(iicbb_getsda, intel_iicbb_getsda), 575 DEVMETHOD(iicbb_getscl, intel_iicbb_getscl), 576 DEVMETHOD_END 577 }; 578 static driver_t intel_iicbb_driver = { 579 "intel_iicbb", 580 intel_iicbb_methods, 581 sizeof(struct intel_iic_softc) 582 }; 583 static devclass_t intel_iicbb_devclass; 584 DRIVER_MODULE_ORDERED(intel_iicbb, drm, intel_iicbb_driver, 585 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST); 586 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0); 587 588 int 589 intel_setup_gmbus(struct drm_device *dev) 590 { 591 struct drm_i915_private *dev_priv; 592 device_t iic_dev; 593 int i, ret; 594 595 dev_priv = dev->dev_private; 596 lockinit(&dev_priv->gmbus_lock, "gmbus", 0, LK_CANRECURSE); 597 dev_priv->gmbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 598 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 599 dev_priv->bbbus_bridge = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 600 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 601 dev_priv->gmbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 602 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 603 dev_priv->bbbus = kmalloc(sizeof(device_t) * GMBUS_NUM_PORTS, 604 DRM_MEM_DRIVER, M_WAITOK | M_ZERO); 605 606 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 607 /* 608 * Initialized bbbus_bridge before gmbus_bridge, since 609 * gmbus may decide to force quirk transfer in the 610 * attachment code. 611 */ 612 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev, 613 "intel_iicbb", i); 614 if (dev_priv->bbbus_bridge[i] == NULL) { 615 DRM_ERROR("bbbus bridge %d creation failed\n", i); 616 ret = ENXIO; 617 goto err; 618 } 619 device_quiet(dev_priv->bbbus_bridge[i]); 620 ret = device_probe_and_attach(dev_priv->bbbus_bridge[i]); 621 if (ret != 0) { 622 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i, 623 ret); 624 goto err; 625 } 626 627 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb", 628 -1); 629 if (iic_dev == NULL) { 630 DRM_ERROR("bbbus bridge doesn't have iicbb child\n"); 631 goto err; 632 } 633 iic_dev = device_find_child(iic_dev, "iicbus", -1); 634 if (iic_dev == NULL) { 635 DRM_ERROR( 636 "bbbus bridge doesn't have iicbus grandchild\n"); 637 goto err; 638 } 639 640 dev_priv->bbbus[i] = iic_dev; 641 642 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev, 643 "intel_gmbus", i); 644 if (dev_priv->gmbus_bridge[i] == NULL) { 645 DRM_ERROR("gmbus bridge %d creation failed\n", i); 646 ret = ENXIO; 647 goto err; 648 } 649 device_quiet(dev_priv->gmbus_bridge[i]); 650 ret = device_probe_and_attach(dev_priv->gmbus_bridge[i]); 651 if (ret != 0) { 652 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i, 653 ret); 654 ret = ENXIO; 655 goto err; 656 } 657 658 iic_dev = device_find_child(dev_priv->gmbus_bridge[i], 659 "iicbus", -1); 660 if (iic_dev == NULL) { 661 DRM_ERROR("gmbus bridge doesn't have iicbus child\n"); 662 goto err; 663 } 664 dev_priv->gmbus[i] = iic_dev; 665 666 intel_iic_reset(dev); 667 } 668 669 return (0); 670 671 err: 672 intel_teardown_gmbus_m(dev, i); 673 return (ret); 674 } 675 676 static void 677 intel_teardown_gmbus_m(struct drm_device *dev, int m) 678 { 679 struct drm_i915_private *dev_priv; 680 681 dev_priv = dev->dev_private; 682 683 drm_free(dev_priv->gmbus, DRM_MEM_DRIVER); 684 dev_priv->gmbus = NULL; 685 drm_free(dev_priv->bbbus, DRM_MEM_DRIVER); 686 dev_priv->bbbus = NULL; 687 drm_free(dev_priv->gmbus_bridge, DRM_MEM_DRIVER); 688 dev_priv->gmbus_bridge = NULL; 689 drm_free(dev_priv->bbbus_bridge, DRM_MEM_DRIVER); 690 dev_priv->bbbus_bridge = NULL; 691 lockuninit(&dev_priv->gmbus_lock); 692 } 693 694 void 695 intel_teardown_gmbus(struct drm_device *dev) 696 { 697 698 get_mplock(); 699 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS); 700 rel_mplock(); 701 } 702