1 /* 2 * Copyright 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright © 2006-2009 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Eric Anholt <eric@anholt.net> 26 * Jesse Barnes <jesse.barnes@intel.com> 27 * $FreeBSD: src/sys/dev/drm2/i915/intel_hdmi.c,v 1.1 2012/05/22 11:07:44 kib Exp $ 28 */ 29 30 #include <dev/drm/drmP.h> 31 #include <dev/drm/drm.h> 32 #include <dev/drm/drm_crtc.h> 33 #include <dev/drm/drm_edid.h> 34 #include "i915_drm.h" 35 #include "i915_drv.h" 36 #include "intel_drv.h" 37 38 struct intel_hdmi { 39 struct intel_encoder base; 40 u32 sdvox_reg; 41 int ddc_bus; 42 uint32_t color_range; 43 bool has_hdmi_sink; 44 bool has_audio; 45 enum hdmi_force_audio force_audio; 46 void (*write_infoframe)(struct drm_encoder *encoder, 47 struct dip_infoframe *frame); 48 }; 49 50 static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) 51 { 52 return container_of(encoder, struct intel_hdmi, base.base); 53 } 54 55 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) 56 { 57 return container_of(intel_attached_encoder(connector), 58 struct intel_hdmi, base); 59 } 60 61 void intel_dip_infoframe_csum(struct dip_infoframe *frame) 62 { 63 uint8_t *data = (uint8_t *)frame; 64 uint8_t sum = 0; 65 unsigned i; 66 67 frame->checksum = 0; 68 frame->ecc = 0; 69 70 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) 71 sum += data[i]; 72 73 frame->checksum = 0x100 - sum; 74 } 75 76 static u32 intel_infoframe_index(struct dip_infoframe *frame) 77 { 78 u32 flags = 0; 79 80 switch (frame->type) { 81 case DIP_TYPE_AVI: 82 flags |= VIDEO_DIP_SELECT_AVI; 83 break; 84 case DIP_TYPE_SPD: 85 flags |= VIDEO_DIP_SELECT_SPD; 86 break; 87 default: 88 DRM_DEBUG("unknown info frame type %d\n", frame->type); 89 break; 90 } 91 92 return flags; 93 } 94 95 static u32 intel_infoframe_flags(struct dip_infoframe *frame) 96 { 97 u32 flags = 0; 98 99 switch (frame->type) { 100 case DIP_TYPE_AVI: 101 flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC; 102 break; 103 case DIP_TYPE_SPD: 104 flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC; 105 break; 106 default: 107 DRM_DEBUG("unknown info frame type %d\n", frame->type); 108 break; 109 } 110 111 return flags; 112 } 113 114 static void i9xx_write_infoframe(struct drm_encoder *encoder, 115 struct dip_infoframe *frame) 116 { 117 uint32_t *data = (uint32_t *)frame; 118 struct drm_device *dev = encoder->dev; 119 struct drm_i915_private *dev_priv = dev->dev_private; 120 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 121 u32 port, flags, val = I915_READ(VIDEO_DIP_CTL); 122 unsigned i, len = DIP_HEADER_SIZE + frame->len; 123 124 125 /* XXX first guess at handling video port, is this corrent? */ 126 if (intel_hdmi->sdvox_reg == SDVOB) 127 port = VIDEO_DIP_PORT_B; 128 else if (intel_hdmi->sdvox_reg == SDVOC) 129 port = VIDEO_DIP_PORT_C; 130 else 131 return; 132 133 flags = intel_infoframe_index(frame); 134 135 val &= ~VIDEO_DIP_SELECT_MASK; 136 137 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); 138 139 for (i = 0; i < len; i += 4) { 140 I915_WRITE(VIDEO_DIP_DATA, *data); 141 data++; 142 } 143 144 flags |= intel_infoframe_flags(frame); 145 146 I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags); 147 } 148 149 static void ironlake_write_infoframe(struct drm_encoder *encoder, 150 struct dip_infoframe *frame) 151 { 152 uint32_t *data = (uint32_t *)frame; 153 struct drm_device *dev = encoder->dev; 154 struct drm_i915_private *dev_priv = dev->dev_private; 155 struct drm_crtc *crtc = encoder->crtc; 156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 157 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); 158 unsigned i, len = DIP_HEADER_SIZE + frame->len; 159 u32 flags, val = I915_READ(reg); 160 161 intel_wait_for_vblank(dev, intel_crtc->pipe); 162 163 flags = intel_infoframe_index(frame); 164 165 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ 166 167 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); 168 169 for (i = 0; i < len; i += 4) { 170 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); 171 data++; 172 } 173 174 flags |= intel_infoframe_flags(frame); 175 176 I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags); 177 } 178 179 static void intel_set_infoframe(struct drm_encoder *encoder, 180 struct dip_infoframe *frame) 181 { 182 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 183 184 if (!intel_hdmi->has_hdmi_sink) 185 return; 186 187 intel_dip_infoframe_csum(frame); 188 intel_hdmi->write_infoframe(encoder, frame); 189 } 190 191 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 192 { 193 struct dip_infoframe avi_if = { 194 .type = DIP_TYPE_AVI, 195 .ver = DIP_VERSION_AVI, 196 .len = DIP_LEN_AVI, 197 }; 198 199 intel_set_infoframe(encoder, &avi_if); 200 } 201 202 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 203 { 204 struct dip_infoframe spd_if; 205 206 memset(&spd_if, 0, sizeof(spd_if)); 207 spd_if.type = DIP_TYPE_SPD; 208 spd_if.ver = DIP_VERSION_SPD; 209 spd_if.len = DIP_LEN_SPD; 210 strcpy(spd_if.body.spd.vn, "Intel"); 211 strcpy(spd_if.body.spd.pd, "Integrated gfx"); 212 spd_if.body.spd.sdi = DIP_SPD_PC; 213 214 intel_set_infoframe(encoder, &spd_if); 215 } 216 217 static void intel_hdmi_mode_set(struct drm_encoder *encoder, 218 struct drm_display_mode *mode, 219 struct drm_display_mode *adjusted_mode) 220 { 221 struct drm_device *dev = encoder->dev; 222 struct drm_i915_private *dev_priv = dev->dev_private; 223 struct drm_crtc *crtc = encoder->crtc; 224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 225 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 226 u32 sdvox; 227 228 sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; 229 if (!HAS_PCH_SPLIT(dev)) 230 sdvox |= intel_hdmi->color_range; 231 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 232 sdvox |= SDVO_VSYNC_ACTIVE_HIGH; 233 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 234 sdvox |= SDVO_HSYNC_ACTIVE_HIGH; 235 236 if (intel_crtc->bpp > 24) 237 sdvox |= COLOR_FORMAT_12bpc; 238 else 239 sdvox |= COLOR_FORMAT_8bpc; 240 241 /* Required on CPT */ 242 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) 243 sdvox |= HDMI_MODE_SELECT; 244 245 if (intel_hdmi->has_audio) { 246 DRM_DEBUG_KMS("Enabling HDMI audio on pipe %c\n", 247 pipe_name(intel_crtc->pipe)); 248 sdvox |= SDVO_AUDIO_ENABLE; 249 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; 250 intel_write_eld(encoder, adjusted_mode); 251 } 252 253 if (HAS_PCH_CPT(dev)) 254 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); 255 else if (intel_crtc->pipe == 1) 256 sdvox |= SDVO_PIPE_B_SELECT; 257 258 I915_WRITE(intel_hdmi->sdvox_reg, sdvox); 259 POSTING_READ(intel_hdmi->sdvox_reg); 260 261 intel_hdmi_set_avi_infoframe(encoder); 262 intel_hdmi_set_spd_infoframe(encoder); 263 } 264 265 static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) 266 { 267 struct drm_device *dev = encoder->dev; 268 struct drm_i915_private *dev_priv = dev->dev_private; 269 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 270 u32 temp; 271 u32 enable_bits = SDVO_ENABLE; 272 273 if (intel_hdmi->has_audio) 274 enable_bits |= SDVO_AUDIO_ENABLE; 275 276 temp = I915_READ(intel_hdmi->sdvox_reg); 277 278 /* HW workaround, need to toggle enable bit off and on for 12bpc, but 279 * we do this anyway which shows more stable in testing. 280 */ 281 if (HAS_PCH_SPLIT(dev)) { 282 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); 283 POSTING_READ(intel_hdmi->sdvox_reg); 284 } 285 286 if (mode != DRM_MODE_DPMS_ON) { 287 temp &= ~enable_bits; 288 } else { 289 temp |= enable_bits; 290 } 291 292 I915_WRITE(intel_hdmi->sdvox_reg, temp); 293 POSTING_READ(intel_hdmi->sdvox_reg); 294 295 /* HW workaround, need to write this twice for issue that may result 296 * in first write getting masked. 297 */ 298 if (HAS_PCH_SPLIT(dev)) { 299 I915_WRITE(intel_hdmi->sdvox_reg, temp); 300 POSTING_READ(intel_hdmi->sdvox_reg); 301 } 302 } 303 304 static int intel_hdmi_mode_valid(struct drm_connector *connector, 305 struct drm_display_mode *mode) 306 { 307 if (mode->clock > 165000) 308 return MODE_CLOCK_HIGH; 309 if (mode->clock < 20000) 310 return MODE_CLOCK_LOW; 311 312 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 313 return MODE_NO_DBLESCAN; 314 315 return MODE_OK; 316 } 317 318 static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 319 const struct drm_display_mode *mode, 320 struct drm_display_mode *adjusted_mode) 321 { 322 return true; 323 } 324 325 static enum drm_connector_status 326 intel_hdmi_detect(struct drm_connector *connector, bool force) 327 { 328 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 329 struct drm_i915_private *dev_priv = connector->dev->dev_private; 330 struct edid *edid; 331 enum drm_connector_status status = connector_status_disconnected; 332 333 intel_hdmi->has_hdmi_sink = false; 334 intel_hdmi->has_audio = false; 335 edid = drm_get_edid(connector, dev_priv->gmbus[intel_hdmi->ddc_bus]); 336 337 if (edid) { 338 if (edid->input & DRM_EDID_INPUT_DIGITAL) { 339 status = connector_status_connected; 340 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) 341 intel_hdmi->has_hdmi_sink = 342 drm_detect_hdmi_monitor(edid); 343 intel_hdmi->has_audio = drm_detect_monitor_audio(edid); 344 } 345 connector->display_info.raw_edid = NULL; 346 drm_free(edid, DRM_MEM_KMS); 347 } else { 348 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] got no edid, ddc port %d\n", 349 connector->base.id, drm_get_connector_name(connector), 350 intel_hdmi->ddc_bus); 351 } 352 353 if (status == connector_status_connected) { 354 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) 355 intel_hdmi->has_audio = 356 (intel_hdmi->force_audio == HDMI_AUDIO_ON); 357 } 358 359 return status; 360 } 361 362 static int intel_hdmi_get_modes(struct drm_connector *connector) 363 { 364 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 365 struct drm_i915_private *dev_priv = connector->dev->dev_private; 366 367 /* We should parse the EDID data and find out if it's an HDMI sink so 368 * we can send audio to it. 369 */ 370 371 return intel_ddc_get_modes(connector, 372 dev_priv->gmbus[intel_hdmi->ddc_bus]); 373 } 374 375 static bool 376 intel_hdmi_detect_audio(struct drm_connector *connector) 377 { 378 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 379 struct drm_i915_private *dev_priv = connector->dev->dev_private; 380 struct edid *edid; 381 bool has_audio = false; 382 383 edid = drm_get_edid(connector, dev_priv->gmbus[intel_hdmi->ddc_bus]); 384 if (edid) { 385 if (edid->input & DRM_EDID_INPUT_DIGITAL) 386 has_audio = drm_detect_monitor_audio(edid); 387 388 connector->display_info.raw_edid = NULL; 389 drm_free(edid, DRM_MEM_KMS); 390 } 391 392 return has_audio; 393 } 394 395 static int 396 intel_hdmi_set_property(struct drm_connector *connector, 397 struct drm_property *property, 398 uint64_t val) 399 { 400 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); 401 struct drm_i915_private *dev_priv = connector->dev->dev_private; 402 int ret; 403 404 ret = drm_connector_property_set_value(connector, property, val); 405 if (ret) 406 return ret; 407 408 if (property == dev_priv->force_audio_property) { 409 enum hdmi_force_audio i = val; 410 bool has_audio; 411 412 if (i == intel_hdmi->force_audio) 413 return 0; 414 415 intel_hdmi->force_audio = i; 416 417 if (i == HDMI_AUDIO_AUTO) 418 has_audio = intel_hdmi_detect_audio(connector); 419 else 420 has_audio = (i == HDMI_AUDIO_ON); 421 422 if (i == HDMI_AUDIO_OFF_DVI) 423 intel_hdmi->has_hdmi_sink = 0; 424 425 intel_hdmi->has_audio = has_audio; 426 goto done; 427 } 428 429 if (property == dev_priv->broadcast_rgb_property) { 430 if (val == !!intel_hdmi->color_range) 431 return 0; 432 433 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; 434 goto done; 435 } 436 437 return -EINVAL; 438 439 done: 440 if (intel_hdmi->base.base.crtc) { 441 struct drm_crtc *crtc = intel_hdmi->base.base.crtc; 442 drm_crtc_helper_set_mode(crtc, &crtc->mode, 443 crtc->x, crtc->y, 444 crtc->fb); 445 } 446 447 return 0; 448 } 449 450 static void intel_hdmi_destroy(struct drm_connector *connector) 451 { 452 #if 0 453 drm_sysfs_connector_remove(connector); 454 #endif 455 drm_connector_cleanup(connector); 456 drm_free(connector, DRM_MEM_KMS); 457 } 458 459 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { 460 .dpms = intel_hdmi_dpms, 461 .mode_fixup = intel_hdmi_mode_fixup, 462 .prepare = intel_encoder_prepare, 463 .mode_set = intel_hdmi_mode_set, 464 .commit = intel_encoder_commit, 465 }; 466 467 static const struct drm_connector_funcs intel_hdmi_connector_funcs = { 468 .dpms = drm_helper_connector_dpms, 469 .detect = intel_hdmi_detect, 470 .fill_modes = drm_helper_probe_single_connector_modes, 471 .set_property = intel_hdmi_set_property, 472 .destroy = intel_hdmi_destroy, 473 }; 474 475 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { 476 .get_modes = intel_hdmi_get_modes, 477 .mode_valid = intel_hdmi_mode_valid, 478 .best_encoder = intel_best_encoder, 479 }; 480 481 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { 482 .destroy = intel_encoder_destroy, 483 }; 484 485 static void 486 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) 487 { 488 intel_attach_force_audio_property(connector); 489 intel_attach_broadcast_rgb_property(connector); 490 } 491 492 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) 493 { 494 struct drm_i915_private *dev_priv = dev->dev_private; 495 struct drm_connector *connector; 496 struct intel_encoder *intel_encoder; 497 struct intel_connector *intel_connector; 498 struct intel_hdmi *intel_hdmi; 499 int i; 500 501 intel_hdmi = kmalloc(sizeof(struct intel_hdmi), DRM_MEM_KMS, 502 M_WAITOK | M_ZERO); 503 intel_connector = kmalloc(sizeof(struct intel_connector), DRM_MEM_KMS, 504 M_WAITOK | M_ZERO); 505 506 intel_encoder = &intel_hdmi->base; 507 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, 508 DRM_MODE_ENCODER_TMDS); 509 510 connector = &intel_connector->base; 511 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, 512 DRM_MODE_CONNECTOR_HDMIA); 513 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); 514 515 intel_encoder->type = INTEL_OUTPUT_HDMI; 516 517 connector->polled = DRM_CONNECTOR_POLL_HPD; 518 connector->interlace_allowed = 1; 519 connector->doublescan_allowed = 0; 520 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 521 522 /* Set up the DDC bus. */ 523 if (sdvox_reg == SDVOB) { 524 intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); 525 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 526 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 527 } else if (sdvox_reg == SDVOC) { 528 intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); 529 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 530 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 531 } else if (sdvox_reg == HDMIB) { 532 intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); 533 intel_hdmi->ddc_bus = GMBUS_PORT_DPB; 534 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; 535 } else if (sdvox_reg == HDMIC) { 536 intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); 537 intel_hdmi->ddc_bus = GMBUS_PORT_DPC; 538 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; 539 } else if (sdvox_reg == HDMID) { 540 intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); 541 intel_hdmi->ddc_bus = GMBUS_PORT_DPD; 542 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; 543 } 544 545 546 intel_hdmi->sdvox_reg = sdvox_reg; 547 548 if (!HAS_PCH_SPLIT(dev)) { 549 intel_hdmi->write_infoframe = i9xx_write_infoframe; 550 I915_WRITE(VIDEO_DIP_CTL, 0); 551 } else { 552 intel_hdmi->write_infoframe = ironlake_write_infoframe; 553 for_each_pipe(i) 554 I915_WRITE(TVIDEO_DIP_CTL(i), 0); 555 } 556 557 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); 558 559 intel_hdmi_add_properties(intel_hdmi, connector); 560 561 intel_connector_attach_encoder(intel_connector, intel_encoder); 562 #if 0 563 drm_sysfs_connector_add(connector); 564 #endif 565 566 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 567 * 0xd. Failure to do so will result in spurious interrupts being 568 * generated on the port when a cable is not attached. 569 */ 570 if (IS_G4X(dev) && !IS_GM45(dev)) { 571 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 572 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 573 } 574 } 575