1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 #ifndef _INTEL_GUC_FWIF_H 24 #define _INTEL_GUC_FWIF_H 25 26 /* 27 * This file is partially autogenerated, although currently with some manual 28 * fixups afterwards. In future, it should be entirely autogenerated, in order 29 * to ensure that the definitions herein remain in sync with those used by the 30 * GuC's own firmware. 31 * 32 * EDITING THIS FILE IS THEREFORE NOT RECOMMENDED - YOUR CHANGES MAY BE LOST. 33 */ 34 35 #define GFXCORE_FAMILY_GEN9 12 36 #define GFXCORE_FAMILY_UNKNOWN 0x7fffffff 37 38 #define GUC_CTX_PRIORITY_KMD_HIGH 0 39 #define GUC_CTX_PRIORITY_HIGH 1 40 #define GUC_CTX_PRIORITY_KMD_NORMAL 2 41 #define GUC_CTX_PRIORITY_NORMAL 3 42 #define GUC_CTX_PRIORITY_NUM 4 43 44 #define GUC_MAX_GPU_CONTEXTS 1024 45 #define GUC_INVALID_CTX_ID GUC_MAX_GPU_CONTEXTS 46 47 #define GUC_RENDER_ENGINE 0 48 #define GUC_VIDEO_ENGINE 1 49 #define GUC_BLITTER_ENGINE 2 50 #define GUC_VIDEOENHANCE_ENGINE 3 51 #define GUC_VIDEO_ENGINE2 4 52 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 53 54 /* Work queue item header definitions */ 55 #define WQ_STATUS_ACTIVE 1 56 #define WQ_STATUS_SUSPENDED 2 57 #define WQ_STATUS_CMD_ERROR 3 58 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 59 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 60 #define WQ_TYPE_SHIFT 0 61 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) 62 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) 63 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) 64 #define WQ_TARGET_SHIFT 10 65 #define WQ_LEN_SHIFT 16 66 #define WQ_NO_WCFLUSH_WAIT (1 << 27) 67 #define WQ_PRESENT_WORKLOAD (1 << 28) 68 #define WQ_WORKLOAD_SHIFT 29 69 #define WQ_WORKLOAD_GENERAL (0 << WQ_WORKLOAD_SHIFT) 70 #define WQ_WORKLOAD_GPGPU (1 << WQ_WORKLOAD_SHIFT) 71 #define WQ_WORKLOAD_TOUCH (2 << WQ_WORKLOAD_SHIFT) 72 73 #define WQ_RING_TAIL_SHIFT 20 74 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ 75 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) 76 77 #define GUC_DOORBELL_ENABLED 1 78 #define GUC_DOORBELL_DISABLED 0 79 80 #define GUC_CTX_DESC_ATTR_ACTIVE (1 << 0) 81 #define GUC_CTX_DESC_ATTR_PENDING_DB (1 << 1) 82 #define GUC_CTX_DESC_ATTR_KERNEL (1 << 2) 83 #define GUC_CTX_DESC_ATTR_PREEMPT (1 << 3) 84 #define GUC_CTX_DESC_ATTR_RESET (1 << 4) 85 #define GUC_CTX_DESC_ATTR_WQLOCKED (1 << 5) 86 #define GUC_CTX_DESC_ATTR_PCH (1 << 6) 87 #define GUC_CTX_DESC_ATTR_TERMINATED (1 << 7) 88 89 /* The guc control data is 10 DWORDs */ 90 #define GUC_CTL_CTXINFO 0 91 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 92 #define GUC_CTL_BASE_ADDR_SHIFT 12 93 94 #define GUC_CTL_ARAT_HIGH 1 95 #define GUC_CTL_ARAT_LOW 2 96 97 #define GUC_CTL_DEVICE_INFO 3 98 #define GUC_CTL_GTTYPE_SHIFT 0 99 #define GUC_CTL_COREFAMILY_SHIFT 7 100 101 #define GUC_CTL_LOG_PARAMS 4 102 #define GUC_LOG_VALID (1 << 0) 103 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 104 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 105 #define GUC_LOG_CRASH_PAGES 1 106 #define GUC_LOG_CRASH_SHIFT 4 107 #define GUC_LOG_DPC_PAGES 3 108 #define GUC_LOG_DPC_SHIFT 6 109 #define GUC_LOG_ISR_PAGES 3 110 #define GUC_LOG_ISR_SHIFT 9 111 #define GUC_LOG_BUF_ADDR_SHIFT 12 112 113 #define GUC_CTL_PAGE_FAULT_CONTROL 5 114 115 #define GUC_CTL_WA 6 116 #define GUC_CTL_WA_UK_BY_DRIVER (1 << 3) 117 118 #define GUC_CTL_FEATURE 7 119 #define GUC_CTL_VCS2_ENABLED (1 << 0) 120 #define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1) 121 #define GUC_CTL_FEATURE2 (1 << 2) 122 #define GUC_CTL_POWER_GATING (1 << 3) 123 #define GUC_CTL_DISABLE_SCHEDULER (1 << 4) 124 #define GUC_CTL_PREEMPTION_LOG (1 << 5) 125 #define GUC_CTL_ENABLE_SLPC (1 << 7) 126 #define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8) 127 128 #define GUC_CTL_DEBUG 8 129 #define GUC_LOG_VERBOSITY_SHIFT 0 130 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 131 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 132 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 133 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 134 /* Verbosity range-check limits, without the shift */ 135 #define GUC_LOG_VERBOSITY_MIN 0 136 #define GUC_LOG_VERBOSITY_MAX 3 137 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 138 #define GUC_LOG_DESTINATION_MASK (3 << 4) 139 #define GUC_LOG_DISABLED (1 << 6) 140 #define GUC_PROFILE_ENABLED (1 << 7) 141 #define GUC_WQ_TRACK_ENABLED (1 << 8) 142 #define GUC_ADS_ENABLED (1 << 9) 143 #define GUC_DEBUG_RESERVED (1 << 10) 144 #define GUC_ADS_ADDR_SHIFT 11 145 #define GUC_ADS_ADDR_MASK 0xfffff800 146 147 #define GUC_CTL_RSRVD 9 148 149 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 150 151 /** 152 * DOC: GuC Firmware Layout 153 * 154 * The GuC firmware layout looks like this: 155 * 156 * +-------------------------------+ 157 * | guc_css_header | 158 * | contains major/minor version | 159 * +-------------------------------+ 160 * | uCode | 161 * +-------------------------------+ 162 * | RSA signature | 163 * +-------------------------------+ 164 * | modulus key | 165 * +-------------------------------+ 166 * | exponent val | 167 * +-------------------------------+ 168 * 169 * The firmware may or may not have modulus key and exponent data. The header, 170 * uCode and RSA signature are must-have components that will be used by driver. 171 * Length of each components, which is all in dwords, can be found in header. 172 * In the case that modulus and exponent are not present in fw, a.k.a truncated 173 * image, the length value still appears in header. 174 * 175 * Driver will do some basic fw size validation based on the following rules: 176 * 177 * 1. Header, uCode and RSA are must-have components. 178 * 2. All firmware components, if they present, are in the sequence illustrated 179 * in the layout table above. 180 * 3. Length info of each component can be found in header, in dwords. 181 * 4. Modulus and exponent key are not required by driver. They may not appear 182 * in fw. So driver will load a truncated firmware in this case. 183 */ 184 185 struct guc_css_header { 186 uint32_t module_type; 187 /* header_size includes all non-uCode bits, including css_header, rsa 188 * key, modulus key and exponent data. */ 189 uint32_t header_size_dw; 190 uint32_t header_version; 191 uint32_t module_id; 192 uint32_t module_vendor; 193 union { 194 struct { 195 uint8_t day; 196 uint8_t month; 197 uint16_t year; 198 }; 199 uint32_t date; 200 }; 201 uint32_t size_dw; /* uCode plus header_size_dw */ 202 uint32_t key_size_dw; 203 uint32_t modulus_size_dw; 204 uint32_t exponent_size_dw; 205 union { 206 struct { 207 uint8_t hour; 208 uint8_t min; 209 uint16_t sec; 210 }; 211 uint32_t time; 212 }; 213 214 char username[8]; 215 char buildnumber[12]; 216 uint32_t device_id; 217 uint32_t guc_sw_version; 218 uint32_t prod_preprod_fw; 219 uint32_t reserved[12]; 220 uint32_t header_info; 221 } __packed; 222 223 struct guc_doorbell_info { 224 u32 db_status; 225 u32 cookie; 226 u32 reserved[14]; 227 } __packed; 228 229 union guc_doorbell_qw { 230 struct { 231 u32 db_status; 232 u32 cookie; 233 }; 234 u64 value_qw; 235 } __packed; 236 237 #define GUC_MAX_DOORBELLS 256 238 #define GUC_INVALID_DOORBELL_ID (GUC_MAX_DOORBELLS) 239 240 #define GUC_DB_SIZE (PAGE_SIZE) 241 #define GUC_WQ_SIZE (PAGE_SIZE * 2) 242 243 /* Work item for submitting workloads into work queue of GuC. */ 244 struct guc_wq_item { 245 u32 header; 246 u32 context_desc; 247 u32 ring_tail; 248 u32 fence_id; 249 } __packed; 250 251 struct guc_process_desc { 252 u32 context_id; 253 u64 db_base_addr; 254 u32 head; 255 u32 tail; 256 u32 error_offset; 257 u64 wq_base_addr; 258 u32 wq_size_bytes; 259 u32 wq_status; 260 u32 engine_presence; 261 u32 priority; 262 u32 reserved[30]; 263 } __packed; 264 265 /* engine id and context id is packed into guc_execlist_context.context_id*/ 266 #define GUC_ELC_CTXID_OFFSET 0 267 #define GUC_ELC_ENGINE_OFFSET 29 268 269 /* The execlist context including software and HW information */ 270 struct guc_execlist_context { 271 u32 context_desc; 272 u32 context_id; 273 u32 ring_status; 274 u32 ring_lcra; 275 u32 ring_begin; 276 u32 ring_end; 277 u32 ring_next_free_location; 278 u32 ring_current_tail_pointer_value; 279 u8 engine_state_submit_value; 280 u8 engine_state_wait_value; 281 u16 pagefault_count; 282 u16 engine_submit_queue_count; 283 } __packed; 284 285 /*Context descriptor for communicating between uKernel and Driver*/ 286 struct guc_context_desc { 287 u32 sched_common_area; 288 u32 context_id; 289 u32 pas_id; 290 u8 engines_used; 291 u64 db_trigger_cpu; 292 u32 db_trigger_uk; 293 u64 db_trigger_phy; 294 u16 db_id; 295 296 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; 297 298 u8 attribute; 299 300 u32 priority; 301 302 u32 wq_sampled_tail_offset; 303 u32 wq_total_submit_enqueues; 304 305 u32 process_desc; 306 u32 wq_addr; 307 u32 wq_size; 308 309 u32 engine_presence; 310 311 u8 engine_suspended; 312 313 u8 reserved0[3]; 314 u64 reserved1[1]; 315 316 u64 desc_private; 317 } __packed; 318 319 #define GUC_FORCEWAKE_RENDER (1 << 0) 320 #define GUC_FORCEWAKE_MEDIA (1 << 1) 321 322 #define GUC_POWER_UNSPECIFIED 0 323 #define GUC_POWER_D0 1 324 #define GUC_POWER_D1 2 325 #define GUC_POWER_D2 3 326 #define GUC_POWER_D3 4 327 328 /* Scheduling policy settings */ 329 330 /* Reset engine upon preempt failure */ 331 #define POLICY_RESET_ENGINE (1<<0) 332 /* Preempt to idle on quantum expiry */ 333 #define POLICY_PREEMPT_TO_IDLE (1<<1) 334 335 #define POLICY_MAX_NUM_WI 15 336 337 struct guc_policy { 338 /* Time for one workload to execute. (in micro seconds) */ 339 u32 execution_quantum; 340 u32 reserved1; 341 342 /* Time to wait for a preemption request to completed before issuing a 343 * reset. (in micro seconds). */ 344 u32 preemption_time; 345 346 /* How much time to allow to run after the first fault is observed. 347 * Then preempt afterwards. (in micro seconds) */ 348 u32 fault_time; 349 350 u32 policy_flags; 351 u32 reserved[2]; 352 } __packed; 353 354 struct guc_policies { 355 struct guc_policy policy[GUC_CTX_PRIORITY_NUM][GUC_MAX_ENGINES_NUM]; 356 357 /* In micro seconds. How much time to allow before DPC processing is 358 * called back via interrupt (to prevent DPC queue drain starving). 359 * Typically 1000s of micro seconds (example only, not granularity). */ 360 u32 dpc_promote_time; 361 362 /* Must be set to take these new values. */ 363 u32 is_valid; 364 365 /* Max number of WIs to process per call. A large value may keep CS 366 * idle. */ 367 u32 max_num_work_items; 368 369 u32 reserved[19]; 370 } __packed; 371 372 /* GuC MMIO reg state struct */ 373 374 #define GUC_REGSET_FLAGS_NONE 0x0 375 #define GUC_REGSET_POWERCYCLE 0x1 376 #define GUC_REGSET_MASKED 0x2 377 #define GUC_REGSET_ENGINERESET 0x4 378 #define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8 379 #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 380 381 #define GUC_REGSET_MAX_REGISTERS 25 382 #define GUC_MMIO_WHITE_LIST_START 0x24d0 383 #define GUC_MMIO_WHITE_LIST_MAX 12 384 #define GUC_S3_SAVE_SPACE_PAGES 10 385 386 struct guc_mmio_regset { 387 struct __packed { 388 u32 offset; 389 u32 value; 390 u32 flags; 391 } registers[GUC_REGSET_MAX_REGISTERS]; 392 393 u32 values_valid; 394 u32 number_of_registers; 395 } __packed; 396 397 struct guc_mmio_reg_state { 398 struct guc_mmio_regset global_reg; 399 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM]; 400 401 /* MMIO registers that are set as non privileged */ 402 struct __packed { 403 u32 mmio_start; 404 u32 offsets[GUC_MMIO_WHITE_LIST_MAX]; 405 u32 count; 406 } mmio_white_list[GUC_MAX_ENGINES_NUM]; 407 } __packed; 408 409 /* GuC Additional Data Struct */ 410 411 struct guc_ads { 412 u32 reg_state_addr; 413 u32 reg_state_buffer; 414 u32 golden_context_lrca; 415 u32 scheduler_policies; 416 u32 reserved0[3]; 417 u32 eng_state_size[GUC_MAX_ENGINES_NUM]; 418 u32 reserved2[4]; 419 } __packed; 420 421 /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */ 422 enum host2guc_action { 423 HOST2GUC_ACTION_DEFAULT = 0x0, 424 HOST2GUC_ACTION_SAMPLE_FORCEWAKE = 0x6, 425 HOST2GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 426 HOST2GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 427 HOST2GUC_ACTION_ENTER_S_STATE = 0x501, 428 HOST2GUC_ACTION_EXIT_S_STATE = 0x502, 429 HOST2GUC_ACTION_SLPC_REQUEST = 0x3003, 430 HOST2GUC_ACTION_LIMIT 431 }; 432 433 /* 434 * The GuC sends its response to a command by overwriting the 435 * command in SS0. The response is distinguishable from a command 436 * by the fact that all the MASK bits are set. The remaining bits 437 * give more detail. 438 */ 439 #define GUC2HOST_RESPONSE_MASK ((u32)0xF0000000) 440 #define GUC2HOST_IS_RESPONSE(x) ((u32)(x) >= GUC2HOST_RESPONSE_MASK) 441 #define GUC2HOST_STATUS(x) (GUC2HOST_RESPONSE_MASK | (x)) 442 443 /* GUC will return status back to SOFT_SCRATCH_O_REG */ 444 enum guc2host_status { 445 GUC2HOST_STATUS_SUCCESS = GUC2HOST_STATUS(0x0), 446 GUC2HOST_STATUS_ALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x10), 447 GUC2HOST_STATUS_DEALLOCATE_DOORBELL_FAIL = GUC2HOST_STATUS(0x20), 448 GUC2HOST_STATUS_GENERIC_FAIL = GUC2HOST_STATUS(0x0000F000) 449 }; 450 451 #endif 452