1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Shobhit Kumar <shobhit.kumar@intel.com> 25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> 26 */ 27 28 #include <linux/kernel.h> 29 #include "intel_drv.h" 30 #include "i915_drv.h" 31 #include "intel_dsi.h" 32 33 #define DSI_HSS_PACKET_SIZE 4 34 #define DSI_HSE_PACKET_SIZE 4 35 #define DSI_HSA_PACKET_EXTRA_SIZE 6 36 #define DSI_HBP_PACKET_EXTRA_SIZE 6 37 #define DSI_HACTIVE_PACKET_EXTRA_SIZE 6 38 #define DSI_HFP_PACKET_EXTRA_SIZE 6 39 #define DSI_EOTP_PACKET_SIZE 4 40 41 static int dsi_pixel_format_bpp(int pixel_format) 42 { 43 int bpp; 44 45 switch (pixel_format) { 46 default: 47 case VID_MODE_FORMAT_RGB888: 48 case VID_MODE_FORMAT_RGB666_LOOSE: 49 bpp = 24; 50 break; 51 case VID_MODE_FORMAT_RGB666: 52 bpp = 18; 53 break; 54 case VID_MODE_FORMAT_RGB565: 55 bpp = 16; 56 break; 57 } 58 59 return bpp; 60 } 61 62 struct dsi_mnp { 63 u32 dsi_pll_ctrl; 64 u32 dsi_pll_div; 65 }; 66 67 static const u32 lfsr_converts[] = { 68 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 69 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 70 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ 71 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ 72 }; 73 74 #ifdef DSI_CLK_FROM_RR 75 76 static u32 dsi_rr_formula(const struct drm_display_mode *mode, 77 int pixel_format, int video_mode_format, 78 int lane_count, bool eotp) 79 { 80 u32 bpp; 81 u32 hactive, vactive, hfp, hsync, hbp, vfp, vsync, vbp; 82 u32 hsync_bytes, hbp_bytes, hactive_bytes, hfp_bytes; 83 u32 bytes_per_line, bytes_per_frame; 84 u32 num_frames; 85 u32 bytes_per_x_frames, bytes_per_x_frames_x_lanes; 86 u32 dsi_bit_clock_hz; 87 u32 dsi_clk; 88 89 bpp = dsi_pixel_format_bpp(pixel_format); 90 91 hactive = mode->hdisplay; 92 vactive = mode->vdisplay; 93 hfp = mode->hsync_start - mode->hdisplay; 94 hsync = mode->hsync_end - mode->hsync_start; 95 hbp = mode->htotal - mode->hsync_end; 96 97 vfp = mode->vsync_start - mode->vdisplay; 98 vsync = mode->vsync_end - mode->vsync_start; 99 vbp = mode->vtotal - mode->vsync_end; 100 101 hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); 102 hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); 103 hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); 104 hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); 105 106 bytes_per_line = DSI_HSS_PACKET_SIZE + hsync_bytes + 107 DSI_HSA_PACKET_EXTRA_SIZE + DSI_HSE_PACKET_SIZE + 108 hbp_bytes + DSI_HBP_PACKET_EXTRA_SIZE + 109 hactive_bytes + DSI_HACTIVE_PACKET_EXTRA_SIZE + 110 hfp_bytes + DSI_HFP_PACKET_EXTRA_SIZE; 111 112 /* 113 * XXX: Need to accurately calculate LP to HS transition timeout and add 114 * it to bytes_per_line/bytes_per_frame. 115 */ 116 117 if (eotp && video_mode_format == VIDEO_MODE_BURST) 118 bytes_per_line += DSI_EOTP_PACKET_SIZE; 119 120 bytes_per_frame = vsync * bytes_per_line + vbp * bytes_per_line + 121 vactive * bytes_per_line + vfp * bytes_per_line; 122 123 if (eotp && 124 (video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE || 125 video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS)) 126 bytes_per_frame += DSI_EOTP_PACKET_SIZE; 127 128 num_frames = drm_mode_vrefresh(mode); 129 bytes_per_x_frames = num_frames * bytes_per_frame; 130 131 bytes_per_x_frames_x_lanes = bytes_per_x_frames / lane_count; 132 133 /* the dsi clock is divided by 2 in the hardware to get dsi ddr clock */ 134 dsi_bit_clock_hz = bytes_per_x_frames_x_lanes * 8; 135 dsi_clk = dsi_bit_clock_hz / 1000; 136 137 if (eotp && video_mode_format == VIDEO_MODE_BURST) 138 dsi_clk *= 2; 139 140 return dsi_clk; 141 } 142 143 #else 144 145 /* Get DSI clock from pixel clock */ 146 static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) 147 { 148 u32 dsi_clk_khz; 149 u32 bpp = dsi_pixel_format_bpp(pixel_format); 150 151 /* DSI data rate = pixel clock * bits per pixel / lane count 152 pixel clock is converted from KHz to Hz */ 153 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); 154 155 return dsi_clk_khz; 156 } 157 158 #endif 159 160 static int dsi_calc_mnp(struct drm_i915_private *dev_priv, 161 struct dsi_mnp *dsi_mnp, int target_dsi_clk) 162 { 163 unsigned int calc_m = 0, calc_p = 0; 164 unsigned int m_min, m_max, p_min = 2, p_max = 6; 165 unsigned int m, n, p; 166 int ref_clk; 167 int delta = target_dsi_clk; 168 u32 m_seed; 169 170 /* target_dsi_clk is expected in kHz */ 171 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { 172 DRM_ERROR("DSI CLK Out of Range\n"); 173 return -ECHRNG; 174 } 175 176 if (IS_CHERRYVIEW(dev_priv)) { 177 ref_clk = 100000; 178 n = 4; 179 m_min = 70; 180 m_max = 96; 181 } else { 182 ref_clk = 25000; 183 n = 1; 184 m_min = 62; 185 m_max = 92; 186 } 187 188 for (m = m_min; m <= m_max && delta; m++) { 189 for (p = p_min; p <= p_max && delta; p++) { 190 /* 191 * Find the optimal m and p divisors with minimal delta 192 * +/- the required clock 193 */ 194 int calc_dsi_clk = (m * ref_clk) / (p * n); 195 int d = abs(target_dsi_clk - calc_dsi_clk); 196 if (d < delta) { 197 delta = d; 198 calc_m = m; 199 calc_p = p; 200 } 201 } 202 } 203 204 /* register has log2(N1), this works fine for powers of two */ 205 n = ffs(n) - 1; 206 m_seed = lfsr_converts[calc_m - 62]; 207 dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); 208 dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | 209 m_seed << DSI_PLL_M1_DIV_SHIFT; 210 211 return 0; 212 } 213 214 /* 215 * XXX: The muxing and gating is hard coded for now. Need to add support for 216 * sharing PLLs with two DSI outputs. 217 */ 218 static void vlv_configure_dsi_pll(struct intel_encoder *encoder) 219 { 220 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 221 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 222 int ret; 223 struct dsi_mnp dsi_mnp; 224 u32 dsi_clk; 225 226 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 227 intel_dsi->lane_count); 228 229 ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); 230 if (ret) { 231 DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); 232 return; 233 } 234 235 if (intel_dsi->ports & (1 << PORT_A)) 236 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; 237 238 if (intel_dsi->ports & (1 << PORT_C)) 239 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; 240 241 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", 242 dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); 243 244 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); 245 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); 246 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); 247 } 248 249 void vlv_enable_dsi_pll(struct intel_encoder *encoder) 250 { 251 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 252 u32 tmp; 253 254 DRM_DEBUG_KMS("\n"); 255 256 mutex_lock(&dev_priv->sb_lock); 257 258 vlv_configure_dsi_pll(encoder); 259 260 /* wait at least 0.5 us after ungating before enabling VCO */ 261 usleep_range(1, 10); 262 263 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 264 tmp |= DSI_PLL_VCO_EN; 265 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 266 267 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & 268 DSI_PLL_LOCK, 20)) { 269 270 mutex_unlock(&dev_priv->sb_lock); 271 DRM_ERROR("DSI PLL lock failed\n"); 272 return; 273 } 274 mutex_unlock(&dev_priv->sb_lock); 275 276 DRM_DEBUG_KMS("DSI PLL locked\n"); 277 } 278 279 void vlv_disable_dsi_pll(struct intel_encoder *encoder) 280 { 281 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 282 u32 tmp; 283 284 DRM_DEBUG_KMS("\n"); 285 286 mutex_lock(&dev_priv->sb_lock); 287 288 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 289 tmp &= ~DSI_PLL_VCO_EN; 290 tmp |= DSI_PLL_LDO_GATE; 291 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 292 293 mutex_unlock(&dev_priv->sb_lock); 294 } 295 296 static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) 297 { 298 int bpp = dsi_pixel_format_bpp(pixel_format); 299 300 WARN(bpp != pipe_bpp, 301 "bpp match assertion failure (expected %d, current %d)\n", 302 bpp, pipe_bpp); 303 } 304 305 u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp) 306 { 307 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 308 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 309 u32 dsi_clock, pclk; 310 u32 pll_ctl, pll_div; 311 u32 m = 0, p = 0, n; 312 int refclk = 25000; 313 int i; 314 315 DRM_DEBUG_KMS("\n"); 316 317 mutex_lock(&dev_priv->sb_lock); 318 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 319 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); 320 mutex_unlock(&dev_priv->sb_lock); 321 322 /* mask out other bits and extract the P1 divisor */ 323 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; 324 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); 325 326 /* N1 divisor */ 327 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; 328 n = 1 << n; /* register has log2(N1) */ 329 330 /* mask out the other bits and extract the M1 divisor */ 331 pll_div &= DSI_PLL_M1_DIV_MASK; 332 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; 333 334 while (pll_ctl) { 335 pll_ctl = pll_ctl >> 1; 336 p++; 337 } 338 p--; 339 340 if (!p) { 341 DRM_ERROR("wrong P1 divisor\n"); 342 return 0; 343 } 344 345 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { 346 if (lfsr_converts[i] == pll_div) 347 break; 348 } 349 350 if (i == ARRAY_SIZE(lfsr_converts)) { 351 DRM_ERROR("wrong m_seed programmed\n"); 352 return 0; 353 } 354 355 m = i + 62; 356 357 dsi_clock = (m * refclk) / (p * n); 358 359 /* pixel_format and pipe_bpp should agree */ 360 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); 361 362 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); 363 364 return pclk; 365 } 366