1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Shobhit Kumar <shobhit.kumar@intel.com> 25 * Yogesh Mohan Marimuthu <yogesh.mohan.marimuthu@intel.com> 26 */ 27 28 #include <linux/kernel.h> 29 #include "intel_drv.h" 30 #include "i915_drv.h" 31 #include "intel_dsi.h" 32 33 int dsi_pixel_format_bpp(int pixel_format) 34 { 35 int bpp; 36 37 switch (pixel_format) { 38 default: 39 case VID_MODE_FORMAT_RGB888: 40 case VID_MODE_FORMAT_RGB666_LOOSE: 41 bpp = 24; 42 break; 43 case VID_MODE_FORMAT_RGB666: 44 bpp = 18; 45 break; 46 case VID_MODE_FORMAT_RGB565: 47 bpp = 16; 48 break; 49 } 50 51 return bpp; 52 } 53 54 struct dsi_mnp { 55 u32 dsi_pll_ctrl; 56 u32 dsi_pll_div; 57 }; 58 59 static const u32 lfsr_converts[] = { 60 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */ 61 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */ 62 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */ 63 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */ 64 }; 65 66 /* Get DSI clock from pixel clock */ 67 static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) 68 { 69 u32 dsi_clk_khz; 70 u32 bpp = dsi_pixel_format_bpp(pixel_format); 71 72 /* DSI data rate = pixel clock * bits per pixel / lane count 73 pixel clock is converted from KHz to Hz */ 74 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); 75 76 return dsi_clk_khz; 77 } 78 79 static int dsi_calc_mnp(struct drm_i915_private *dev_priv, 80 struct dsi_mnp *dsi_mnp, int target_dsi_clk) 81 { 82 unsigned int calc_m = 0, calc_p = 0; 83 unsigned int m_min, m_max, p_min = 2, p_max = 6; 84 unsigned int m, n, p; 85 int ref_clk; 86 int delta = target_dsi_clk; 87 u32 m_seed; 88 89 /* target_dsi_clk is expected in kHz */ 90 if (target_dsi_clk < 300000 || target_dsi_clk > 1150000) { 91 DRM_ERROR("DSI CLK Out of Range\n"); 92 return -ECHRNG; 93 } 94 95 if (IS_CHERRYVIEW(dev_priv)) { 96 ref_clk = 100000; 97 n = 4; 98 m_min = 70; 99 m_max = 96; 100 } else { 101 ref_clk = 25000; 102 n = 1; 103 m_min = 62; 104 m_max = 92; 105 } 106 107 for (m = m_min; m <= m_max && delta; m++) { 108 for (p = p_min; p <= p_max && delta; p++) { 109 /* 110 * Find the optimal m and p divisors with minimal delta 111 * +/- the required clock 112 */ 113 int calc_dsi_clk = (m * ref_clk) / (p * n); 114 int d = abs(target_dsi_clk - calc_dsi_clk); 115 if (d < delta) { 116 delta = d; 117 calc_m = m; 118 calc_p = p; 119 } 120 } 121 } 122 123 /* register has log2(N1), this works fine for powers of two */ 124 n = ffs(n) - 1; 125 m_seed = lfsr_converts[calc_m - 62]; 126 dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); 127 dsi_mnp->dsi_pll_div = n << DSI_PLL_N1_DIV_SHIFT | 128 m_seed << DSI_PLL_M1_DIV_SHIFT; 129 130 return 0; 131 } 132 133 /* 134 * XXX: The muxing and gating is hard coded for now. Need to add support for 135 * sharing PLLs with two DSI outputs. 136 */ 137 static void vlv_configure_dsi_pll(struct intel_encoder *encoder) 138 { 139 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 140 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 141 int ret; 142 struct dsi_mnp dsi_mnp; 143 u32 dsi_clk; 144 145 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 146 intel_dsi->lane_count); 147 148 ret = dsi_calc_mnp(dev_priv, &dsi_mnp, dsi_clk); 149 if (ret) { 150 DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); 151 return; 152 } 153 154 if (intel_dsi->ports & (1 << PORT_A)) 155 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; 156 157 if (intel_dsi->ports & (1 << PORT_C)) 158 dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; 159 160 DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", 161 dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); 162 163 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0); 164 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, dsi_mnp.dsi_pll_div); 165 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, dsi_mnp.dsi_pll_ctrl); 166 } 167 168 static void vlv_enable_dsi_pll(struct intel_encoder *encoder) 169 { 170 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 171 u32 tmp; 172 173 DRM_DEBUG_KMS("\n"); 174 175 mutex_lock(&dev_priv->sb_lock); 176 177 vlv_configure_dsi_pll(encoder); 178 179 /* wait at least 0.5 us after ungating before enabling VCO */ 180 usleep_range(1, 10); 181 182 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 183 tmp |= DSI_PLL_VCO_EN; 184 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 185 186 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & 187 DSI_PLL_LOCK, 20)) { 188 189 mutex_unlock(&dev_priv->sb_lock); 190 DRM_ERROR("DSI PLL lock failed\n"); 191 return; 192 } 193 mutex_unlock(&dev_priv->sb_lock); 194 195 DRM_DEBUG_KMS("DSI PLL locked\n"); 196 } 197 198 static void vlv_disable_dsi_pll(struct intel_encoder *encoder) 199 { 200 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 201 u32 tmp; 202 203 DRM_DEBUG_KMS("\n"); 204 205 mutex_lock(&dev_priv->sb_lock); 206 207 tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 208 tmp &= ~DSI_PLL_VCO_EN; 209 tmp |= DSI_PLL_LDO_GATE; 210 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); 211 212 mutex_unlock(&dev_priv->sb_lock); 213 } 214 215 static void bxt_disable_dsi_pll(struct intel_encoder *encoder) 216 { 217 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 218 u32 val; 219 220 DRM_DEBUG_KMS("\n"); 221 222 val = I915_READ(BXT_DSI_PLL_ENABLE); 223 val &= ~BXT_DSI_PLL_DO_ENABLE; 224 I915_WRITE(BXT_DSI_PLL_ENABLE, val); 225 226 /* 227 * PLL lock should deassert within 200us. 228 * Wait up to 1ms before timing out. 229 */ 230 if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE) 231 & BXT_DSI_PLL_LOCKED) == 0, 1)) 232 DRM_ERROR("Timeout waiting for PLL lock deassertion\n"); 233 } 234 235 static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) 236 { 237 int bpp = dsi_pixel_format_bpp(pixel_format); 238 239 WARN(bpp != pipe_bpp, 240 "bpp match assertion failure (expected %d, current %d)\n", 241 bpp, pipe_bpp); 242 } 243 244 static u32 vlv_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) 245 { 246 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 247 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 248 u32 dsi_clock, pclk; 249 u32 pll_ctl, pll_div; 250 u32 m = 0, p = 0, n; 251 int refclk = 25000; 252 int i; 253 254 DRM_DEBUG_KMS("\n"); 255 256 mutex_lock(&dev_priv->sb_lock); 257 pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); 258 pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); 259 mutex_unlock(&dev_priv->sb_lock); 260 261 /* mask out other bits and extract the P1 divisor */ 262 pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; 263 pll_ctl = pll_ctl >> (DSI_PLL_P1_POST_DIV_SHIFT - 2); 264 265 /* N1 divisor */ 266 n = (pll_div & DSI_PLL_N1_DIV_MASK) >> DSI_PLL_N1_DIV_SHIFT; 267 n = 1 << n; /* register has log2(N1) */ 268 269 /* mask out the other bits and extract the M1 divisor */ 270 pll_div &= DSI_PLL_M1_DIV_MASK; 271 pll_div = pll_div >> DSI_PLL_M1_DIV_SHIFT; 272 273 while (pll_ctl) { 274 pll_ctl = pll_ctl >> 1; 275 p++; 276 } 277 p--; 278 279 if (!p) { 280 DRM_ERROR("wrong P1 divisor\n"); 281 return 0; 282 } 283 284 for (i = 0; i < ARRAY_SIZE(lfsr_converts); i++) { 285 if (lfsr_converts[i] == pll_div) 286 break; 287 } 288 289 if (i == ARRAY_SIZE(lfsr_converts)) { 290 DRM_ERROR("wrong m_seed programmed\n"); 291 return 0; 292 } 293 294 m = i + 62; 295 296 dsi_clock = (m * refclk) / (p * n); 297 298 /* pixel_format and pipe_bpp should agree */ 299 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); 300 301 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, pipe_bpp); 302 303 return pclk; 304 } 305 306 static u32 bxt_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) 307 { 308 u32 pclk; 309 u32 dsi_clk; 310 u32 dsi_ratio; 311 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 312 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 313 314 /* Divide by zero */ 315 if (!pipe_bpp) { 316 DRM_ERROR("Invalid BPP(0)\n"); 317 return 0; 318 } 319 320 dsi_ratio = I915_READ(BXT_DSI_PLL_CTL) & 321 BXT_DSI_PLL_RATIO_MASK; 322 323 /* Invalid DSI ratio ? */ 324 if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || 325 dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { 326 DRM_ERROR("Invalid DSI pll ratio(%u) programmed\n", dsi_ratio); 327 return 0; 328 } 329 330 dsi_clk = (dsi_ratio * BXT_REF_CLOCK_KHZ) / 2; 331 332 /* pixel_format and pipe_bpp should agree */ 333 assert_bpp_mismatch(intel_dsi->pixel_format, pipe_bpp); 334 335 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, pipe_bpp); 336 337 DRM_DEBUG_DRIVER("Calculated pclk=%u\n", pclk); 338 return pclk; 339 } 340 341 u32 intel_dsi_get_pclk(struct intel_encoder *encoder, int pipe_bpp) 342 { 343 if (IS_BROXTON(encoder->base.dev)) 344 return bxt_dsi_get_pclk(encoder, pipe_bpp); 345 else 346 return vlv_dsi_get_pclk(encoder, pipe_bpp); 347 } 348 349 static void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 350 { 351 u32 temp; 352 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 353 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 354 355 temp = I915_READ(MIPI_CTRL(port)); 356 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 357 I915_WRITE(MIPI_CTRL(port), temp | 358 intel_dsi->escape_clk_div << 359 ESCAPE_CLOCK_DIVIDER_SHIFT); 360 } 361 362 /* Program BXT Mipi clocks and dividers */ 363 static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port) 364 { 365 u32 tmp; 366 u32 divider; 367 u32 dsi_rate; 368 u32 pll_ratio; 369 struct drm_i915_private *dev_priv = dev->dev_private; 370 371 /* Clear old configurations */ 372 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); 373 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 374 tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); 375 tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); 376 tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); 377 378 /* Get the current DSI rate(actual) */ 379 pll_ratio = I915_READ(BXT_DSI_PLL_CTL) & 380 BXT_DSI_PLL_RATIO_MASK; 381 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; 382 383 /* Max possible output of clock is 39.5 MHz, program value -1 */ 384 divider = (dsi_rate / BXT_MAX_VAR_OUTPUT_KHZ) - 1; 385 tmp |= BXT_MIPI_ESCLK_VAR_DIV(port, divider); 386 387 /* 388 * Tx escape clock must be as close to 20MHz possible, but should 389 * not exceed it. Hence select divide by 2 390 */ 391 tmp |= BXT_MIPI_TX_ESCLK_8XDIV_BY2(port); 392 393 tmp |= BXT_MIPI_RX_ESCLK_8X_BY3(port); 394 395 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); 396 } 397 398 static bool bxt_configure_dsi_pll(struct intel_encoder *encoder) 399 { 400 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 401 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 402 u8 dsi_ratio; 403 u32 dsi_clk; 404 u32 val; 405 406 dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, 407 intel_dsi->lane_count); 408 409 /* 410 * From clock diagram, to get PLL ratio divider, divide double of DSI 411 * link rate (i.e., 2*8x=16x frequency value) by ref clock. Make sure to 412 * round 'up' the result 413 */ 414 dsi_ratio = DIV_ROUND_UP(dsi_clk * 2, BXT_REF_CLOCK_KHZ); 415 if (dsi_ratio < BXT_DSI_PLL_RATIO_MIN || 416 dsi_ratio > BXT_DSI_PLL_RATIO_MAX) { 417 DRM_ERROR("Cant get a suitable ratio from DSI PLL ratios\n"); 418 return false; 419 } 420 421 /* 422 * Program DSI ratio and Select MIPIC and MIPIA PLL output as 8x 423 * Spec says both have to be programmed, even if one is not getting 424 * used. Configure MIPI_CLOCK_CTL dividers in modeset 425 */ 426 val = I915_READ(BXT_DSI_PLL_CTL); 427 val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; 428 val &= ~BXT_DSI_FREQ_SEL_MASK; 429 val &= ~BXT_DSI_PLL_RATIO_MASK; 430 val |= (dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2); 431 432 /* As per recommendation from hardware team, 433 * Prog PVD ratio =1 if dsi ratio <= 50 434 */ 435 if (dsi_ratio <= 50) { 436 val &= ~BXT_DSI_PLL_PVD_RATIO_MASK; 437 val |= BXT_DSI_PLL_PVD_RATIO_1; 438 } 439 440 I915_WRITE(BXT_DSI_PLL_CTL, val); 441 POSTING_READ(BXT_DSI_PLL_CTL); 442 443 return true; 444 } 445 446 static void bxt_enable_dsi_pll(struct intel_encoder *encoder) 447 { 448 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 449 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 450 enum port port; 451 u32 val; 452 453 DRM_DEBUG_KMS("\n"); 454 455 val = I915_READ(BXT_DSI_PLL_ENABLE); 456 457 if (val & BXT_DSI_PLL_DO_ENABLE) { 458 WARN(1, "DSI PLL already enabled. Disabling it.\n"); 459 val &= ~BXT_DSI_PLL_DO_ENABLE; 460 I915_WRITE(BXT_DSI_PLL_ENABLE, val); 461 } 462 463 /* Configure PLL vales */ 464 if (!bxt_configure_dsi_pll(encoder)) { 465 DRM_ERROR("Configure DSI PLL failed, abort PLL enable\n"); 466 return; 467 } 468 469 /* Program TX, RX, Dphy clocks */ 470 for_each_dsi_port(port, intel_dsi->ports) 471 bxt_dsi_program_clocks(encoder->base.dev, port); 472 473 /* Enable DSI PLL */ 474 val = I915_READ(BXT_DSI_PLL_ENABLE); 475 val |= BXT_DSI_PLL_DO_ENABLE; 476 I915_WRITE(BXT_DSI_PLL_ENABLE, val); 477 478 /* Timeout and fail if PLL not locked */ 479 if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) { 480 DRM_ERROR("Timed out waiting for DSI PLL to lock\n"); 481 return; 482 } 483 484 DRM_DEBUG_KMS("DSI PLL locked\n"); 485 } 486 487 void intel_enable_dsi_pll(struct intel_encoder *encoder) 488 { 489 struct drm_device *dev = encoder->base.dev; 490 491 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 492 vlv_enable_dsi_pll(encoder); 493 else if (IS_BROXTON(dev)) 494 bxt_enable_dsi_pll(encoder); 495 } 496 497 void intel_disable_dsi_pll(struct intel_encoder *encoder) 498 { 499 struct drm_device *dev = encoder->base.dev; 500 501 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 502 vlv_disable_dsi_pll(encoder); 503 else if (IS_BROXTON(dev)) 504 bxt_disable_dsi_pll(encoder); 505 } 506 507 static void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 508 { 509 u32 tmp; 510 struct drm_device *dev = encoder->base.dev; 511 struct drm_i915_private *dev_priv = dev->dev_private; 512 513 /* Clear old configurations */ 514 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); 515 tmp &= ~(BXT_MIPI_TX_ESCLK_FIXDIV_MASK(port)); 516 tmp &= ~(BXT_MIPI_RX_ESCLK_FIXDIV_MASK(port)); 517 tmp &= ~(BXT_MIPI_ESCLK_VAR_DIV_MASK(port)); 518 tmp &= ~(BXT_MIPI_DPHY_DIVIDER_MASK(port)); 519 I915_WRITE(BXT_MIPI_CLOCK_CTL, tmp); 520 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); 521 } 522 523 void intel_dsi_reset_clocks(struct intel_encoder *encoder, enum port port) 524 { 525 struct drm_device *dev = encoder->base.dev; 526 527 if (IS_BROXTON(dev)) 528 bxt_dsi_reset_clocks(encoder, port); 529 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) 530 vlv_dsi_reset_clocks(encoder, port); 531 } 532