1 /* 2 * Copyright © 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Jani Nikula <jani.nikula@intel.com> 24 */ 25 26 #include <drm/drmP.h> 27 #include <drm/drm_crtc.h> 28 #include <drm/drm_edid.h> 29 #include <drm/i915_drm.h> 30 #include <linux/slab.h> 31 #include "i915_drv.h" 32 #include "intel_drv.h" 33 #include "intel_dsi.h" 34 #include "intel_dsi_cmd.h" 35 36 /* the sub-encoders aka panel drivers */ 37 static const struct intel_dsi_device intel_dsi_devices[] = { 38 { 39 .panel_id = MIPI_DSI_GENERIC_PANEL_ID, 40 .name = "vbt-generic-dsi-vid-mode-display", 41 .dev_ops = &vbt_generic_dsi_display_ops, 42 }, 43 }; 44 45 static void band_gap_reset(struct drm_i915_private *dev_priv) 46 { 47 mutex_lock(&dev_priv->dpio_lock); 48 49 vlv_flisdsi_write(dev_priv, 0x08, 0x0001); 50 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); 51 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); 52 udelay(150); 53 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); 54 vlv_flisdsi_write(dev_priv, 0x08, 0x0000); 55 56 mutex_unlock(&dev_priv->dpio_lock); 57 } 58 59 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) 60 { 61 return container_of(intel_attached_encoder(connector), 62 struct intel_dsi, base); 63 } 64 65 static inline bool is_vid_mode(struct intel_dsi *intel_dsi) 66 { 67 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; 68 } 69 70 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) 71 { 72 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; 73 } 74 75 static void intel_dsi_hot_plug(struct intel_encoder *encoder) 76 { 77 DRM_DEBUG_KMS("\n"); 78 } 79 80 static bool intel_dsi_compute_config(struct intel_encoder *encoder, 81 struct intel_crtc_config *config) 82 { 83 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 84 base); 85 struct intel_connector *intel_connector = intel_dsi->attached_connector; 86 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 87 struct drm_display_mode *adjusted_mode = &config->adjusted_mode; 88 struct drm_display_mode *mode = &config->requested_mode; 89 90 DRM_DEBUG_KMS("\n"); 91 92 if (fixed_mode) 93 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 94 95 if (intel_dsi->dev.dev_ops->mode_fixup) 96 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, 97 mode, adjusted_mode); 98 99 return true; 100 } 101 102 static void intel_dsi_device_ready(struct intel_encoder *encoder) 103 { 104 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 105 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 106 int pipe = intel_crtc->pipe; 107 u32 val; 108 109 DRM_DEBUG_KMS("\n"); 110 111 mutex_lock(&dev_priv->dpio_lock); 112 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms 113 * needed everytime after power gate */ 114 vlv_flisdsi_write(dev_priv, 0x04, 0x0004); 115 mutex_unlock(&dev_priv->dpio_lock); 116 117 /* bandgap reset is needed after everytime we do power gate */ 118 band_gap_reset(dev_priv); 119 120 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER); 121 usleep_range(2500, 3000); 122 123 val = I915_READ(MIPI_PORT_CTRL(pipe)); 124 I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD); 125 usleep_range(1000, 1500); 126 127 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT); 128 usleep_range(2500, 3000); 129 130 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY); 131 usleep_range(2500, 3000); 132 } 133 134 static void intel_dsi_enable(struct intel_encoder *encoder) 135 { 136 struct drm_device *dev = encoder->base.dev; 137 struct drm_i915_private *dev_priv = dev->dev_private; 138 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 139 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 140 int pipe = intel_crtc->pipe; 141 u32 temp; 142 143 DRM_DEBUG_KMS("\n"); 144 145 if (is_cmd_mode(intel_dsi)) 146 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4); 147 else { 148 msleep(20); /* XXX */ 149 dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); 150 msleep(100); 151 152 if (intel_dsi->dev.dev_ops->enable) 153 intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); 154 155 /* assert ip_tg_enable signal */ 156 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK; 157 temp = temp | intel_dsi->port_bits; 158 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE); 159 POSTING_READ(MIPI_PORT_CTRL(pipe)); 160 } 161 } 162 163 static void intel_dsi_pre_enable(struct intel_encoder *encoder) 164 { 165 struct drm_device *dev = encoder->base.dev; 166 struct drm_i915_private *dev_priv = dev->dev_private; 167 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 168 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 169 enum i915_pipe pipe = intel_crtc->pipe; 170 u32 tmp; 171 172 DRM_DEBUG_KMS("\n"); 173 174 /* Disable DPOunit clock gating, can stall pipe 175 * and we need DPLL REFA always enabled */ 176 tmp = I915_READ(DPLL(pipe)); 177 tmp |= DPLL_REFA_CLK_ENABLE_VLV; 178 I915_WRITE(DPLL(pipe), tmp); 179 180 tmp = I915_READ(DSPCLK_GATE_D); 181 tmp |= DPOUNIT_CLOCK_GATE_DISABLE; 182 I915_WRITE(DSPCLK_GATE_D, tmp); 183 184 /* put device in ready state */ 185 intel_dsi_device_ready(encoder); 186 187 msleep(intel_dsi->panel_on_delay); 188 189 if (intel_dsi->dev.dev_ops->panel_reset) 190 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); 191 192 if (intel_dsi->dev.dev_ops->send_otp_cmds) 193 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); 194 195 /* Enable port in pre-enable phase itself because as per hw team 196 * recommendation, port should be enabled befor plane & pipe */ 197 intel_dsi_enable(encoder); 198 } 199 200 static void intel_dsi_enable_nop(struct intel_encoder *encoder) 201 { 202 DRM_DEBUG_KMS("\n"); 203 204 /* for DSI port enable has to be done before pipe 205 * and plane enable, so port enable is done in 206 * pre_enable phase itself unlike other encoders 207 */ 208 } 209 210 static void intel_dsi_pre_disable(struct intel_encoder *encoder) 211 { 212 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 213 214 DRM_DEBUG_KMS("\n"); 215 216 if (is_vid_mode(intel_dsi)) { 217 /* Send Shutdown command to the panel in LP mode */ 218 dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); 219 msleep(10); 220 } 221 } 222 223 static void intel_dsi_disable(struct intel_encoder *encoder) 224 { 225 struct drm_device *dev = encoder->base.dev; 226 struct drm_i915_private *dev_priv = dev->dev_private; 227 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 228 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 229 int pipe = intel_crtc->pipe; 230 u32 temp; 231 232 DRM_DEBUG_KMS("\n"); 233 234 if (is_vid_mode(intel_dsi)) { 235 /* de-assert ip_tg_enable signal */ 236 temp = I915_READ(MIPI_PORT_CTRL(pipe)); 237 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE); 238 POSTING_READ(MIPI_PORT_CTRL(pipe)); 239 240 msleep(2); 241 } 242 243 /* Panel commands can be sent when clock is in LP11 */ 244 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x0); 245 246 temp = I915_READ(MIPI_CTRL(pipe)); 247 temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 248 I915_WRITE(MIPI_CTRL(pipe), temp | 249 intel_dsi->escape_clk_div << 250 ESCAPE_CLOCK_DIVIDER_SHIFT); 251 252 I915_WRITE(MIPI_EOT_DISABLE(pipe), CLOCKSTOP); 253 254 temp = I915_READ(MIPI_DSI_FUNC_PRG(pipe)); 255 temp &= ~VID_MODE_FORMAT_MASK; 256 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), temp); 257 258 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x1); 259 260 /* if disable packets are sent before sending shutdown packet then in 261 * some next enable sequence send turn on packet error is observed */ 262 if (intel_dsi->dev.dev_ops->disable) 263 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); 264 } 265 266 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) 267 { 268 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 269 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 270 int pipe = intel_crtc->pipe; 271 u32 val; 272 273 DRM_DEBUG_KMS("\n"); 274 275 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); 276 usleep_range(2000, 2500); 277 278 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT); 279 usleep_range(2000, 2500); 280 281 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER); 282 usleep_range(2000, 2500); 283 284 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT) 285 == 0x00000), 30)) 286 DRM_ERROR("DSI LP not going Low\n"); 287 288 val = I915_READ(MIPI_PORT_CTRL(pipe)); 289 I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD); 290 usleep_range(1000, 1500); 291 292 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00); 293 usleep_range(2000, 2500); 294 295 vlv_disable_dsi_pll(encoder); 296 } 297 298 static void intel_dsi_post_disable(struct intel_encoder *encoder) 299 { 300 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 301 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); 302 u32 val; 303 304 DRM_DEBUG_KMS("\n"); 305 306 intel_dsi_disable(encoder); 307 308 intel_dsi_clear_device_ready(encoder); 309 310 val = I915_READ(DSPCLK_GATE_D); 311 val &= ~DPOUNIT_CLOCK_GATE_DISABLE; 312 I915_WRITE(DSPCLK_GATE_D, val); 313 314 if (intel_dsi->dev.dev_ops->disable_panel_power) 315 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); 316 317 msleep(intel_dsi->panel_off_delay); 318 msleep(intel_dsi->panel_pwr_cycle_delay); 319 } 320 321 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, 322 enum i915_pipe *pipe) 323 { 324 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 325 enum intel_display_power_domain power_domain; 326 u32 port, func; 327 enum i915_pipe p; 328 329 DRM_DEBUG_KMS("\n"); 330 331 power_domain = intel_display_port_power_domain(encoder); 332 if (!intel_display_power_enabled(dev_priv, power_domain)) 333 return false; 334 335 /* XXX: this only works for one DSI output */ 336 for (p = PIPE_A; p <= PIPE_B; p++) { 337 port = I915_READ(MIPI_PORT_CTRL(p)); 338 func = I915_READ(MIPI_DSI_FUNC_PRG(p)); 339 340 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { 341 if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) { 342 *pipe = p; 343 return true; 344 } 345 } 346 } 347 348 return false; 349 } 350 351 static void intel_dsi_get_config(struct intel_encoder *encoder, 352 struct intel_crtc_config *pipe_config) 353 { 354 DRM_DEBUG_KMS("\n"); 355 356 /* XXX: read flags, set to adjusted_mode */ 357 } 358 359 static enum drm_mode_status 360 intel_dsi_mode_valid(struct drm_connector *connector, 361 struct drm_display_mode *mode) 362 { 363 struct intel_connector *intel_connector = to_intel_connector(connector); 364 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 365 struct intel_dsi *intel_dsi = intel_attached_dsi(connector); 366 367 DRM_DEBUG_KMS("\n"); 368 369 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 370 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); 371 return MODE_NO_DBLESCAN; 372 } 373 374 if (fixed_mode) { 375 if (mode->hdisplay > fixed_mode->hdisplay) 376 return MODE_PANEL; 377 if (mode->vdisplay > fixed_mode->vdisplay) 378 return MODE_PANEL; 379 } 380 381 return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); 382 } 383 384 /* return txclkesc cycles in terms of divider and duration in us */ 385 static u16 txclkesc(u32 divider, unsigned int us) 386 { 387 switch (divider) { 388 case ESCAPE_CLOCK_DIVIDER_1: 389 default: 390 return 20 * us; 391 case ESCAPE_CLOCK_DIVIDER_2: 392 return 10 * us; 393 case ESCAPE_CLOCK_DIVIDER_4: 394 return 5 * us; 395 } 396 } 397 398 /* return pixels in terms of txbyteclkhs */ 399 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count) 400 { 401 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count); 402 } 403 404 static void set_dsi_timings(struct drm_encoder *encoder, 405 const struct drm_display_mode *mode) 406 { 407 struct drm_device *dev = encoder->dev; 408 struct drm_i915_private *dev_priv = dev->dev_private; 409 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 410 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 411 int pipe = intel_crtc->pipe; 412 unsigned int bpp = intel_crtc->config.pipe_bpp; 413 unsigned int lane_count = intel_dsi->lane_count; 414 415 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; 416 417 hactive = mode->hdisplay; 418 hfp = mode->hsync_start - mode->hdisplay; 419 hsync = mode->hsync_end - mode->hsync_start; 420 hbp = mode->htotal - mode->hsync_end; 421 422 vfp = mode->vsync_start - mode->vdisplay; 423 vsync = mode->vsync_end - mode->vsync_start; 424 vbp = mode->vtotal - mode->vsync_end; 425 426 /* horizontal values are in terms of high speed byte clock */ 427 hactive = txbyteclkhs(hactive, bpp, lane_count); 428 hfp = txbyteclkhs(hfp, bpp, lane_count); 429 hsync = txbyteclkhs(hsync, bpp, lane_count); 430 hbp = txbyteclkhs(hbp, bpp, lane_count); 431 432 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive); 433 I915_WRITE(MIPI_HFP_COUNT(pipe), hfp); 434 435 /* meaningful for video mode non-burst sync pulse mode only, can be zero 436 * for non-burst sync events and burst modes */ 437 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync); 438 I915_WRITE(MIPI_HBP_COUNT(pipe), hbp); 439 440 /* vertical values are in terms of lines */ 441 I915_WRITE(MIPI_VFP_COUNT(pipe), vfp); 442 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync); 443 I915_WRITE(MIPI_VBP_COUNT(pipe), vbp); 444 } 445 446 static void intel_dsi_prepare(struct intel_encoder *intel_encoder) 447 { 448 struct drm_encoder *encoder = &intel_encoder->base; 449 struct drm_device *dev = encoder->dev; 450 struct drm_i915_private *dev_priv = dev->dev_private; 451 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); 452 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 453 struct drm_display_mode *adjusted_mode = 454 &intel_crtc->config.adjusted_mode; 455 int pipe = intel_crtc->pipe; 456 unsigned int bpp = intel_crtc->config.pipe_bpp; 457 u32 val, tmp; 458 459 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); 460 461 /* escape clock divider, 20MHz, shared for A and C. device ready must be 462 * off when doing this! txclkesc? */ 463 tmp = I915_READ(MIPI_CTRL(0)); 464 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; 465 I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1); 466 467 /* read request priority is per pipe */ 468 tmp = I915_READ(MIPI_CTRL(pipe)); 469 tmp &= ~READ_REQUEST_PRIORITY_MASK; 470 I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH); 471 472 /* XXX: why here, why like this? handling in irq handler?! */ 473 I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff); 474 I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff); 475 476 I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg); 477 478 I915_WRITE(MIPI_DPI_RESOLUTION(pipe), 479 adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | 480 adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT); 481 482 set_dsi_timings(encoder, adjusted_mode); 483 484 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; 485 if (is_cmd_mode(intel_dsi)) { 486 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; 487 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ 488 } else { 489 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; 490 491 /* XXX: cross-check bpp vs. pixel format? */ 492 val |= intel_dsi->pixel_format; 493 } 494 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val); 495 496 /* timeouts for recovery. one frame IIUC. if counter expires, EOT and 497 * stop state. */ 498 499 /* 500 * In burst mode, value greater than one DPI line Time in byte clock 501 * (txbyteclkhs) To timeout this timer 1+ of the above said value is 502 * recommended. 503 * 504 * In non-burst mode, Value greater than one DPI frame time in byte 505 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value 506 * is recommended. 507 * 508 * In DBI only mode, value greater than one DBI frame time in byte 509 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value 510 * is recommended. 511 */ 512 513 if (is_vid_mode(intel_dsi) && 514 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 515 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), 516 txbyteclkhs(adjusted_mode->htotal, bpp, 517 intel_dsi->lane_count) + 1); 518 } else { 519 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe), 520 txbyteclkhs(adjusted_mode->vtotal * 521 adjusted_mode->htotal, 522 bpp, intel_dsi->lane_count) + 1); 523 } 524 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout); 525 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val); 526 I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val); 527 528 /* dphy stuff */ 529 530 /* in terms of low power clock */ 531 I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(intel_dsi->escape_clk_div, 100)); 532 533 val = 0; 534 if (intel_dsi->eotp_pkt == 0) 535 val |= EOT_DISABLE; 536 537 if (intel_dsi->clock_stop) 538 val |= CLOCKSTOP; 539 540 /* recovery disables */ 541 I915_WRITE(MIPI_EOT_DISABLE(pipe), val); 542 543 /* in terms of low power clock */ 544 I915_WRITE(MIPI_INIT_COUNT(pipe), intel_dsi->init_count); 545 546 /* in terms of txbyteclkhs. actual high to low switch + 547 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. 548 * 549 * XXX: write MIPI_STOP_STATE_STALL? 550 */ 551 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 552 intel_dsi->hs_to_lp_count); 553 554 /* XXX: low power clock equivalence in terms of byte clock. the number 555 * of byte clocks occupied in one low power clock. based on txbyteclkhs 556 * and txclkesc. txclkesc time / txbyteclk time * (105 + 557 * MIPI_STOP_STATE_STALL) / 105.??? 558 */ 559 I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk); 560 561 /* the bw essential for transmitting 16 long packets containing 252 562 * bytes meant for dcs write memory command is programmed in this 563 * register in terms of byte clocks. based on dsi transfer rate and the 564 * number of lanes configured the time taken to transmit 16 long packets 565 * in a dsi stream varies. */ 566 I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer); 567 568 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe), 569 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | 570 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); 571 572 if (is_vid_mode(intel_dsi)) 573 /* Some panels might have resolution which is not a multiple of 574 * 64 like 1366 x 768. Enable RANDOM resolution support for such 575 * panels by default */ 576 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe), 577 intel_dsi->video_frmt_cfg_bits | 578 intel_dsi->video_mode_format | 579 IP_TG_CONFIG | 580 RANDOM_DPI_DISPLAY_RESOLUTION); 581 } 582 583 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) 584 { 585 DRM_DEBUG_KMS("\n"); 586 587 intel_dsi_prepare(encoder); 588 589 vlv_enable_dsi_pll(encoder); 590 } 591 592 static enum drm_connector_status 593 intel_dsi_detect(struct drm_connector *connector, bool force) 594 { 595 struct intel_dsi *intel_dsi = intel_attached_dsi(connector); 596 struct intel_encoder *intel_encoder = &intel_dsi->base; 597 enum intel_display_power_domain power_domain; 598 enum drm_connector_status connector_status; 599 struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; 600 601 DRM_DEBUG_KMS("\n"); 602 power_domain = intel_display_port_power_domain(intel_encoder); 603 604 intel_display_power_get(dev_priv, power_domain); 605 connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); 606 intel_display_power_put(dev_priv, power_domain); 607 608 return connector_status; 609 } 610 611 static int intel_dsi_get_modes(struct drm_connector *connector) 612 { 613 struct intel_connector *intel_connector = to_intel_connector(connector); 614 struct drm_display_mode *mode; 615 616 DRM_DEBUG_KMS("\n"); 617 618 if (!intel_connector->panel.fixed_mode) { 619 DRM_DEBUG_KMS("no fixed mode\n"); 620 return 0; 621 } 622 623 mode = drm_mode_duplicate(connector->dev, 624 intel_connector->panel.fixed_mode); 625 if (!mode) { 626 DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); 627 return 0; 628 } 629 630 drm_mode_probed_add(connector, mode); 631 return 1; 632 } 633 634 static void intel_dsi_destroy(struct drm_connector *connector) 635 { 636 struct intel_connector *intel_connector = to_intel_connector(connector); 637 638 DRM_DEBUG_KMS("\n"); 639 intel_panel_fini(&intel_connector->panel); 640 drm_connector_cleanup(connector); 641 kfree(connector); 642 } 643 644 static const struct drm_encoder_funcs intel_dsi_funcs = { 645 .destroy = intel_encoder_destroy, 646 }; 647 648 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { 649 .get_modes = intel_dsi_get_modes, 650 .mode_valid = intel_dsi_mode_valid, 651 .best_encoder = intel_best_encoder, 652 }; 653 654 static const struct drm_connector_funcs intel_dsi_connector_funcs = { 655 .dpms = intel_connector_dpms, 656 .detect = intel_dsi_detect, 657 .destroy = intel_dsi_destroy, 658 .fill_modes = drm_helper_probe_single_connector_modes, 659 }; 660 661 bool intel_dsi_init(struct drm_device *dev) 662 { 663 struct intel_dsi *intel_dsi; 664 struct intel_encoder *intel_encoder; 665 struct drm_encoder *encoder; 666 struct intel_connector *intel_connector; 667 struct drm_connector *connector; 668 struct drm_display_mode *fixed_mode = NULL; 669 struct drm_i915_private *dev_priv = dev->dev_private; 670 const struct intel_dsi_device *dsi; 671 unsigned int i; 672 673 DRM_DEBUG_KMS("\n"); 674 675 /* There is no detection method for MIPI so rely on VBT */ 676 if (!dev_priv->vbt.has_mipi) 677 return false; 678 679 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 680 if (!intel_dsi) 681 return false; 682 683 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); 684 if (!intel_connector) { 685 kfree(intel_dsi); 686 return false; 687 } 688 689 intel_encoder = &intel_dsi->base; 690 encoder = &intel_encoder->base; 691 intel_dsi->attached_connector = intel_connector; 692 693 if (IS_VALLEYVIEW(dev)) { 694 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; 695 } else { 696 DRM_ERROR("Unsupported Mipi device to reg base"); 697 return false; 698 } 699 700 connector = &intel_connector->base; 701 702 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); 703 704 /* XXX: very likely not all of these are needed */ 705 intel_encoder->hot_plug = intel_dsi_hot_plug; 706 intel_encoder->compute_config = intel_dsi_compute_config; 707 intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; 708 intel_encoder->pre_enable = intel_dsi_pre_enable; 709 intel_encoder->enable = intel_dsi_enable_nop; 710 intel_encoder->disable = intel_dsi_pre_disable; 711 intel_encoder->post_disable = intel_dsi_post_disable; 712 intel_encoder->get_hw_state = intel_dsi_get_hw_state; 713 intel_encoder->get_config = intel_dsi_get_config; 714 715 intel_connector->get_hw_state = intel_connector_get_hw_state; 716 intel_connector->unregister = intel_connector_unregister; 717 718 for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { 719 dsi = &intel_dsi_devices[i]; 720 intel_dsi->dev = *dsi; 721 722 if (dsi->dev_ops->init(&intel_dsi->dev)) 723 break; 724 } 725 726 if (i == ARRAY_SIZE(intel_dsi_devices)) { 727 DRM_DEBUG_KMS("no device found\n"); 728 goto err; 729 } 730 731 intel_encoder->type = INTEL_OUTPUT_DSI; 732 intel_encoder->crtc_mask = (1 << 0); /* XXX */ 733 734 intel_encoder->cloneable = 0; 735 drm_connector_init(dev, connector, &intel_dsi_connector_funcs, 736 DRM_MODE_CONNECTOR_DSI); 737 738 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); 739 740 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ 741 connector->interlace_allowed = false; 742 connector->doublescan_allowed = false; 743 744 intel_connector_attach_encoder(intel_connector, intel_encoder); 745 746 drm_sysfs_connector_add(connector); 747 748 fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); 749 if (!fixed_mode) { 750 DRM_DEBUG_KMS("no fixed mode\n"); 751 goto err; 752 } 753 754 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 755 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 756 757 return true; 758 759 err: 760 drm_encoder_cleanup(&intel_encoder->base); 761 kfree(intel_dsi); 762 kfree(intel_connector); 763 764 return false; 765 } 766