1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * $FreeBSD: src/sys/dev/drm2/i915/intel_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 26 */ 27 28 #ifndef DRM_INTEL_DRV_H 29 #define DRM_INTEL_DRV_H 30 31 #include <linux/delay.h> 32 #include <drm/i915_drm.h> 33 #include "i915_drv.h" 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_fb_helper.h> 37 #include <drm/drm_dp_helper.h> 38 39 #define _wait_for(COND, MS, W) ({ \ 40 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 41 int ret__ = 0; \ 42 while (!(COND)) { \ 43 if (time_after(jiffies, timeout__)) { \ 44 ret__ = -ETIMEDOUT; \ 45 break; \ 46 } \ 47 if (W && drm_can_sleep()) { \ 48 msleep(W); \ 49 } else { \ 50 cpu_pause(); \ 51 } \ 52 } \ 53 ret__; \ 54 }) 55 56 /* XXX: poor substitute for the Linux version of this routine */ 57 static inline 58 unsigned long usecs_to_jiffies(const unsigned int u) 59 { 60 unsigned long jiffies; 61 62 jiffies = (u * hz) / 1000000; 63 if (jiffies < 1) 64 return 1; 65 else 66 return jiffies; 67 } 68 69 #define wait_for_atomic_us(COND, US) ({ \ 70 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \ 71 int ret__ = 0; \ 72 while (!(COND)) { \ 73 if (time_after(jiffies, timeout__)) { \ 74 ret__ = -ETIMEDOUT; \ 75 break; \ 76 } \ 77 cpu_pause(); \ 78 } \ 79 ret__; \ 80 }) 81 82 #define _intel_wait_for(DEV, COND, MS, W, WMSG) \ 83 ({ \ 84 int end, ret; \ 85 \ 86 end = ticks + (MS) * hz / 1000; \ 87 ret = 0; \ 88 \ 89 while (!(COND)) { \ 90 if (time_after(ticks, end)) { \ 91 ret = -ETIMEDOUT; \ 92 break; \ 93 } \ 94 DELAY(1000); \ 95 } \ 96 \ 97 ret; \ 98 }) 99 100 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 101 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 102 103 #define KHz(x) (1000*x) 104 #define MHz(x) KHz(1000*x) 105 106 /* store information about an Ixxx DVO */ 107 /* The i830->i865 use multiple DVOs with multiple i2cs */ 108 /* the i915, i945 have a single sDVO i2c bus - which is different */ 109 #define MAX_OUTPUTS 6 110 /* maximum connectors per crtcs in the mode set */ 111 #define INTELFB_CONN_LIMIT 4 112 113 #define INTEL_I2C_BUS_DVO 1 114 #define INTEL_I2C_BUS_SDVO 2 115 116 /* these are outputs from the chip - integrated only 117 external chips are via DVO or SDVO output */ 118 #define INTEL_OUTPUT_UNUSED 0 119 #define INTEL_OUTPUT_ANALOG 1 120 #define INTEL_OUTPUT_DVO 2 121 #define INTEL_OUTPUT_SDVO 3 122 #define INTEL_OUTPUT_LVDS 4 123 #define INTEL_OUTPUT_TVOUT 5 124 #define INTEL_OUTPUT_HDMI 6 125 #define INTEL_OUTPUT_DISPLAYPORT 7 126 #define INTEL_OUTPUT_EDP 8 127 128 /* Intel Pipe Clone Bit */ 129 #define INTEL_HDMIB_CLONE_BIT 1 130 #define INTEL_HDMIC_CLONE_BIT 2 131 #define INTEL_HDMID_CLONE_BIT 3 132 #define INTEL_HDMIE_CLONE_BIT 4 133 #define INTEL_HDMIF_CLONE_BIT 5 134 #define INTEL_SDVO_NON_TV_CLONE_BIT 6 135 #define INTEL_SDVO_TV_CLONE_BIT 7 136 #define INTEL_SDVO_LVDS_CLONE_BIT 8 137 #define INTEL_ANALOG_CLONE_BIT 9 138 #define INTEL_TV_CLONE_BIT 10 139 #define INTEL_DP_B_CLONE_BIT 11 140 #define INTEL_DP_C_CLONE_BIT 12 141 #define INTEL_DP_D_CLONE_BIT 13 142 #define INTEL_LVDS_CLONE_BIT 14 143 #define INTEL_DVO_TMDS_CLONE_BIT 15 144 #define INTEL_DVO_LVDS_CLONE_BIT 16 145 #define INTEL_EDP_CLONE_BIT 17 146 147 #define INTEL_DVO_CHIP_NONE 0 148 #define INTEL_DVO_CHIP_LVDS 1 149 #define INTEL_DVO_CHIP_TMDS 2 150 #define INTEL_DVO_CHIP_TVOUT 4 151 152 /* drm_display_mode->private_flags */ 153 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) 154 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) 155 #define INTEL_MODE_DP_FORCE_6BPC (0x10) 156 /* This flag must be set by the encoder's mode_fixup if it changes the crtc 157 * timings in the mode to prevent the crtc fixup from overwriting them. 158 * Currently only lvds needs that. */ 159 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) 160 161 static inline void 162 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, 163 int multiplier) 164 { 165 mode->clock *= multiplier; 166 mode->private_flags |= multiplier; 167 } 168 169 static inline int 170 intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) 171 { 172 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; 173 } 174 175 struct intel_framebuffer { 176 struct drm_framebuffer base; 177 struct drm_i915_gem_object *obj; 178 }; 179 180 struct intel_fbdev { 181 struct drm_fb_helper helper; 182 struct intel_framebuffer ifb; 183 struct list_head fbdev_list; 184 struct drm_display_mode *our_mode; 185 }; 186 187 struct intel_encoder { 188 struct drm_encoder base; 189 int type; 190 bool needs_tv_clock; 191 void (*hot_plug)(struct intel_encoder *); 192 int crtc_mask; 193 int clone_mask; 194 }; 195 196 struct intel_connector { 197 struct drm_connector base; 198 struct intel_encoder *encoder; 199 }; 200 201 struct intel_crtc { 202 struct drm_crtc base; 203 enum i915_pipe pipe; 204 enum plane plane; 205 u8 lut_r[256], lut_g[256], lut_b[256]; 206 int dpms_mode; 207 bool active; /* is the crtc on? independent of the dpms mode */ 208 bool primary_disabled; /* is the crtc obscured by a plane? */ 209 bool busy; /* is scanout buffer being updated frequently? */ 210 struct callout idle_callout; 211 bool lowfreq_avail; 212 struct intel_overlay *overlay; 213 struct intel_unpin_work *unpin_work; 214 int fdi_lanes; 215 216 struct drm_i915_gem_object *cursor_bo; 217 uint32_t cursor_addr; 218 int16_t cursor_x, cursor_y; 219 int16_t cursor_width, cursor_height; 220 bool cursor_visible; 221 unsigned int bpp; 222 223 bool no_pll; /* tertiary pipe for IVB */ 224 bool use_pll_a; 225 }; 226 227 struct intel_plane { 228 struct drm_plane base; 229 enum i915_pipe pipe; 230 struct drm_i915_gem_object *obj; 231 bool can_scale; 232 int max_downscale; 233 u32 lut_r[1024], lut_g[1024], lut_b[1024]; 234 void (*update_plane)(struct drm_plane *plane, 235 struct drm_framebuffer *fb, 236 struct drm_i915_gem_object *obj, 237 int crtc_x, int crtc_y, 238 unsigned int crtc_w, unsigned int crtc_h, 239 uint32_t x, uint32_t y, 240 uint32_t src_w, uint32_t src_h); 241 void (*disable_plane)(struct drm_plane *plane); 242 int (*update_colorkey)(struct drm_plane *plane, 243 struct drm_intel_sprite_colorkey *key); 244 void (*get_colorkey)(struct drm_plane *plane, 245 struct drm_intel_sprite_colorkey *key); 246 }; 247 248 struct intel_watermark_params { 249 unsigned long fifo_size; 250 unsigned long max_wm; 251 unsigned long default_wm; 252 unsigned long guard_size; 253 unsigned long cacheline_size; 254 }; 255 256 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 257 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 258 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 259 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 260 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 261 262 #define DIP_HEADER_SIZE 5 263 264 #define DIP_TYPE_AVI 0x82 265 #define DIP_VERSION_AVI 0x2 266 #define DIP_LEN_AVI 13 267 268 #define DIP_TYPE_SPD 0x83 269 #define DIP_VERSION_SPD 0x1 270 #define DIP_LEN_SPD 25 271 #define DIP_SPD_UNKNOWN 0 272 #define DIP_SPD_DSTB 0x1 273 #define DIP_SPD_DVDP 0x2 274 #define DIP_SPD_DVHS 0x3 275 #define DIP_SPD_HDDVR 0x4 276 #define DIP_SPD_DVC 0x5 277 #define DIP_SPD_DSC 0x6 278 #define DIP_SPD_VCD 0x7 279 #define DIP_SPD_GAME 0x8 280 #define DIP_SPD_PC 0x9 281 #define DIP_SPD_BD 0xa 282 #define DIP_SPD_SCD 0xb 283 284 struct dip_infoframe { 285 uint8_t type; /* HB0 */ 286 uint8_t ver; /* HB1 */ 287 uint8_t len; /* HB2 - body len, not including checksum */ 288 uint8_t ecc; /* Header ECC */ 289 uint8_t checksum; /* PB0 */ 290 union { 291 struct { 292 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ 293 uint8_t Y_A_B_S; 294 /* PB2 - C 7:6, M 5:4, R 3:0 */ 295 uint8_t C_M_R; 296 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ 297 uint8_t ITC_EC_Q_SC; 298 /* PB4 - VIC 6:0 */ 299 uint8_t VIC; 300 /* PB5 - PR 3:0 */ 301 uint8_t PR; 302 /* PB6 to PB13 */ 303 uint16_t top_bar_end; 304 uint16_t bottom_bar_start; 305 uint16_t left_bar_end; 306 uint16_t right_bar_start; 307 } avi; 308 struct { 309 uint8_t vn[8]; 310 uint8_t pd[16]; 311 uint8_t sdi; 312 } spd; 313 uint8_t payload[27]; 314 } __attribute__ ((packed)) body; 315 } __attribute__((packed)); 316 317 #define DP_MAX_DOWNSTREAM_PORTS 0x10 318 #define DP_LINK_CONFIGURATION_SIZE 9 319 320 struct intel_dp { 321 struct intel_encoder base; 322 uint32_t output_reg; 323 uint32_t DP; 324 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 325 bool has_audio; 326 enum hdmi_force_audio force_audio; 327 uint32_t color_range; 328 int dpms_mode; 329 uint8_t link_bw; 330 uint8_t lane_count; 331 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 332 device_t dp_iic_bus; 333 device_t adapter; 334 bool is_pch_edp; 335 uint8_t train_set[4]; 336 int panel_power_up_delay; 337 int panel_power_down_delay; 338 int panel_power_cycle_delay; 339 int backlight_on_delay; 340 int backlight_off_delay; 341 struct delayed_work panel_vdd_work; 342 bool want_panel_vdd; 343 struct drm_display_mode *panel_fixed_mode; /* for eDP */ 344 }; 345 346 static inline struct drm_crtc * 347 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 348 { 349 struct drm_i915_private *dev_priv = dev->dev_private; 350 return dev_priv->pipe_to_crtc_mapping[pipe]; 351 } 352 353 static inline struct drm_crtc * 354 intel_get_crtc_for_plane(struct drm_device *dev, int plane) 355 { 356 struct drm_i915_private *dev_priv = dev->dev_private; 357 return dev_priv->plane_to_crtc_mapping[plane]; 358 } 359 360 struct intel_unpin_work { 361 struct work_struct work; 362 struct drm_device *dev; 363 struct drm_i915_gem_object *old_fb_obj; 364 struct drm_i915_gem_object *pending_flip_obj; 365 struct drm_pending_vblank_event *event; 366 atomic_t pending; 367 #define INTEL_FLIP_INACTIVE 0 368 #define INTEL_FLIP_PENDING 1 369 #define INTEL_FLIP_COMPLETE 2 370 bool enable_stall_check; 371 }; 372 373 struct intel_fbc_work { 374 struct delayed_work work; 375 struct drm_crtc *crtc; 376 struct drm_framebuffer *fb; 377 int interval; 378 }; 379 380 int intel_connector_update_modes(struct drm_connector *connector, 381 struct edid *edid); 382 int intel_ddc_get_modes(struct drm_connector *c, device_t adapter); 383 extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus); 384 385 extern void intel_attach_force_audio_property(struct drm_connector *connector); 386 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 387 388 extern void intel_crt_init(struct drm_device *dev); 389 extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); 390 void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); 391 extern bool intel_sdvo_init(struct drm_device *dev, int output_device); 392 extern void intel_dvo_init(struct drm_device *dev); 393 extern void intel_tv_init(struct drm_device *dev); 394 extern void intel_mark_busy(struct drm_device *dev); 395 extern void intel_mark_idle(struct drm_device *dev); 396 extern bool intel_lvds_init(struct drm_device *dev); 397 extern void intel_dp_init(struct drm_device *dev, int dp_reg); 398 void 399 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 400 struct drm_display_mode *adjusted_mode); 401 extern bool intel_dpd_is_edp(struct drm_device *dev); 402 extern void intel_edp_link_config(struct intel_encoder *, int *, int *); 403 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); 404 extern int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe); 405 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, 406 enum plane plane); 407 408 /* intel_panel.c */ 409 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 410 struct drm_display_mode *adjusted_mode); 411 extern void intel_pch_panel_fitting(struct drm_device *dev, 412 int fitting_mode, 413 const struct drm_display_mode *mode, 414 struct drm_display_mode *adjusted_mode); 415 extern u32 intel_panel_get_max_backlight(struct drm_device *dev); 416 extern u32 intel_panel_get_backlight(struct drm_device *dev); 417 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); 418 extern int intel_panel_setup_backlight(struct drm_device *dev); 419 extern void intel_panel_enable_backlight(struct drm_device *dev); 420 extern void intel_panel_disable_backlight(struct drm_device *dev); 421 extern void intel_panel_destroy_backlight(struct drm_device *dev); 422 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); 423 424 extern void intel_crtc_load_lut(struct drm_crtc *crtc); 425 extern void intel_encoder_prepare(struct drm_encoder *encoder); 426 extern void intel_encoder_commit(struct drm_encoder *encoder); 427 extern void intel_encoder_destroy(struct drm_encoder *encoder); 428 429 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) 430 { 431 return to_intel_connector(connector)->encoder; 432 } 433 434 extern void intel_connector_attach_encoder(struct intel_connector *connector, 435 struct intel_encoder *encoder); 436 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 437 438 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 439 struct drm_crtc *crtc); 440 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 441 struct drm_file *file_priv); 442 extern enum transcoder 443 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 444 enum i915_pipe pipe); 445 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); 446 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); 447 448 struct intel_load_detect_pipe { 449 struct drm_framebuffer *release_fb; 450 bool load_detect_temp; 451 int dpms_mode; 452 }; 453 extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 454 struct drm_connector *connector, 455 struct drm_display_mode *mode, 456 struct intel_load_detect_pipe *old); 457 extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, 458 struct drm_connector *connector, 459 struct intel_load_detect_pipe *old); 460 461 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 462 u16 blue, int regno); 463 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 464 u16 *blue, int regno); 465 extern void intel_enable_clock_gating(struct drm_device *dev); 466 extern void ironlake_disable_rc6(struct drm_device *dev); 467 extern void ironlake_enable_drps(struct drm_device *dev); 468 extern void ironlake_disable_drps(struct drm_device *dev); 469 extern void gen6_enable_rps(struct drm_i915_private *dev_priv); 470 extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv); 471 extern void gen6_disable_rps(struct drm_device *dev); 472 extern void intel_init_emon(struct drm_device *dev); 473 474 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, 475 struct drm_i915_gem_object *obj, 476 struct intel_ring_buffer *pipelined); 477 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 478 479 extern int intel_framebuffer_init(struct drm_device *dev, 480 struct intel_framebuffer *ifb, 481 struct drm_mode_fb_cmd2 *mode_cmd, 482 struct drm_i915_gem_object *obj); 483 extern int intel_fbdev_init(struct drm_device *dev); 484 extern void intel_fbdev_fini(struct drm_device *dev); 485 486 extern void intel_prepare_page_flip(struct drm_device *dev, int plane); 487 extern void intel_finish_page_flip(struct drm_device *dev, int pipe); 488 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 489 490 extern void intel_setup_overlay(struct drm_device *dev); 491 extern void intel_cleanup_overlay(struct drm_device *dev); 492 extern int intel_overlay_switch_off(struct intel_overlay *overlay); 493 extern int intel_overlay_put_image(struct drm_device *dev, void *data, 494 struct drm_file *file_priv); 495 extern int intel_overlay_attrs(struct drm_device *dev, void *data, 496 struct drm_file *file_priv); 497 498 extern void intel_fb_output_poll_changed(struct drm_device *dev); 499 extern void intel_fb_restore_mode(struct drm_device *dev); 500 501 extern void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 502 bool state); 503 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 504 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 505 506 extern void intel_init_clock_gating(struct drm_device *dev); 507 extern void intel_write_eld(struct drm_encoder *encoder, 508 struct drm_display_mode *mode); 509 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); 510 511 /* For use by IVB LP watermark workaround in intel_sprite.c */ 512 extern void intel_update_watermarks(struct drm_device *dev); 513 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 514 uint32_t sprite_width, 515 int pixel_size); 516 517 extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, 518 unsigned int bpp, 519 unsigned int pitch); 520 521 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 522 struct drm_file *file_priv); 523 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 524 struct drm_file *file_priv); 525 526 /* Power-related functions, located in intel_pm.c */ 527 /* FBC */ 528 extern void i8xx_disable_fbc(struct drm_device *dev); 529 extern void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 530 extern bool i8xx_fbc_enabled(struct drm_device *dev); 531 extern void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 532 extern void g4x_disable_fbc(struct drm_device *dev); 533 extern bool g4x_fbc_enabled(struct drm_device *dev); 534 extern void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 535 extern void ironlake_disable_fbc(struct drm_device *dev); 536 extern bool ironlake_fbc_enabled(struct drm_device *dev); 537 extern bool intel_fbc_enabled(struct drm_device *dev); 538 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 539 extern void intel_update_fbc(struct drm_device *dev); 540 541 extern void intel_init_power_wells(struct drm_device *dev); 542 extern void intel_enable_gt_powersave(struct drm_device *dev); 543 extern void intel_disable_gt_powersave(struct drm_device *dev); 544 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); 545 546 /* Watermarks */ 547 extern void pineview_update_wm(struct drm_device *dev); 548 extern void valleyview_update_wm(struct drm_device *dev); 549 extern void g4x_update_wm(struct drm_device *dev); 550 extern void i965_update_wm(struct drm_device *dev); 551 extern void i9xx_update_wm(struct drm_device *dev); 552 extern void i830_update_wm(struct drm_device *dev); 553 extern void ironlake_update_wm(struct drm_device *dev); 554 extern void sandybridge_update_wm(struct drm_device *dev); 555 extern void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, 556 uint32_t sprite_width, int pixel_size); 557 extern const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 558 int is_ddr3, 559 int fsb, 560 int mem); 561 extern void pineview_disable_cxsr(struct drm_device *dev); 562 extern int i9xx_get_fifo_size(struct drm_device *dev, int plane); 563 extern int i85x_get_fifo_size(struct drm_device *dev, int plane); 564 extern int i845_get_fifo_size(struct drm_device *dev, int plane); 565 extern int i830_get_fifo_size(struct drm_device *dev, int plane); 566 567 /* Clock gating */ 568 extern void ironlake_init_clock_gating(struct drm_device *dev); 569 extern void gen6_init_clock_gating(struct drm_device *dev); 570 extern void ivybridge_init_clock_gating(struct drm_device *dev); 571 extern void valleyview_init_clock_gating(struct drm_device *dev); 572 extern void g4x_init_clock_gating(struct drm_device *dev); 573 extern void crestline_init_clock_gating(struct drm_device *dev); 574 extern void broadwater_init_clock_gating(struct drm_device *dev); 575 extern void gen3_init_clock_gating(struct drm_device *dev); 576 extern void i85x_init_clock_gating(struct drm_device *dev); 577 extern void i830_init_clock_gating(struct drm_device *dev); 578 extern void ibx_init_clock_gating(struct drm_device *dev); 579 extern void cpt_init_clock_gating(struct drm_device *dev); 580 581 #endif 582