1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * $FreeBSD: src/sys/dev/drm2/i915/intel_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 26 */ 27 28 #ifndef DRM_INTEL_DRV_H 29 #define DRM_INTEL_DRV_H 30 31 #include <linux/delay.h> 32 #include <drm/i915_drm.h> 33 #include "i915_drv.h" 34 #include <drm/drm_crtc.h> 35 #include <drm/drm_crtc_helper.h> 36 #include <drm/drm_fb_helper.h> 37 #include <drm/drm_dp_helper.h> 38 39 #define _wait_for(COND, MS, W) ({ \ 40 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 41 int ret__ = 0; \ 42 while (!(COND)) { \ 43 if (time_after(jiffies, timeout__)) { \ 44 ret__ = -ETIMEDOUT; \ 45 break; \ 46 } \ 47 if (W && drm_can_sleep()) { \ 48 msleep(W); \ 49 } else { \ 50 cpu_pause(); \ 51 } \ 52 } \ 53 ret__; \ 54 }) 55 56 #define _intel_wait_for(DEV, COND, MS, W, WMSG) \ 57 ({ \ 58 int end, ret; \ 59 \ 60 end = ticks + (MS) * hz / 1000; \ 61 ret = 0; \ 62 \ 63 while (!(COND)) { \ 64 if (time_after(ticks, end)) { \ 65 ret = -ETIMEDOUT; \ 66 break; \ 67 } \ 68 DELAY(1000); \ 69 } \ 70 \ 71 ret; \ 72 }) 73 74 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 75 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 76 77 #define KHz(x) (1000*x) 78 #define MHz(x) KHz(1000*x) 79 80 /* store information about an Ixxx DVO */ 81 /* The i830->i865 use multiple DVOs with multiple i2cs */ 82 /* the i915, i945 have a single sDVO i2c bus - which is different */ 83 #define MAX_OUTPUTS 6 84 /* maximum connectors per crtcs in the mode set */ 85 #define INTELFB_CONN_LIMIT 4 86 87 #define INTEL_I2C_BUS_DVO 1 88 #define INTEL_I2C_BUS_SDVO 2 89 90 /* these are outputs from the chip - integrated only 91 external chips are via DVO or SDVO output */ 92 #define INTEL_OUTPUT_UNUSED 0 93 #define INTEL_OUTPUT_ANALOG 1 94 #define INTEL_OUTPUT_DVO 2 95 #define INTEL_OUTPUT_SDVO 3 96 #define INTEL_OUTPUT_LVDS 4 97 #define INTEL_OUTPUT_TVOUT 5 98 #define INTEL_OUTPUT_HDMI 6 99 #define INTEL_OUTPUT_DISPLAYPORT 7 100 #define INTEL_OUTPUT_EDP 8 101 102 /* Intel Pipe Clone Bit */ 103 #define INTEL_HDMIB_CLONE_BIT 1 104 #define INTEL_HDMIC_CLONE_BIT 2 105 #define INTEL_HDMID_CLONE_BIT 3 106 #define INTEL_HDMIE_CLONE_BIT 4 107 #define INTEL_HDMIF_CLONE_BIT 5 108 #define INTEL_SDVO_NON_TV_CLONE_BIT 6 109 #define INTEL_SDVO_TV_CLONE_BIT 7 110 #define INTEL_SDVO_LVDS_CLONE_BIT 8 111 #define INTEL_ANALOG_CLONE_BIT 9 112 #define INTEL_TV_CLONE_BIT 10 113 #define INTEL_DP_B_CLONE_BIT 11 114 #define INTEL_DP_C_CLONE_BIT 12 115 #define INTEL_DP_D_CLONE_BIT 13 116 #define INTEL_LVDS_CLONE_BIT 14 117 #define INTEL_DVO_TMDS_CLONE_BIT 15 118 #define INTEL_DVO_LVDS_CLONE_BIT 16 119 #define INTEL_EDP_CLONE_BIT 17 120 121 #define INTEL_DVO_CHIP_NONE 0 122 #define INTEL_DVO_CHIP_LVDS 1 123 #define INTEL_DVO_CHIP_TMDS 2 124 #define INTEL_DVO_CHIP_TVOUT 4 125 126 /* drm_display_mode->private_flags */ 127 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) 128 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) 129 #define INTEL_MODE_DP_FORCE_6BPC (0x10) 130 /* This flag must be set by the encoder's mode_fixup if it changes the crtc 131 * timings in the mode to prevent the crtc fixup from overwriting them. 132 * Currently only lvds needs that. */ 133 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) 134 135 static inline void 136 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, 137 int multiplier) 138 { 139 mode->clock *= multiplier; 140 mode->private_flags |= multiplier; 141 } 142 143 static inline int 144 intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) 145 { 146 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; 147 } 148 149 struct intel_framebuffer { 150 struct drm_framebuffer base; 151 struct drm_i915_gem_object *obj; 152 }; 153 154 struct intel_fbdev { 155 struct drm_fb_helper helper; 156 struct intel_framebuffer ifb; 157 struct list_head fbdev_list; 158 struct drm_display_mode *our_mode; 159 }; 160 161 struct intel_encoder { 162 struct drm_encoder base; 163 int type; 164 bool needs_tv_clock; 165 void (*hot_plug)(struct intel_encoder *); 166 int crtc_mask; 167 int clone_mask; 168 }; 169 170 struct intel_connector { 171 struct drm_connector base; 172 struct intel_encoder *encoder; 173 }; 174 175 struct intel_crtc { 176 struct drm_crtc base; 177 enum i915_pipe pipe; 178 enum plane plane; 179 u8 lut_r[256], lut_g[256], lut_b[256]; 180 int dpms_mode; 181 bool active; /* is the crtc on? independent of the dpms mode */ 182 bool primary_disabled; /* is the crtc obscured by a plane? */ 183 bool busy; /* is scanout buffer being updated frequently? */ 184 struct callout idle_callout; 185 bool lowfreq_avail; 186 struct intel_overlay *overlay; 187 struct intel_unpin_work *unpin_work; 188 int fdi_lanes; 189 190 struct drm_i915_gem_object *cursor_bo; 191 uint32_t cursor_addr; 192 int16_t cursor_x, cursor_y; 193 int16_t cursor_width, cursor_height; 194 bool cursor_visible; 195 unsigned int bpp; 196 197 bool no_pll; /* tertiary pipe for IVB */ 198 bool use_pll_a; 199 }; 200 201 struct intel_plane { 202 struct drm_plane base; 203 enum i915_pipe pipe; 204 struct drm_i915_gem_object *obj; 205 bool can_scale; 206 int max_downscale; 207 u32 lut_r[1024], lut_g[1024], lut_b[1024]; 208 void (*update_plane)(struct drm_plane *plane, 209 struct drm_framebuffer *fb, 210 struct drm_i915_gem_object *obj, 211 int crtc_x, int crtc_y, 212 unsigned int crtc_w, unsigned int crtc_h, 213 uint32_t x, uint32_t y, 214 uint32_t src_w, uint32_t src_h); 215 void (*disable_plane)(struct drm_plane *plane); 216 int (*update_colorkey)(struct drm_plane *plane, 217 struct drm_intel_sprite_colorkey *key); 218 void (*get_colorkey)(struct drm_plane *plane, 219 struct drm_intel_sprite_colorkey *key); 220 }; 221 222 struct intel_watermark_params { 223 unsigned long fifo_size; 224 unsigned long max_wm; 225 unsigned long default_wm; 226 unsigned long guard_size; 227 unsigned long cacheline_size; 228 }; 229 230 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 231 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 232 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 233 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 234 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 235 236 #define DIP_HEADER_SIZE 5 237 238 #define DIP_TYPE_AVI 0x82 239 #define DIP_VERSION_AVI 0x2 240 #define DIP_LEN_AVI 13 241 242 #define DIP_TYPE_SPD 0x83 243 #define DIP_VERSION_SPD 0x1 244 #define DIP_LEN_SPD 25 245 #define DIP_SPD_UNKNOWN 0 246 #define DIP_SPD_DSTB 0x1 247 #define DIP_SPD_DVDP 0x2 248 #define DIP_SPD_DVHS 0x3 249 #define DIP_SPD_HDDVR 0x4 250 #define DIP_SPD_DVC 0x5 251 #define DIP_SPD_DSC 0x6 252 #define DIP_SPD_VCD 0x7 253 #define DIP_SPD_GAME 0x8 254 #define DIP_SPD_PC 0x9 255 #define DIP_SPD_BD 0xa 256 #define DIP_SPD_SCD 0xb 257 258 struct dip_infoframe { 259 uint8_t type; /* HB0 */ 260 uint8_t ver; /* HB1 */ 261 uint8_t len; /* HB2 - body len, not including checksum */ 262 uint8_t ecc; /* Header ECC */ 263 uint8_t checksum; /* PB0 */ 264 union { 265 struct { 266 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ 267 uint8_t Y_A_B_S; 268 /* PB2 - C 7:6, M 5:4, R 3:0 */ 269 uint8_t C_M_R; 270 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ 271 uint8_t ITC_EC_Q_SC; 272 /* PB4 - VIC 6:0 */ 273 uint8_t VIC; 274 /* PB5 - PR 3:0 */ 275 uint8_t PR; 276 /* PB6 to PB13 */ 277 uint16_t top_bar_end; 278 uint16_t bottom_bar_start; 279 uint16_t left_bar_end; 280 uint16_t right_bar_start; 281 } avi; 282 struct { 283 uint8_t vn[8]; 284 uint8_t pd[16]; 285 uint8_t sdi; 286 } spd; 287 uint8_t payload[27]; 288 } __attribute__ ((packed)) body; 289 } __attribute__((packed)); 290 291 static inline struct drm_crtc * 292 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 293 { 294 struct drm_i915_private *dev_priv = dev->dev_private; 295 return dev_priv->pipe_to_crtc_mapping[pipe]; 296 } 297 298 static inline struct drm_crtc * 299 intel_get_crtc_for_plane(struct drm_device *dev, int plane) 300 { 301 struct drm_i915_private *dev_priv = dev->dev_private; 302 return dev_priv->plane_to_crtc_mapping[plane]; 303 } 304 305 struct intel_unpin_work { 306 struct task task; 307 struct drm_device *dev; 308 struct drm_i915_gem_object *old_fb_obj; 309 struct drm_i915_gem_object *pending_flip_obj; 310 struct drm_pending_vblank_event *event; 311 atomic_t pending; 312 bool enable_stall_check; 313 }; 314 315 struct intel_fbc_work { 316 struct timeout_task task; 317 struct drm_crtc *crtc; 318 struct drm_framebuffer *fb; 319 int interval; 320 }; 321 322 int intel_connector_update_modes(struct drm_connector *connector, 323 struct edid *edid); 324 int intel_ddc_get_modes(struct drm_connector *c, device_t adapter); 325 extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus); 326 327 extern void intel_attach_force_audio_property(struct drm_connector *connector); 328 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 329 330 extern void intel_crt_init(struct drm_device *dev); 331 extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg); 332 void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); 333 extern bool intel_sdvo_init(struct drm_device *dev, int output_device); 334 extern void intel_dvo_init(struct drm_device *dev); 335 extern void intel_tv_init(struct drm_device *dev); 336 extern void intel_mark_busy(struct drm_device *dev); 337 extern bool intel_lvds_init(struct drm_device *dev); 338 extern void intel_dp_init(struct drm_device *dev, int dp_reg); 339 void 340 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 341 struct drm_display_mode *adjusted_mode); 342 extern bool intel_dpd_is_edp(struct drm_device *dev); 343 extern void intel_edp_link_config(struct intel_encoder *, int *, int *); 344 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); 345 extern int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe); 346 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, 347 enum plane plane); 348 349 /* intel_panel.c */ 350 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 351 struct drm_display_mode *adjusted_mode); 352 extern void intel_pch_panel_fitting(struct drm_device *dev, 353 int fitting_mode, 354 const struct drm_display_mode *mode, 355 struct drm_display_mode *adjusted_mode); 356 extern u32 intel_panel_get_max_backlight(struct drm_device *dev); 357 extern u32 intel_panel_get_backlight(struct drm_device *dev); 358 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); 359 extern int intel_panel_setup_backlight(struct drm_device *dev); 360 extern void intel_panel_enable_backlight(struct drm_device *dev); 361 extern void intel_panel_disable_backlight(struct drm_device *dev); 362 extern void intel_panel_destroy_backlight(struct drm_device *dev); 363 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); 364 365 extern void intel_crtc_load_lut(struct drm_crtc *crtc); 366 extern void intel_encoder_prepare(struct drm_encoder *encoder); 367 extern void intel_encoder_commit(struct drm_encoder *encoder); 368 extern void intel_encoder_destroy(struct drm_encoder *encoder); 369 370 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) 371 { 372 return to_intel_connector(connector)->encoder; 373 } 374 375 extern void intel_connector_attach_encoder(struct intel_connector *connector, 376 struct intel_encoder *encoder); 377 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 378 379 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 380 struct drm_crtc *crtc); 381 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 382 struct drm_file *file_priv); 383 extern enum transcoder 384 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 385 enum i915_pipe pipe); 386 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); 387 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); 388 389 struct intel_load_detect_pipe { 390 struct drm_framebuffer *release_fb; 391 bool load_detect_temp; 392 int dpms_mode; 393 }; 394 extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder, 395 struct drm_connector *connector, 396 struct drm_display_mode *mode, 397 struct intel_load_detect_pipe *old); 398 extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder, 399 struct drm_connector *connector, 400 struct intel_load_detect_pipe *old); 401 402 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 403 u16 blue, int regno); 404 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 405 u16 *blue, int regno); 406 extern void intel_enable_clock_gating(struct drm_device *dev); 407 extern void ironlake_disable_rc6(struct drm_device *dev); 408 extern void ironlake_enable_drps(struct drm_device *dev); 409 extern void ironlake_disable_drps(struct drm_device *dev); 410 extern void gen6_enable_rps(struct drm_i915_private *dev_priv); 411 extern void gen6_update_ring_freq(struct drm_i915_private *dev_priv); 412 extern void gen6_disable_rps(struct drm_device *dev); 413 extern void intel_init_emon(struct drm_device *dev); 414 415 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, 416 struct drm_i915_gem_object *obj, 417 struct intel_ring_buffer *pipelined); 418 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 419 420 extern int intel_framebuffer_init(struct drm_device *dev, 421 struct intel_framebuffer *ifb, 422 struct drm_mode_fb_cmd2 *mode_cmd, 423 struct drm_i915_gem_object *obj); 424 extern int intel_fbdev_init(struct drm_device *dev); 425 extern void intel_fbdev_fini(struct drm_device *dev); 426 427 extern void intel_prepare_page_flip(struct drm_device *dev, int plane); 428 extern void intel_finish_page_flip(struct drm_device *dev, int pipe); 429 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 430 431 extern void intel_setup_overlay(struct drm_device *dev); 432 extern void intel_cleanup_overlay(struct drm_device *dev); 433 extern int intel_overlay_switch_off(struct intel_overlay *overlay); 434 extern int intel_overlay_put_image(struct drm_device *dev, void *data, 435 struct drm_file *file_priv); 436 extern int intel_overlay_attrs(struct drm_device *dev, void *data, 437 struct drm_file *file_priv); 438 439 extern void intel_fb_output_poll_changed(struct drm_device *dev); 440 extern void intel_fb_restore_mode(struct drm_device *dev); 441 442 extern void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 443 bool state); 444 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 445 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 446 447 extern void intel_init_clock_gating(struct drm_device *dev); 448 extern void intel_write_eld(struct drm_encoder *encoder, 449 struct drm_display_mode *mode); 450 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); 451 452 /* For use by IVB LP watermark workaround in intel_sprite.c */ 453 extern void intel_update_watermarks(struct drm_device *dev); 454 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 455 uint32_t sprite_width, 456 int pixel_size); 457 458 extern unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y, 459 unsigned int bpp, 460 unsigned int pitch); 461 462 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 463 struct drm_file *file_priv); 464 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 465 struct drm_file *file_priv); 466 467 /* Power-related functions, located in intel_pm.c */ 468 /* FBC */ 469 extern void i8xx_disable_fbc(struct drm_device *dev); 470 extern void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 471 extern bool i8xx_fbc_enabled(struct drm_device *dev); 472 extern void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 473 extern void g4x_disable_fbc(struct drm_device *dev); 474 extern bool g4x_fbc_enabled(struct drm_device *dev); 475 extern void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 476 extern void ironlake_disable_fbc(struct drm_device *dev); 477 extern bool ironlake_fbc_enabled(struct drm_device *dev); 478 extern bool intel_fbc_enabled(struct drm_device *dev); 479 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 480 extern void intel_update_fbc(struct drm_device *dev); 481 482 /* Watermarks */ 483 extern void pineview_update_wm(struct drm_device *dev); 484 extern void valleyview_update_wm(struct drm_device *dev); 485 extern void g4x_update_wm(struct drm_device *dev); 486 extern void i965_update_wm(struct drm_device *dev); 487 extern void i9xx_update_wm(struct drm_device *dev); 488 extern void i830_update_wm(struct drm_device *dev); 489 extern void ironlake_update_wm(struct drm_device *dev); 490 extern void sandybridge_update_wm(struct drm_device *dev); 491 extern void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, 492 uint32_t sprite_width, int pixel_size); 493 extern const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, 494 int is_ddr3, 495 int fsb, 496 int mem); 497 extern void pineview_disable_cxsr(struct drm_device *dev); 498 extern int i9xx_get_fifo_size(struct drm_device *dev, int plane); 499 extern int i85x_get_fifo_size(struct drm_device *dev, int plane); 500 extern int i845_get_fifo_size(struct drm_device *dev, int plane); 501 extern int i830_get_fifo_size(struct drm_device *dev, int plane); 502 503 /* Clock gating */ 504 extern void ironlake_init_clock_gating(struct drm_device *dev); 505 extern void gen6_init_clock_gating(struct drm_device *dev); 506 extern void ivybridge_init_clock_gating(struct drm_device *dev); 507 extern void valleyview_init_clock_gating(struct drm_device *dev); 508 extern void g4x_init_clock_gating(struct drm_device *dev); 509 extern void crestline_init_clock_gating(struct drm_device *dev); 510 extern void broadwater_init_clock_gating(struct drm_device *dev); 511 extern void gen3_init_clock_gating(struct drm_device *dev); 512 extern void i85x_init_clock_gating(struct drm_device *dev); 513 extern void i830_init_clock_gating(struct drm_device *dev); 514 extern void ibx_init_clock_gating(struct drm_device *dev); 515 extern void cpt_init_clock_gating(struct drm_device *dev); 516 517 #endif 518