1 /* 2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 */ 25 #ifndef __INTEL_DRV_H__ 26 #define __INTEL_DRV_H__ 27 28 #include <linux/i2c.h> 29 #include <drm/i915_drm.h> 30 #include "i915_drv.h" 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_fb_helper.h> 34 #include <drm/drm_dp_helper.h> 35 36 #define _wait_for(COND, MS, W) ({ \ 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \ 38 int ret__ = 0; \ 39 while (!(COND)) { \ 40 if (time_after(jiffies, timeout__)) { \ 41 ret__ = -ETIMEDOUT; \ 42 break; \ 43 } \ 44 if (W && drm_can_sleep()) { \ 45 msleep(W); \ 46 } else { \ 47 cpu_pause(); \ 48 } \ 49 } \ 50 ret__; \ 51 }) 52 53 #define wait_for_atomic_us(COND, US) ({ \ 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \ 55 int ret__ = 0; \ 56 while (!(COND)) { \ 57 if (time_after(jiffies, timeout__)) { \ 58 ret__ = -ETIMEDOUT; \ 59 break; \ 60 } \ 61 cpu_pause(); \ 62 } \ 63 ret__; \ 64 }) 65 66 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 67 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0) 68 69 #define KHz(x) (1000*x) 70 #define MHz(x) KHz(1000*x) 71 72 /* 73 * Display related stuff 74 */ 75 76 /* store information about an Ixxx DVO */ 77 /* The i830->i865 use multiple DVOs with multiple i2cs */ 78 /* the i915, i945 have a single sDVO i2c bus - which is different */ 79 #define MAX_OUTPUTS 6 80 /* maximum connectors per crtcs in the mode set */ 81 #define INTELFB_CONN_LIMIT 4 82 83 #define INTEL_I2C_BUS_DVO 1 84 #define INTEL_I2C_BUS_SDVO 2 85 86 /* these are outputs from the chip - integrated only 87 external chips are via DVO or SDVO output */ 88 #define INTEL_OUTPUT_UNUSED 0 89 #define INTEL_OUTPUT_ANALOG 1 90 #define INTEL_OUTPUT_DVO 2 91 #define INTEL_OUTPUT_SDVO 3 92 #define INTEL_OUTPUT_LVDS 4 93 #define INTEL_OUTPUT_TVOUT 5 94 #define INTEL_OUTPUT_HDMI 6 95 #define INTEL_OUTPUT_DISPLAYPORT 7 96 #define INTEL_OUTPUT_EDP 8 97 #define INTEL_OUTPUT_UNKNOWN 9 98 99 #define INTEL_DVO_CHIP_NONE 0 100 #define INTEL_DVO_CHIP_LVDS 1 101 #define INTEL_DVO_CHIP_TMDS 2 102 #define INTEL_DVO_CHIP_TVOUT 4 103 104 /* drm_display_mode->private_flags */ 105 #define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0) 106 #define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT) 107 #define INTEL_MODE_DP_FORCE_6BPC (0x10) 108 /* This flag must be set by the encoder's mode_fixup if it changes the crtc 109 * timings in the mode to prevent the crtc fixup from overwriting them. 110 * Currently only lvds needs that. */ 111 #define INTEL_MODE_CRTC_TIMINGS_SET (0x20) 112 /* 113 * Set when limited 16-235 (as opposed to full 0-255) RGB color range is 114 * to be used. 115 */ 116 #define INTEL_MODE_LIMITED_COLOR_RANGE (0x40) 117 118 static inline void 119 intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, 120 int multiplier) 121 { 122 mode->clock *= multiplier; 123 mode->private_flags |= multiplier; 124 } 125 126 static inline int 127 intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode) 128 { 129 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT; 130 } 131 132 struct intel_framebuffer { 133 struct drm_framebuffer base; 134 struct drm_i915_gem_object *obj; 135 }; 136 137 struct intel_fbdev { 138 struct drm_fb_helper helper; 139 struct intel_framebuffer ifb; 140 struct list_head fbdev_list; 141 struct drm_display_mode *our_mode; 142 }; 143 144 struct intel_encoder { 145 struct drm_encoder base; 146 /* 147 * The new crtc this encoder will be driven from. Only differs from 148 * base->crtc while a modeset is in progress. 149 */ 150 struct intel_crtc *new_crtc; 151 152 int type; 153 bool needs_tv_clock; 154 /* 155 * Intel hw has only one MUX where encoders could be clone, hence a 156 * simple flag is enough to compute the possible_clones mask. 157 */ 158 bool cloneable; 159 bool connectors_active; 160 void (*hot_plug)(struct intel_encoder *); 161 void (*pre_pll_enable)(struct intel_encoder *); 162 void (*pre_enable)(struct intel_encoder *); 163 void (*enable)(struct intel_encoder *); 164 void (*disable)(struct intel_encoder *); 165 void (*post_disable)(struct intel_encoder *); 166 /* Read out the current hw state of this connector, returning true if 167 * the encoder is active. If the encoder is enabled it also set the pipe 168 * it is connected to in the pipe parameter. */ 169 bool (*get_hw_state)(struct intel_encoder *, enum i915_pipe *pipe); 170 int crtc_mask; 171 }; 172 173 struct intel_panel { 174 struct drm_display_mode *fixed_mode; 175 int fitting_mode; 176 }; 177 178 struct intel_connector { 179 struct drm_connector base; 180 /* 181 * The fixed encoder this connector is connected to. 182 */ 183 struct intel_encoder *encoder; 184 185 /* 186 * The new encoder this connector will be driven. Only differs from 187 * encoder while a modeset is in progress. 188 */ 189 struct intel_encoder *new_encoder; 190 191 /* Reads out the current hw, returning true if the connector is enabled 192 * and active (i.e. dpms ON state). */ 193 bool (*get_hw_state)(struct intel_connector *); 194 195 /* Panel info for eDP and LVDS */ 196 struct intel_panel panel; 197 198 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */ 199 struct edid *edid; 200 }; 201 202 struct intel_crtc { 203 struct drm_crtc base; 204 enum i915_pipe pipe; 205 enum plane plane; 206 enum transcoder cpu_transcoder; 207 u8 lut_r[256], lut_g[256], lut_b[256]; 208 /* 209 * Whether the crtc and the connected output pipeline is active. Implies 210 * that crtc->enabled is set, i.e. the current mode configuration has 211 * some outputs connected to this crtc. 212 */ 213 bool active; 214 bool eld_vld; 215 bool primary_disabled; /* is the crtc obscured by a plane? */ 216 bool lowfreq_avail; 217 struct intel_overlay *overlay; 218 struct intel_unpin_work *unpin_work; 219 int fdi_lanes; 220 221 atomic_t unpin_work_count; 222 223 /* Display surface base address adjustement for pageflips. Note that on 224 * gen4+ this only adjusts up to a tile, offsets within a tile are 225 * handled in the hw itself (with the TILEOFF register). */ 226 unsigned long dspaddr_offset; 227 228 struct drm_i915_gem_object *cursor_bo; 229 uint32_t cursor_addr; 230 int16_t cursor_x, cursor_y; 231 int16_t cursor_width, cursor_height; 232 bool cursor_visible; 233 unsigned int bpp; 234 235 /* We can share PLLs across outputs if the timings match */ 236 struct intel_pch_pll *pch_pll; 237 uint32_t ddi_pll_sel; 238 239 /* reset counter value when the last flip was submitted */ 240 unsigned int reset_counter; 241 }; 242 243 struct intel_plane { 244 struct drm_plane base; 245 enum i915_pipe pipe; 246 struct drm_i915_gem_object *obj; 247 bool can_scale; 248 int max_downscale; 249 u32 lut_r[1024], lut_g[1024], lut_b[1024]; 250 void (*update_plane)(struct drm_plane *plane, 251 struct drm_framebuffer *fb, 252 struct drm_i915_gem_object *obj, 253 int crtc_x, int crtc_y, 254 unsigned int crtc_w, unsigned int crtc_h, 255 uint32_t x, uint32_t y, 256 uint32_t src_w, uint32_t src_h); 257 void (*disable_plane)(struct drm_plane *plane); 258 int (*update_colorkey)(struct drm_plane *plane, 259 struct drm_intel_sprite_colorkey *key); 260 void (*get_colorkey)(struct drm_plane *plane, 261 struct drm_intel_sprite_colorkey *key); 262 }; 263 264 struct intel_watermark_params { 265 unsigned long fifo_size; 266 unsigned long max_wm; 267 unsigned long default_wm; 268 unsigned long guard_size; 269 unsigned long cacheline_size; 270 }; 271 272 struct cxsr_latency { 273 int is_desktop; 274 int is_ddr3; 275 unsigned long fsb_freq; 276 unsigned long mem_freq; 277 unsigned long display_sr; 278 unsigned long display_hpll_disable; 279 unsigned long cursor_sr; 280 unsigned long cursor_hpll_disable; 281 }; 282 283 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base) 284 #define to_intel_connector(x) container_of(x, struct intel_connector, base) 285 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base) 286 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base) 287 #define to_intel_plane(x) container_of(x, struct intel_plane, base) 288 289 #define DIP_HEADER_SIZE 5 290 291 #define DIP_TYPE_AVI 0x82 292 #define DIP_VERSION_AVI 0x2 293 #define DIP_LEN_AVI 13 294 #define DIP_AVI_PR_1 0 295 #define DIP_AVI_PR_2 1 296 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2) 297 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2) 298 #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2) 299 300 #define DIP_TYPE_SPD 0x83 301 #define DIP_VERSION_SPD 0x1 302 #define DIP_LEN_SPD 25 303 #define DIP_SPD_UNKNOWN 0 304 #define DIP_SPD_DSTB 0x1 305 #define DIP_SPD_DVDP 0x2 306 #define DIP_SPD_DVHS 0x3 307 #define DIP_SPD_HDDVR 0x4 308 #define DIP_SPD_DVC 0x5 309 #define DIP_SPD_DSC 0x6 310 #define DIP_SPD_VCD 0x7 311 #define DIP_SPD_GAME 0x8 312 #define DIP_SPD_PC 0x9 313 #define DIP_SPD_BD 0xa 314 #define DIP_SPD_SCD 0xb 315 316 struct dip_infoframe { 317 uint8_t type; /* HB0 */ 318 uint8_t ver; /* HB1 */ 319 uint8_t len; /* HB2 - body len, not including checksum */ 320 uint8_t ecc; /* Header ECC */ 321 uint8_t checksum; /* PB0 */ 322 union { 323 struct { 324 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */ 325 uint8_t Y_A_B_S; 326 /* PB2 - C 7:6, M 5:4, R 3:0 */ 327 uint8_t C_M_R; 328 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */ 329 uint8_t ITC_EC_Q_SC; 330 /* PB4 - VIC 6:0 */ 331 uint8_t VIC; 332 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */ 333 uint8_t YQ_CN_PR; 334 /* PB6 to PB13 */ 335 uint16_t top_bar_end; 336 uint16_t bottom_bar_start; 337 uint16_t left_bar_end; 338 uint16_t right_bar_start; 339 } __attribute__ ((packed)) avi; 340 struct { 341 uint8_t vn[8]; 342 uint8_t pd[16]; 343 uint8_t sdi; 344 } __attribute__ ((packed)) spd; 345 uint8_t payload[27]; 346 } __attribute__ ((packed)) body; 347 } __attribute__((packed)); 348 349 struct intel_hdmi { 350 u32 sdvox_reg; 351 int ddc_bus; 352 uint32_t color_range; 353 bool color_range_auto; 354 bool has_hdmi_sink; 355 bool has_audio; 356 enum hdmi_force_audio force_audio; 357 bool rgb_quant_range_selectable; 358 void (*write_infoframe)(struct drm_encoder *encoder, 359 struct dip_infoframe *frame); 360 void (*set_infoframes)(struct drm_encoder *encoder, 361 struct drm_display_mode *adjusted_mode); 362 }; 363 364 #define DP_MAX_DOWNSTREAM_PORTS 0x10 365 #define DP_LINK_CONFIGURATION_SIZE 9 366 367 struct intel_dp { 368 uint32_t output_reg; 369 uint32_t DP; 370 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; 371 bool has_audio; 372 enum hdmi_force_audio force_audio; 373 uint32_t color_range; 374 bool color_range_auto; 375 uint8_t link_bw; 376 uint8_t lane_count; 377 uint8_t dpcd[DP_RECEIVER_CAP_SIZE]; 378 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; 379 device_t dp_iic_bus; 380 device_t adapter; 381 bool is_pch_edp; 382 uint8_t train_set[4]; 383 int panel_power_up_delay; 384 int panel_power_down_delay; 385 int panel_power_cycle_delay; 386 int backlight_on_delay; 387 int backlight_off_delay; 388 struct delayed_work panel_vdd_work; 389 bool want_panel_vdd; 390 struct intel_connector *attached_connector; 391 }; 392 393 struct intel_digital_port { 394 struct intel_encoder base; 395 enum port port; 396 u32 port_reversal; 397 struct intel_dp dp; 398 struct intel_hdmi hdmi; 399 }; 400 401 static inline struct drm_crtc * 402 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe) 403 { 404 struct drm_i915_private *dev_priv = dev->dev_private; 405 return dev_priv->pipe_to_crtc_mapping[pipe]; 406 } 407 408 static inline struct drm_crtc * 409 intel_get_crtc_for_plane(struct drm_device *dev, int plane) 410 { 411 struct drm_i915_private *dev_priv = dev->dev_private; 412 return dev_priv->plane_to_crtc_mapping[plane]; 413 } 414 415 struct intel_unpin_work { 416 struct work_struct work; 417 struct drm_crtc *crtc; 418 struct drm_i915_gem_object *old_fb_obj; 419 struct drm_i915_gem_object *pending_flip_obj; 420 struct drm_pending_vblank_event *event; 421 atomic_t pending; 422 #define INTEL_FLIP_INACTIVE 0 423 #define INTEL_FLIP_PENDING 1 424 #define INTEL_FLIP_COMPLETE 2 425 bool enable_stall_check; 426 }; 427 428 struct intel_fbc_work { 429 struct delayed_work work; 430 struct drm_crtc *crtc; 431 struct drm_framebuffer *fb; 432 int interval; 433 }; 434 435 int intel_pch_rawclk(struct drm_device *dev); 436 437 int intel_connector_update_modes(struct drm_connector *connector, 438 struct edid *edid); 439 int intel_ddc_get_modes(struct drm_connector *c, device_t adapter); 440 441 extern void intel_attach_force_audio_property(struct drm_connector *connector); 442 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector); 443 444 extern void intel_crt_init(struct drm_device *dev); 445 extern void intel_hdmi_init(struct drm_device *dev, 446 int sdvox_reg, enum port port); 447 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, 448 struct intel_connector *intel_connector); 449 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder); 450 extern bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, 451 const struct drm_display_mode *mode, 452 struct drm_display_mode *adjusted_mode); 453 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if); 454 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, 455 bool is_sdvob); 456 extern void intel_dvo_init(struct drm_device *dev); 457 extern void intel_tv_init(struct drm_device *dev); 458 extern void intel_mark_busy(struct drm_device *dev); 459 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj); 460 extern void intel_mark_idle(struct drm_device *dev); 461 extern bool intel_lvds_init(struct drm_device *dev); 462 extern bool intel_is_dual_link_lvds(struct drm_device *dev); 463 extern void intel_dp_init(struct drm_device *dev, int output_reg, 464 enum port port); 465 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 466 struct intel_connector *intel_connector); 467 void 468 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 469 struct drm_display_mode *adjusted_mode); 470 extern void intel_dp_init_link_config(struct intel_dp *intel_dp); 471 extern void intel_dp_start_link_train(struct intel_dp *intel_dp); 472 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp); 473 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 474 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder); 475 extern void intel_dp_check_link_status(struct intel_dp *intel_dp); 476 extern bool intel_dp_mode_fixup(struct drm_encoder *encoder, 477 const struct drm_display_mode *mode, 478 struct drm_display_mode *adjusted_mode); 479 extern bool intel_dpd_is_edp(struct drm_device *dev); 480 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp); 481 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp); 482 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp); 483 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp); 484 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); 485 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 486 extern void intel_edp_link_config(struct intel_encoder *, int *, int *); 487 extern int intel_edp_target_clock(struct intel_encoder *, 488 struct drm_display_mode *mode); 489 extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); 490 extern int intel_plane_init(struct drm_device *dev, enum i915_pipe pipe); 491 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv, 492 enum plane plane); 493 494 /* intel_panel.c */ 495 extern int intel_panel_init(struct intel_panel *panel, 496 struct drm_display_mode *fixed_mode); 497 extern void intel_panel_fini(struct intel_panel *panel); 498 499 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, 500 struct drm_display_mode *adjusted_mode); 501 extern void intel_pch_panel_fitting(struct drm_device *dev, 502 int fitting_mode, 503 const struct drm_display_mode *mode, 504 struct drm_display_mode *adjusted_mode); 505 extern u32 intel_panel_get_max_backlight(struct drm_device *dev); 506 extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); 507 extern int intel_panel_setup_backlight(struct drm_connector *connector); 508 extern void intel_panel_enable_backlight(struct drm_device *dev, 509 enum i915_pipe pipe); 510 extern void intel_panel_disable_backlight(struct drm_device *dev); 511 extern void intel_panel_destroy_backlight(struct drm_device *dev); 512 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev); 513 514 struct intel_set_config { 515 struct drm_encoder **save_connector_encoders; 516 struct drm_crtc **save_encoder_crtcs; 517 518 bool fb_changed; 519 bool mode_changed; 520 }; 521 522 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, 523 int x, int y, struct drm_framebuffer *old_fb); 524 extern void intel_modeset_disable(struct drm_device *dev); 525 extern void intel_crtc_restore_mode(struct drm_crtc *crtc); 526 extern void intel_crtc_load_lut(struct drm_crtc *crtc); 527 extern void intel_crtc_update_dpms(struct drm_crtc *crtc); 528 extern void intel_encoder_noop(struct drm_encoder *encoder); 529 extern void intel_encoder_destroy(struct drm_encoder *encoder); 530 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode); 531 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder); 532 extern void intel_connector_dpms(struct drm_connector *, int mode); 533 extern bool intel_connector_get_hw_state(struct intel_connector *connector); 534 extern void intel_modeset_check_state(struct drm_device *dev); 535 536 537 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector) 538 { 539 return to_intel_connector(connector)->encoder; 540 } 541 542 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder) 543 { 544 struct intel_digital_port *intel_dig_port = 545 container_of(encoder, struct intel_digital_port, base.base); 546 return &intel_dig_port->dp; 547 } 548 549 static inline struct intel_digital_port * 550 enc_to_dig_port(struct drm_encoder *encoder) 551 { 552 return container_of(encoder, struct intel_digital_port, base.base); 553 } 554 555 static inline struct intel_digital_port * 556 dp_to_dig_port(struct intel_dp *intel_dp) 557 { 558 return container_of(intel_dp, struct intel_digital_port, dp); 559 } 560 561 static inline struct intel_digital_port * 562 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi) 563 { 564 return container_of(intel_hdmi, struct intel_digital_port, hdmi); 565 } 566 567 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 568 struct intel_digital_port *port); 569 570 extern void intel_connector_attach_encoder(struct intel_connector *connector, 571 struct intel_encoder *encoder); 572 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector); 573 574 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 575 struct drm_crtc *crtc); 576 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 577 struct drm_file *file_priv); 578 extern enum transcoder 579 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 580 enum i915_pipe pipe); 581 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe); 582 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); 583 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 584 585 struct intel_load_detect_pipe { 586 struct drm_framebuffer *release_fb; 587 bool load_detect_temp; 588 int dpms_mode; 589 }; 590 extern bool intel_get_load_detect_pipe(struct drm_connector *connector, 591 struct drm_display_mode *mode, 592 struct intel_load_detect_pipe *old); 593 extern void intel_release_load_detect_pipe(struct drm_connector *connector, 594 struct intel_load_detect_pipe *old); 595 596 extern void intelfb_restore(void); 597 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 598 u16 blue, int regno); 599 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 600 u16 *blue, int regno); 601 extern void intel_enable_clock_gating(struct drm_device *dev); 602 603 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, 604 struct drm_i915_gem_object *obj, 605 struct intel_ring_buffer *pipelined); 606 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj); 607 608 extern int intel_framebuffer_init(struct drm_device *dev, 609 struct intel_framebuffer *ifb, 610 struct drm_mode_fb_cmd2 *mode_cmd, 611 struct drm_i915_gem_object *obj); 612 extern int intel_fbdev_init(struct drm_device *dev); 613 extern void intel_fbdev_initial_config(struct drm_device *dev); 614 extern void intel_fbdev_fini(struct drm_device *dev); 615 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state); 616 extern void intel_prepare_page_flip(struct drm_device *dev, int plane); 617 extern void intel_finish_page_flip(struct drm_device *dev, int pipe); 618 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane); 619 620 extern void intel_setup_overlay(struct drm_device *dev); 621 extern void intel_cleanup_overlay(struct drm_device *dev); 622 extern int intel_overlay_switch_off(struct intel_overlay *overlay); 623 extern int intel_overlay_put_image(struct drm_device *dev, void *data, 624 struct drm_file *file_priv); 625 extern int intel_overlay_attrs(struct drm_device *dev, void *data, 626 struct drm_file *file_priv); 627 628 extern void intel_fb_output_poll_changed(struct drm_device *dev); 629 extern void intel_fb_restore_mode(struct drm_device *dev); 630 631 extern void assert_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 632 bool state); 633 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) 634 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) 635 636 extern void intel_init_clock_gating(struct drm_device *dev); 637 extern void intel_write_eld(struct drm_encoder *encoder, 638 struct drm_display_mode *mode); 639 extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe); 640 extern void intel_prepare_ddi(struct drm_device *dev); 641 extern void hsw_fdi_link_train(struct drm_crtc *crtc); 642 extern void intel_ddi_init(struct drm_device *dev, enum port port); 643 644 /* For use by IVB LP watermark workaround in intel_sprite.c */ 645 extern void intel_update_watermarks(struct drm_device *dev); 646 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, 647 uint32_t sprite_width, 648 int pixel_size); 649 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe, 650 struct drm_display_mode *mode); 651 652 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y, 653 unsigned int tiling_mode, 654 unsigned int bpp, 655 unsigned int pitch); 656 657 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data, 658 struct drm_file *file_priv); 659 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data, 660 struct drm_file *file_priv); 661 662 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg); 663 664 /* Power-related functions, located in intel_pm.c */ 665 extern void intel_init_pm(struct drm_device *dev); 666 /* FBC */ 667 extern bool intel_fbc_enabled(struct drm_device *dev); 668 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); 669 extern void intel_update_fbc(struct drm_device *dev); 670 /* IPS */ 671 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv); 672 extern void intel_gpu_ips_teardown(void); 673 674 extern void intel_init_power_well(struct drm_device *dev); 675 extern void intel_set_power_well(struct drm_device *dev, bool enable); 676 extern void intel_enable_gt_powersave(struct drm_device *dev); 677 extern void intel_disable_gt_powersave(struct drm_device *dev); 678 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv); 679 extern void ironlake_teardown_rc6(struct drm_device *dev); 680 681 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 682 enum i915_pipe *pipe); 683 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv); 684 extern void intel_ddi_pll_init(struct drm_device *dev); 685 extern void intel_ddi_enable_pipe_func(struct drm_crtc *crtc); 686 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 687 enum transcoder cpu_transcoder); 688 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc); 689 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc); 690 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev); 691 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock); 692 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc); 693 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc); 694 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder); 695 extern bool 696 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 697 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc); 698 699 #endif /* __INTEL_DRV_H__ */ 700