1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <drm/drmP.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_crtc_helper.h> 31 #include <drm/drm_edid.h> 32 #include "intel_drv.h" 33 #include <drm/i915_drm.h> 34 #include "i915_drv.h" 35 #include <linux/err.h> 36 37 #define DP_LINK_CHECK_TIMEOUT (10 * 1000) 38 39 /** 40 * is_edp - is the given port attached to an eDP panel (either CPU or PCH) 41 * @intel_dp: DP struct 42 * 43 * If a CPU or PCH DP output is attached to an eDP panel, this function 44 * will return true, and false otherwise. 45 */ 46 static bool is_edp(struct intel_dp *intel_dp) 47 { 48 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 49 50 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 51 } 52 53 /** 54 * is_pch_edp - is the port on the PCH and attached to an eDP panel? 55 * @intel_dp: DP struct 56 * 57 * Returns true if the given DP struct corresponds to a PCH DP port attached 58 * to an eDP panel, false otherwise. Helpful for determining whether we 59 * may need FDI resources for a given DP output or not. 60 */ 61 static bool is_pch_edp(struct intel_dp *intel_dp) 62 { 63 return intel_dp->is_pch_edp; 64 } 65 66 /** 67 * is_cpu_edp - is the port on the CPU and attached to an eDP panel? 68 * @intel_dp: DP struct 69 * 70 * Returns true if the given DP struct corresponds to a CPU eDP port. 71 */ 72 static bool is_cpu_edp(struct intel_dp *intel_dp) 73 { 74 return is_edp(intel_dp) && !is_pch_edp(intel_dp); 75 } 76 77 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) 78 { 79 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 80 81 return intel_dig_port->base.base.dev; 82 } 83 84 static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 85 { 86 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 87 } 88 89 /** 90 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? 91 * @encoder: DRM encoder 92 * 93 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed 94 * by intel_display.c. 95 */ 96 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) 97 { 98 struct intel_dp *intel_dp; 99 100 if (!encoder) 101 return false; 102 103 intel_dp = enc_to_intel_dp(encoder); 104 105 return is_pch_edp(intel_dp); 106 } 107 108 static void intel_dp_link_down(struct intel_dp *intel_dp); 109 110 void 111 intel_edp_link_config(struct intel_encoder *intel_encoder, 112 int *lane_num, int *link_bw) 113 { 114 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 115 116 *lane_num = intel_dp->lane_count; 117 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); 118 } 119 120 int 121 intel_edp_target_clock(struct intel_encoder *intel_encoder, 122 struct drm_display_mode *mode) 123 { 124 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 125 struct intel_connector *intel_connector = intel_dp->attached_connector; 126 127 if (intel_connector->panel.fixed_mode) 128 return intel_connector->panel.fixed_mode->clock; 129 else 130 return mode->clock; 131 } 132 133 static int 134 intel_dp_max_link_bw(struct intel_dp *intel_dp) 135 { 136 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; 137 138 switch (max_link_bw) { 139 case DP_LINK_BW_1_62: 140 case DP_LINK_BW_2_7: 141 break; 142 default: 143 max_link_bw = DP_LINK_BW_1_62; 144 break; 145 } 146 return max_link_bw; 147 } 148 149 static int 150 intel_dp_link_clock(uint8_t link_bw) 151 { 152 if (link_bw == DP_LINK_BW_2_7) 153 return 270000; 154 else 155 return 162000; 156 } 157 158 /* 159 * The units on the numbers in the next two are... bizarre. Examples will 160 * make it clearer; this one parallels an example in the eDP spec. 161 * 162 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: 163 * 164 * 270000 * 1 * 8 / 10 == 216000 165 * 166 * The actual data capacity of that configuration is 2.16Gbit/s, so the 167 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - 168 * or equivalently, kilopixels per second - so for 1680x1050R it'd be 169 * 119000. At 18bpp that's 2142000 kilobits per second. 170 * 171 * Thus the strange-looking division by 10 in intel_dp_link_required, to 172 * get the result in decakilobits instead of kilobits. 173 */ 174 175 static int 176 intel_dp_link_required(int pixel_clock, int bpp) 177 { 178 return (pixel_clock * bpp + 9) / 10; 179 } 180 181 static int 182 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 183 { 184 return (max_link_clock * max_lanes * 8) / 10; 185 } 186 187 static bool 188 intel_dp_adjust_dithering(struct intel_dp *intel_dp, 189 struct drm_display_mode *mode, 190 bool adjust_mode) 191 { 192 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); 193 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); 194 int max_rate, mode_rate; 195 196 mode_rate = intel_dp_link_required(mode->clock, 24); 197 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 198 199 if (mode_rate > max_rate) { 200 mode_rate = intel_dp_link_required(mode->clock, 18); 201 if (mode_rate > max_rate) 202 return false; 203 204 if (adjust_mode) 205 mode->private_flags 206 |= INTEL_MODE_DP_FORCE_6BPC; 207 208 return true; 209 } 210 211 return true; 212 } 213 214 static int 215 intel_dp_mode_valid(struct drm_connector *connector, 216 struct drm_display_mode *mode) 217 { 218 struct intel_dp *intel_dp = intel_attached_dp(connector); 219 struct intel_connector *intel_connector = to_intel_connector(connector); 220 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 221 222 if (is_edp(intel_dp) && fixed_mode) { 223 if (mode->hdisplay > fixed_mode->hdisplay) 224 return MODE_PANEL; 225 226 if (mode->vdisplay > fixed_mode->vdisplay) 227 return MODE_PANEL; 228 } 229 230 if (!intel_dp_adjust_dithering(intel_dp, mode, false)) 231 return MODE_CLOCK_HIGH; 232 233 if (mode->clock < 10000) 234 return MODE_CLOCK_LOW; 235 236 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 237 return MODE_H_ILLEGAL; 238 239 return MODE_OK; 240 } 241 242 static uint32_t 243 pack_aux(uint8_t *src, int src_bytes) 244 { 245 int i; 246 uint32_t v = 0; 247 248 if (src_bytes > 4) 249 src_bytes = 4; 250 for (i = 0; i < src_bytes; i++) 251 v |= ((uint32_t) src[i]) << ((3-i) * 8); 252 return v; 253 } 254 255 static void 256 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) 257 { 258 int i; 259 if (dst_bytes > 4) 260 dst_bytes = 4; 261 for (i = 0; i < dst_bytes; i++) 262 dst[i] = src >> ((3-i) * 8); 263 } 264 265 /* hrawclock is 1/4 the FSB frequency */ 266 static int 267 intel_hrawclk(struct drm_device *dev) 268 { 269 struct drm_i915_private *dev_priv = dev->dev_private; 270 uint32_t clkcfg; 271 272 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ 273 if (IS_VALLEYVIEW(dev)) 274 return 200; 275 276 clkcfg = I915_READ(CLKCFG); 277 switch (clkcfg & CLKCFG_FSB_MASK) { 278 case CLKCFG_FSB_400: 279 return 100; 280 case CLKCFG_FSB_533: 281 return 133; 282 case CLKCFG_FSB_667: 283 return 166; 284 case CLKCFG_FSB_800: 285 return 200; 286 case CLKCFG_FSB_1067: 287 return 266; 288 case CLKCFG_FSB_1333: 289 return 333; 290 /* these two are just a guess; one of them might be right */ 291 case CLKCFG_FSB_1600: 292 case CLKCFG_FSB_1600_ALT: 293 return 400; 294 default: 295 return 133; 296 } 297 } 298 299 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) 300 { 301 struct drm_device *dev = intel_dp_to_dev(intel_dp); 302 struct drm_i915_private *dev_priv = dev->dev_private; 303 304 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; 305 } 306 307 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) 308 { 309 struct drm_device *dev = intel_dp_to_dev(intel_dp); 310 struct drm_i915_private *dev_priv = dev->dev_private; 311 312 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; 313 } 314 315 static void 316 intel_dp_check_edp(struct intel_dp *intel_dp) 317 { 318 struct drm_device *dev = intel_dp_to_dev(intel_dp); 319 struct drm_i915_private *dev_priv = dev->dev_private; 320 321 if (!is_edp(intel_dp)) 322 return; 323 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { 324 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 325 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 326 I915_READ(PCH_PP_STATUS), 327 I915_READ(PCH_PP_CONTROL)); 328 } 329 } 330 331 static int 332 intel_dp_aux_ch(struct intel_dp *intel_dp, 333 uint8_t *send, int send_bytes, 334 uint8_t *recv, int recv_size) 335 { 336 uint32_t output_reg = intel_dp->output_reg; 337 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 338 struct drm_device *dev = intel_dig_port->base.base.dev; 339 struct drm_i915_private *dev_priv = dev->dev_private; 340 uint32_t ch_ctl = output_reg + 0x10; 341 uint32_t ch_data = ch_ctl + 4; 342 int i; 343 int recv_bytes; 344 uint32_t status; 345 uint32_t aux_clock_divider; 346 int try, precharge; 347 348 if (IS_HASWELL(dev)) { 349 switch (intel_dig_port->port) { 350 case PORT_A: 351 ch_ctl = DPA_AUX_CH_CTL; 352 ch_data = DPA_AUX_CH_DATA1; 353 break; 354 case PORT_B: 355 ch_ctl = PCH_DPB_AUX_CH_CTL; 356 ch_data = PCH_DPB_AUX_CH_DATA1; 357 break; 358 case PORT_C: 359 ch_ctl = PCH_DPC_AUX_CH_CTL; 360 ch_data = PCH_DPC_AUX_CH_DATA1; 361 break; 362 case PORT_D: 363 ch_ctl = PCH_DPD_AUX_CH_CTL; 364 ch_data = PCH_DPD_AUX_CH_DATA1; 365 break; 366 default: 367 BUG(); 368 } 369 } 370 371 intel_dp_check_edp(intel_dp); 372 /* The clock divider is based off the hrawclk, 373 * and would like to run at 2MHz. So, take the 374 * hrawclk value and divide by 2 and use that 375 * 376 * Note that PCH attached eDP panels should use a 125MHz input 377 * clock divider. 378 */ 379 if (is_cpu_edp(intel_dp)) { 380 if (IS_HASWELL(dev)) 381 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; 382 else if (IS_VALLEYVIEW(dev)) 383 aux_clock_divider = 100; 384 else if (IS_GEN6(dev) || IS_GEN7(dev)) 385 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ 386 else 387 aux_clock_divider = 225; /* eDP input clock at 450Mhz */ 388 } else if (HAS_PCH_SPLIT(dev)) 389 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); 390 else 391 aux_clock_divider = intel_hrawclk(dev) / 2; 392 393 if (IS_GEN6(dev)) 394 precharge = 3; 395 else 396 precharge = 5; 397 398 /* Try to wait for any previous AUX channel activity */ 399 for (try = 0; try < 3; try++) { 400 status = I915_READ(ch_ctl); 401 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 402 break; 403 msleep(1); 404 } 405 406 if (try == 3) { 407 WARN(1, "dp_aux_ch not started status 0x%08x\n", 408 I915_READ(ch_ctl)); 409 return -EBUSY; 410 } 411 412 /* Must try at least 3 times according to DP spec */ 413 for (try = 0; try < 5; try++) { 414 /* Load the send data into the aux channel data registers */ 415 for (i = 0; i < send_bytes; i += 4) 416 I915_WRITE(ch_data + i, 417 pack_aux(send + i, send_bytes - i)); 418 419 /* Send the command and wait for it to complete */ 420 I915_WRITE(ch_ctl, 421 DP_AUX_CH_CTL_SEND_BUSY | 422 DP_AUX_CH_CTL_TIME_OUT_400us | 423 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 424 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 425 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | 426 DP_AUX_CH_CTL_DONE | 427 DP_AUX_CH_CTL_TIME_OUT_ERROR | 428 DP_AUX_CH_CTL_RECEIVE_ERROR); 429 for (;;) { 430 status = I915_READ(ch_ctl); 431 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 432 break; 433 udelay(100); 434 } 435 436 /* Clear done status and any errors */ 437 I915_WRITE(ch_ctl, 438 status | 439 DP_AUX_CH_CTL_DONE | 440 DP_AUX_CH_CTL_TIME_OUT_ERROR | 441 DP_AUX_CH_CTL_RECEIVE_ERROR); 442 443 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | 444 DP_AUX_CH_CTL_RECEIVE_ERROR)) 445 continue; 446 if (status & DP_AUX_CH_CTL_DONE) 447 break; 448 } 449 450 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 451 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 452 return -EBUSY; 453 } 454 455 /* Check for timeout or receive error. 456 * Timeouts occur when the sink is not connected 457 */ 458 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 459 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 460 return -EIO; 461 } 462 463 /* Timeouts occur when the device isn't connected, so they're 464 * "normal" -- don't fill the kernel log with these */ 465 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 466 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 467 return -ETIMEDOUT; 468 } 469 470 /* Unload any bytes sent back from the other side */ 471 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 472 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 473 if (recv_bytes > recv_size) 474 recv_bytes = recv_size; 475 476 for (i = 0; i < recv_bytes; i += 4) 477 unpack_aux(I915_READ(ch_data + i), 478 recv + i, recv_bytes - i); 479 480 return recv_bytes; 481 } 482 483 /* Write data to the aux channel in native mode */ 484 static int 485 intel_dp_aux_native_write(struct intel_dp *intel_dp, 486 uint16_t address, uint8_t *send, int send_bytes) 487 { 488 int ret; 489 uint8_t msg[20]; 490 int msg_bytes; 491 uint8_t ack; 492 493 intel_dp_check_edp(intel_dp); 494 if (send_bytes > 16) 495 return -1; 496 msg[0] = AUX_NATIVE_WRITE << 4; 497 msg[1] = address >> 8; 498 msg[2] = address & 0xff; 499 msg[3] = send_bytes - 1; 500 memcpy(&msg[4], send, send_bytes); 501 msg_bytes = send_bytes + 4; 502 for (;;) { 503 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); 504 if (ret < 0) 505 return ret; 506 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) 507 break; 508 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 509 udelay(100); 510 else 511 return -EIO; 512 } 513 return send_bytes; 514 } 515 516 /* Write a single byte to the aux channel in native mode */ 517 static int 518 intel_dp_aux_native_write_1(struct intel_dp *intel_dp, 519 uint16_t address, uint8_t byte) 520 { 521 return intel_dp_aux_native_write(intel_dp, address, &byte, 1); 522 } 523 524 /* read bytes from a native aux channel */ 525 static int 526 intel_dp_aux_native_read(struct intel_dp *intel_dp, 527 uint16_t address, uint8_t *recv, int recv_bytes) 528 { 529 uint8_t msg[4]; 530 int msg_bytes; 531 uint8_t reply[20]; 532 int reply_bytes; 533 uint8_t ack; 534 int ret; 535 536 intel_dp_check_edp(intel_dp); 537 msg[0] = AUX_NATIVE_READ << 4; 538 msg[1] = address >> 8; 539 msg[2] = address & 0xff; 540 msg[3] = recv_bytes - 1; 541 542 msg_bytes = 4; 543 reply_bytes = recv_bytes + 1; 544 545 for (;;) { 546 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, 547 reply, reply_bytes); 548 if (ret == 0) 549 return -EPROTO; 550 if (ret < 0) 551 return ret; 552 ack = reply[0]; 553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { 554 memcpy(recv, reply + 1, ret - 1); 555 return ret - 1; 556 } 557 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) 558 udelay(100); 559 else 560 return -EIO; 561 } 562 } 563 564 static int 565 intel_dp_i2c_aux_ch(device_t idev, int mode, uint8_t write_byte, 566 uint8_t *read_byte) 567 { 568 struct iic_dp_aux_data *data; 569 struct intel_dp *intel_dp; 570 uint16_t address; 571 uint8_t msg[5]; 572 uint8_t reply[2]; 573 unsigned retry; 574 int msg_bytes; 575 int reply_bytes; 576 int ret; 577 578 data = device_get_softc(idev); 579 intel_dp = data->priv; 580 address = data->address; 581 582 intel_dp_check_edp(intel_dp); 583 /* Set up the command byte */ 584 if (mode & MODE_I2C_READ) 585 msg[0] = AUX_I2C_READ << 4; 586 else 587 msg[0] = AUX_I2C_WRITE << 4; 588 589 if (!(mode & MODE_I2C_STOP)) 590 msg[0] |= AUX_I2C_MOT << 4; 591 592 msg[1] = address >> 8; 593 msg[2] = address; 594 595 switch (mode) { 596 case MODE_I2C_WRITE: 597 msg[3] = 0; 598 msg[4] = write_byte; 599 msg_bytes = 5; 600 reply_bytes = 1; 601 break; 602 case MODE_I2C_READ: 603 msg[3] = 0; 604 msg_bytes = 4; 605 reply_bytes = 2; 606 break; 607 default: 608 msg_bytes = 3; 609 reply_bytes = 1; 610 break; 611 } 612 613 for (retry = 0; retry < 5; retry++) { 614 ret = intel_dp_aux_ch(intel_dp, 615 msg, msg_bytes, 616 reply, reply_bytes); 617 if (ret < 0) { 618 DRM_DEBUG_KMS("aux_ch failed %d\n", ret); 619 return ret; 620 } 621 622 switch (reply[0] & AUX_NATIVE_REPLY_MASK) { 623 case AUX_NATIVE_REPLY_ACK: 624 /* I2C-over-AUX Reply field is only valid 625 * when paired with AUX ACK. 626 */ 627 break; 628 case AUX_NATIVE_REPLY_NACK: 629 DRM_DEBUG_KMS("aux_ch native nack\n"); 630 return -EREMOTEIO; 631 case AUX_NATIVE_REPLY_DEFER: 632 udelay(100); 633 continue; 634 default: 635 DRM_ERROR("aux_ch invalid native reply 0x%02x\n", 636 reply[0]); 637 return -EREMOTEIO; 638 } 639 640 switch (reply[0] & AUX_I2C_REPLY_MASK) { 641 case AUX_I2C_REPLY_ACK: 642 if (mode == MODE_I2C_READ) { 643 *read_byte = reply[1]; 644 } 645 return (0/*reply_bytes - 1*/); 646 case AUX_I2C_REPLY_NACK: 647 DRM_DEBUG_KMS("aux_i2c nack\n"); 648 return -EREMOTEIO; 649 case AUX_I2C_REPLY_DEFER: 650 DRM_DEBUG_KMS("aux_i2c defer\n"); 651 udelay(100); 652 break; 653 default: 654 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); 655 return -EREMOTEIO; 656 } 657 } 658 659 DRM_ERROR("too many retries, giving up\n"); 660 return -EREMOTEIO; 661 } 662 663 static int 664 intel_dp_i2c_init(struct intel_dp *intel_dp, 665 struct intel_connector *intel_connector, const char *name) 666 { 667 int ret; 668 669 DRM_DEBUG_KMS("i2c_init %s\n", name); 670 671 ironlake_edp_panel_vdd_on(intel_dp); 672 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name, 673 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus, 674 &intel_dp->adapter); 675 ironlake_edp_panel_vdd_off(intel_dp, false); 676 return (ret); 677 } 678 679 bool 680 intel_dp_mode_fixup(struct drm_encoder *encoder, 681 const struct drm_display_mode *mode, 682 struct drm_display_mode *adjusted_mode) 683 { 684 struct drm_device *dev = encoder->dev; 685 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 686 struct intel_connector *intel_connector = intel_dp->attached_connector; 687 int lane_count, clock; 688 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); 689 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; 690 int bpp, mode_rate; 691 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; 692 693 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 694 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 695 adjusted_mode); 696 intel_pch_panel_fitting(dev, 697 intel_connector->panel.fitting_mode, 698 mode, adjusted_mode); 699 } 700 701 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 702 return false; 703 704 DRM_DEBUG_KMS("DP link computation with max lane count %i " 705 "max bw %02x pixel clock %iKHz\n", 706 max_lane_count, bws[max_clock], adjusted_mode->clock); 707 708 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) 709 return false; 710 711 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; 712 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); 713 714 for (clock = 0; clock <= max_clock; clock++) { 715 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { 716 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); 717 718 if (mode_rate <= link_avail) { 719 intel_dp->link_bw = bws[clock]; 720 intel_dp->lane_count = lane_count; 721 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); 722 DRM_DEBUG_KMS("DP link bw %02x lane " 723 "count %d clock %d bpp %d\n", 724 intel_dp->link_bw, intel_dp->lane_count, 725 adjusted_mode->clock, bpp); 726 DRM_DEBUG_KMS("DP link bw required %i available %i\n", 727 mode_rate, link_avail); 728 return true; 729 } 730 } 731 } 732 733 return false; 734 } 735 736 struct intel_dp_m_n { 737 uint32_t tu; 738 uint32_t gmch_m; 739 uint32_t gmch_n; 740 uint32_t link_m; 741 uint32_t link_n; 742 }; 743 744 static void 745 intel_reduce_ratio(uint32_t *num, uint32_t *den) 746 { 747 while (*num > 0xffffff || *den > 0xffffff) { 748 *num >>= 1; 749 *den >>= 1; 750 } 751 } 752 753 static void 754 intel_dp_compute_m_n(int bpp, 755 int nlanes, 756 int pixel_clock, 757 int link_clock, 758 struct intel_dp_m_n *m_n) 759 { 760 m_n->tu = 64; 761 m_n->gmch_m = (pixel_clock * bpp) >> 3; 762 m_n->gmch_n = link_clock * nlanes; 763 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 764 m_n->link_m = pixel_clock; 765 m_n->link_n = link_clock; 766 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 767 } 768 769 void 770 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, 771 struct drm_display_mode *adjusted_mode) 772 { 773 struct drm_device *dev = crtc->dev; 774 struct intel_encoder *intel_encoder; 775 struct intel_dp *intel_dp; 776 struct drm_i915_private *dev_priv = dev->dev_private; 777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 778 int lane_count = 4; 779 struct intel_dp_m_n m_n; 780 int pipe = intel_crtc->pipe; 781 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 782 int target_clock; 783 784 /* 785 * Find the lane count in the intel_encoder private 786 */ 787 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 788 intel_dp = enc_to_intel_dp(&intel_encoder->base); 789 790 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 791 intel_encoder->type == INTEL_OUTPUT_EDP) 792 { 793 lane_count = intel_dp->lane_count; 794 break; 795 } 796 } 797 798 target_clock = mode->clock; 799 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 800 if (intel_encoder->type == INTEL_OUTPUT_EDP) { 801 target_clock = intel_edp_target_clock(intel_encoder, 802 mode); 803 break; 804 } 805 } 806 807 /* 808 * Compute the GMCH and Link ratios. The '3' here is 809 * the number of bytes_per_pixel post-LUT, which we always 810 * set up for 8-bits of R/G/B, or 3 bytes total. 811 */ 812 intel_dp_compute_m_n(intel_crtc->bpp, lane_count, 813 target_clock, adjusted_mode->clock, &m_n); 814 815 if (IS_HASWELL(dev)) { 816 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), 817 TU_SIZE(m_n.tu) | m_n.gmch_m); 818 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); 819 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); 820 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); 821 } else if (HAS_PCH_SPLIT(dev)) { 822 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); 823 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); 824 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); 825 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); 826 } else if (IS_VALLEYVIEW(dev)) { 827 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); 828 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); 829 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); 830 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); 831 } else { 832 I915_WRITE(PIPE_GMCH_DATA_M(pipe), 833 TU_SIZE(m_n.tu) | m_n.gmch_m); 834 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); 835 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); 836 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); 837 } 838 } 839 840 void intel_dp_init_link_config(struct intel_dp *intel_dp) 841 { 842 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 843 intel_dp->link_configuration[0] = intel_dp->link_bw; 844 intel_dp->link_configuration[1] = intel_dp->lane_count; 845 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; 846 /* 847 * Check for DPCD version > 1.1 and enhanced framing support 848 */ 849 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 850 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { 851 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 852 } 853 } 854 855 static void 856 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, 857 struct drm_display_mode *adjusted_mode) 858 { 859 struct drm_device *dev = encoder->dev; 860 struct drm_i915_private *dev_priv = dev->dev_private; 861 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 862 struct drm_crtc *crtc = encoder->crtc; 863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 864 865 /* 866 * There are four kinds of DP registers: 867 * 868 * IBX PCH 869 * SNB CPU 870 * IVB CPU 871 * CPT PCH 872 * 873 * IBX PCH and CPU are the same for almost everything, 874 * except that the CPU DP PLL is configured in this 875 * register 876 * 877 * CPT PCH is quite different, having many bits moved 878 * to the TRANS_DP_CTL register instead. That 879 * configuration happens (oddly) in ironlake_pch_enable 880 */ 881 882 /* Preserve the BIOS-computed detected bit. This is 883 * supposed to be read-only. 884 */ 885 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 886 887 /* Handle DP bits in common between all three register formats */ 888 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 889 890 switch (intel_dp->lane_count) { 891 case 1: 892 intel_dp->DP |= DP_PORT_WIDTH_1; 893 break; 894 case 2: 895 intel_dp->DP |= DP_PORT_WIDTH_2; 896 break; 897 case 4: 898 intel_dp->DP |= DP_PORT_WIDTH_4; 899 break; 900 } 901 if (intel_dp->has_audio) { 902 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 903 pipe_name(intel_crtc->pipe)); 904 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 905 intel_write_eld(encoder, adjusted_mode); 906 } 907 908 intel_dp_init_link_config(intel_dp); 909 910 /* Split out the IBX/CPU vs CPT settings */ 911 912 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { 913 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 914 intel_dp->DP |= DP_SYNC_HS_HIGH; 915 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 916 intel_dp->DP |= DP_SYNC_VS_HIGH; 917 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 918 919 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 920 intel_dp->DP |= DP_ENHANCED_FRAMING; 921 922 intel_dp->DP |= intel_crtc->pipe << 29; 923 924 /* don't miss out required setting for eDP */ 925 if (adjusted_mode->clock < 200000) 926 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 927 else 928 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 929 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 930 intel_dp->DP |= intel_dp->color_range; 931 932 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 933 intel_dp->DP |= DP_SYNC_HS_HIGH; 934 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 935 intel_dp->DP |= DP_SYNC_VS_HIGH; 936 intel_dp->DP |= DP_LINK_TRAIN_OFF; 937 938 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) 939 intel_dp->DP |= DP_ENHANCED_FRAMING; 940 941 if (intel_crtc->pipe == 1) 942 intel_dp->DP |= DP_PIPEB_SELECT; 943 944 if (is_cpu_edp(intel_dp)) { 945 /* don't miss out required setting for eDP */ 946 if (adjusted_mode->clock < 200000) 947 intel_dp->DP |= DP_PLL_FREQ_160MHZ; 948 else 949 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 950 } 951 } else { 952 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 953 } 954 } 955 956 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 957 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 958 959 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 960 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 961 962 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 963 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 964 965 static void ironlake_wait_panel_status(struct intel_dp *intel_dp, 966 u32 mask, 967 u32 value) 968 { 969 struct drm_device *dev = intel_dp_to_dev(intel_dp); 970 struct drm_i915_private *dev_priv = dev->dev_private; 971 972 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 973 mask, value, 974 I915_READ(PCH_PP_STATUS), 975 I915_READ(PCH_PP_CONTROL)); 976 977 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { 978 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 979 I915_READ(PCH_PP_STATUS), 980 I915_READ(PCH_PP_CONTROL)); 981 } 982 } 983 984 static void ironlake_wait_panel_on(struct intel_dp *intel_dp) 985 { 986 DRM_DEBUG_KMS("Wait for panel power on\n"); 987 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 988 } 989 990 static void ironlake_wait_panel_off(struct intel_dp *intel_dp) 991 { 992 DRM_DEBUG_KMS("Wait for panel power off time\n"); 993 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 994 } 995 996 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) 997 { 998 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 999 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 1000 } 1001 1002 1003 /* Read the current pp_control value, unlocking the register if it 1004 * is locked 1005 */ 1006 1007 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) 1008 { 1009 u32 control = I915_READ(PCH_PP_CONTROL); 1010 1011 control &= ~PANEL_UNLOCK_MASK; 1012 control |= PANEL_UNLOCK_REGS; 1013 return control; 1014 } 1015 1016 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) 1017 { 1018 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1019 struct drm_i915_private *dev_priv = dev->dev_private; 1020 u32 pp; 1021 1022 if (!is_edp(intel_dp)) 1023 return; 1024 DRM_DEBUG_KMS("Turn eDP VDD on\n"); 1025 1026 WARN(intel_dp->want_panel_vdd, 1027 "eDP VDD already requested on\n"); 1028 1029 intel_dp->want_panel_vdd = true; 1030 1031 if (ironlake_edp_have_panel_vdd(intel_dp)) { 1032 DRM_DEBUG_KMS("eDP VDD already on\n"); 1033 return; 1034 } 1035 1036 if (!ironlake_edp_have_panel_power(intel_dp)) 1037 ironlake_wait_panel_power_cycle(intel_dp); 1038 1039 pp = ironlake_get_pp_control(dev_priv); 1040 pp |= EDP_FORCE_VDD; 1041 I915_WRITE(PCH_PP_CONTROL, pp); 1042 POSTING_READ(PCH_PP_CONTROL); 1043 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1044 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1045 1046 /* 1047 * If the panel wasn't on, delay before accessing aux channel 1048 */ 1049 if (!ironlake_edp_have_panel_power(intel_dp)) { 1050 DRM_DEBUG_KMS("eDP was not running\n"); 1051 msleep(intel_dp->panel_power_up_delay); 1052 } 1053 } 1054 1055 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) 1056 { 1057 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1058 struct drm_i915_private *dev_priv = dev->dev_private; 1059 u32 pp; 1060 1061 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { 1062 pp = ironlake_get_pp_control(dev_priv); 1063 pp &= ~EDP_FORCE_VDD; 1064 I915_WRITE(PCH_PP_CONTROL, pp); 1065 POSTING_READ(PCH_PP_CONTROL); 1066 1067 /* Make sure sequencer is idle before allowing subsequent activity */ 1068 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", 1069 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); 1070 1071 DELAY(intel_dp->panel_power_down_delay * 1000); 1072 } 1073 } 1074 1075 static void ironlake_panel_vdd_work(struct work_struct *__work) 1076 { 1077 struct intel_dp *intel_dp = container_of(to_delayed_work(__work), 1078 struct intel_dp, panel_vdd_work); 1079 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1080 1081 lockmgr(&dev->mode_config.mutex, LK_EXCLUSIVE); 1082 ironlake_panel_vdd_off_sync(intel_dp); 1083 lockmgr(&dev->mode_config.mutex, LK_RELEASE); 1084 } 1085 1086 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 1087 { 1088 if (!is_edp(intel_dp)) 1089 return; 1090 1091 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); 1092 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); 1093 1094 intel_dp->want_panel_vdd = false; 1095 1096 if (sync) { 1097 ironlake_panel_vdd_off_sync(intel_dp); 1098 } else { 1099 /* 1100 * Queue the timer to fire a long 1101 * time from now (relative to the power down delay) 1102 * to keep the panel power up across a sequence of operations 1103 */ 1104 schedule_delayed_work(&intel_dp->panel_vdd_work, 1105 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); 1106 } 1107 } 1108 1109 void ironlake_edp_panel_on(struct intel_dp *intel_dp) 1110 { 1111 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1112 struct drm_i915_private *dev_priv = dev->dev_private; 1113 u32 pp; 1114 1115 if (!is_edp(intel_dp)) 1116 return; 1117 1118 DRM_DEBUG_KMS("Turn eDP power on\n"); 1119 1120 if (ironlake_edp_have_panel_power(intel_dp)) { 1121 DRM_DEBUG_KMS("eDP power already on\n"); 1122 return; 1123 } 1124 1125 ironlake_wait_panel_power_cycle(intel_dp); 1126 1127 pp = ironlake_get_pp_control(dev_priv); 1128 if (IS_GEN5(dev)) { 1129 /* ILK workaround: disable reset around power sequence */ 1130 pp &= ~PANEL_POWER_RESET; 1131 I915_WRITE(PCH_PP_CONTROL, pp); 1132 POSTING_READ(PCH_PP_CONTROL); 1133 } 1134 1135 pp |= POWER_TARGET_ON; 1136 if (!IS_GEN5(dev)) 1137 pp |= PANEL_POWER_RESET; 1138 1139 I915_WRITE(PCH_PP_CONTROL, pp); 1140 POSTING_READ(PCH_PP_CONTROL); 1141 1142 ironlake_wait_panel_on(intel_dp); 1143 1144 if (IS_GEN5(dev)) { 1145 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 1146 I915_WRITE(PCH_PP_CONTROL, pp); 1147 POSTING_READ(PCH_PP_CONTROL); 1148 } 1149 } 1150 1151 void ironlake_edp_panel_off(struct intel_dp *intel_dp) 1152 { 1153 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1154 struct drm_i915_private *dev_priv = dev->dev_private; 1155 u32 pp; 1156 1157 if (!is_edp(intel_dp)) 1158 return; 1159 1160 DRM_DEBUG_KMS("Turn eDP power off\n"); 1161 1162 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1163 1164 pp = ironlake_get_pp_control(dev_priv); 1165 /* We need to switch off panel power _and_ force vdd, for otherwise some 1166 * panels get very unhappy and cease to work. */ 1167 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1168 I915_WRITE(PCH_PP_CONTROL, pp); 1169 POSTING_READ(PCH_PP_CONTROL); 1170 1171 intel_dp->want_panel_vdd = false; 1172 1173 ironlake_wait_panel_off(intel_dp); 1174 } 1175 1176 void ironlake_edp_backlight_on(struct intel_dp *intel_dp) 1177 { 1178 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1179 struct drm_device *dev = intel_dig_port->base.base.dev; 1180 struct drm_i915_private *dev_priv = dev->dev_private; 1181 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; 1182 u32 pp; 1183 1184 if (!is_edp(intel_dp)) 1185 return; 1186 1187 DRM_DEBUG_KMS("\n"); 1188 /* 1189 * If we enable the backlight right away following a panel power 1190 * on, we may see slight flicker as the panel syncs with the eDP 1191 * link. So delay a bit to make sure the image is solid before 1192 * allowing it to appear. 1193 */ 1194 DELAY(intel_dp->backlight_on_delay * 1000); 1195 pp = ironlake_get_pp_control(dev_priv); 1196 pp |= EDP_BLC_ENABLE; 1197 I915_WRITE(PCH_PP_CONTROL, pp); 1198 POSTING_READ(PCH_PP_CONTROL); 1199 1200 intel_panel_enable_backlight(dev, pipe); 1201 } 1202 1203 void ironlake_edp_backlight_off(struct intel_dp *intel_dp) 1204 { 1205 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1206 struct drm_i915_private *dev_priv = dev->dev_private; 1207 u32 pp; 1208 1209 if (!is_edp(intel_dp)) 1210 return; 1211 1212 intel_panel_disable_backlight(dev); 1213 1214 DRM_DEBUG_KMS("\n"); 1215 pp = ironlake_get_pp_control(dev_priv); 1216 pp &= ~EDP_BLC_ENABLE; 1217 I915_WRITE(PCH_PP_CONTROL, pp); 1218 POSTING_READ(PCH_PP_CONTROL); 1219 DELAY(intel_dp->backlight_off_delay * 1000); 1220 } 1221 1222 static void ironlake_edp_pll_on(struct intel_dp *intel_dp) 1223 { 1224 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1225 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1226 struct drm_device *dev = crtc->dev; 1227 struct drm_i915_private *dev_priv = dev->dev_private; 1228 u32 dpa_ctl; 1229 1230 assert_pipe_disabled(dev_priv, 1231 to_intel_crtc(crtc)->pipe); 1232 1233 DRM_DEBUG_KMS("\n"); 1234 dpa_ctl = I915_READ(DP_A); 1235 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); 1236 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1237 1238 /* We don't adjust intel_dp->DP while tearing down the link, to 1239 * facilitate link retraining (e.g. after hotplug). Hence clear all 1240 * enable bits here to ensure that we don't enable too much. */ 1241 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 1242 intel_dp->DP |= DP_PLL_ENABLE; 1243 I915_WRITE(DP_A, intel_dp->DP); 1244 POSTING_READ(DP_A); 1245 udelay(200); 1246 } 1247 1248 static void ironlake_edp_pll_off(struct intel_dp *intel_dp) 1249 { 1250 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1251 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 1252 struct drm_device *dev = crtc->dev; 1253 struct drm_i915_private *dev_priv = dev->dev_private; 1254 u32 dpa_ctl; 1255 1256 assert_pipe_disabled(dev_priv, 1257 to_intel_crtc(crtc)->pipe); 1258 1259 dpa_ctl = I915_READ(DP_A); 1260 WARN((dpa_ctl & DP_PLL_ENABLE) == 0, 1261 "dp pll off, should be on\n"); 1262 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); 1263 1264 /* We can't rely on the value tracked for the DP register in 1265 * intel_dp->DP because link_down must not change that (otherwise link 1266 * re-training will fail. */ 1267 dpa_ctl &= ~DP_PLL_ENABLE; 1268 I915_WRITE(DP_A, dpa_ctl); 1269 POSTING_READ(DP_A); 1270 udelay(200); 1271 } 1272 1273 /* If the sink supports it, try to set the power state appropriately */ 1274 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 1275 { 1276 int ret, i; 1277 1278 /* Should have a valid DPCD by this point */ 1279 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1280 return; 1281 1282 if (mode != DRM_MODE_DPMS_ON) { 1283 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, 1284 DP_SET_POWER_D3); 1285 if (ret != 1) 1286 DRM_DEBUG("failed to write sink power state\n"); 1287 } else { 1288 /* 1289 * When turning on, we need to retry for 1ms to give the sink 1290 * time to wake up. 1291 */ 1292 for (i = 0; i < 3; i++) { 1293 ret = intel_dp_aux_native_write_1(intel_dp, 1294 DP_SET_POWER, 1295 DP_SET_POWER_D0); 1296 if (ret == 1) 1297 break; 1298 DELAY(1000); 1299 } 1300 } 1301 } 1302 1303 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 1304 enum i915_pipe *pipe) 1305 { 1306 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1307 struct drm_device *dev = encoder->base.dev; 1308 struct drm_i915_private *dev_priv = dev->dev_private; 1309 u32 tmp = I915_READ(intel_dp->output_reg); 1310 1311 if (!(tmp & DP_PORT_EN)) 1312 return false; 1313 1314 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { 1315 *pipe = PORT_TO_PIPE_CPT(tmp); 1316 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { 1317 *pipe = PORT_TO_PIPE(tmp); 1318 } else { 1319 u32 trans_sel; 1320 u32 trans_dp; 1321 int i; 1322 1323 switch (intel_dp->output_reg) { 1324 case PCH_DP_B: 1325 trans_sel = TRANS_DP_PORT_SEL_B; 1326 break; 1327 case PCH_DP_C: 1328 trans_sel = TRANS_DP_PORT_SEL_C; 1329 break; 1330 case PCH_DP_D: 1331 trans_sel = TRANS_DP_PORT_SEL_D; 1332 break; 1333 default: 1334 return true; 1335 } 1336 1337 for_each_pipe(i) { 1338 trans_dp = I915_READ(TRANS_DP_CTL(i)); 1339 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { 1340 *pipe = i; 1341 return true; 1342 } 1343 } 1344 1345 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", 1346 intel_dp->output_reg); 1347 } 1348 1349 return true; 1350 } 1351 1352 static void intel_disable_dp(struct intel_encoder *encoder) 1353 { 1354 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1355 1356 /* Make sure the panel is off before trying to change the mode. But also 1357 * ensure that we have vdd while we switch off the panel. */ 1358 ironlake_edp_panel_vdd_on(intel_dp); 1359 ironlake_edp_backlight_off(intel_dp); 1360 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1361 ironlake_edp_panel_off(intel_dp); 1362 1363 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ 1364 if (!is_cpu_edp(intel_dp)) 1365 intel_dp_link_down(intel_dp); 1366 } 1367 1368 static void intel_post_disable_dp(struct intel_encoder *encoder) 1369 { 1370 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1371 1372 if (is_cpu_edp(intel_dp)) { 1373 intel_dp_link_down(intel_dp); 1374 ironlake_edp_pll_off(intel_dp); 1375 } 1376 } 1377 1378 static void intel_enable_dp(struct intel_encoder *encoder) 1379 { 1380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1381 struct drm_device *dev = encoder->base.dev; 1382 struct drm_i915_private *dev_priv = dev->dev_private; 1383 uint32_t dp_reg = I915_READ(intel_dp->output_reg); 1384 1385 if (WARN_ON(dp_reg & DP_PORT_EN)) 1386 return; 1387 1388 ironlake_edp_panel_vdd_on(intel_dp); 1389 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1390 intel_dp_start_link_train(intel_dp); 1391 ironlake_edp_panel_on(intel_dp); 1392 ironlake_edp_panel_vdd_off(intel_dp, true); 1393 intel_dp_complete_link_train(intel_dp); 1394 ironlake_edp_backlight_on(intel_dp); 1395 } 1396 1397 static void intel_pre_enable_dp(struct intel_encoder *encoder) 1398 { 1399 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 1400 1401 if (is_cpu_edp(intel_dp)) 1402 ironlake_edp_pll_on(intel_dp); 1403 } 1404 1405 /* 1406 * Native read with retry for link status and receiver capability reads for 1407 * cases where the sink may still be asleep. 1408 */ 1409 static bool 1410 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, 1411 uint8_t *recv, int recv_bytes) 1412 { 1413 int ret, i; 1414 1415 /* 1416 * Sinks are *supposed* to come up within 1ms from an off state, 1417 * but we're also supposed to retry 3 times per the spec. 1418 */ 1419 for (i = 0; i < 3; i++) { 1420 ret = intel_dp_aux_native_read(intel_dp, address, recv, 1421 recv_bytes); 1422 if (ret == recv_bytes) 1423 return true; 1424 DELAY(1000); 1425 } 1426 1427 return false; 1428 } 1429 1430 /* 1431 * Fetch AUX CH registers 0x202 - 0x207 which contain 1432 * link status information 1433 */ 1434 static bool 1435 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1436 { 1437 return intel_dp_aux_native_read_retry(intel_dp, 1438 DP_LANE0_1_STATUS, 1439 link_status, 1440 DP_LINK_STATUS_SIZE); 1441 } 1442 1443 #if 0 1444 static char *voltage_names[] = { 1445 "0.4V", "0.6V", "0.8V", "1.2V" 1446 }; 1447 static char *pre_emph_names[] = { 1448 "0dB", "3.5dB", "6dB", "9.5dB" 1449 }; 1450 static char *link_train_names[] = { 1451 "pattern 1", "pattern 2", "idle", "off" 1452 }; 1453 #endif 1454 1455 /* 1456 * These are source-specific values; current Intel hardware supports 1457 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB 1458 */ 1459 1460 static uint8_t 1461 intel_dp_voltage_max(struct intel_dp *intel_dp) 1462 { 1463 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1464 1465 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) 1466 return DP_TRAIN_VOLTAGE_SWING_800; 1467 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) 1468 return DP_TRAIN_VOLTAGE_SWING_1200; 1469 else 1470 return DP_TRAIN_VOLTAGE_SWING_800; 1471 } 1472 1473 static uint8_t 1474 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) 1475 { 1476 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1477 1478 if (IS_HASWELL(dev)) { 1479 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1480 case DP_TRAIN_VOLTAGE_SWING_400: 1481 return DP_TRAIN_PRE_EMPHASIS_9_5; 1482 case DP_TRAIN_VOLTAGE_SWING_600: 1483 return DP_TRAIN_PRE_EMPHASIS_6; 1484 case DP_TRAIN_VOLTAGE_SWING_800: 1485 return DP_TRAIN_PRE_EMPHASIS_3_5; 1486 case DP_TRAIN_VOLTAGE_SWING_1200: 1487 default: 1488 return DP_TRAIN_PRE_EMPHASIS_0; 1489 } 1490 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { 1491 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1492 case DP_TRAIN_VOLTAGE_SWING_400: 1493 return DP_TRAIN_PRE_EMPHASIS_6; 1494 case DP_TRAIN_VOLTAGE_SWING_600: 1495 case DP_TRAIN_VOLTAGE_SWING_800: 1496 return DP_TRAIN_PRE_EMPHASIS_3_5; 1497 default: 1498 return DP_TRAIN_PRE_EMPHASIS_0; 1499 } 1500 } else { 1501 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 1502 case DP_TRAIN_VOLTAGE_SWING_400: 1503 return DP_TRAIN_PRE_EMPHASIS_6; 1504 case DP_TRAIN_VOLTAGE_SWING_600: 1505 return DP_TRAIN_PRE_EMPHASIS_6; 1506 case DP_TRAIN_VOLTAGE_SWING_800: 1507 return DP_TRAIN_PRE_EMPHASIS_3_5; 1508 case DP_TRAIN_VOLTAGE_SWING_1200: 1509 default: 1510 return DP_TRAIN_PRE_EMPHASIS_0; 1511 } 1512 } 1513 } 1514 1515 static void 1516 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) 1517 { 1518 uint8_t v = 0; 1519 uint8_t p = 0; 1520 int lane; 1521 uint8_t voltage_max; 1522 uint8_t preemph_max; 1523 1524 for (lane = 0; lane < intel_dp->lane_count; lane++) { 1525 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 1526 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 1527 1528 if (this_v > v) 1529 v = this_v; 1530 if (this_p > p) 1531 p = this_p; 1532 } 1533 1534 voltage_max = intel_dp_voltage_max(intel_dp); 1535 if (v >= voltage_max) 1536 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 1537 1538 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); 1539 if (p >= preemph_max) 1540 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 1541 1542 for (lane = 0; lane < 4; lane++) 1543 intel_dp->train_set[lane] = v | p; 1544 } 1545 1546 static uint32_t 1547 intel_dp_signal_levels(uint8_t train_set) 1548 { 1549 uint32_t signal_levels = 0; 1550 1551 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 1552 case DP_TRAIN_VOLTAGE_SWING_400: 1553 default: 1554 signal_levels |= DP_VOLTAGE_0_4; 1555 break; 1556 case DP_TRAIN_VOLTAGE_SWING_600: 1557 signal_levels |= DP_VOLTAGE_0_6; 1558 break; 1559 case DP_TRAIN_VOLTAGE_SWING_800: 1560 signal_levels |= DP_VOLTAGE_0_8; 1561 break; 1562 case DP_TRAIN_VOLTAGE_SWING_1200: 1563 signal_levels |= DP_VOLTAGE_1_2; 1564 break; 1565 } 1566 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 1567 case DP_TRAIN_PRE_EMPHASIS_0: 1568 default: 1569 signal_levels |= DP_PRE_EMPHASIS_0; 1570 break; 1571 case DP_TRAIN_PRE_EMPHASIS_3_5: 1572 signal_levels |= DP_PRE_EMPHASIS_3_5; 1573 break; 1574 case DP_TRAIN_PRE_EMPHASIS_6: 1575 signal_levels |= DP_PRE_EMPHASIS_6; 1576 break; 1577 case DP_TRAIN_PRE_EMPHASIS_9_5: 1578 signal_levels |= DP_PRE_EMPHASIS_9_5; 1579 break; 1580 } 1581 return signal_levels; 1582 } 1583 1584 /* Gen6's DP voltage swing and pre-emphasis control */ 1585 static uint32_t 1586 intel_gen6_edp_signal_levels(uint8_t train_set) 1587 { 1588 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1589 DP_TRAIN_PRE_EMPHASIS_MASK); 1590 switch (signal_levels) { 1591 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1592 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1593 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1594 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1595 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 1596 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1597 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1598 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 1599 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1600 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1601 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 1602 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1603 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: 1604 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 1605 default: 1606 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1607 "0x%x\n", signal_levels); 1608 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 1609 } 1610 } 1611 1612 /* Gen7's DP voltage swing and pre-emphasis control */ 1613 static uint32_t 1614 intel_gen7_edp_signal_levels(uint8_t train_set) 1615 { 1616 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1617 DP_TRAIN_PRE_EMPHASIS_MASK); 1618 switch (signal_levels) { 1619 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1620 return EDP_LINK_TRAIN_400MV_0DB_IVB; 1621 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1622 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 1623 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1624 return EDP_LINK_TRAIN_400MV_6DB_IVB; 1625 1626 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1627 return EDP_LINK_TRAIN_600MV_0DB_IVB; 1628 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1629 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 1630 1631 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1632 return EDP_LINK_TRAIN_800MV_0DB_IVB; 1633 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1634 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 1635 1636 default: 1637 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1638 "0x%x\n", signal_levels); 1639 return EDP_LINK_TRAIN_500MV_0DB_IVB; 1640 } 1641 } 1642 1643 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ 1644 static uint32_t 1645 intel_dp_signal_levels_hsw(uint8_t train_set) 1646 { 1647 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 1648 DP_TRAIN_PRE_EMPHASIS_MASK); 1649 switch (signal_levels) { 1650 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: 1651 return DDI_BUF_EMP_400MV_0DB_HSW; 1652 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: 1653 return DDI_BUF_EMP_400MV_3_5DB_HSW; 1654 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: 1655 return DDI_BUF_EMP_400MV_6DB_HSW; 1656 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: 1657 return DDI_BUF_EMP_400MV_9_5DB_HSW; 1658 1659 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: 1660 return DDI_BUF_EMP_600MV_0DB_HSW; 1661 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: 1662 return DDI_BUF_EMP_600MV_3_5DB_HSW; 1663 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: 1664 return DDI_BUF_EMP_600MV_6DB_HSW; 1665 1666 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: 1667 return DDI_BUF_EMP_800MV_0DB_HSW; 1668 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: 1669 return DDI_BUF_EMP_800MV_3_5DB_HSW; 1670 default: 1671 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 1672 "0x%x\n", signal_levels); 1673 return DDI_BUF_EMP_400MV_0DB_HSW; 1674 } 1675 } 1676 1677 static bool 1678 intel_dp_set_link_train(struct intel_dp *intel_dp, 1679 uint32_t dp_reg_value, 1680 uint8_t dp_train_pat) 1681 { 1682 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1683 struct drm_device *dev = intel_dig_port->base.base.dev; 1684 struct drm_i915_private *dev_priv = dev->dev_private; 1685 enum port port = intel_dig_port->port; 1686 int ret; 1687 uint32_t temp; 1688 1689 if (IS_HASWELL(dev)) { 1690 temp = I915_READ(DP_TP_CTL(port)); 1691 1692 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 1693 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 1694 else 1695 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 1696 1697 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 1698 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 1699 case DP_TRAINING_PATTERN_DISABLE: 1700 temp |= DP_TP_CTL_LINK_TRAIN_IDLE; 1701 I915_WRITE(DP_TP_CTL(port), temp); 1702 1703 if (wait_for((I915_READ(DP_TP_STATUS(port)) & 1704 DP_TP_STATUS_IDLE_DONE), 1)) 1705 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 1706 1707 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 1708 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 1709 1710 break; 1711 case DP_TRAINING_PATTERN_1: 1712 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 1713 break; 1714 case DP_TRAINING_PATTERN_2: 1715 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 1716 break; 1717 case DP_TRAINING_PATTERN_3: 1718 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 1719 break; 1720 } 1721 I915_WRITE(DP_TP_CTL(port), temp); 1722 1723 } else if (HAS_PCH_CPT(dev) && 1724 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { 1725 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; 1726 1727 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 1728 case DP_TRAINING_PATTERN_DISABLE: 1729 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT; 1730 break; 1731 case DP_TRAINING_PATTERN_1: 1732 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT; 1733 break; 1734 case DP_TRAINING_PATTERN_2: 1735 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; 1736 break; 1737 case DP_TRAINING_PATTERN_3: 1738 DRM_ERROR("DP training pattern 3 not supported\n"); 1739 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; 1740 break; 1741 } 1742 1743 } else { 1744 dp_reg_value &= ~DP_LINK_TRAIN_MASK; 1745 1746 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 1747 case DP_TRAINING_PATTERN_DISABLE: 1748 dp_reg_value |= DP_LINK_TRAIN_OFF; 1749 break; 1750 case DP_TRAINING_PATTERN_1: 1751 dp_reg_value |= DP_LINK_TRAIN_PAT_1; 1752 break; 1753 case DP_TRAINING_PATTERN_2: 1754 dp_reg_value |= DP_LINK_TRAIN_PAT_2; 1755 break; 1756 case DP_TRAINING_PATTERN_3: 1757 DRM_ERROR("DP training pattern 3 not supported\n"); 1758 dp_reg_value |= DP_LINK_TRAIN_PAT_2; 1759 break; 1760 } 1761 } 1762 1763 I915_WRITE(intel_dp->output_reg, dp_reg_value); 1764 POSTING_READ(intel_dp->output_reg); 1765 1766 intel_dp_aux_native_write_1(intel_dp, 1767 DP_TRAINING_PATTERN_SET, 1768 dp_train_pat); 1769 1770 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != 1771 DP_TRAINING_PATTERN_DISABLE) { 1772 ret = intel_dp_aux_native_write(intel_dp, 1773 DP_TRAINING_LANE0_SET, 1774 intel_dp->train_set, 1775 intel_dp->lane_count); 1776 if (ret != intel_dp->lane_count) 1777 return false; 1778 } 1779 1780 return true; 1781 } 1782 1783 /* Enable corresponding port and start training pattern 1 */ 1784 void 1785 intel_dp_start_link_train(struct intel_dp *intel_dp) 1786 { 1787 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; 1788 struct drm_device *dev = encoder->dev; 1789 int i; 1790 uint8_t voltage; 1791 bool clock_recovery = false; 1792 int voltage_tries, loop_tries; 1793 uint32_t DP = intel_dp->DP; 1794 1795 if (IS_HASWELL(dev)) 1796 intel_ddi_prepare_link_retrain(encoder); 1797 1798 /* Write the link configuration data */ 1799 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1800 intel_dp->link_configuration, 1801 DP_LINK_CONFIGURATION_SIZE); 1802 1803 DP |= DP_PORT_EN; 1804 1805 memset(intel_dp->train_set, 0, 4); 1806 voltage = 0xff; 1807 voltage_tries = 0; 1808 loop_tries = 0; 1809 clock_recovery = false; 1810 for (;;) { 1811 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1812 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1813 uint32_t signal_levels; 1814 1815 if (IS_HASWELL(dev)) { 1816 signal_levels = intel_dp_signal_levels_hsw( 1817 intel_dp->train_set[0]); 1818 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; 1819 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { 1820 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); 1821 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; 1822 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1823 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1824 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1825 } else { 1826 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); 1827 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1828 } 1829 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", 1830 signal_levels); 1831 1832 /* Set training pattern 1 */ 1833 if (!intel_dp_set_link_train(intel_dp, DP, 1834 DP_TRAINING_PATTERN_1 | 1835 DP_LINK_SCRAMBLING_DISABLE)) 1836 break; 1837 1838 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 1839 if (!intel_dp_get_link_status(intel_dp, link_status)) { 1840 DRM_ERROR("failed to get link status\n"); 1841 break; 1842 } 1843 1844 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1845 DRM_DEBUG_KMS("clock recovery OK\n"); 1846 clock_recovery = true; 1847 break; 1848 } 1849 1850 /* Check to see if we've tried the max voltage */ 1851 for (i = 0; i < intel_dp->lane_count; i++) 1852 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 1853 break; 1854 if (i == intel_dp->lane_count) { 1855 if (++loop_tries == 5) { 1856 DRM_DEBUG_KMS("too many full retries, give up\n"); 1857 break; 1858 } 1859 memset(intel_dp->train_set, 0, 4); 1860 voltage_tries = 0; 1861 continue; 1862 } 1863 1864 /* Check to see if we've tried the same voltage 5 times */ 1865 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) { 1866 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 1867 voltage_tries = 0; 1868 } else 1869 ++voltage_tries; 1870 1871 /* Compute new intel_dp->train_set as requested by target */ 1872 intel_get_adjust_train(intel_dp, link_status); 1873 } 1874 1875 intel_dp->DP = DP; 1876 } 1877 1878 void 1879 intel_dp_complete_link_train(struct intel_dp *intel_dp) 1880 { 1881 struct drm_device *dev = intel_dp_to_dev(intel_dp); 1882 bool channel_eq = false; 1883 int tries, cr_tries; 1884 uint32_t DP = intel_dp->DP; 1885 1886 /* channel equalization */ 1887 tries = 0; 1888 cr_tries = 0; 1889 channel_eq = false; 1890 for (;;) { 1891 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ 1892 uint32_t signal_levels; 1893 uint8_t link_status[DP_LINK_STATUS_SIZE]; 1894 1895 if (cr_tries > 5) { 1896 DRM_ERROR("failed to train DP, aborting\n"); 1897 intel_dp_link_down(intel_dp); 1898 break; 1899 } 1900 1901 if (IS_HASWELL(dev)) { 1902 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]); 1903 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; 1904 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { 1905 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); 1906 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; 1907 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { 1908 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); 1909 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; 1910 } else { 1911 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); 1912 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; 1913 } 1914 1915 /* channel eq pattern */ 1916 if (!intel_dp_set_link_train(intel_dp, DP, 1917 DP_TRAINING_PATTERN_2 | 1918 DP_LINK_SCRAMBLING_DISABLE)) 1919 break; 1920 1921 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 1922 if (!intel_dp_get_link_status(intel_dp, link_status)) 1923 break; 1924 1925 /* Make sure clock is still ok */ 1926 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { 1927 intel_dp_start_link_train(intel_dp); 1928 cr_tries++; 1929 continue; 1930 } 1931 1932 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 1933 channel_eq = true; 1934 break; 1935 } 1936 1937 /* Try 5 times, then try clock recovery if that fails */ 1938 if (tries > 5) { 1939 intel_dp_link_down(intel_dp); 1940 intel_dp_start_link_train(intel_dp); 1941 tries = 0; 1942 cr_tries++; 1943 continue; 1944 } 1945 1946 /* Compute new intel_dp->train_set as requested by target */ 1947 intel_get_adjust_train(intel_dp, link_status); 1948 ++tries; 1949 } 1950 1951 if (channel_eq) 1952 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n"); 1953 1954 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); 1955 } 1956 1957 static void 1958 intel_dp_link_down(struct intel_dp *intel_dp) 1959 { 1960 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1961 struct drm_device *dev = intel_dig_port->base.base.dev; 1962 struct drm_i915_private *dev_priv = dev->dev_private; 1963 uint32_t DP = intel_dp->DP; 1964 1965 /* 1966 * DDI code has a strict mode set sequence and we should try to respect 1967 * it, otherwise we might hang the machine in many different ways. So we 1968 * really should be disabling the port only on a complete crtc_disable 1969 * sequence. This function is just called under two conditions on DDI 1970 * code: 1971 * - Link train failed while doing crtc_enable, and on this case we 1972 * really should respect the mode set sequence and wait for a 1973 * crtc_disable. 1974 * - Someone turned the monitor off and intel_dp_check_link_status 1975 * called us. We don't need to disable the whole port on this case, so 1976 * when someone turns the monitor on again, 1977 * intel_ddi_prepare_link_retrain will take care of redoing the link 1978 * train. 1979 */ 1980 if (IS_HASWELL(dev)) 1981 return; 1982 1983 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 1984 return; 1985 1986 DRM_DEBUG_KMS("\n"); 1987 1988 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { 1989 DP &= ~DP_LINK_TRAIN_MASK_CPT; 1990 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); 1991 } else { 1992 DP &= ~DP_LINK_TRAIN_MASK; 1993 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); 1994 } 1995 POSTING_READ(intel_dp->output_reg); 1996 1997 msleep(17); 1998 1999 if (HAS_PCH_IBX(dev) && 2000 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { 2001 struct drm_crtc *crtc = intel_dig_port->base.base.crtc; 2002 2003 /* Hardware workaround: leaving our transcoder select 2004 * set to transcoder B while it's off will prevent the 2005 * corresponding HDMI output on transcoder A. 2006 * 2007 * Combine this with another hardware workaround: 2008 * transcoder select bit can only be cleared while the 2009 * port is enabled. 2010 */ 2011 DP &= ~DP_PIPEB_SELECT; 2012 I915_WRITE(intel_dp->output_reg, DP); 2013 2014 /* Changes to enable or select take place the vblank 2015 * after being written. 2016 */ 2017 if (crtc == NULL) { 2018 /* We can arrive here never having been attached 2019 * to a CRTC, for instance, due to inheriting 2020 * random state from the BIOS. 2021 * 2022 * If the pipe is not running, play safe and 2023 * wait for the clocks to stabilise before 2024 * continuing. 2025 */ 2026 POSTING_READ(intel_dp->output_reg); 2027 msleep(50); 2028 } else 2029 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); 2030 } 2031 2032 DP &= ~DP_AUDIO_OUTPUT_ENABLE; 2033 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 2034 POSTING_READ(intel_dp->output_reg); 2035 msleep(intel_dp->panel_power_down_delay); 2036 } 2037 2038 static bool 2039 intel_dp_get_dpcd(struct intel_dp *intel_dp) 2040 { 2041 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, 2042 sizeof(intel_dp->dpcd)) == 0) 2043 return false; /* aux transfer failed */ 2044 2045 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 2046 return false; /* DPCD not present */ 2047 2048 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 2049 DP_DWN_STRM_PORT_PRESENT)) 2050 return true; /* native DP sink */ 2051 2052 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 2053 return true; /* no per-port downstream info */ 2054 2055 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, 2056 intel_dp->downstream_ports, 2057 DP_MAX_DOWNSTREAM_PORTS) == 0) 2058 return false; /* downstream port status fetch failed */ 2059 2060 return true; 2061 } 2062 2063 static void 2064 intel_dp_probe_oui(struct intel_dp *intel_dp) 2065 { 2066 u8 buf[3]; 2067 2068 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 2069 return; 2070 2071 ironlake_edp_panel_vdd_on(intel_dp); 2072 2073 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) 2074 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 2075 buf[0], buf[1], buf[2]); 2076 2077 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) 2078 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 2079 buf[0], buf[1], buf[2]); 2080 2081 ironlake_edp_panel_vdd_off(intel_dp, false); 2082 } 2083 2084 static bool 2085 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2086 { 2087 int ret; 2088 2089 ret = intel_dp_aux_native_read_retry(intel_dp, 2090 DP_DEVICE_SERVICE_IRQ_VECTOR, 2091 sink_irq_vector, 1); 2092 if (!ret) 2093 return false; 2094 2095 return true; 2096 } 2097 2098 static void 2099 intel_dp_handle_test_request(struct intel_dp *intel_dp) 2100 { 2101 /* NAK by default */ 2102 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); 2103 } 2104 2105 /* 2106 * According to DP spec 2107 * 5.1.2: 2108 * 1. Read DPCD 2109 * 2. Configure link according to Receiver Capabilities 2110 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 2111 * 4. Check link status on receipt of hot-plug interrupt 2112 */ 2113 2114 void 2115 intel_dp_check_link_status(struct intel_dp *intel_dp) 2116 { 2117 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; 2118 u8 sink_irq_vector; 2119 u8 link_status[DP_LINK_STATUS_SIZE]; 2120 2121 if (!intel_encoder->connectors_active) 2122 return; 2123 2124 if (WARN_ON(!intel_encoder->base.crtc)) 2125 return; 2126 2127 /* Try to read receiver status if the link appears to be up */ 2128 if (!intel_dp_get_link_status(intel_dp, link_status)) { 2129 intel_dp_link_down(intel_dp); 2130 return; 2131 } 2132 2133 /* Now read the DPCD to see if it's actually running */ 2134 if (!intel_dp_get_dpcd(intel_dp)) { 2135 intel_dp_link_down(intel_dp); 2136 return; 2137 } 2138 2139 /* Try to read the source of the interrupt */ 2140 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 2141 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { 2142 /* Clear interrupt source */ 2143 intel_dp_aux_native_write_1(intel_dp, 2144 DP_DEVICE_SERVICE_IRQ_VECTOR, 2145 sink_irq_vector); 2146 2147 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) 2148 intel_dp_handle_test_request(intel_dp); 2149 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) 2150 DRM_DEBUG_KMS("CP or sink specific irq unhandled\n"); 2151 } 2152 2153 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { 2154 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", 2155 drm_get_encoder_name(&intel_encoder->base)); 2156 intel_dp_start_link_train(intel_dp); 2157 intel_dp_complete_link_train(intel_dp); 2158 } 2159 } 2160 2161 /* XXX this is probably wrong for multiple downstream ports */ 2162 static enum drm_connector_status 2163 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 2164 { 2165 uint8_t *dpcd = intel_dp->dpcd; 2166 bool hpd; 2167 uint8_t type; 2168 2169 if (!intel_dp_get_dpcd(intel_dp)) 2170 return connector_status_disconnected; 2171 2172 /* if there's no downstream port, we're done */ 2173 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) 2174 return connector_status_connected; 2175 2176 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 2177 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD); 2178 if (hpd) { 2179 uint8_t reg; 2180 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, 2181 ®, 1)) 2182 return connector_status_unknown; 2183 return DP_GET_SINK_COUNT(reg) ? connector_status_connected 2184 : connector_status_disconnected; 2185 } 2186 2187 /* If no HPD, poke DDC gently */ 2188 if (drm_probe_ddc(intel_dp->adapter)) 2189 return connector_status_connected; 2190 2191 /* Well we tried, say unknown for unreliable port types */ 2192 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 2193 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID) 2194 return connector_status_unknown; 2195 2196 /* Anything else is out of spec, warn and ignore */ 2197 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 2198 return connector_status_disconnected; 2199 } 2200 2201 static enum drm_connector_status 2202 ironlake_dp_detect(struct intel_dp *intel_dp) 2203 { 2204 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2205 enum drm_connector_status status; 2206 2207 /* Can't disconnect eDP, but you can close the lid... */ 2208 if (is_edp(intel_dp)) { 2209 status = intel_panel_detect(dev); 2210 if (status == connector_status_unknown) 2211 status = connector_status_connected; 2212 return status; 2213 } 2214 2215 return intel_dp_detect_dpcd(intel_dp); 2216 } 2217 2218 static enum drm_connector_status 2219 g4x_dp_detect(struct intel_dp *intel_dp) 2220 { 2221 struct drm_device *dev = intel_dp_to_dev(intel_dp); 2222 struct drm_i915_private *dev_priv = dev->dev_private; 2223 uint32_t bit; 2224 2225 switch (intel_dp->output_reg) { 2226 case DP_B: 2227 bit = DPB_HOTPLUG_LIVE_STATUS; 2228 break; 2229 case DP_C: 2230 bit = DPC_HOTPLUG_LIVE_STATUS; 2231 break; 2232 case DP_D: 2233 bit = DPD_HOTPLUG_LIVE_STATUS; 2234 break; 2235 default: 2236 return connector_status_unknown; 2237 } 2238 2239 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) 2240 return connector_status_disconnected; 2241 2242 return intel_dp_detect_dpcd(intel_dp); 2243 } 2244 2245 static struct edid * 2246 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter) 2247 { 2248 struct intel_connector *intel_connector = to_intel_connector(connector); 2249 2250 /* use cached edid if we have one */ 2251 if (intel_connector->edid) { 2252 struct edid *edid; 2253 int size; 2254 2255 /* invalid edid */ 2256 if (IS_ERR(intel_connector->edid)) 2257 return NULL; 2258 2259 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; 2260 edid = kmalloc(size, DRM_MEM_KMS, M_WAITOK); 2261 if (!edid) 2262 return NULL; 2263 2264 memcpy(edid, intel_connector->edid, size); 2265 return edid; 2266 } 2267 2268 return drm_get_edid(connector, adapter); 2269 } 2270 2271 static int 2272 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter) 2273 { 2274 struct intel_connector *intel_connector = to_intel_connector(connector); 2275 2276 /* use cached edid if we have one */ 2277 if (intel_connector->edid) { 2278 /* invalid edid */ 2279 if (IS_ERR(intel_connector->edid)) 2280 return 0; 2281 2282 return intel_connector_update_modes(connector, 2283 intel_connector->edid); 2284 } 2285 2286 return intel_ddc_get_modes(connector, adapter); 2287 } 2288 2289 /** 2290 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. 2291 * 2292 * \return true if DP port is connected. 2293 * \return false if DP port is disconnected. 2294 */ 2295 static enum drm_connector_status 2296 intel_dp_detect(struct drm_connector *connector, bool force) 2297 { 2298 struct intel_dp *intel_dp = intel_attached_dp(connector); 2299 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2300 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2301 struct drm_device *dev = connector->dev; 2302 enum drm_connector_status status; 2303 struct edid *edid = NULL; 2304 2305 intel_dp->has_audio = false; 2306 2307 if (HAS_PCH_SPLIT(dev)) 2308 status = ironlake_dp_detect(intel_dp); 2309 else 2310 status = g4x_dp_detect(intel_dp); 2311 2312 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", 2313 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], 2314 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], 2315 intel_dp->dpcd[6], intel_dp->dpcd[7]); 2316 2317 if (status != connector_status_connected) 2318 return status; 2319 2320 intel_dp_probe_oui(intel_dp); 2321 2322 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { 2323 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); 2324 } else { 2325 edid = intel_dp_get_edid(connector, intel_dp->adapter); 2326 if (edid) { 2327 intel_dp->has_audio = drm_detect_monitor_audio(edid); 2328 kfree(edid, DRM_MEM_KMS); 2329 } 2330 } 2331 2332 if (intel_encoder->type != INTEL_OUTPUT_EDP) 2333 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 2334 return connector_status_connected; 2335 } 2336 2337 static int intel_dp_get_modes(struct drm_connector *connector) 2338 { 2339 struct intel_dp *intel_dp = intel_attached_dp(connector); 2340 struct intel_connector *intel_connector = to_intel_connector(connector); 2341 struct drm_device *dev = connector->dev; 2342 int ret; 2343 2344 /* We should parse the EDID data and find out if it has an audio sink 2345 */ 2346 2347 ret = intel_dp_get_edid_modes(connector, intel_dp->adapter); 2348 if (ret) 2349 return ret; 2350 2351 /* if eDP has no EDID, fall back to fixed mode */ 2352 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 2353 struct drm_display_mode *mode; 2354 mode = drm_mode_duplicate(dev, 2355 intel_connector->panel.fixed_mode); 2356 if (mode) { 2357 drm_mode_probed_add(connector, mode); 2358 return 1; 2359 } 2360 } 2361 return 0; 2362 } 2363 2364 static bool 2365 intel_dp_detect_audio(struct drm_connector *connector) 2366 { 2367 struct intel_dp *intel_dp = intel_attached_dp(connector); 2368 struct edid *edid; 2369 bool has_audio = false; 2370 2371 edid = intel_dp_get_edid(connector, intel_dp->adapter); 2372 if (edid) { 2373 has_audio = drm_detect_monitor_audio(edid); 2374 2375 drm_free(edid, DRM_MEM_KMS); 2376 } 2377 2378 return has_audio; 2379 } 2380 2381 static int 2382 intel_dp_set_property(struct drm_connector *connector, 2383 struct drm_property *property, 2384 uint64_t val) 2385 { 2386 struct drm_i915_private *dev_priv = connector->dev->dev_private; 2387 struct intel_connector *intel_connector = to_intel_connector(connector); 2388 struct intel_encoder *intel_encoder = intel_attached_encoder(connector); 2389 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 2390 int ret; 2391 2392 ret = drm_object_property_set_value(&connector->base, property, val); 2393 if (ret) 2394 return ret; 2395 2396 if (property == dev_priv->force_audio_property) { 2397 int i = val; 2398 bool has_audio; 2399 2400 if (i == intel_dp->force_audio) 2401 return 0; 2402 2403 intel_dp->force_audio = i; 2404 2405 if (i == HDMI_AUDIO_AUTO) 2406 has_audio = intel_dp_detect_audio(connector); 2407 else 2408 has_audio = (i == HDMI_AUDIO_ON); 2409 2410 if (has_audio == intel_dp->has_audio) 2411 return 0; 2412 2413 intel_dp->has_audio = has_audio; 2414 goto done; 2415 } 2416 2417 if (property == dev_priv->broadcast_rgb_property) { 2418 if (val == !!intel_dp->color_range) 2419 return 0; 2420 2421 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; 2422 goto done; 2423 } 2424 2425 if (is_edp(intel_dp) && 2426 property == connector->dev->mode_config.scaling_mode_property) { 2427 if (val == DRM_MODE_SCALE_NONE) { 2428 DRM_DEBUG_KMS("no scaling not supported\n"); 2429 return -EINVAL; 2430 } 2431 2432 if (intel_connector->panel.fitting_mode == val) { 2433 /* the eDP scaling property is not changed */ 2434 return 0; 2435 } 2436 intel_connector->panel.fitting_mode = val; 2437 2438 goto done; 2439 } 2440 2441 return -EINVAL; 2442 2443 done: 2444 if (intel_encoder->base.crtc) { 2445 struct drm_crtc *crtc = intel_encoder->base.crtc; 2446 intel_set_mode(crtc, &crtc->mode, 2447 crtc->x, crtc->y, crtc->fb); 2448 } 2449 2450 return 0; 2451 } 2452 2453 static void 2454 intel_dp_destroy(struct drm_connector *connector) 2455 { 2456 struct intel_dp *intel_dp = intel_attached_dp(connector); 2457 struct intel_connector *intel_connector = to_intel_connector(connector); 2458 2459 if (!IS_ERR_OR_NULL(intel_connector->edid)) 2460 kfree(intel_connector->edid, DRM_MEM_KMS); 2461 2462 if (is_edp(intel_dp)) 2463 intel_panel_fini(&intel_connector->panel); 2464 2465 #if 0 2466 drm_sysfs_connector_remove(connector); 2467 #endif 2468 drm_connector_cleanup(connector); 2469 drm_free(connector, DRM_MEM_KMS); 2470 } 2471 2472 void intel_dp_encoder_destroy(struct drm_encoder *encoder) 2473 { 2474 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2475 struct intel_dp *intel_dp = &intel_dig_port->dp; 2476 struct drm_device *dev = encoder->dev; 2477 2478 if (intel_dp->dp_iic_bus != NULL) { 2479 if (intel_dp->adapter != NULL) { 2480 device_delete_child(intel_dp->dp_iic_bus, 2481 intel_dp->adapter); 2482 } 2483 device_delete_child(dev->dev, intel_dp->dp_iic_bus); 2484 } 2485 drm_encoder_cleanup(encoder); 2486 if (is_edp(intel_dp)) { 2487 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 2488 ironlake_panel_vdd_off_sync(intel_dp); 2489 } 2490 drm_free(intel_dp, DRM_MEM_KMS); 2491 } 2492 2493 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { 2494 .mode_fixup = intel_dp_mode_fixup, 2495 .mode_set = intel_dp_mode_set, 2496 .disable = intel_encoder_noop, 2497 }; 2498 2499 static const struct drm_connector_funcs intel_dp_connector_funcs = { 2500 .dpms = intel_connector_dpms, 2501 .detect = intel_dp_detect, 2502 .fill_modes = drm_helper_probe_single_connector_modes, 2503 .set_property = intel_dp_set_property, 2504 .destroy = intel_dp_destroy, 2505 }; 2506 2507 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 2508 .get_modes = intel_dp_get_modes, 2509 .mode_valid = intel_dp_mode_valid, 2510 .best_encoder = intel_best_encoder, 2511 }; 2512 2513 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 2514 .destroy = intel_dp_encoder_destroy, 2515 }; 2516 2517 static void 2518 intel_dp_hot_plug(struct intel_encoder *intel_encoder) 2519 { 2520 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 2521 2522 intel_dp_check_link_status(intel_dp); 2523 } 2524 2525 /* Return which DP Port should be selected for Transcoder DP control */ 2526 int 2527 intel_trans_dp_port_sel(struct drm_crtc *crtc) 2528 { 2529 struct drm_device *dev = crtc->dev; 2530 struct intel_encoder *intel_encoder; 2531 struct intel_dp *intel_dp; 2532 2533 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 2534 intel_dp = enc_to_intel_dp(&intel_encoder->base); 2535 2536 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 2537 intel_encoder->type == INTEL_OUTPUT_EDP) 2538 return intel_dp->output_reg; 2539 } 2540 2541 return -1; 2542 } 2543 2544 /* check the VBT to see whether the eDP is on DP-D port */ 2545 bool intel_dpd_is_edp(struct drm_device *dev) 2546 { 2547 struct drm_i915_private *dev_priv = dev->dev_private; 2548 struct child_device_config *p_child; 2549 int i; 2550 2551 if (!dev_priv->child_dev_num) 2552 return false; 2553 2554 for (i = 0; i < dev_priv->child_dev_num; i++) { 2555 p_child = dev_priv->child_dev + i; 2556 2557 if (p_child->dvo_port == PORT_IDPD && 2558 p_child->device_type == DEVICE_TYPE_eDP) 2559 return true; 2560 } 2561 return false; 2562 } 2563 2564 static void 2565 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 2566 { 2567 struct intel_connector *intel_connector = to_intel_connector(connector); 2568 2569 intel_attach_force_audio_property(connector); 2570 intel_attach_broadcast_rgb_property(connector); 2571 2572 if (is_edp(intel_dp)) { 2573 drm_mode_create_scaling_mode_property(connector->dev); 2574 drm_object_attach_property( 2575 &connector->base, 2576 connector->dev->mode_config.scaling_mode_property, 2577 DRM_MODE_SCALE_ASPECT); 2578 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; 2579 } 2580 } 2581 2582 static void 2583 intel_dp_init_panel_power_sequencer(struct drm_device *dev, 2584 struct intel_dp *intel_dp, 2585 struct edp_power_seq *out) 2586 { 2587 struct drm_i915_private *dev_priv = dev->dev_private; 2588 struct edp_power_seq cur, vbt, spec, final; 2589 u32 pp_on, pp_off, pp_div, pp; 2590 2591 /* Workaround: Need to write PP_CONTROL with the unlock key as 2592 * the very first thing. */ 2593 pp = ironlake_get_pp_control(dev_priv); 2594 I915_WRITE(PCH_PP_CONTROL, pp); 2595 2596 pp_on = I915_READ(PCH_PP_ON_DELAYS); 2597 pp_off = I915_READ(PCH_PP_OFF_DELAYS); 2598 pp_div = I915_READ(PCH_PP_DIVISOR); 2599 2600 /* Pull timing values out of registers */ 2601 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> 2602 PANEL_POWER_UP_DELAY_SHIFT; 2603 2604 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> 2605 PANEL_LIGHT_ON_DELAY_SHIFT; 2606 2607 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> 2608 PANEL_LIGHT_OFF_DELAY_SHIFT; 2609 2610 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> 2611 PANEL_POWER_DOWN_DELAY_SHIFT; 2612 2613 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> 2614 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; 2615 2616 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2617 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); 2618 2619 vbt = dev_priv->edp.pps; 2620 2621 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 2622 * our hw here, which are all in 100usec. */ 2623 spec.t1_t3 = 210 * 10; 2624 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 2625 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 2626 spec.t10 = 500 * 10; 2627 /* This one is special and actually in units of 100ms, but zero 2628 * based in the hw (so we need to add 100 ms). But the sw vbt 2629 * table multiplies it with 1000 to make it in units of 100usec, 2630 * too. */ 2631 spec.t11_t12 = (510 + 100) * 10; 2632 2633 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 2634 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); 2635 2636 /* Use the max of the register settings and vbt. If both are 2637 * unset, fall back to the spec limits. */ 2638 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ 2639 spec.field : \ 2640 max(cur.field, vbt.field)) 2641 assign_final(t1_t3); 2642 assign_final(t8); 2643 assign_final(t9); 2644 assign_final(t10); 2645 assign_final(t11_t12); 2646 #undef assign_final 2647 2648 #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) 2649 intel_dp->panel_power_up_delay = get_delay(t1_t3); 2650 intel_dp->backlight_on_delay = get_delay(t8); 2651 intel_dp->backlight_off_delay = get_delay(t9); 2652 intel_dp->panel_power_down_delay = get_delay(t10); 2653 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 2654 #undef get_delay 2655 2656 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 2657 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 2658 intel_dp->panel_power_cycle_delay); 2659 2660 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 2661 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 2662 2663 if (out) 2664 *out = final; 2665 } 2666 2667 static void 2668 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, 2669 struct intel_dp *intel_dp, 2670 struct edp_power_seq *seq) 2671 { 2672 struct drm_i915_private *dev_priv = dev->dev_private; 2673 u32 pp_on, pp_off, pp_div; 2674 2675 /* And finally store the new values in the power sequencer. */ 2676 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | 2677 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); 2678 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | 2679 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); 2680 /* Compute the divisor for the pp clock, simply match the Bspec 2681 * formula. */ 2682 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1) 2683 << PP_REFERENCE_DIVIDER_SHIFT; 2684 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) 2685 << PANEL_POWER_CYCLE_DELAY_SHIFT); 2686 2687 /* Haswell doesn't have any port selection bits for the panel 2688 * power sequencer any more. */ 2689 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { 2690 if (is_cpu_edp(intel_dp)) 2691 pp_on |= PANEL_POWER_PORT_DP_A; 2692 else 2693 pp_on |= PANEL_POWER_PORT_DP_D; 2694 } 2695 2696 I915_WRITE(PCH_PP_ON_DELAYS, pp_on); 2697 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off); 2698 I915_WRITE(PCH_PP_DIVISOR, pp_div); 2699 2700 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 2701 I915_READ(PCH_PP_ON_DELAYS), 2702 I915_READ(PCH_PP_OFF_DELAYS), 2703 I915_READ(PCH_PP_DIVISOR)); 2704 } 2705 2706 void 2707 intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 2708 struct intel_connector *intel_connector) 2709 { 2710 struct drm_connector *connector = &intel_connector->base; 2711 struct intel_dp *intel_dp = &intel_dig_port->dp; 2712 struct intel_encoder *intel_encoder = &intel_dig_port->base; 2713 struct drm_device *dev = intel_encoder->base.dev; 2714 struct drm_i915_private *dev_priv = dev->dev_private; 2715 struct drm_display_mode *fixed_mode = NULL; 2716 struct edp_power_seq power_seq = { 0 }; 2717 enum port port = intel_dig_port->port; 2718 const char *name = NULL; 2719 int type; 2720 2721 /* Preserve the current hw state. */ 2722 intel_dp->DP = I915_READ(intel_dp->output_reg); 2723 intel_dp->attached_connector = intel_connector; 2724 2725 if (HAS_PCH_SPLIT(dev) && port == PORT_D) 2726 if (intel_dpd_is_edp(dev)) 2727 intel_dp->is_pch_edp = true; 2728 2729 /* 2730 * FIXME : We need to initialize built-in panels before external panels. 2731 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup 2732 */ 2733 if (IS_VALLEYVIEW(dev) && port == PORT_C) { 2734 type = DRM_MODE_CONNECTOR_eDP; 2735 intel_encoder->type = INTEL_OUTPUT_EDP; 2736 } else if (port == PORT_A || is_pch_edp(intel_dp)) { 2737 type = DRM_MODE_CONNECTOR_eDP; 2738 intel_encoder->type = INTEL_OUTPUT_EDP; 2739 } else { 2740 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for 2741 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't 2742 * rewrite it. 2743 */ 2744 type = DRM_MODE_CONNECTOR_DisplayPort; 2745 } 2746 2747 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 2748 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 2749 2750 connector->polled = DRM_CONNECTOR_POLL_HPD; 2751 connector->interlace_allowed = true; 2752 connector->doublescan_allowed = 0; 2753 2754 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, 2755 ironlake_panel_vdd_work); 2756 2757 intel_connector_attach_encoder(intel_connector, intel_encoder); 2758 #if 0 2759 drm_sysfs_connector_add(connector); 2760 #endif 2761 2762 if (IS_HASWELL(dev)) 2763 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 2764 else 2765 intel_connector->get_hw_state = intel_connector_get_hw_state; 2766 2767 /* Set up the DDC bus. */ 2768 switch (port) { 2769 case PORT_A: 2770 name = "DPDDC-A"; 2771 break; 2772 case PORT_B: 2773 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS; 2774 name = "DPDDC-B"; 2775 break; 2776 case PORT_C: 2777 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS; 2778 name = "DPDDC-C"; 2779 break; 2780 case PORT_D: 2781 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS; 2782 name = "DPDDC-D"; 2783 break; 2784 default: 2785 WARN(1, "Invalid port %c\n", port_name(port)); 2786 break; 2787 } 2788 2789 if (is_edp(intel_dp)) 2790 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); 2791 2792 intel_dp_i2c_init(intel_dp, intel_connector, name); 2793 2794 /* Cache DPCD and EDID for edp. */ 2795 if (is_edp(intel_dp)) { 2796 bool ret; 2797 struct drm_display_mode *scan; 2798 struct edid *edid; 2799 2800 ironlake_edp_panel_vdd_on(intel_dp); 2801 ret = intel_dp_get_dpcd(intel_dp); 2802 ironlake_edp_panel_vdd_off(intel_dp, false); 2803 2804 if (ret) { 2805 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 2806 dev_priv->no_aux_handshake = 2807 intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 2808 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 2809 } else { 2810 /* if this fails, presume the device is a ghost */ 2811 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 2812 intel_dp_encoder_destroy(&intel_encoder->base); 2813 intel_dp_destroy(connector); 2814 return; 2815 } 2816 2817 /* We now know it's not a ghost, init power sequence regs. */ 2818 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, 2819 &power_seq); 2820 2821 ironlake_edp_panel_vdd_on(intel_dp); 2822 edid = drm_get_edid(connector, intel_dp->adapter); 2823 if (edid) { 2824 if (drm_add_edid_modes(connector, edid)) { 2825 drm_mode_connector_update_edid_property(connector, edid); 2826 drm_edid_to_eld(connector, edid); 2827 } else { 2828 kfree(edid, DRM_MEM_KMS); 2829 edid = ERR_PTR(-EINVAL); 2830 } 2831 } else { 2832 edid = ERR_PTR(-ENOENT); 2833 } 2834 intel_connector->edid = edid; 2835 2836 /* prefer fixed mode from EDID if available */ 2837 list_for_each_entry(scan, &connector->probed_modes, head) { 2838 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { 2839 fixed_mode = drm_mode_duplicate(dev, scan); 2840 break; 2841 } 2842 } 2843 2844 /* fallback to VBT if available for eDP */ 2845 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) { 2846 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); 2847 if (fixed_mode) 2848 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; 2849 } 2850 2851 ironlake_edp_panel_vdd_off(intel_dp, false); 2852 } 2853 2854 if (is_edp(intel_dp)) { 2855 intel_panel_init(&intel_connector->panel, fixed_mode); 2856 intel_panel_setup_backlight(connector); 2857 } 2858 2859 intel_dp_add_properties(intel_dp, connector); 2860 2861 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 2862 * 0xd. Failure to do so will result in spurious interrupts being 2863 * generated on the port when a cable is not attached. 2864 */ 2865 if (IS_G4X(dev) && !IS_GM45(dev)) { 2866 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 2867 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 2868 } 2869 } 2870 2871 void 2872 intel_dp_init(struct drm_device *dev, int output_reg, enum port port) 2873 { 2874 struct intel_digital_port *intel_dig_port; 2875 struct intel_encoder *intel_encoder; 2876 struct drm_encoder *encoder; 2877 struct intel_connector *intel_connector; 2878 2879 intel_dig_port = kmalloc(sizeof(struct intel_digital_port), DRM_MEM_KMS, 2880 M_WAITOK | M_ZERO); 2881 if (!intel_dig_port) 2882 return; 2883 2884 intel_connector = kmalloc(sizeof(struct intel_connector), DRM_MEM_KMS, 2885 M_WAITOK | M_ZERO); 2886 if (!intel_connector) { 2887 kfree(intel_dig_port, DRM_MEM_KMS); 2888 return; 2889 } 2890 2891 intel_encoder = &intel_dig_port->base; 2892 encoder = &intel_encoder->base; 2893 2894 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, 2895 DRM_MODE_ENCODER_TMDS); 2896 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); 2897 2898 intel_encoder->enable = intel_enable_dp; 2899 intel_encoder->pre_enable = intel_pre_enable_dp; 2900 intel_encoder->disable = intel_disable_dp; 2901 intel_encoder->post_disable = intel_post_disable_dp; 2902 intel_encoder->get_hw_state = intel_dp_get_hw_state; 2903 2904 intel_dig_port->port = port; 2905 intel_dig_port->dp.output_reg = output_reg; 2906 2907 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; 2908 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 2909 intel_encoder->cloneable = false; 2910 intel_encoder->hot_plug = intel_dp_hot_plug; 2911 2912 intel_dp_init_connector(intel_dig_port, intel_connector); 2913 } 2914