1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <ddb/ddb.h> 28 #include <sys/limits.h> 29 30 #include <drm/drmP.h> 31 #include <drm/drm_edid.h> 32 #include "intel_drv.h" 33 #include <drm/i915_drm.h> 34 #include "i915_drv.h" 35 #include <drm/drm_dp_helper.h> 36 #include <drm/drm_crtc_helper.h> 37 38 #include <linux/err.h> 39 40 bool intel_pipe_has_type(struct drm_crtc *crtc, int type); 41 static void intel_increase_pllclock(struct drm_crtc *crtc); 42 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); 43 44 typedef struct { 45 /* given values */ 46 int n; 47 int m1, m2; 48 int p1, p2; 49 /* derived values */ 50 int dot; 51 int vco; 52 int m; 53 int p; 54 } intel_clock_t; 55 56 typedef struct { 57 int min, max; 58 } intel_range_t; 59 60 typedef struct { 61 int dot_limit; 62 int p2_slow, p2_fast; 63 } intel_p2_t; 64 65 #define INTEL_P2_NUM 2 66 typedef struct intel_limit intel_limit_t; 67 struct intel_limit { 68 intel_range_t dot, vco, n, m, m1, m2, p, p1; 69 intel_p2_t p2; 70 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, 71 int, int, intel_clock_t *, intel_clock_t *); 72 }; 73 74 /* FDI */ 75 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */ 76 77 int 78 intel_pch_rawclk(struct drm_device *dev) 79 { 80 struct drm_i915_private *dev_priv = dev->dev_private; 81 82 WARN_ON(!HAS_PCH_SPLIT(dev)); 83 84 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; 85 } 86 87 static bool 88 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 89 int target, int refclk, intel_clock_t *match_clock, 90 intel_clock_t *best_clock); 91 static bool 92 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 93 int target, int refclk, intel_clock_t *match_clock, 94 intel_clock_t *best_clock); 95 96 static bool 97 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc, 98 int target, int refclk, intel_clock_t *match_clock, 99 intel_clock_t *best_clock); 100 static bool 101 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc, 102 int target, int refclk, intel_clock_t *match_clock, 103 intel_clock_t *best_clock); 104 105 static bool 106 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, 107 int target, int refclk, intel_clock_t *match_clock, 108 intel_clock_t *best_clock); 109 110 static inline u32 /* units of 100MHz */ 111 intel_fdi_link_freq(struct drm_device *dev) 112 { 113 if (IS_GEN5(dev)) { 114 struct drm_i915_private *dev_priv = dev->dev_private; 115 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; 116 } else 117 return 27; 118 } 119 120 static const intel_limit_t intel_limits_i8xx_dvo = { 121 .dot = { .min = 25000, .max = 350000 }, 122 .vco = { .min = 930000, .max = 1400000 }, 123 .n = { .min = 3, .max = 16 }, 124 .m = { .min = 96, .max = 140 }, 125 .m1 = { .min = 18, .max = 26 }, 126 .m2 = { .min = 6, .max = 16 }, 127 .p = { .min = 4, .max = 128 }, 128 .p1 = { .min = 2, .max = 33 }, 129 .p2 = { .dot_limit = 165000, 130 .p2_slow = 4, .p2_fast = 2 }, 131 .find_pll = intel_find_best_PLL, 132 }; 133 134 static const intel_limit_t intel_limits_i8xx_lvds = { 135 .dot = { .min = 25000, .max = 350000 }, 136 .vco = { .min = 930000, .max = 1400000 }, 137 .n = { .min = 3, .max = 16 }, 138 .m = { .min = 96, .max = 140 }, 139 .m1 = { .min = 18, .max = 26 }, 140 .m2 = { .min = 6, .max = 16 }, 141 .p = { .min = 4, .max = 128 }, 142 .p1 = { .min = 1, .max = 6 }, 143 .p2 = { .dot_limit = 165000, 144 .p2_slow = 14, .p2_fast = 7 }, 145 .find_pll = intel_find_best_PLL, 146 }; 147 148 static const intel_limit_t intel_limits_i9xx_sdvo = { 149 .dot = { .min = 20000, .max = 400000 }, 150 .vco = { .min = 1400000, .max = 2800000 }, 151 .n = { .min = 1, .max = 6 }, 152 .m = { .min = 70, .max = 120 }, 153 .m1 = { .min = 8, .max = 18 }, 154 .m2 = { .min = 3, .max = 7 }, 155 .p = { .min = 5, .max = 80 }, 156 .p1 = { .min = 1, .max = 8 }, 157 .p2 = { .dot_limit = 200000, 158 .p2_slow = 10, .p2_fast = 5 }, 159 .find_pll = intel_find_best_PLL, 160 }; 161 162 static const intel_limit_t intel_limits_i9xx_lvds = { 163 .dot = { .min = 20000, .max = 400000 }, 164 .vco = { .min = 1400000, .max = 2800000 }, 165 .n = { .min = 1, .max = 6 }, 166 .m = { .min = 70, .max = 120 }, 167 .m1 = { .min = 8, .max = 18 }, 168 .m2 = { .min = 3, .max = 7 }, 169 .p = { .min = 7, .max = 98 }, 170 .p1 = { .min = 1, .max = 8 }, 171 .p2 = { .dot_limit = 112000, 172 .p2_slow = 14, .p2_fast = 7 }, 173 .find_pll = intel_find_best_PLL, 174 }; 175 176 177 static const intel_limit_t intel_limits_g4x_sdvo = { 178 .dot = { .min = 25000, .max = 270000 }, 179 .vco = { .min = 1750000, .max = 3500000}, 180 .n = { .min = 1, .max = 4 }, 181 .m = { .min = 104, .max = 138 }, 182 .m1 = { .min = 17, .max = 23 }, 183 .m2 = { .min = 5, .max = 11 }, 184 .p = { .min = 10, .max = 30 }, 185 .p1 = { .min = 1, .max = 3}, 186 .p2 = { .dot_limit = 270000, 187 .p2_slow = 10, 188 .p2_fast = 10 189 }, 190 .find_pll = intel_g4x_find_best_PLL, 191 }; 192 193 static const intel_limit_t intel_limits_g4x_hdmi = { 194 .dot = { .min = 22000, .max = 400000 }, 195 .vco = { .min = 1750000, .max = 3500000}, 196 .n = { .min = 1, .max = 4 }, 197 .m = { .min = 104, .max = 138 }, 198 .m1 = { .min = 16, .max = 23 }, 199 .m2 = { .min = 5, .max = 11 }, 200 .p = { .min = 5, .max = 80 }, 201 .p1 = { .min = 1, .max = 8}, 202 .p2 = { .dot_limit = 165000, 203 .p2_slow = 10, .p2_fast = 5 }, 204 .find_pll = intel_g4x_find_best_PLL, 205 }; 206 207 static const intel_limit_t intel_limits_g4x_single_channel_lvds = { 208 .dot = { .min = 20000, .max = 115000 }, 209 .vco = { .min = 1750000, .max = 3500000 }, 210 .n = { .min = 1, .max = 3 }, 211 .m = { .min = 104, .max = 138 }, 212 .m1 = { .min = 17, .max = 23 }, 213 .m2 = { .min = 5, .max = 11 }, 214 .p = { .min = 28, .max = 112 }, 215 .p1 = { .min = 2, .max = 8 }, 216 .p2 = { .dot_limit = 0, 217 .p2_slow = 14, .p2_fast = 14 218 }, 219 .find_pll = intel_g4x_find_best_PLL, 220 }; 221 222 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { 223 .dot = { .min = 80000, .max = 224000 }, 224 .vco = { .min = 1750000, .max = 3500000 }, 225 .n = { .min = 1, .max = 3 }, 226 .m = { .min = 104, .max = 138 }, 227 .m1 = { .min = 17, .max = 23 }, 228 .m2 = { .min = 5, .max = 11 }, 229 .p = { .min = 14, .max = 42 }, 230 .p1 = { .min = 2, .max = 6 }, 231 .p2 = { .dot_limit = 0, 232 .p2_slow = 7, .p2_fast = 7 233 }, 234 .find_pll = intel_g4x_find_best_PLL, 235 }; 236 237 static const intel_limit_t intel_limits_g4x_display_port = { 238 .dot = { .min = 161670, .max = 227000 }, 239 .vco = { .min = 1750000, .max = 3500000}, 240 .n = { .min = 1, .max = 2 }, 241 .m = { .min = 97, .max = 108 }, 242 .m1 = { .min = 0x10, .max = 0x12 }, 243 .m2 = { .min = 0x05, .max = 0x06 }, 244 .p = { .min = 10, .max = 20 }, 245 .p1 = { .min = 1, .max = 2}, 246 .p2 = { .dot_limit = 0, 247 .p2_slow = 10, .p2_fast = 10 }, 248 .find_pll = intel_find_pll_g4x_dp, 249 }; 250 251 static const intel_limit_t intel_limits_pineview_sdvo = { 252 .dot = { .min = 20000, .max = 400000}, 253 .vco = { .min = 1700000, .max = 3500000 }, 254 /* Pineview's Ncounter is a ring counter */ 255 .n = { .min = 3, .max = 6 }, 256 .m = { .min = 2, .max = 256 }, 257 /* Pineview only has one combined m divider, which we treat as m2. */ 258 .m1 = { .min = 0, .max = 0 }, 259 .m2 = { .min = 0, .max = 254 }, 260 .p = { .min = 5, .max = 80 }, 261 .p1 = { .min = 1, .max = 8 }, 262 .p2 = { .dot_limit = 200000, 263 .p2_slow = 10, .p2_fast = 5 }, 264 .find_pll = intel_find_best_PLL, 265 }; 266 267 static const intel_limit_t intel_limits_pineview_lvds = { 268 .dot = { .min = 20000, .max = 400000 }, 269 .vco = { .min = 1700000, .max = 3500000 }, 270 .n = { .min = 3, .max = 6 }, 271 .m = { .min = 2, .max = 256 }, 272 .m1 = { .min = 0, .max = 0 }, 273 .m2 = { .min = 0, .max = 254 }, 274 .p = { .min = 7, .max = 112 }, 275 .p1 = { .min = 1, .max = 8 }, 276 .p2 = { .dot_limit = 112000, 277 .p2_slow = 14, .p2_fast = 14 }, 278 .find_pll = intel_find_best_PLL, 279 }; 280 281 /* Ironlake / Sandybridge 282 * 283 * We calculate clock using (register_value + 2) for N/M1/M2, so here 284 * the range value for them is (actual_value - 2). 285 */ 286 static const intel_limit_t intel_limits_ironlake_dac = { 287 .dot = { .min = 25000, .max = 350000 }, 288 .vco = { .min = 1760000, .max = 3510000 }, 289 .n = { .min = 1, .max = 5 }, 290 .m = { .min = 79, .max = 127 }, 291 .m1 = { .min = 12, .max = 22 }, 292 .m2 = { .min = 5, .max = 9 }, 293 .p = { .min = 5, .max = 80 }, 294 .p1 = { .min = 1, .max = 8 }, 295 .p2 = { .dot_limit = 225000, 296 .p2_slow = 10, .p2_fast = 5 }, 297 .find_pll = intel_g4x_find_best_PLL, 298 }; 299 300 static const intel_limit_t intel_limits_ironlake_single_lvds = { 301 .dot = { .min = 25000, .max = 350000 }, 302 .vco = { .min = 1760000, .max = 3510000 }, 303 .n = { .min = 1, .max = 3 }, 304 .m = { .min = 79, .max = 118 }, 305 .m1 = { .min = 12, .max = 22 }, 306 .m2 = { .min = 5, .max = 9 }, 307 .p = { .min = 28, .max = 112 }, 308 .p1 = { .min = 2, .max = 8 }, 309 .p2 = { .dot_limit = 225000, 310 .p2_slow = 14, .p2_fast = 14 }, 311 .find_pll = intel_g4x_find_best_PLL, 312 }; 313 314 static const intel_limit_t intel_limits_ironlake_dual_lvds = { 315 .dot = { .min = 25000, .max = 350000 }, 316 .vco = { .min = 1760000, .max = 3510000 }, 317 .n = { .min = 1, .max = 3 }, 318 .m = { .min = 79, .max = 127 }, 319 .m1 = { .min = 12, .max = 22 }, 320 .m2 = { .min = 5, .max = 9 }, 321 .p = { .min = 14, .max = 56 }, 322 .p1 = { .min = 2, .max = 8 }, 323 .p2 = { .dot_limit = 225000, 324 .p2_slow = 7, .p2_fast = 7 }, 325 .find_pll = intel_g4x_find_best_PLL, 326 }; 327 328 /* LVDS 100mhz refclk limits. */ 329 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { 330 .dot = { .min = 25000, .max = 350000 }, 331 .vco = { .min = 1760000, .max = 3510000 }, 332 .n = { .min = 1, .max = 2 }, 333 .m = { .min = 79, .max = 126 }, 334 .m1 = { .min = 12, .max = 22 }, 335 .m2 = { .min = 5, .max = 9 }, 336 .p = { .min = 28, .max = 112 }, 337 .p1 = { .min = 2, .max = 8 }, 338 .p2 = { .dot_limit = 225000, 339 .p2_slow = 14, .p2_fast = 14 }, 340 .find_pll = intel_g4x_find_best_PLL, 341 }; 342 343 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { 344 .dot = { .min = 25000, .max = 350000 }, 345 .vco = { .min = 1760000, .max = 3510000 }, 346 .n = { .min = 1, .max = 3 }, 347 .m = { .min = 79, .max = 126 }, 348 .m1 = { .min = 12, .max = 22 }, 349 .m2 = { .min = 5, .max = 9 }, 350 .p = { .min = 14, .max = 42 }, 351 .p1 = { .min = 2, .max = 6 }, 352 .p2 = { .dot_limit = 225000, 353 .p2_slow = 7, .p2_fast = 7 }, 354 .find_pll = intel_g4x_find_best_PLL, 355 }; 356 357 static const intel_limit_t intel_limits_ironlake_display_port = { 358 .dot = { .min = 25000, .max = 350000 }, 359 .vco = { .min = 1760000, .max = 3510000}, 360 .n = { .min = 1, .max = 2 }, 361 .m = { .min = 81, .max = 90 }, 362 .m1 = { .min = 12, .max = 22 }, 363 .m2 = { .min = 5, .max = 9 }, 364 .p = { .min = 10, .max = 20 }, 365 .p1 = { .min = 1, .max = 2}, 366 .p2 = { .dot_limit = 0, 367 .p2_slow = 10, .p2_fast = 10 }, 368 .find_pll = intel_find_pll_ironlake_dp, 369 }; 370 371 static const intel_limit_t intel_limits_vlv_dac = { 372 .dot = { .min = 25000, .max = 270000 }, 373 .vco = { .min = 4000000, .max = 6000000 }, 374 .n = { .min = 1, .max = 7 }, 375 .m = { .min = 22, .max = 450 }, /* guess */ 376 .m1 = { .min = 2, .max = 3 }, 377 .m2 = { .min = 11, .max = 156 }, 378 .p = { .min = 10, .max = 30 }, 379 .p1 = { .min = 2, .max = 3 }, 380 .p2 = { .dot_limit = 270000, 381 .p2_slow = 2, .p2_fast = 20 }, 382 .find_pll = intel_vlv_find_best_pll, 383 }; 384 385 static const intel_limit_t intel_limits_vlv_hdmi = { 386 .dot = { .min = 20000, .max = 165000 }, 387 .vco = { .min = 4000000, .max = 5994000}, 388 .n = { .min = 1, .max = 7 }, 389 .m = { .min = 60, .max = 300 }, /* guess */ 390 .m1 = { .min = 2, .max = 3 }, 391 .m2 = { .min = 11, .max = 156 }, 392 .p = { .min = 10, .max = 30 }, 393 .p1 = { .min = 2, .max = 3 }, 394 .p2 = { .dot_limit = 270000, 395 .p2_slow = 2, .p2_fast = 20 }, 396 .find_pll = intel_vlv_find_best_pll, 397 }; 398 399 static const intel_limit_t intel_limits_vlv_dp = { 400 .dot = { .min = 25000, .max = 270000 }, 401 .vco = { .min = 4000000, .max = 6000000 }, 402 .n = { .min = 1, .max = 7 }, 403 .m = { .min = 22, .max = 450 }, 404 .m1 = { .min = 2, .max = 3 }, 405 .m2 = { .min = 11, .max = 156 }, 406 .p = { .min = 10, .max = 30 }, 407 .p1 = { .min = 2, .max = 3 }, 408 .p2 = { .dot_limit = 270000, 409 .p2_slow = 2, .p2_fast = 20 }, 410 .find_pll = intel_vlv_find_best_pll, 411 }; 412 413 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) 414 { 415 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 416 417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { 418 DRM_ERROR("DPIO idle wait timed out\n"); 419 return 0; 420 } 421 422 I915_WRITE(DPIO_REG, reg); 423 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | 424 DPIO_BYTE); 425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { 426 DRM_ERROR("DPIO read wait timed out\n"); 427 return 0; 428 } 429 430 return I915_READ(DPIO_DATA); 431 } 432 433 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, 434 u32 val) 435 { 436 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 437 438 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { 439 DRM_ERROR("DPIO idle wait timed out\n"); 440 return; 441 } 442 443 I915_WRITE(DPIO_DATA, val); 444 I915_WRITE(DPIO_REG, reg); 445 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | 446 DPIO_BYTE); 447 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) 448 DRM_ERROR("DPIO write wait timed out\n"); 449 } 450 451 static void vlv_init_dpio(struct drm_device *dev) 452 { 453 struct drm_i915_private *dev_priv = dev->dev_private; 454 455 /* Reset the DPIO config */ 456 I915_WRITE(DPIO_CTL, 0); 457 POSTING_READ(DPIO_CTL); 458 I915_WRITE(DPIO_CTL, 1); 459 POSTING_READ(DPIO_CTL); 460 } 461 462 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, 463 int refclk) 464 { 465 struct drm_device *dev = crtc->dev; 466 const intel_limit_t *limit; 467 468 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 469 if (intel_is_dual_link_lvds(dev)) { 470 /* LVDS dual channel */ 471 if (refclk == 100000) 472 limit = &intel_limits_ironlake_dual_lvds_100m; 473 else 474 limit = &intel_limits_ironlake_dual_lvds; 475 } else { 476 if (refclk == 100000) 477 limit = &intel_limits_ironlake_single_lvds_100m; 478 else 479 limit = &intel_limits_ironlake_single_lvds; 480 } 481 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 482 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) 483 limit = &intel_limits_ironlake_display_port; 484 else 485 limit = &intel_limits_ironlake_dac; 486 487 return limit; 488 } 489 490 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) 491 { 492 struct drm_device *dev = crtc->dev; 493 const intel_limit_t *limit; 494 495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 496 if (intel_is_dual_link_lvds(dev)) 497 /* LVDS with dual channel */ 498 limit = &intel_limits_g4x_dual_channel_lvds; 499 else 500 /* LVDS with dual channel */ 501 limit = &intel_limits_g4x_single_channel_lvds; 502 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || 503 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { 504 limit = &intel_limits_g4x_hdmi; 505 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { 506 limit = &intel_limits_g4x_sdvo; 507 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 508 limit = &intel_limits_g4x_display_port; 509 } else /* The option is for other outputs */ 510 limit = &intel_limits_i9xx_sdvo; 511 512 return limit; 513 } 514 515 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) 516 { 517 struct drm_device *dev = crtc->dev; 518 const intel_limit_t *limit; 519 520 if (HAS_PCH_SPLIT(dev)) 521 limit = intel_ironlake_limit(crtc, refclk); 522 else if (IS_G4X(dev)) { 523 limit = intel_g4x_limit(crtc); 524 } else if (IS_PINEVIEW(dev)) { 525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 526 limit = &intel_limits_pineview_lvds; 527 else 528 limit = &intel_limits_pineview_sdvo; 529 } else if (IS_VALLEYVIEW(dev)) { 530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) 531 limit = &intel_limits_vlv_dac; 532 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 533 limit = &intel_limits_vlv_hdmi; 534 else 535 limit = &intel_limits_vlv_dp; 536 } else if (!IS_GEN2(dev)) { 537 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 538 limit = &intel_limits_i9xx_lvds; 539 else 540 limit = &intel_limits_i9xx_sdvo; 541 } else { 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 543 limit = &intel_limits_i8xx_lvds; 544 else 545 limit = &intel_limits_i8xx_dvo; 546 } 547 return limit; 548 } 549 550 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 551 static void pineview_clock(int refclk, intel_clock_t *clock) 552 { 553 clock->m = clock->m2 + 2; 554 clock->p = clock->p1 * clock->p2; 555 clock->vco = refclk * clock->m / clock->n; 556 clock->dot = clock->vco / clock->p; 557 } 558 559 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) 560 { 561 if (IS_PINEVIEW(dev)) { 562 pineview_clock(refclk, clock); 563 return; 564 } 565 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); 566 clock->p = clock->p1 * clock->p2; 567 clock->vco = refclk * clock->m / (clock->n + 2); 568 clock->dot = clock->vco / clock->p; 569 } 570 571 /** 572 * Returns whether any output on the specified pipe is of the specified type 573 */ 574 bool intel_pipe_has_type(struct drm_crtc *crtc, int type) 575 { 576 struct drm_device *dev = crtc->dev; 577 struct intel_encoder *encoder; 578 579 for_each_encoder_on_crtc(dev, crtc, encoder) 580 if (encoder->type == type) 581 return true; 582 583 return false; 584 } 585 586 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) 587 /** 588 * Returns whether the given set of divisors are valid for a given refclk with 589 * the given connectors. 590 */ 591 592 static bool intel_PLL_is_valid(struct drm_device *dev, 593 const intel_limit_t *limit, 594 const intel_clock_t *clock) 595 { 596 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 597 INTELPllInvalid("p1 out of range\n"); 598 if (clock->p < limit->p.min || limit->p.max < clock->p) 599 INTELPllInvalid("p out of range\n"); 600 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 601 INTELPllInvalid("m2 out of range\n"); 602 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 603 INTELPllInvalid("m1 out of range\n"); 604 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev)) 605 INTELPllInvalid("m1 <= m2\n"); 606 if (clock->m < limit->m.min || limit->m.max < clock->m) 607 INTELPllInvalid("m out of range\n"); 608 if (clock->n < limit->n.min || limit->n.max < clock->n) 609 INTELPllInvalid("n out of range\n"); 610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 611 INTELPllInvalid("vco out of range\n"); 612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 613 * connector, etc., rather than just a single range. 614 */ 615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 616 INTELPllInvalid("dot out of range\n"); 617 618 return true; 619 } 620 621 static bool 622 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 623 int target, int refclk, intel_clock_t *match_clock, 624 intel_clock_t *best_clock) 625 626 { 627 struct drm_device *dev = crtc->dev; 628 intel_clock_t clock; 629 int err = target; 630 631 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 632 /* 633 * For LVDS just rely on its current settings for dual-channel. 634 * We haven't figured out how to reliably set up different 635 * single/dual channel state, if we even can. 636 */ 637 if (intel_is_dual_link_lvds(dev)) 638 clock.p2 = limit->p2.p2_fast; 639 else 640 clock.p2 = limit->p2.p2_slow; 641 } else { 642 if (target < limit->p2.dot_limit) 643 clock.p2 = limit->p2.p2_slow; 644 else 645 clock.p2 = limit->p2.p2_fast; 646 } 647 648 memset(best_clock, 0, sizeof(*best_clock)); 649 650 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 651 clock.m1++) { 652 for (clock.m2 = limit->m2.min; 653 clock.m2 <= limit->m2.max; clock.m2++) { 654 /* m1 is always 0 in Pineview */ 655 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev)) 656 break; 657 for (clock.n = limit->n.min; 658 clock.n <= limit->n.max; clock.n++) { 659 for (clock.p1 = limit->p1.min; 660 clock.p1 <= limit->p1.max; clock.p1++) { 661 int this_err; 662 663 intel_clock(dev, refclk, &clock); 664 if (!intel_PLL_is_valid(dev, limit, 665 &clock)) 666 continue; 667 if (match_clock && 668 clock.p != match_clock->p) 669 continue; 670 671 this_err = abs(clock.dot - target); 672 if (this_err < err) { 673 *best_clock = clock; 674 err = this_err; 675 } 676 } 677 } 678 } 679 } 680 681 return (err != target); 682 } 683 684 static bool 685 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, 686 int target, int refclk, intel_clock_t *match_clock, 687 intel_clock_t *best_clock) 688 { 689 struct drm_device *dev = crtc->dev; 690 intel_clock_t clock; 691 int max_n; 692 bool found; 693 /* approximately equals target * 0.00585 */ 694 int err_most = (target >> 8) + (target >> 9); 695 found = false; 696 697 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 698 int lvds_reg; 699 700 if (HAS_PCH_SPLIT(dev)) 701 lvds_reg = PCH_LVDS; 702 else 703 lvds_reg = LVDS; 704 if (intel_is_dual_link_lvds(dev)) 705 clock.p2 = limit->p2.p2_fast; 706 else 707 clock.p2 = limit->p2.p2_slow; 708 } else { 709 if (target < limit->p2.dot_limit) 710 clock.p2 = limit->p2.p2_slow; 711 else 712 clock.p2 = limit->p2.p2_fast; 713 } 714 715 memset(best_clock, 0, sizeof(*best_clock)); 716 max_n = limit->n.max; 717 /* based on hardware requirement, prefer smaller n to precision */ 718 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 719 /* based on hardware requirement, prefere larger m1,m2 */ 720 for (clock.m1 = limit->m1.max; 721 clock.m1 >= limit->m1.min; clock.m1--) { 722 for (clock.m2 = limit->m2.max; 723 clock.m2 >= limit->m2.min; clock.m2--) { 724 for (clock.p1 = limit->p1.max; 725 clock.p1 >= limit->p1.min; clock.p1--) { 726 int this_err; 727 728 intel_clock(dev, refclk, &clock); 729 if (!intel_PLL_is_valid(dev, limit, 730 &clock)) 731 continue; 732 if (match_clock && 733 clock.p != match_clock->p) 734 continue; 735 736 this_err = abs(clock.dot - target); 737 if (this_err < err_most) { 738 *best_clock = clock; 739 err_most = this_err; 740 max_n = clock.n; 741 found = true; 742 } 743 } 744 } 745 } 746 } 747 return found; 748 } 749 750 static bool 751 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 752 int target, int refclk, intel_clock_t *match_clock, 753 intel_clock_t *best_clock) 754 { 755 struct drm_device *dev = crtc->dev; 756 intel_clock_t clock; 757 758 if (target < 200000) { 759 clock.n = 1; 760 clock.p1 = 2; 761 clock.p2 = 10; 762 clock.m1 = 12; 763 clock.m2 = 9; 764 } else { 765 clock.n = 2; 766 clock.p1 = 1; 767 clock.p2 = 10; 768 clock.m1 = 14; 769 clock.m2 = 8; 770 } 771 intel_clock(dev, refclk, &clock); 772 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 773 return true; 774 } 775 776 /* DisplayPort has only two frequencies, 162MHz and 270MHz */ 777 static bool 778 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, 779 int target, int refclk, intel_clock_t *match_clock, 780 intel_clock_t *best_clock) 781 { 782 intel_clock_t clock; 783 if (target < 200000) { 784 clock.p1 = 2; 785 clock.p2 = 10; 786 clock.n = 2; 787 clock.m1 = 23; 788 clock.m2 = 8; 789 } else { 790 clock.p1 = 1; 791 clock.p2 = 10; 792 clock.n = 1; 793 clock.m1 = 14; 794 clock.m2 = 2; 795 } 796 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); 797 clock.p = (clock.p1 * clock.p2); 798 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; 799 clock.vco = 0; 800 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 801 return true; 802 } 803 804 static bool 805 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc, 806 int target, int refclk, intel_clock_t *match_clock, 807 intel_clock_t *best_clock) 808 { 809 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2; 810 u32 m, n, fastclk; 811 u32 updrate, minupdate, fracbits, p; 812 unsigned long bestppm, ppm, absppm; 813 int dotclk, flag; 814 815 flag = 0; 816 dotclk = target * 1000; 817 bestppm = 1000000; 818 ppm = absppm = 0; 819 fastclk = dotclk / (2*100); 820 updrate = 0; 821 minupdate = 19200; 822 fracbits = 1; 823 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0; 824 bestm1 = bestm2 = bestp1 = bestp2 = 0; 825 826 /* based on hardware requirement, prefer smaller n to precision */ 827 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) { 828 updrate = refclk / n; 829 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) { 830 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) { 831 if (p2 > 10) 832 p2 = p2 - 1; 833 p = p1 * p2; 834 /* based on hardware requirement, prefer bigger m1,m2 values */ 835 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) { 836 m2 = (((2*(fastclk * p * n / m1 )) + 837 refclk) / (2*refclk)); 838 m = m1 * m2; 839 vco = updrate * m; 840 if (vco >= limit->vco.min && vco < limit->vco.max) { 841 ppm = 1000000 * ((vco / p) - fastclk) / fastclk; 842 absppm = (ppm > 0) ? ppm : (-ppm); 843 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) { 844 bestppm = 0; 845 flag = 1; 846 } 847 if (absppm < bestppm - 10) { 848 bestppm = absppm; 849 flag = 1; 850 } 851 if (flag) { 852 bestn = n; 853 bestm1 = m1; 854 bestm2 = m2; 855 bestp1 = p1; 856 bestp2 = p2; 857 flag = 0; 858 } 859 } 860 } 861 } 862 } 863 } 864 best_clock->n = bestn; 865 best_clock->m1 = bestm1; 866 best_clock->m2 = bestm2; 867 best_clock->p1 = bestp1; 868 best_clock->p2 = bestp2; 869 870 return true; 871 } 872 873 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, 874 enum i915_pipe pipe) 875 { 876 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 878 879 return intel_crtc->cpu_transcoder; 880 } 881 882 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) 883 { 884 struct drm_i915_private *dev_priv = dev->dev_private; 885 u32 frame, frame_reg = PIPEFRAME(pipe); 886 887 frame = I915_READ(frame_reg); 888 889 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) 890 DRM_DEBUG_KMS("vblank wait timed out\n"); 891 } 892 893 /** 894 * intel_wait_for_vblank - wait for vblank on a given pipe 895 * @dev: drm device 896 * @pipe: pipe to wait for 897 * 898 * Wait for vblank to occur on a given pipe. Needed for various bits of 899 * mode setting code. 900 */ 901 void intel_wait_for_vblank(struct drm_device *dev, int pipe) 902 { 903 struct drm_i915_private *dev_priv = dev->dev_private; 904 int pipestat_reg = PIPESTAT(pipe); 905 906 if (INTEL_INFO(dev)->gen >= 5) { 907 ironlake_wait_for_vblank(dev, pipe); 908 return; 909 } 910 911 /* Clear existing vblank status. Note this will clear any other 912 * sticky status fields as well. 913 * 914 * This races with i915_driver_irq_handler() with the result 915 * that either function could miss a vblank event. Here it is not 916 * fatal, as we will either wait upon the next vblank interrupt or 917 * timeout. Generally speaking intel_wait_for_vblank() is only 918 * called during modeset at which time the GPU should be idle and 919 * should *not* be performing page flips and thus not waiting on 920 * vblanks... 921 * Currently, the result of us stealing a vblank from the irq 922 * handler is that a single frame will be skipped during swapbuffers. 923 */ 924 I915_WRITE(pipestat_reg, 925 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); 926 927 /* Wait for vblank interrupt bit to set */ 928 if (wait_for(I915_READ(pipestat_reg) & 929 PIPE_VBLANK_INTERRUPT_STATUS, 930 50)) 931 DRM_DEBUG_KMS("vblank wait timed out\n"); 932 } 933 934 /* 935 * intel_wait_for_pipe_off - wait for pipe to turn off 936 * @dev: drm device 937 * @pipe: pipe to wait for 938 * 939 * After disabling a pipe, we can't wait for vblank in the usual way, 940 * spinning on the vblank interrupt status bit, since we won't actually 941 * see an interrupt when the pipe is disabled. 942 * 943 * On Gen4 and above: 944 * wait for the pipe register state bit to turn off 945 * 946 * Otherwise: 947 * wait for the display line value to settle (it usually 948 * ends up stopping at the start of the next frame). 949 * 950 */ 951 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) 952 { 953 struct drm_i915_private *dev_priv = dev->dev_private; 954 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 955 pipe); 956 957 if (INTEL_INFO(dev)->gen >= 4) { 958 int reg = PIPECONF(cpu_transcoder); 959 960 /* Wait for the Pipe State to go off */ 961 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 962 100)) 963 WARN(1, "pipe_off wait timed out\n"); 964 } else { 965 u32 last_line, line_mask; 966 int reg = PIPEDSL(pipe); 967 unsigned long timeout = jiffies + msecs_to_jiffies(100); 968 969 if (IS_GEN2(dev)) 970 line_mask = DSL_LINEMASK_GEN2; 971 else 972 line_mask = DSL_LINEMASK_GEN3; 973 974 /* Wait for the display line to settle */ 975 do { 976 last_line = I915_READ(reg) & line_mask; 977 mdelay(5); 978 } while (((I915_READ(reg) & line_mask) != last_line) && 979 time_after(timeout, jiffies)); 980 if (time_after(jiffies, timeout)) 981 WARN(1, "pipe_off wait timed out\n"); 982 } 983 } 984 985 /* 986 * ibx_digital_port_connected - is the specified port connected? 987 * @dev_priv: i915 private structure 988 * @port: the port to test 989 * 990 * Returns true if @port is connected, false otherwise. 991 */ 992 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, 993 struct intel_digital_port *port) 994 { 995 u32 bit; 996 997 if (HAS_PCH_IBX(dev_priv->dev)) { 998 switch(port->port) { 999 case PORT_B: 1000 bit = SDE_PORTB_HOTPLUG; 1001 break; 1002 case PORT_C: 1003 bit = SDE_PORTC_HOTPLUG; 1004 break; 1005 case PORT_D: 1006 bit = SDE_PORTD_HOTPLUG; 1007 break; 1008 default: 1009 return true; 1010 } 1011 } else { 1012 switch(port->port) { 1013 case PORT_B: 1014 bit = SDE_PORTB_HOTPLUG_CPT; 1015 break; 1016 case PORT_C: 1017 bit = SDE_PORTC_HOTPLUG_CPT; 1018 break; 1019 case PORT_D: 1020 bit = SDE_PORTD_HOTPLUG_CPT; 1021 break; 1022 default: 1023 return true; 1024 } 1025 } 1026 1027 return I915_READ(SDEISR) & bit; 1028 } 1029 1030 static const char *state_string(bool enabled) 1031 { 1032 return enabled ? "on" : "off"; 1033 } 1034 1035 /* Only for pre-ILK configs */ 1036 static void assert_pll(struct drm_i915_private *dev_priv, 1037 enum i915_pipe pipe, bool state) 1038 { 1039 int reg; 1040 u32 val; 1041 bool cur_state; 1042 1043 reg = DPLL(pipe); 1044 val = I915_READ(reg); 1045 cur_state = !!(val & DPLL_VCO_ENABLE); 1046 WARN(cur_state != state, 1047 "PLL state assertion failure (expected %s, current %s)\n", 1048 state_string(state), state_string(cur_state)); 1049 } 1050 #define assert_pll_enabled(d, p) assert_pll(d, p, true) 1051 #define assert_pll_disabled(d, p) assert_pll(d, p, false) 1052 1053 /* For ILK+ */ 1054 static void assert_pch_pll(struct drm_i915_private *dev_priv, 1055 struct intel_pch_pll *pll, 1056 struct intel_crtc *crtc, 1057 bool state) 1058 { 1059 u32 val; 1060 bool cur_state; 1061 1062 if (HAS_PCH_LPT(dev_priv->dev)) { 1063 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n"); 1064 return; 1065 } 1066 1067 if (WARN (!pll, 1068 "asserting PCH PLL %s with no PLL\n", state_string(state))) 1069 return; 1070 1071 val = I915_READ(pll->pll_reg); 1072 cur_state = !!(val & DPLL_VCO_ENABLE); 1073 WARN(cur_state != state, 1074 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n", 1075 pll->pll_reg, state_string(state), state_string(cur_state), val); 1076 1077 /* Make sure the selected PLL is correctly attached to the transcoder */ 1078 if (crtc && HAS_PCH_CPT(dev_priv->dev)) { 1079 u32 pch_dpll; 1080 1081 pch_dpll = I915_READ(PCH_DPLL_SEL); 1082 cur_state = pll->pll_reg == _PCH_DPLL_B; 1083 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state, 1084 "PLL[%d] not attached to this transcoder %d: %08x\n", 1085 cur_state, crtc->pipe, pch_dpll)) { 1086 cur_state = !!(val >> (4*crtc->pipe + 3)); 1087 WARN(cur_state != state, 1088 "PLL[%d] not %s on this transcoder %d: %08x\n", 1089 pll->pll_reg == _PCH_DPLL_B, 1090 state_string(state), 1091 crtc->pipe, 1092 val); 1093 } 1094 } 1095 } 1096 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true) 1097 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false) 1098 1099 static void assert_fdi_tx(struct drm_i915_private *dev_priv, 1100 enum i915_pipe pipe, bool state) 1101 { 1102 int reg; 1103 u32 val; 1104 bool cur_state; 1105 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1106 pipe); 1107 1108 if (HAS_DDI(dev_priv->dev)) { 1109 /* DDI does not have a specific FDI_TX register */ 1110 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1111 val = I915_READ(reg); 1112 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); 1113 } else { 1114 reg = FDI_TX_CTL(pipe); 1115 val = I915_READ(reg); 1116 cur_state = !!(val & FDI_TX_ENABLE); 1117 } 1118 WARN(cur_state != state, 1119 "FDI TX state assertion failure (expected %s, current %s)\n", 1120 state_string(state), state_string(cur_state)); 1121 } 1122 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) 1123 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) 1124 1125 static void assert_fdi_rx(struct drm_i915_private *dev_priv, 1126 enum i915_pipe pipe, bool state) 1127 { 1128 int reg; 1129 u32 val; 1130 bool cur_state; 1131 1132 reg = FDI_RX_CTL(pipe); 1133 val = I915_READ(reg); 1134 cur_state = !!(val & FDI_RX_ENABLE); 1135 WARN(cur_state != state, 1136 "FDI RX state assertion failure (expected %s, current %s)\n", 1137 state_string(state), state_string(cur_state)); 1138 } 1139 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) 1140 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) 1141 1142 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, 1143 enum i915_pipe pipe) 1144 { 1145 int reg; 1146 u32 val; 1147 1148 /* ILK FDI PLL is always enabled */ 1149 if (dev_priv->info->gen == 5) 1150 return; 1151 1152 /* On Haswell, DDI ports are responsible for the FDI PLL setup */ 1153 if (HAS_DDI(dev_priv->dev)) 1154 return; 1155 1156 reg = FDI_TX_CTL(pipe); 1157 val = I915_READ(reg); 1158 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); 1159 } 1160 1161 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv, 1162 enum i915_pipe pipe) 1163 { 1164 int reg; 1165 u32 val; 1166 1167 reg = FDI_RX_CTL(pipe); 1168 val = I915_READ(reg); 1169 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n"); 1170 } 1171 1172 static void assert_panel_unlocked(struct drm_i915_private *dev_priv, 1173 enum i915_pipe pipe) 1174 { 1175 int pp_reg, lvds_reg; 1176 u32 val; 1177 enum i915_pipe panel_pipe = PIPE_A; 1178 bool locked = true; 1179 1180 if (HAS_PCH_SPLIT(dev_priv->dev)) { 1181 pp_reg = PCH_PP_CONTROL; 1182 lvds_reg = PCH_LVDS; 1183 } else { 1184 pp_reg = PP_CONTROL; 1185 lvds_reg = LVDS; 1186 } 1187 1188 val = I915_READ(pp_reg); 1189 if (!(val & PANEL_POWER_ON) || 1190 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS)) 1191 locked = false; 1192 1193 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT) 1194 panel_pipe = PIPE_B; 1195 1196 WARN(panel_pipe == pipe && locked, 1197 "panel assertion failure, pipe %c regs locked\n", 1198 pipe_name(pipe)); 1199 } 1200 1201 void assert_pipe(struct drm_i915_private *dev_priv, 1202 enum i915_pipe pipe, bool state) 1203 { 1204 int reg; 1205 u32 val; 1206 bool cur_state; 1207 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1208 pipe); 1209 1210 /* if we need the pipe A quirk it must be always on */ 1211 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) 1212 state = true; 1213 1214 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP && 1215 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) { 1216 cur_state = false; 1217 } else { 1218 reg = PIPECONF(cpu_transcoder); 1219 val = I915_READ(reg); 1220 cur_state = !!(val & PIPECONF_ENABLE); 1221 } 1222 1223 WARN(cur_state != state, 1224 "pipe %c assertion failure (expected %s, current %s)\n", 1225 pipe_name(pipe), state_string(state), state_string(cur_state)); 1226 } 1227 1228 static void assert_plane(struct drm_i915_private *dev_priv, 1229 enum plane plane, bool state) 1230 { 1231 int reg; 1232 u32 val; 1233 bool cur_state; 1234 1235 reg = DSPCNTR(plane); 1236 val = I915_READ(reg); 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE); 1238 WARN(cur_state != state, 1239 "plane %c assertion failure (expected %s, current %s)\n", 1240 plane_name(plane), state_string(state), state_string(cur_state)); 1241 } 1242 1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true) 1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false) 1245 1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv, 1247 enum i915_pipe pipe) 1248 { 1249 int reg, i; 1250 u32 val; 1251 int cur_pipe; 1252 1253 /* Planes are fixed to pipes on ILK+ */ 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) { 1255 reg = DSPCNTR(pipe); 1256 val = I915_READ(reg); 1257 WARN((val & DISPLAY_PLANE_ENABLE), 1258 "plane %c assertion failure, should be disabled but not\n", 1259 plane_name(pipe)); 1260 return; 1261 } 1262 1263 /* Need to check both planes against the pipe */ 1264 for (i = 0; i < 2; i++) { 1265 reg = DSPCNTR(i); 1266 val = I915_READ(reg); 1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> 1268 DISPPLANE_SEL_PIPE_SHIFT; 1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n", 1271 plane_name(i), pipe_name(pipe)); 1272 } 1273 } 1274 1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) 1276 { 1277 u32 val; 1278 bool enabled; 1279 1280 if (HAS_PCH_LPT(dev_priv->dev)) { 1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n"); 1282 return; 1283 } 1284 1285 val = I915_READ(PCH_DREF_CONTROL); 1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | 1287 DREF_SUPERSPREAD_SOURCE_MASK)); 1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); 1289 } 1290 1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv, 1292 enum i915_pipe pipe) 1293 { 1294 int reg; 1295 u32 val; 1296 bool enabled; 1297 1298 reg = TRANSCONF(pipe); 1299 val = I915_READ(reg); 1300 enabled = !!(val & TRANS_ENABLE); 1301 WARN(enabled, 1302 "transcoder assertion failed, should be off on pipe %c but is still active\n", 1303 pipe_name(pipe)); 1304 } 1305 1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, 1307 enum i915_pipe pipe, u32 port_sel, u32 val) 1308 { 1309 if ((val & DP_PORT_EN) == 0) 1310 return false; 1311 1312 if (HAS_PCH_CPT(dev_priv->dev)) { 1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); 1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); 1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) 1316 return false; 1317 } else { 1318 if ((val & DP_PIPE_MASK) != (pipe << 30)) 1319 return false; 1320 } 1321 return true; 1322 } 1323 1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, 1325 enum i915_pipe pipe, u32 val) 1326 { 1327 if ((val & PORT_ENABLE) == 0) 1328 return false; 1329 1330 if (HAS_PCH_CPT(dev_priv->dev)) { 1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1332 return false; 1333 } else { 1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe)) 1335 return false; 1336 } 1337 return true; 1338 } 1339 1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, 1341 enum i915_pipe pipe, u32 val) 1342 { 1343 if ((val & LVDS_PORT_EN) == 0) 1344 return false; 1345 1346 if (HAS_PCH_CPT(dev_priv->dev)) { 1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1348 return false; 1349 } else { 1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) 1351 return false; 1352 } 1353 return true; 1354 } 1355 1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, 1357 enum i915_pipe pipe, u32 val) 1358 { 1359 if ((val & ADPA_DAC_ENABLE) == 0) 1360 return false; 1361 if (HAS_PCH_CPT(dev_priv->dev)) { 1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) 1363 return false; 1364 } else { 1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) 1366 return false; 1367 } 1368 return true; 1369 } 1370 1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, 1372 enum i915_pipe pipe, int reg, u32 port_sel) 1373 { 1374 u32 val = I915_READ(reg); 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", 1377 reg, pipe_name(pipe)); 1378 1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 1380 && (val & DP_PIPEB_SELECT), 1381 "IBX PCH dp port still using transcoder B\n"); 1382 } 1383 1384 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, 1385 enum i915_pipe pipe, int reg) 1386 { 1387 u32 val = I915_READ(reg); 1388 WARN(hdmi_pipe_enabled(dev_priv, pipe, val), 1389 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", 1390 reg, pipe_name(pipe)); 1391 1392 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0 1393 && (val & SDVO_PIPE_B_SELECT), 1394 "IBX PCH hdmi port still using transcoder B\n"); 1395 } 1396 1397 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, 1398 enum i915_pipe pipe) 1399 { 1400 int reg; 1401 u32 val; 1402 1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); 1404 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); 1405 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); 1406 1407 reg = PCH_ADPA; 1408 val = I915_READ(reg); 1409 WARN(adpa_pipe_enabled(dev_priv, pipe, val), 1410 "PCH VGA enabled on transcoder %c, should be disabled\n", 1411 pipe_name(pipe)); 1412 1413 reg = PCH_LVDS; 1414 val = I915_READ(reg); 1415 WARN(lvds_pipe_enabled(dev_priv, pipe, val), 1416 "PCH LVDS enabled on transcoder %c, should be disabled\n", 1417 pipe_name(pipe)); 1418 1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB); 1420 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC); 1421 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID); 1422 } 1423 1424 /** 1425 * intel_enable_pll - enable a PLL 1426 * @dev_priv: i915 private structure 1427 * @pipe: pipe PLL to enable 1428 * 1429 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to 1430 * make sure the PLL reg is writable first though, since the panel write 1431 * protect mechanism may be enabled. 1432 * 1433 * Note! This is for pre-ILK only. 1434 * 1435 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running. 1436 */ 1437 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1438 { 1439 int reg; 1440 u32 val; 1441 1442 /* No really, not for ILK+ */ 1443 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5); 1444 1445 /* PLL is protected by panel, make sure we can write it */ 1446 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev)) 1447 assert_panel_unlocked(dev_priv, pipe); 1448 1449 reg = DPLL(pipe); 1450 val = I915_READ(reg); 1451 val |= DPLL_VCO_ENABLE; 1452 1453 /* We do this three times for luck */ 1454 I915_WRITE(reg, val); 1455 POSTING_READ(reg); 1456 udelay(150); /* wait for warmup */ 1457 I915_WRITE(reg, val); 1458 POSTING_READ(reg); 1459 udelay(150); /* wait for warmup */ 1460 I915_WRITE(reg, val); 1461 POSTING_READ(reg); 1462 udelay(150); /* wait for warmup */ 1463 } 1464 1465 /** 1466 * intel_disable_pll - disable a PLL 1467 * @dev_priv: i915 private structure 1468 * @pipe: pipe PLL to disable 1469 * 1470 * Disable the PLL for @pipe, making sure the pipe is off first. 1471 * 1472 * Note! This is for pre-ILK only. 1473 */ 1474 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 1475 { 1476 int reg; 1477 u32 val; 1478 1479 /* Don't disable pipe A or pipe A PLLs if needed */ 1480 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1481 return; 1482 1483 /* Make sure the pipe isn't still relying on us */ 1484 assert_pipe_disabled(dev_priv, pipe); 1485 1486 reg = DPLL(pipe); 1487 val = I915_READ(reg); 1488 val &= ~DPLL_VCO_ENABLE; 1489 I915_WRITE(reg, val); 1490 POSTING_READ(reg); 1491 } 1492 1493 /* SBI access */ 1494 static void 1495 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 1496 enum intel_sbi_destination destination) 1497 { 1498 u32 tmp; 1499 1500 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 1501 1502 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) { 1503 DRM_ERROR("timeout waiting for SBI to become ready\n"); 1504 return; 1505 } 1506 1507 I915_WRITE(SBI_ADDR, (reg << 16)); 1508 I915_WRITE(SBI_DATA, value); 1509 1510 if (destination == SBI_ICLK) 1511 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; 1512 else 1513 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; 1514 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); 1515 1516 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, 1517 100)) { 1518 DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); 1519 return; 1520 } 1521 } 1522 1523 static u32 1524 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, 1525 enum intel_sbi_destination destination) 1526 { 1527 u32 value = 0; 1528 1529 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); 1530 1531 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, 100)) { 1532 DRM_ERROR("timeout waiting for SBI to become ready\n"); 1533 return 0; 1534 } 1535 1536 I915_WRITE(SBI_ADDR, (reg << 16)); 1537 1538 if (destination == SBI_ICLK) 1539 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; 1540 else 1541 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; 1542 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); 1543 1544 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, 1545 100)) { 1546 DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); 1547 return 0; 1548 } 1549 1550 return I915_READ(SBI_DATA); 1551 } 1552 1553 /** 1554 * ironlake_enable_pch_pll - enable PCH PLL 1555 * @dev_priv: i915 private structure 1556 * @pipe: pipe PLL to enable 1557 * 1558 * The PCH PLL needs to be enabled before the PCH transcoder, since it 1559 * drives the transcoder clock. 1560 */ 1561 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc) 1562 { 1563 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1564 struct intel_pch_pll *pll; 1565 int reg; 1566 u32 val; 1567 1568 /* PCH PLLs only available on ILK, SNB and IVB */ 1569 BUG_ON(dev_priv->info->gen < 5); 1570 pll = intel_crtc->pch_pll; 1571 if (pll == NULL) 1572 return; 1573 1574 if (WARN_ON(pll->refcount == 0)) 1575 return; 1576 1577 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n", 1578 pll->pll_reg, pll->active, pll->on, 1579 intel_crtc->base.base.id); 1580 1581 /* PCH refclock must be enabled first */ 1582 assert_pch_refclk_enabled(dev_priv); 1583 1584 if (pll->active++ && pll->on) { 1585 assert_pch_pll_enabled(dev_priv, pll, NULL); 1586 return; 1587 } 1588 1589 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg); 1590 1591 reg = pll->pll_reg; 1592 val = I915_READ(reg); 1593 val |= DPLL_VCO_ENABLE; 1594 I915_WRITE(reg, val); 1595 POSTING_READ(reg); 1596 udelay(200); 1597 1598 pll->on = true; 1599 } 1600 1601 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc) 1602 { 1603 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 1604 struct intel_pch_pll *pll = intel_crtc->pch_pll; 1605 int reg; 1606 u32 val; 1607 1608 /* PCH only available on ILK+ */ 1609 BUG_ON(dev_priv->info->gen < 5); 1610 if (pll == NULL) 1611 return; 1612 1613 if (WARN_ON(pll->refcount == 0)) 1614 return; 1615 1616 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n", 1617 pll->pll_reg, pll->active, pll->on, 1618 intel_crtc->base.base.id); 1619 1620 if (WARN_ON(pll->active == 0)) { 1621 assert_pch_pll_disabled(dev_priv, pll, NULL); 1622 return; 1623 } 1624 1625 if (--pll->active) { 1626 assert_pch_pll_enabled(dev_priv, pll, NULL); 1627 return; 1628 } 1629 1630 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg); 1631 1632 /* Make sure transcoder isn't still depending on us */ 1633 assert_transcoder_disabled(dev_priv, intel_crtc->pipe); 1634 1635 reg = pll->pll_reg; 1636 val = I915_READ(reg); 1637 val &= ~DPLL_VCO_ENABLE; 1638 I915_WRITE(reg, val); 1639 POSTING_READ(reg); 1640 udelay(200); 1641 1642 pll->on = false; 1643 } 1644 1645 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1646 enum i915_pipe pipe) 1647 { 1648 struct drm_device *dev = dev_priv->dev; 1649 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 1650 uint32_t reg, val, pipeconf_val; 1651 1652 /* PCH only available on ILK+ */ 1653 BUG_ON(dev_priv->info->gen < 5); 1654 1655 /* Make sure PCH DPLL is enabled */ 1656 assert_pch_pll_enabled(dev_priv, 1657 to_intel_crtc(crtc)->pch_pll, 1658 to_intel_crtc(crtc)); 1659 1660 /* FDI must be feeding us bits for PCH ports */ 1661 assert_fdi_tx_enabled(dev_priv, pipe); 1662 assert_fdi_rx_enabled(dev_priv, pipe); 1663 1664 if (HAS_PCH_CPT(dev)) { 1665 /* Workaround: Set the timing override bit before enabling the 1666 * pch transcoder. */ 1667 reg = TRANS_CHICKEN2(pipe); 1668 val = I915_READ(reg); 1669 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 1670 I915_WRITE(reg, val); 1671 } 1672 1673 reg = TRANSCONF(pipe); 1674 val = I915_READ(reg); 1675 pipeconf_val = I915_READ(PIPECONF(pipe)); 1676 1677 if (HAS_PCH_IBX(dev_priv->dev)) { 1678 /* 1679 * make the BPC in transcoder be consistent with 1680 * that in pipeconf reg. 1681 */ 1682 val &= ~PIPECONF_BPC_MASK; 1683 val |= pipeconf_val & PIPECONF_BPC_MASK; 1684 } 1685 1686 val &= ~TRANS_INTERLACE_MASK; 1687 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) 1688 if (HAS_PCH_IBX(dev_priv->dev) && 1689 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) 1690 val |= TRANS_LEGACY_INTERLACED_ILK; 1691 else 1692 val |= TRANS_INTERLACED; 1693 else 1694 val |= TRANS_PROGRESSIVE; 1695 1696 I915_WRITE(reg, val | TRANS_ENABLE); 1697 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) 1698 DRM_ERROR("failed to enable transcoder %d\n", pipe); 1699 } 1700 1701 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, 1702 enum transcoder cpu_transcoder) 1703 { 1704 u32 val, pipeconf_val; 1705 1706 /* PCH only available on ILK+ */ 1707 BUG_ON(dev_priv->info->gen < 5); 1708 1709 /* FDI must be feeding us bits for PCH ports */ 1710 assert_fdi_tx_enabled(dev_priv, (enum i915_pipe) cpu_transcoder); 1711 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); 1712 1713 /* Workaround: set timing override bit. */ 1714 val = I915_READ(_TRANSA_CHICKEN2); 1715 val |= TRANS_CHICKEN2_TIMING_OVERRIDE; 1716 I915_WRITE(_TRANSA_CHICKEN2, val); 1717 1718 val = TRANS_ENABLE; 1719 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); 1720 1721 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == 1722 PIPECONF_INTERLACED_ILK) 1723 val |= TRANS_INTERLACED; 1724 else 1725 val |= TRANS_PROGRESSIVE; 1726 1727 I915_WRITE(TRANSCONF(TRANSCODER_A), val); 1728 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100)) 1729 DRM_ERROR("Failed to enable PCH transcoder\n"); 1730 } 1731 1732 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, 1733 enum i915_pipe pipe) 1734 { 1735 struct drm_device *dev = dev_priv->dev; 1736 uint32_t reg, val; 1737 1738 /* FDI relies on the transcoder */ 1739 assert_fdi_tx_disabled(dev_priv, pipe); 1740 assert_fdi_rx_disabled(dev_priv, pipe); 1741 1742 /* Ports must be off as well */ 1743 assert_pch_ports_disabled(dev_priv, pipe); 1744 1745 reg = TRANSCONF(pipe); 1746 val = I915_READ(reg); 1747 val &= ~TRANS_ENABLE; 1748 I915_WRITE(reg, val); 1749 /* wait for PCH transcoder off, transcoder state */ 1750 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) 1751 DRM_ERROR("failed to disable transcoder %d\n", pipe); 1752 1753 if (!HAS_PCH_IBX(dev)) { 1754 /* Workaround: Clear the timing override chicken bit again. */ 1755 reg = TRANS_CHICKEN2(pipe); 1756 val = I915_READ(reg); 1757 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 1758 I915_WRITE(reg, val); 1759 } 1760 } 1761 1762 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 1763 { 1764 u32 val; 1765 1766 val = I915_READ(_TRANSACONF); 1767 val &= ~TRANS_ENABLE; 1768 I915_WRITE(_TRANSACONF, val); 1769 /* wait for PCH transcoder off, transcoder state */ 1770 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50)) 1771 DRM_ERROR("Failed to disable PCH transcoder\n"); 1772 1773 /* Workaround: clear timing override bit. */ 1774 val = I915_READ(_TRANSA_CHICKEN2); 1775 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; 1776 I915_WRITE(_TRANSA_CHICKEN2, val); 1777 } 1778 1779 /** 1780 * intel_enable_pipe - enable a pipe, asserting requirements 1781 * @dev_priv: i915 private structure 1782 * @pipe: pipe to enable 1783 * @pch_port: on ILK+, is this pipe driving a PCH port or not 1784 * 1785 * Enable @pipe, making sure that various hardware specific requirements 1786 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. 1787 * 1788 * @pipe should be %PIPE_A or %PIPE_B. 1789 * 1790 * Will wait until the pipe is actually running (i.e. first vblank) before 1791 * returning. 1792 */ 1793 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum i915_pipe pipe, 1794 bool pch_port) 1795 { 1796 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1797 pipe); 1798 enum i915_pipe pch_transcoder; 1799 int reg; 1800 u32 val; 1801 1802 if (HAS_PCH_LPT(dev_priv->dev)) 1803 pch_transcoder = TRANSCODER_A; 1804 else 1805 pch_transcoder = pipe; 1806 1807 /* 1808 * A pipe without a PLL won't actually be able to drive bits from 1809 * a plane. On ILK+ the pipe PLLs are integrated, so we don't 1810 * need the check. 1811 */ 1812 if (!HAS_PCH_SPLIT(dev_priv->dev)) 1813 assert_pll_enabled(dev_priv, pipe); 1814 else { 1815 if (pch_port) { 1816 /* if driving the PCH, we need FDI enabled */ 1817 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); 1818 assert_fdi_tx_pll_enabled(dev_priv, 1819 (enum i915_pipe) cpu_transcoder); 1820 } 1821 /* FIXME: assert CPU port conditions for SNB+ */ 1822 } 1823 1824 reg = PIPECONF(cpu_transcoder); 1825 val = I915_READ(reg); 1826 if (val & PIPECONF_ENABLE) 1827 return; 1828 1829 I915_WRITE(reg, val | PIPECONF_ENABLE); 1830 intel_wait_for_vblank(dev_priv->dev, pipe); 1831 } 1832 1833 /** 1834 * intel_disable_pipe - disable a pipe, asserting requirements 1835 * @dev_priv: i915 private structure 1836 * @pipe: pipe to disable 1837 * 1838 * Disable @pipe, making sure that various hardware specific requirements 1839 * are met, if applicable, e.g. plane disabled, panel fitter off, etc. 1840 * 1841 * @pipe should be %PIPE_A or %PIPE_B. 1842 * 1843 * Will wait until the pipe has shut down before returning. 1844 */ 1845 static void intel_disable_pipe(struct drm_i915_private *dev_priv, 1846 enum i915_pipe pipe) 1847 { 1848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, 1849 pipe); 1850 int reg; 1851 u32 val; 1852 1853 /* 1854 * Make sure planes won't keep trying to pump pixels to us, 1855 * or we might hang the display. 1856 */ 1857 assert_planes_disabled(dev_priv, pipe); 1858 1859 /* Don't disable pipe A or pipe A PLLs if needed */ 1860 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) 1861 return; 1862 1863 reg = PIPECONF(cpu_transcoder); 1864 val = I915_READ(reg); 1865 if ((val & PIPECONF_ENABLE) == 0) 1866 return; 1867 1868 I915_WRITE(reg, val & ~PIPECONF_ENABLE); 1869 intel_wait_for_pipe_off(dev_priv->dev, pipe); 1870 } 1871 1872 /* 1873 * Plane regs are double buffered, going from enabled->disabled needs a 1874 * trigger in order to latch. The display address reg provides this. 1875 */ 1876 void intel_flush_display_plane(struct drm_i915_private *dev_priv, 1877 enum plane plane) 1878 { 1879 if (dev_priv->info->gen >= 4) 1880 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane))); 1881 else 1882 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); 1883 } 1884 1885 /** 1886 * intel_enable_plane - enable a display plane on a given pipe 1887 * @dev_priv: i915 private structure 1888 * @plane: plane to enable 1889 * @pipe: pipe being fed 1890 * 1891 * Enable @plane on @pipe, making sure that @pipe is running first. 1892 */ 1893 static void intel_enable_plane(struct drm_i915_private *dev_priv, 1894 enum plane plane, enum i915_pipe pipe) 1895 { 1896 int reg; 1897 u32 val; 1898 1899 /* If the pipe isn't enabled, we can't pump pixels and may hang */ 1900 assert_pipe_enabled(dev_priv, pipe); 1901 1902 reg = DSPCNTR(plane); 1903 val = I915_READ(reg); 1904 if (val & DISPLAY_PLANE_ENABLE) 1905 return; 1906 1907 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); 1908 intel_flush_display_plane(dev_priv, plane); 1909 intel_wait_for_vblank(dev_priv->dev, pipe); 1910 } 1911 1912 /** 1913 * intel_disable_plane - disable a display plane 1914 * @dev_priv: i915 private structure 1915 * @plane: plane to disable 1916 * @pipe: pipe consuming the data 1917 * 1918 * Disable @plane; should be an independent operation. 1919 */ 1920 static void intel_disable_plane(struct drm_i915_private *dev_priv, 1921 enum plane plane, enum i915_pipe pipe) 1922 { 1923 int reg; 1924 u32 val; 1925 1926 reg = DSPCNTR(plane); 1927 val = I915_READ(reg); 1928 if ((val & DISPLAY_PLANE_ENABLE) == 0) 1929 return; 1930 1931 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); 1932 intel_flush_display_plane(dev_priv, plane); 1933 intel_wait_for_vblank(dev_priv->dev, pipe); 1934 } 1935 1936 int 1937 intel_pin_and_fence_fb_obj(struct drm_device *dev, 1938 struct drm_i915_gem_object *obj, 1939 struct intel_ring_buffer *pipelined) 1940 { 1941 struct drm_i915_private *dev_priv = dev->dev_private; 1942 u32 alignment; 1943 int ret; 1944 1945 switch (obj->tiling_mode) { 1946 case I915_TILING_NONE: 1947 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) 1948 alignment = 128 * 1024; 1949 else if (INTEL_INFO(dev)->gen >= 4) 1950 alignment = 4 * 1024; 1951 else 1952 alignment = 64 * 1024; 1953 break; 1954 case I915_TILING_X: 1955 /* pin() will align the object as required by fence */ 1956 alignment = 0; 1957 break; 1958 case I915_TILING_Y: 1959 /* FIXME: Is this true? */ 1960 DRM_ERROR("Y tiled not allowed for scan out buffers\n"); 1961 return -EINVAL; 1962 default: 1963 BUG(); 1964 } 1965 1966 dev_priv->mm.interruptible = false; 1967 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); 1968 if (ret) 1969 goto err_interruptible; 1970 1971 /* Install a fence for tiled scan-out. Pre-i965 always needs a 1972 * fence, whereas 965+ only requires a fence if using 1973 * framebuffer compression. For simplicity, we always install 1974 * a fence as the cost is not that onerous. 1975 */ 1976 ret = i915_gem_object_get_fence(obj); 1977 if (ret) 1978 goto err_unpin; 1979 1980 i915_gem_object_pin_fence(obj); 1981 1982 dev_priv->mm.interruptible = true; 1983 return 0; 1984 1985 err_unpin: 1986 i915_gem_object_unpin(obj); 1987 err_interruptible: 1988 dev_priv->mm.interruptible = true; 1989 return ret; 1990 } 1991 1992 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) 1993 { 1994 i915_gem_object_unpin_fence(obj); 1995 i915_gem_object_unpin(obj); 1996 } 1997 1998 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel 1999 * is assumed to be a power-of-two. */ 2000 unsigned long intel_gen4_compute_page_offset(int *x, int *y, 2001 unsigned int tiling_mode, 2002 unsigned int cpp, 2003 unsigned int pitch) 2004 { 2005 if (tiling_mode != I915_TILING_NONE) { 2006 unsigned int tile_rows, tiles; 2007 2008 tile_rows = *y / 8; 2009 *y %= 8; 2010 2011 tiles = *x / (512/cpp); 2012 *x %= 512/cpp; 2013 2014 return tile_rows * pitch * 8 + tiles * 4096; 2015 } else { 2016 unsigned int offset; 2017 2018 offset = *y * pitch + *x * cpp; 2019 *y = 0; 2020 *x = (offset & 4095) / cpp; 2021 return offset & -4096; 2022 } 2023 } 2024 2025 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, 2026 int x, int y) 2027 { 2028 struct drm_device *dev = crtc->dev; 2029 struct drm_i915_private *dev_priv = dev->dev_private; 2030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2031 struct intel_framebuffer *intel_fb; 2032 struct drm_i915_gem_object *obj; 2033 int plane = intel_crtc->plane; 2034 unsigned long linear_offset; 2035 u32 dspcntr; 2036 u32 reg; 2037 2038 switch (plane) { 2039 case 0: 2040 case 1: 2041 break; 2042 default: 2043 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 2044 return -EINVAL; 2045 } 2046 2047 intel_fb = to_intel_framebuffer(fb); 2048 obj = intel_fb->obj; 2049 2050 reg = DSPCNTR(plane); 2051 dspcntr = I915_READ(reg); 2052 /* Mask out pixel format bits in case we change it */ 2053 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 2054 switch (fb->pixel_format) { 2055 case DRM_FORMAT_C8: 2056 dspcntr |= DISPPLANE_8BPP; 2057 break; 2058 case DRM_FORMAT_XRGB1555: 2059 case DRM_FORMAT_ARGB1555: 2060 dspcntr |= DISPPLANE_BGRX555; 2061 break; 2062 case DRM_FORMAT_RGB565: 2063 dspcntr |= DISPPLANE_BGRX565; 2064 break; 2065 case DRM_FORMAT_XRGB8888: 2066 case DRM_FORMAT_ARGB8888: 2067 dspcntr |= DISPPLANE_BGRX888; 2068 break; 2069 case DRM_FORMAT_XBGR8888: 2070 case DRM_FORMAT_ABGR8888: 2071 dspcntr |= DISPPLANE_RGBX888; 2072 break; 2073 case DRM_FORMAT_XRGB2101010: 2074 case DRM_FORMAT_ARGB2101010: 2075 dspcntr |= DISPPLANE_BGRX101010; 2076 break; 2077 case DRM_FORMAT_XBGR2101010: 2078 case DRM_FORMAT_ABGR2101010: 2079 dspcntr |= DISPPLANE_RGBX101010; 2080 break; 2081 default: 2082 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); 2083 return -EINVAL; 2084 } 2085 2086 if (INTEL_INFO(dev)->gen >= 4) { 2087 if (obj->tiling_mode != I915_TILING_NONE) 2088 dspcntr |= DISPPLANE_TILED; 2089 else 2090 dspcntr &= ~DISPPLANE_TILED; 2091 } 2092 2093 I915_WRITE(reg, dspcntr); 2094 2095 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 2096 2097 if (INTEL_INFO(dev)->gen >= 4) { 2098 intel_crtc->dspaddr_offset = 2099 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, 2100 fb->bits_per_pixel / 8, 2101 fb->pitches[0]); 2102 linear_offset -= intel_crtc->dspaddr_offset; 2103 } else { 2104 intel_crtc->dspaddr_offset = linear_offset; 2105 } 2106 2107 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", 2108 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); 2109 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 2110 if (INTEL_INFO(dev)->gen >= 4) { 2111 I915_MODIFY_DISPBASE(DSPSURF(plane), 2112 obj->gtt_offset + intel_crtc->dspaddr_offset); 2113 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 2114 I915_WRITE(DSPLINOFF(plane), linear_offset); 2115 } else 2116 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset); 2117 POSTING_READ(reg); 2118 2119 return 0; 2120 } 2121 2122 static int ironlake_update_plane(struct drm_crtc *crtc, 2123 struct drm_framebuffer *fb, int x, int y) 2124 { 2125 struct drm_device *dev = crtc->dev; 2126 struct drm_i915_private *dev_priv = dev->dev_private; 2127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2128 struct intel_framebuffer *intel_fb; 2129 struct drm_i915_gem_object *obj; 2130 int plane = intel_crtc->plane; 2131 unsigned long linear_offset; 2132 u32 dspcntr; 2133 u32 reg; 2134 2135 switch (plane) { 2136 case 0: 2137 case 1: 2138 case 2: 2139 break; 2140 default: 2141 DRM_ERROR("Can't update plane %d in SAREA\n", plane); 2142 return -EINVAL; 2143 } 2144 2145 intel_fb = to_intel_framebuffer(fb); 2146 obj = intel_fb->obj; 2147 2148 reg = DSPCNTR(plane); 2149 dspcntr = I915_READ(reg); 2150 /* Mask out pixel format bits in case we change it */ 2151 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK; 2152 switch (fb->pixel_format) { 2153 case DRM_FORMAT_C8: 2154 dspcntr |= DISPPLANE_8BPP; 2155 break; 2156 case DRM_FORMAT_RGB565: 2157 dspcntr |= DISPPLANE_BGRX565; 2158 break; 2159 case DRM_FORMAT_XRGB8888: 2160 case DRM_FORMAT_ARGB8888: 2161 dspcntr |= DISPPLANE_BGRX888; 2162 break; 2163 case DRM_FORMAT_XBGR8888: 2164 case DRM_FORMAT_ABGR8888: 2165 dspcntr |= DISPPLANE_RGBX888; 2166 break; 2167 case DRM_FORMAT_XRGB2101010: 2168 case DRM_FORMAT_ARGB2101010: 2169 dspcntr |= DISPPLANE_BGRX101010; 2170 break; 2171 case DRM_FORMAT_XBGR2101010: 2172 case DRM_FORMAT_ABGR2101010: 2173 dspcntr |= DISPPLANE_RGBX101010; 2174 break; 2175 default: 2176 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format); 2177 return -EINVAL; 2178 } 2179 2180 if (obj->tiling_mode != I915_TILING_NONE) 2181 dspcntr |= DISPPLANE_TILED; 2182 else 2183 dspcntr &= ~DISPPLANE_TILED; 2184 2185 /* must disable */ 2186 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; 2187 2188 I915_WRITE(reg, dspcntr); 2189 2190 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8); 2191 intel_crtc->dspaddr_offset = 2192 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, 2193 fb->bits_per_pixel / 8, 2194 fb->pitches[0]); 2195 linear_offset -= intel_crtc->dspaddr_offset; 2196 2197 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n", 2198 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]); 2199 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); 2200 I915_MODIFY_DISPBASE(DSPSURF(plane), 2201 obj->gtt_offset + intel_crtc->dspaddr_offset); 2202 if (IS_HASWELL(dev)) { 2203 I915_WRITE(DSPOFFSET(plane), (y << 16) | x); 2204 } else { 2205 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); 2206 I915_WRITE(DSPLINOFF(plane), linear_offset); 2207 } 2208 POSTING_READ(reg); 2209 2210 return 0; 2211 } 2212 2213 /* Assume fb object is pinned & idle & fenced and just update base pointers */ 2214 static int 2215 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, 2216 int x, int y, enum mode_set_atomic state) 2217 { 2218 struct drm_device *dev = crtc->dev; 2219 struct drm_i915_private *dev_priv = dev->dev_private; 2220 2221 if (dev_priv->display.disable_fbc) 2222 dev_priv->display.disable_fbc(dev); 2223 intel_increase_pllclock(crtc); 2224 2225 return dev_priv->display.update_plane(crtc, fb, x, y); 2226 } 2227 2228 static int 2229 intel_finish_fb(struct drm_framebuffer *old_fb) 2230 { 2231 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj; 2232 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 2233 bool was_interruptible = dev_priv->mm.interruptible; 2234 int ret; 2235 2236 /* Big Hammer, we also need to ensure that any pending 2237 * MI_WAIT_FOR_EVENT inside a user batch buffer on the 2238 * current scanout is retired before unpinning the old 2239 * framebuffer. 2240 * 2241 * This should only fail upon a hung GPU, in which case we 2242 * can safely continue. 2243 */ 2244 dev_priv->mm.interruptible = false; 2245 ret = i915_gem_object_finish_gpu(obj); 2246 dev_priv->mm.interruptible = was_interruptible; 2247 2248 return ret; 2249 } 2250 2251 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y) 2252 { 2253 struct drm_device *dev = crtc->dev; 2254 #if 0 2255 struct drm_i915_master_private *master_priv; 2256 #else 2257 drm_i915_private_t *dev_priv = dev->dev_private; 2258 #endif 2259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2260 2261 #if 0 2262 if (!dev->primary->master) 2263 return; 2264 2265 master_priv = dev->primary->master->driver_priv; 2266 if (!master_priv->sarea_priv) 2267 return; 2268 #else 2269 if (!dev_priv->sarea_priv) 2270 return; 2271 #endif 2272 2273 switch (intel_crtc->pipe) { 2274 case 0: 2275 #if 0 2276 master_priv->sarea_priv->pipeA_x = x; 2277 master_priv->sarea_priv->pipeA_y = y; 2278 #else 2279 dev_priv->sarea_priv->planeA_x = x; 2280 dev_priv->sarea_priv->planeA_y = y; 2281 #endif 2282 break; 2283 case 1: 2284 #if 0 2285 master_priv->sarea_priv->pipeB_x = x; 2286 master_priv->sarea_priv->pipeB_y = y; 2287 #else 2288 dev_priv->sarea_priv->planeB_x = x; 2289 dev_priv->sarea_priv->planeB_y = y; 2290 #endif 2291 break; 2292 default: 2293 break; 2294 } 2295 } 2296 2297 static int 2298 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, 2299 struct drm_framebuffer *fb) 2300 { 2301 struct drm_device *dev = crtc->dev; 2302 struct drm_i915_private *dev_priv = dev->dev_private; 2303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2304 struct drm_framebuffer *old_fb; 2305 int ret; 2306 2307 /* no fb bound */ 2308 if (!fb) { 2309 DRM_ERROR("No FB bound\n"); 2310 return 0; 2311 } 2312 2313 if(intel_crtc->plane > dev_priv->num_pipe) { 2314 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n", 2315 intel_crtc->plane, 2316 dev_priv->num_pipe); 2317 return -EINVAL; 2318 } 2319 2320 mutex_lock(&dev->struct_mutex); 2321 ret = intel_pin_and_fence_fb_obj(dev, 2322 to_intel_framebuffer(fb)->obj, 2323 NULL); 2324 if (ret != 0) { 2325 mutex_unlock(&dev->struct_mutex); 2326 DRM_ERROR("pin & fence failed\n"); 2327 return ret; 2328 } 2329 2330 if (crtc->fb) 2331 intel_finish_fb(crtc->fb); 2332 2333 ret = dev_priv->display.update_plane(crtc, fb, x, y); 2334 if (ret) { 2335 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj); 2336 mutex_unlock(&dev->struct_mutex); 2337 DRM_ERROR("failed to update base address\n"); 2338 return ret; 2339 } 2340 2341 old_fb = crtc->fb; 2342 crtc->fb = fb; 2343 crtc->x = x; 2344 crtc->y = y; 2345 2346 if (old_fb) { 2347 intel_wait_for_vblank(dev, intel_crtc->pipe); 2348 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj); 2349 } 2350 2351 intel_update_fbc(dev); 2352 mutex_unlock(&dev->struct_mutex); 2353 2354 intel_crtc_update_sarea_pos(crtc, x, y); 2355 2356 return 0; 2357 } 2358 2359 static void intel_fdi_normal_train(struct drm_crtc *crtc) 2360 { 2361 struct drm_device *dev = crtc->dev; 2362 struct drm_i915_private *dev_priv = dev->dev_private; 2363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2364 int pipe = intel_crtc->pipe; 2365 u32 reg, temp; 2366 2367 /* enable normal train */ 2368 reg = FDI_TX_CTL(pipe); 2369 temp = I915_READ(reg); 2370 if (IS_IVYBRIDGE(dev)) { 2371 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 2372 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; 2373 } else { 2374 temp &= ~FDI_LINK_TRAIN_NONE; 2375 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; 2376 } 2377 I915_WRITE(reg, temp); 2378 2379 reg = FDI_RX_CTL(pipe); 2380 temp = I915_READ(reg); 2381 if (HAS_PCH_CPT(dev)) { 2382 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2383 temp |= FDI_LINK_TRAIN_NORMAL_CPT; 2384 } else { 2385 temp &= ~FDI_LINK_TRAIN_NONE; 2386 temp |= FDI_LINK_TRAIN_NONE; 2387 } 2388 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); 2389 2390 /* wait one idle pattern time */ 2391 POSTING_READ(reg); 2392 udelay(1000); 2393 2394 /* IVB wants error correction enabled */ 2395 if (IS_IVYBRIDGE(dev)) 2396 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | 2397 FDI_FE_ERRC_ENABLE); 2398 } 2399 2400 static void ivb_modeset_global_resources(struct drm_device *dev) 2401 { 2402 struct drm_i915_private *dev_priv = dev->dev_private; 2403 struct intel_crtc *pipe_B_crtc = 2404 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); 2405 struct intel_crtc *pipe_C_crtc = 2406 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); 2407 uint32_t temp; 2408 2409 /* When everything is off disable fdi C so that we could enable fdi B 2410 * with all lanes. XXX: This misses the case where a pipe is not using 2411 * any pch resources and so doesn't need any fdi lanes. */ 2412 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) { 2413 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); 2414 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); 2415 2416 temp = I915_READ(SOUTH_CHICKEN1); 2417 temp &= ~FDI_BC_BIFURCATION_SELECT; 2418 DRM_DEBUG_KMS("disabling fdi C rx\n"); 2419 I915_WRITE(SOUTH_CHICKEN1, temp); 2420 } 2421 } 2422 2423 /* The FDI link training functions for ILK/Ibexpeak. */ 2424 static void ironlake_fdi_link_train(struct drm_crtc *crtc) 2425 { 2426 struct drm_device *dev = crtc->dev; 2427 struct drm_i915_private *dev_priv = dev->dev_private; 2428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2429 int pipe = intel_crtc->pipe; 2430 int plane = intel_crtc->plane; 2431 u32 reg, temp, tries; 2432 2433 /* FDI needs bits from pipe & plane first */ 2434 assert_pipe_enabled(dev_priv, pipe); 2435 assert_plane_enabled(dev_priv, plane); 2436 2437 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2438 for train result */ 2439 reg = FDI_RX_IMR(pipe); 2440 temp = I915_READ(reg); 2441 temp &= ~FDI_RX_SYMBOL_LOCK; 2442 temp &= ~FDI_RX_BIT_LOCK; 2443 I915_WRITE(reg, temp); 2444 I915_READ(reg); 2445 udelay(150); 2446 2447 /* enable CPU FDI TX and PCH FDI RX */ 2448 reg = FDI_TX_CTL(pipe); 2449 temp = I915_READ(reg); 2450 temp &= ~(7 << 19); 2451 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2452 temp &= ~FDI_LINK_TRAIN_NONE; 2453 temp |= FDI_LINK_TRAIN_PATTERN_1; 2454 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2455 2456 reg = FDI_RX_CTL(pipe); 2457 temp = I915_READ(reg); 2458 temp &= ~FDI_LINK_TRAIN_NONE; 2459 temp |= FDI_LINK_TRAIN_PATTERN_1; 2460 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2461 2462 POSTING_READ(reg); 2463 udelay(150); 2464 2465 /* Ironlake workaround, enable clock pointer after FDI enable*/ 2466 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2467 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | 2468 FDI_RX_PHASE_SYNC_POINTER_EN); 2469 2470 reg = FDI_RX_IIR(pipe); 2471 for (tries = 0; tries < 5; tries++) { 2472 temp = I915_READ(reg); 2473 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2474 2475 if ((temp & FDI_RX_BIT_LOCK)) { 2476 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2477 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2478 break; 2479 } 2480 } 2481 if (tries == 5) 2482 DRM_ERROR("FDI train 1 fail!\n"); 2483 2484 /* Train 2 */ 2485 reg = FDI_TX_CTL(pipe); 2486 temp = I915_READ(reg); 2487 temp &= ~FDI_LINK_TRAIN_NONE; 2488 temp |= FDI_LINK_TRAIN_PATTERN_2; 2489 I915_WRITE(reg, temp); 2490 2491 reg = FDI_RX_CTL(pipe); 2492 temp = I915_READ(reg); 2493 temp &= ~FDI_LINK_TRAIN_NONE; 2494 temp |= FDI_LINK_TRAIN_PATTERN_2; 2495 I915_WRITE(reg, temp); 2496 2497 POSTING_READ(reg); 2498 udelay(150); 2499 2500 reg = FDI_RX_IIR(pipe); 2501 for (tries = 0; tries < 5; tries++) { 2502 temp = I915_READ(reg); 2503 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2504 2505 if (temp & FDI_RX_SYMBOL_LOCK) { 2506 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2507 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2508 break; 2509 } 2510 } 2511 if (tries == 5) 2512 DRM_ERROR("FDI train 2 fail!\n"); 2513 2514 DRM_DEBUG_KMS("FDI train done\n"); 2515 2516 } 2517 2518 static const int snb_b_fdi_train_param[] = { 2519 FDI_LINK_TRAIN_400MV_0DB_SNB_B, 2520 FDI_LINK_TRAIN_400MV_6DB_SNB_B, 2521 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, 2522 FDI_LINK_TRAIN_800MV_0DB_SNB_B, 2523 }; 2524 2525 /* The FDI link training functions for SNB/Cougarpoint. */ 2526 static void gen6_fdi_link_train(struct drm_crtc *crtc) 2527 { 2528 struct drm_device *dev = crtc->dev; 2529 struct drm_i915_private *dev_priv = dev->dev_private; 2530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2531 int pipe = intel_crtc->pipe; 2532 u32 reg, temp, i, retry; 2533 2534 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2535 for train result */ 2536 reg = FDI_RX_IMR(pipe); 2537 temp = I915_READ(reg); 2538 temp &= ~FDI_RX_SYMBOL_LOCK; 2539 temp &= ~FDI_RX_BIT_LOCK; 2540 I915_WRITE(reg, temp); 2541 2542 POSTING_READ(reg); 2543 udelay(150); 2544 2545 /* enable CPU FDI TX and PCH FDI RX */ 2546 reg = FDI_TX_CTL(pipe); 2547 temp = I915_READ(reg); 2548 temp &= ~(7 << 19); 2549 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2550 temp &= ~FDI_LINK_TRAIN_NONE; 2551 temp |= FDI_LINK_TRAIN_PATTERN_1; 2552 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2553 /* SNB-B */ 2554 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2555 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2556 2557 I915_WRITE(FDI_RX_MISC(pipe), 2558 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 2559 2560 reg = FDI_RX_CTL(pipe); 2561 temp = I915_READ(reg); 2562 if (HAS_PCH_CPT(dev)) { 2563 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2564 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2565 } else { 2566 temp &= ~FDI_LINK_TRAIN_NONE; 2567 temp |= FDI_LINK_TRAIN_PATTERN_1; 2568 } 2569 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2570 2571 POSTING_READ(reg); 2572 udelay(150); 2573 2574 for (i = 0; i < 4; i++) { 2575 reg = FDI_TX_CTL(pipe); 2576 temp = I915_READ(reg); 2577 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2578 temp |= snb_b_fdi_train_param[i]; 2579 I915_WRITE(reg, temp); 2580 2581 POSTING_READ(reg); 2582 udelay(500); 2583 2584 for (retry = 0; retry < 5; retry++) { 2585 reg = FDI_RX_IIR(pipe); 2586 temp = I915_READ(reg); 2587 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2588 if (temp & FDI_RX_BIT_LOCK) { 2589 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2590 DRM_DEBUG_KMS("FDI train 1 done.\n"); 2591 break; 2592 } 2593 udelay(50); 2594 } 2595 if (retry < 5) 2596 break; 2597 } 2598 if (i == 4) 2599 DRM_ERROR("FDI train 1 fail!\n"); 2600 2601 /* Train 2 */ 2602 reg = FDI_TX_CTL(pipe); 2603 temp = I915_READ(reg); 2604 temp &= ~FDI_LINK_TRAIN_NONE; 2605 temp |= FDI_LINK_TRAIN_PATTERN_2; 2606 if (IS_GEN6(dev)) { 2607 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2608 /* SNB-B */ 2609 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2610 } 2611 I915_WRITE(reg, temp); 2612 2613 reg = FDI_RX_CTL(pipe); 2614 temp = I915_READ(reg); 2615 if (HAS_PCH_CPT(dev)) { 2616 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2617 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2618 } else { 2619 temp &= ~FDI_LINK_TRAIN_NONE; 2620 temp |= FDI_LINK_TRAIN_PATTERN_2; 2621 } 2622 I915_WRITE(reg, temp); 2623 2624 POSTING_READ(reg); 2625 udelay(150); 2626 2627 for (i = 0; i < 4; i++) { 2628 reg = FDI_TX_CTL(pipe); 2629 temp = I915_READ(reg); 2630 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2631 temp |= snb_b_fdi_train_param[i]; 2632 I915_WRITE(reg, temp); 2633 2634 POSTING_READ(reg); 2635 udelay(500); 2636 2637 for (retry = 0; retry < 5; retry++) { 2638 reg = FDI_RX_IIR(pipe); 2639 temp = I915_READ(reg); 2640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2641 if (temp & FDI_RX_SYMBOL_LOCK) { 2642 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2643 DRM_DEBUG_KMS("FDI train 2 done.\n"); 2644 break; 2645 } 2646 udelay(50); 2647 } 2648 if (retry < 5) 2649 break; 2650 } 2651 if (i == 4) 2652 DRM_ERROR("FDI train 2 fail!\n"); 2653 2654 DRM_DEBUG_KMS("FDI train done.\n"); 2655 } 2656 2657 /* Manual link training for Ivy Bridge A0 parts */ 2658 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) 2659 { 2660 struct drm_device *dev = crtc->dev; 2661 struct drm_i915_private *dev_priv = dev->dev_private; 2662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2663 int pipe = intel_crtc->pipe; 2664 u32 reg, temp, i; 2665 2666 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit 2667 for train result */ 2668 reg = FDI_RX_IMR(pipe); 2669 temp = I915_READ(reg); 2670 temp &= ~FDI_RX_SYMBOL_LOCK; 2671 temp &= ~FDI_RX_BIT_LOCK; 2672 I915_WRITE(reg, temp); 2673 2674 POSTING_READ(reg); 2675 udelay(150); 2676 2677 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", 2678 I915_READ(FDI_RX_IIR(pipe))); 2679 2680 /* enable CPU FDI TX and PCH FDI RX */ 2681 reg = FDI_TX_CTL(pipe); 2682 temp = I915_READ(reg); 2683 temp &= ~(7 << 19); 2684 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2685 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); 2686 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; 2687 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2688 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2689 temp |= FDI_COMPOSITE_SYNC; 2690 I915_WRITE(reg, temp | FDI_TX_ENABLE); 2691 2692 I915_WRITE(FDI_RX_MISC(pipe), 2693 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 2694 2695 reg = FDI_RX_CTL(pipe); 2696 temp = I915_READ(reg); 2697 temp &= ~FDI_LINK_TRAIN_AUTO; 2698 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2699 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2700 temp |= FDI_COMPOSITE_SYNC; 2701 I915_WRITE(reg, temp | FDI_RX_ENABLE); 2702 2703 POSTING_READ(reg); 2704 udelay(150); 2705 2706 for (i = 0; i < 4; i++) { 2707 reg = FDI_TX_CTL(pipe); 2708 temp = I915_READ(reg); 2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2710 temp |= snb_b_fdi_train_param[i]; 2711 I915_WRITE(reg, temp); 2712 2713 POSTING_READ(reg); 2714 udelay(500); 2715 2716 reg = FDI_RX_IIR(pipe); 2717 temp = I915_READ(reg); 2718 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2719 2720 if (temp & FDI_RX_BIT_LOCK || 2721 (I915_READ(reg) & FDI_RX_BIT_LOCK)) { 2722 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); 2723 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i); 2724 break; 2725 } 2726 } 2727 if (i == 4) 2728 DRM_ERROR("FDI train 1 fail!\n"); 2729 2730 /* Train 2 */ 2731 reg = FDI_TX_CTL(pipe); 2732 temp = I915_READ(reg); 2733 temp &= ~FDI_LINK_TRAIN_NONE_IVB; 2734 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; 2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2736 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; 2737 I915_WRITE(reg, temp); 2738 2739 reg = FDI_RX_CTL(pipe); 2740 temp = I915_READ(reg); 2741 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2742 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; 2743 I915_WRITE(reg, temp); 2744 2745 POSTING_READ(reg); 2746 udelay(150); 2747 2748 for (i = 0; i < 4; i++) { 2749 reg = FDI_TX_CTL(pipe); 2750 temp = I915_READ(reg); 2751 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; 2752 temp |= snb_b_fdi_train_param[i]; 2753 I915_WRITE(reg, temp); 2754 2755 POSTING_READ(reg); 2756 udelay(500); 2757 2758 reg = FDI_RX_IIR(pipe); 2759 temp = I915_READ(reg); 2760 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); 2761 2762 if (temp & FDI_RX_SYMBOL_LOCK) { 2763 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); 2764 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i); 2765 break; 2766 } 2767 } 2768 if (i == 4) 2769 DRM_ERROR("FDI train 2 fail!\n"); 2770 2771 DRM_DEBUG_KMS("FDI train done.\n"); 2772 } 2773 2774 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) 2775 { 2776 struct drm_device *dev = intel_crtc->base.dev; 2777 struct drm_i915_private *dev_priv = dev->dev_private; 2778 int pipe = intel_crtc->pipe; 2779 u32 reg, temp; 2780 2781 2782 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ 2783 reg = FDI_RX_CTL(pipe); 2784 temp = I915_READ(reg); 2785 temp &= ~((0x7 << 19) | (0x7 << 16)); 2786 temp |= (intel_crtc->fdi_lanes - 1) << 19; 2787 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 2788 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); 2789 2790 POSTING_READ(reg); 2791 udelay(200); 2792 2793 /* Switch from Rawclk to PCDclk */ 2794 temp = I915_READ(reg); 2795 I915_WRITE(reg, temp | FDI_PCDCLK); 2796 2797 POSTING_READ(reg); 2798 udelay(200); 2799 2800 /* Enable CPU FDI TX PLL, always on for Ironlake */ 2801 reg = FDI_TX_CTL(pipe); 2802 temp = I915_READ(reg); 2803 if ((temp & FDI_TX_PLL_ENABLE) == 0) { 2804 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); 2805 2806 POSTING_READ(reg); 2807 udelay(100); 2808 } 2809 } 2810 2811 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) 2812 { 2813 struct drm_device *dev = intel_crtc->base.dev; 2814 struct drm_i915_private *dev_priv = dev->dev_private; 2815 int pipe = intel_crtc->pipe; 2816 u32 reg, temp; 2817 2818 /* Switch from PCDclk to Rawclk */ 2819 reg = FDI_RX_CTL(pipe); 2820 temp = I915_READ(reg); 2821 I915_WRITE(reg, temp & ~FDI_PCDCLK); 2822 2823 /* Disable CPU FDI TX PLL */ 2824 reg = FDI_TX_CTL(pipe); 2825 temp = I915_READ(reg); 2826 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); 2827 2828 POSTING_READ(reg); 2829 udelay(100); 2830 2831 reg = FDI_RX_CTL(pipe); 2832 temp = I915_READ(reg); 2833 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); 2834 2835 /* Wait for the clocks to turn off. */ 2836 POSTING_READ(reg); 2837 udelay(100); 2838 } 2839 2840 static void ironlake_fdi_disable(struct drm_crtc *crtc) 2841 { 2842 struct drm_device *dev = crtc->dev; 2843 struct drm_i915_private *dev_priv = dev->dev_private; 2844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2845 int pipe = intel_crtc->pipe; 2846 u32 reg, temp; 2847 2848 /* disable CPU FDI tx and PCH FDI rx */ 2849 reg = FDI_TX_CTL(pipe); 2850 temp = I915_READ(reg); 2851 I915_WRITE(reg, temp & ~FDI_TX_ENABLE); 2852 POSTING_READ(reg); 2853 2854 reg = FDI_RX_CTL(pipe); 2855 temp = I915_READ(reg); 2856 temp &= ~(0x7 << 16); 2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 2858 I915_WRITE(reg, temp & ~FDI_RX_ENABLE); 2859 2860 POSTING_READ(reg); 2861 udelay(100); 2862 2863 /* Ironlake workaround, disable clock pointer after downing FDI */ 2864 if (HAS_PCH_IBX(dev)) { 2865 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); 2866 } 2867 2868 /* still set train pattern 1 */ 2869 reg = FDI_TX_CTL(pipe); 2870 temp = I915_READ(reg); 2871 temp &= ~FDI_LINK_TRAIN_NONE; 2872 temp |= FDI_LINK_TRAIN_PATTERN_1; 2873 I915_WRITE(reg, temp); 2874 2875 reg = FDI_RX_CTL(pipe); 2876 temp = I915_READ(reg); 2877 if (HAS_PCH_CPT(dev)) { 2878 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; 2879 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; 2880 } else { 2881 temp &= ~FDI_LINK_TRAIN_NONE; 2882 temp |= FDI_LINK_TRAIN_PATTERN_1; 2883 } 2884 /* BPC in FDI rx is consistent with that in PIPECONF */ 2885 temp &= ~(0x07 << 16); 2886 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; 2887 I915_WRITE(reg, temp); 2888 2889 POSTING_READ(reg); 2890 udelay(100); 2891 } 2892 2893 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) 2894 { 2895 struct drm_device *dev = crtc->dev; 2896 struct drm_i915_private *dev_priv = dev->dev_private; 2897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2898 bool pending; 2899 2900 if (i915_reset_in_progress(&dev_priv->gpu_error) || 2901 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) 2902 return false; 2903 2904 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 2905 pending = to_intel_crtc(crtc)->unpin_work != NULL; 2906 lockmgr(&dev->event_lock, LK_RELEASE); 2907 2908 return pending; 2909 } 2910 2911 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) 2912 { 2913 struct drm_device *dev = crtc->dev; 2914 struct drm_i915_private *dev_priv = dev->dev_private; 2915 2916 if (crtc->fb == NULL) 2917 return; 2918 2919 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); 2920 2921 wait_event(dev_priv->pending_flip_queue, 2922 !intel_crtc_has_pending_flip(crtc)); 2923 2924 mutex_lock(&dev->struct_mutex); 2925 intel_finish_fb(crtc->fb); 2926 mutex_unlock(&dev->struct_mutex); 2927 } 2928 2929 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc) 2930 { 2931 struct drm_device *dev = crtc->dev; 2932 struct intel_encoder *intel_encoder; 2933 2934 /* 2935 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that 2936 * must be driven by its own crtc; no sharing is possible. 2937 */ 2938 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 2939 switch (intel_encoder->type) { 2940 case INTEL_OUTPUT_EDP: 2941 if (!intel_encoder_is_pch_edp(&intel_encoder->base)) 2942 return false; 2943 continue; 2944 } 2945 } 2946 2947 return true; 2948 } 2949 2950 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc) 2951 { 2952 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG); 2953 } 2954 2955 /* Program iCLKIP clock to the desired frequency */ 2956 static void lpt_program_iclkip(struct drm_crtc *crtc) 2957 { 2958 struct drm_device *dev = crtc->dev; 2959 struct drm_i915_private *dev_priv = dev->dev_private; 2960 u32 divsel, phaseinc, auxdiv, phasedir = 0; 2961 u32 temp; 2962 2963 mutex_lock(&dev_priv->dpio_lock); 2964 2965 /* It is necessary to ungate the pixclk gate prior to programming 2966 * the divisors, and gate it back when it is done. 2967 */ 2968 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); 2969 2970 /* Disable SSCCTL */ 2971 intel_sbi_write(dev_priv, SBI_SSCCTL6, 2972 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | 2973 SBI_SSCCTL_DISABLE, 2974 SBI_ICLK); 2975 2976 /* 20MHz is a corner case which is out of range for the 7-bit divisor */ 2977 if (crtc->mode.clock == 20000) { 2978 auxdiv = 1; 2979 divsel = 0x41; 2980 phaseinc = 0x20; 2981 } else { 2982 /* The iCLK virtual clock root frequency is in MHz, 2983 * but the crtc->mode.clock in in KHz. To get the divisors, 2984 * it is necessary to divide one by another, so we 2985 * convert the virtual clock precision to KHz here for higher 2986 * precision. 2987 */ 2988 u32 iclk_virtual_root_freq = 172800 * 1000; 2989 u32 iclk_pi_range = 64; 2990 u32 desired_divisor, msb_divisor_value, pi_value; 2991 2992 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock); 2993 msb_divisor_value = desired_divisor / iclk_pi_range; 2994 pi_value = desired_divisor % iclk_pi_range; 2995 2996 auxdiv = 0; 2997 divsel = msb_divisor_value - 2; 2998 phaseinc = pi_value; 2999 } 3000 3001 /* This should not happen with any sane values */ 3002 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & 3003 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); 3004 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & 3005 ~SBI_SSCDIVINTPHASE_INCVAL_MASK); 3006 3007 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", 3008 crtc->mode.clock, 3009 auxdiv, 3010 divsel, 3011 phasedir, 3012 phaseinc); 3013 3014 /* Program SSCDIVINTPHASE6 */ 3015 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); 3016 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; 3017 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); 3018 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; 3019 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); 3020 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); 3021 temp |= SBI_SSCDIVINTPHASE_PROPAGATE; 3022 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); 3023 3024 /* Program SSCAUXDIV */ 3025 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); 3026 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); 3027 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); 3028 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); 3029 3030 /* Enable modulator and associated divider */ 3031 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); 3032 temp &= ~SBI_SSCCTL_DISABLE; 3033 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); 3034 3035 /* Wait for initialization time */ 3036 udelay(24); 3037 3038 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); 3039 3040 mutex_unlock(&dev_priv->dpio_lock); 3041 } 3042 3043 /* 3044 * Enable PCH resources required for PCH ports: 3045 * - PCH PLLs 3046 * - FDI training & RX/TX 3047 * - update transcoder timings 3048 * - DP transcoding bits 3049 * - transcoder 3050 */ 3051 static void ironlake_pch_enable(struct drm_crtc *crtc) 3052 { 3053 struct drm_device *dev = crtc->dev; 3054 struct drm_i915_private *dev_priv = dev->dev_private; 3055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3056 int pipe = intel_crtc->pipe; 3057 u32 reg, temp; 3058 3059 assert_transcoder_disabled(dev_priv, pipe); 3060 3061 /* Write the TU size bits before fdi link training, so that error 3062 * detection works. */ 3063 I915_WRITE(FDI_RX_TUSIZE1(pipe), 3064 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); 3065 3066 /* For PCH output, training FDI link */ 3067 dev_priv->display.fdi_link_train(crtc); 3068 3069 /* XXX: pch pll's can be enabled any time before we enable the PCH 3070 * transcoder, and we actually should do this to not upset any PCH 3071 * transcoder that already use the clock when we share it. 3072 * 3073 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll 3074 * unconditionally resets the pll - we need that to have the right LVDS 3075 * enable sequence. */ 3076 ironlake_enable_pch_pll(intel_crtc); 3077 3078 if (HAS_PCH_CPT(dev)) { 3079 u32 sel; 3080 3081 temp = I915_READ(PCH_DPLL_SEL); 3082 switch (pipe) { 3083 default: 3084 case 0: 3085 temp |= TRANSA_DPLL_ENABLE; 3086 sel = TRANSA_DPLLB_SEL; 3087 break; 3088 case 1: 3089 temp |= TRANSB_DPLL_ENABLE; 3090 sel = TRANSB_DPLLB_SEL; 3091 break; 3092 case 2: 3093 temp |= TRANSC_DPLL_ENABLE; 3094 sel = TRANSC_DPLLB_SEL; 3095 break; 3096 } 3097 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B) 3098 temp |= sel; 3099 else 3100 temp &= ~sel; 3101 I915_WRITE(PCH_DPLL_SEL, temp); 3102 } 3103 3104 /* set transcoder timing, panel must allow it */ 3105 assert_panel_unlocked(dev_priv, pipe); 3106 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe))); 3107 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe))); 3108 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe))); 3109 3110 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); 3111 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); 3112 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); 3113 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe))); 3114 3115 intel_fdi_normal_train(crtc); 3116 3117 /* For PCH DP, enable TRANS_DP_CTL */ 3118 if (HAS_PCH_CPT(dev) && 3119 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 3120 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 3121 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; 3122 reg = TRANS_DP_CTL(pipe); 3123 temp = I915_READ(reg); 3124 temp &= ~(TRANS_DP_PORT_SEL_MASK | 3125 TRANS_DP_SYNC_MASK | 3126 TRANS_DP_BPC_MASK); 3127 temp |= (TRANS_DP_OUTPUT_ENABLE | 3128 TRANS_DP_ENH_FRAMING); 3129 temp |= bpc << 9; /* same format but at 11:9 */ 3130 3131 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) 3132 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; 3133 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) 3134 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; 3135 3136 switch (intel_trans_dp_port_sel(crtc)) { 3137 case PCH_DP_B: 3138 temp |= TRANS_DP_PORT_SEL_B; 3139 break; 3140 case PCH_DP_C: 3141 temp |= TRANS_DP_PORT_SEL_C; 3142 break; 3143 case PCH_DP_D: 3144 temp |= TRANS_DP_PORT_SEL_D; 3145 break; 3146 default: 3147 BUG(); 3148 } 3149 3150 I915_WRITE(reg, temp); 3151 } 3152 3153 ironlake_enable_pch_transcoder(dev_priv, pipe); 3154 } 3155 3156 static void lpt_pch_enable(struct drm_crtc *crtc) 3157 { 3158 struct drm_device *dev = crtc->dev; 3159 struct drm_i915_private *dev_priv = dev->dev_private; 3160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3161 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 3162 3163 assert_transcoder_disabled(dev_priv, TRANSCODER_A); 3164 3165 lpt_program_iclkip(crtc); 3166 3167 /* Set transcoder timing. */ 3168 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder))); 3169 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder))); 3170 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder))); 3171 3172 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder))); 3173 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder))); 3174 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder))); 3175 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder))); 3176 3177 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); 3178 } 3179 3180 static void intel_put_pch_pll(struct intel_crtc *intel_crtc) 3181 { 3182 struct intel_pch_pll *pll = intel_crtc->pch_pll; 3183 3184 if (pll == NULL) 3185 return; 3186 3187 if (pll->refcount == 0) { 3188 WARN(1, "bad PCH PLL refcount\n"); 3189 return; 3190 } 3191 3192 --pll->refcount; 3193 intel_crtc->pch_pll = NULL; 3194 } 3195 3196 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp) 3197 { 3198 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 3199 struct intel_pch_pll *pll; 3200 int i; 3201 3202 pll = intel_crtc->pch_pll; 3203 if (pll) { 3204 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n", 3205 intel_crtc->base.base.id, pll->pll_reg); 3206 goto prepare; 3207 } 3208 3209 if (HAS_PCH_IBX(dev_priv->dev)) { 3210 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ 3211 i = intel_crtc->pipe; 3212 pll = &dev_priv->pch_plls[i]; 3213 3214 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n", 3215 intel_crtc->base.base.id, pll->pll_reg); 3216 3217 goto found; 3218 } 3219 3220 for (i = 0; i < dev_priv->num_pch_pll; i++) { 3221 pll = &dev_priv->pch_plls[i]; 3222 3223 /* Only want to check enabled timings first */ 3224 if (pll->refcount == 0) 3225 continue; 3226 3227 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) && 3228 fp == I915_READ(pll->fp0_reg)) { 3229 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n", 3230 intel_crtc->base.base.id, 3231 pll->pll_reg, pll->refcount, pll->active); 3232 3233 goto found; 3234 } 3235 } 3236 3237 /* Ok no matching timings, maybe there's a free one? */ 3238 for (i = 0; i < dev_priv->num_pch_pll; i++) { 3239 pll = &dev_priv->pch_plls[i]; 3240 if (pll->refcount == 0) { 3241 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n", 3242 intel_crtc->base.base.id, pll->pll_reg); 3243 goto found; 3244 } 3245 } 3246 3247 return NULL; 3248 3249 found: 3250 intel_crtc->pch_pll = pll; 3251 pll->refcount++; 3252 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe); 3253 prepare: /* separate function? */ 3254 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg); 3255 3256 /* Wait for the clocks to stabilize before rewriting the regs */ 3257 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); 3258 POSTING_READ(pll->pll_reg); 3259 udelay(150); 3260 3261 I915_WRITE(pll->fp0_reg, fp); 3262 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE); 3263 pll->on = false; 3264 return pll; 3265 } 3266 3267 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe) 3268 { 3269 struct drm_i915_private *dev_priv = dev->dev_private; 3270 int dslreg = PIPEDSL(pipe); 3271 u32 temp; 3272 3273 temp = I915_READ(dslreg); 3274 udelay(500); 3275 if (wait_for(I915_READ(dslreg) != temp, 5)) { 3276 if (wait_for(I915_READ(dslreg) != temp, 5)) 3277 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe); 3278 } 3279 } 3280 3281 static void ironlake_crtc_enable(struct drm_crtc *crtc) 3282 { 3283 struct drm_device *dev = crtc->dev; 3284 struct drm_i915_private *dev_priv = dev->dev_private; 3285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3286 struct intel_encoder *encoder; 3287 int pipe = intel_crtc->pipe; 3288 int plane = intel_crtc->plane; 3289 u32 temp; 3290 bool is_pch_port; 3291 3292 WARN_ON(!crtc->enabled); 3293 3294 if (intel_crtc->active) 3295 return; 3296 3297 intel_crtc->active = true; 3298 intel_update_watermarks(dev); 3299 3300 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 3301 temp = I915_READ(PCH_LVDS); 3302 if ((temp & LVDS_PORT_EN) == 0) 3303 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN); 3304 } 3305 3306 is_pch_port = ironlake_crtc_driving_pch(crtc); 3307 3308 if (is_pch_port) { 3309 /* Note: FDI PLL enabling _must_ be done before we enable the 3310 * cpu pipes, hence this is separate from all the other fdi/pch 3311 * enabling. */ 3312 ironlake_fdi_pll_enable(intel_crtc); 3313 } else { 3314 assert_fdi_tx_disabled(dev_priv, pipe); 3315 assert_fdi_rx_disabled(dev_priv, pipe); 3316 } 3317 3318 for_each_encoder_on_crtc(dev, crtc, encoder) 3319 if (encoder->pre_enable) 3320 encoder->pre_enable(encoder); 3321 3322 /* Enable panel fitting for LVDS */ 3323 if (dev_priv->pch_pf_size && 3324 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || 3325 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 3326 /* Force use of hard-coded filter coefficients 3327 * as some pre-programmed values are broken, 3328 * e.g. x201. 3329 */ 3330 if (IS_IVYBRIDGE(dev)) 3331 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | 3332 PF_PIPE_SEL_IVB(pipe)); 3333 else 3334 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); 3335 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); 3336 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); 3337 } 3338 3339 /* 3340 * On ILK+ LUT must be loaded before the pipe is running but with 3341 * clocks enabled 3342 */ 3343 intel_crtc_load_lut(crtc); 3344 3345 intel_enable_pipe(dev_priv, pipe, is_pch_port); 3346 intel_enable_plane(dev_priv, plane, pipe); 3347 3348 if (is_pch_port) 3349 ironlake_pch_enable(crtc); 3350 3351 mutex_lock(&dev->struct_mutex); 3352 intel_update_fbc(dev); 3353 mutex_unlock(&dev->struct_mutex); 3354 3355 intel_crtc_update_cursor(crtc, true); 3356 3357 for_each_encoder_on_crtc(dev, crtc, encoder) 3358 encoder->enable(encoder); 3359 3360 if (HAS_PCH_CPT(dev)) 3361 intel_cpt_verify_modeset(dev, intel_crtc->pipe); 3362 3363 /* 3364 * There seems to be a race in PCH platform hw (at least on some 3365 * outputs) where an enabled pipe still completes any pageflip right 3366 * away (as if the pipe is off) instead of waiting for vblank. As soon 3367 * as the first vblank happend, everything works as expected. Hence just 3368 * wait for one vblank before returning to avoid strange things 3369 * happening. 3370 */ 3371 intel_wait_for_vblank(dev, intel_crtc->pipe); 3372 } 3373 3374 static void haswell_crtc_enable(struct drm_crtc *crtc) 3375 { 3376 struct drm_device *dev = crtc->dev; 3377 struct drm_i915_private *dev_priv = dev->dev_private; 3378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3379 struct intel_encoder *encoder; 3380 int pipe = intel_crtc->pipe; 3381 int plane = intel_crtc->plane; 3382 bool is_pch_port; 3383 3384 WARN_ON(!crtc->enabled); 3385 3386 if (intel_crtc->active) 3387 return; 3388 3389 intel_crtc->active = true; 3390 intel_update_watermarks(dev); 3391 3392 is_pch_port = haswell_crtc_driving_pch(crtc); 3393 3394 if (is_pch_port) 3395 dev_priv->display.fdi_link_train(crtc); 3396 3397 for_each_encoder_on_crtc(dev, crtc, encoder) 3398 if (encoder->pre_enable) 3399 encoder->pre_enable(encoder); 3400 3401 intel_ddi_enable_pipe_clock(intel_crtc); 3402 3403 /* Enable panel fitting for eDP */ 3404 if (dev_priv->pch_pf_size && 3405 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { 3406 /* Force use of hard-coded filter coefficients 3407 * as some pre-programmed values are broken, 3408 * e.g. x201. 3409 */ 3410 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | 3411 PF_PIPE_SEL_IVB(pipe)); 3412 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); 3413 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); 3414 } 3415 3416 /* 3417 * On ILK+ LUT must be loaded before the pipe is running but with 3418 * clocks enabled 3419 */ 3420 intel_crtc_load_lut(crtc); 3421 3422 intel_ddi_set_pipe_settings(crtc); 3423 intel_ddi_enable_pipe_func(crtc); 3424 3425 intel_enable_pipe(dev_priv, pipe, is_pch_port); 3426 intel_enable_plane(dev_priv, plane, pipe); 3427 3428 if (is_pch_port) 3429 lpt_pch_enable(crtc); 3430 3431 mutex_lock(&dev->struct_mutex); 3432 intel_update_fbc(dev); 3433 mutex_unlock(&dev->struct_mutex); 3434 3435 intel_crtc_update_cursor(crtc, true); 3436 3437 for_each_encoder_on_crtc(dev, crtc, encoder) 3438 encoder->enable(encoder); 3439 3440 /* 3441 * There seems to be a race in PCH platform hw (at least on some 3442 * outputs) where an enabled pipe still completes any pageflip right 3443 * away (as if the pipe is off) instead of waiting for vblank. As soon 3444 * as the first vblank happend, everything works as expected. Hence just 3445 * wait for one vblank before returning to avoid strange things 3446 * happening. 3447 */ 3448 intel_wait_for_vblank(dev, intel_crtc->pipe); 3449 } 3450 3451 static void ironlake_crtc_disable(struct drm_crtc *crtc) 3452 { 3453 struct drm_device *dev = crtc->dev; 3454 struct drm_i915_private *dev_priv = dev->dev_private; 3455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3456 struct intel_encoder *encoder; 3457 int pipe = intel_crtc->pipe; 3458 int plane = intel_crtc->plane; 3459 u32 reg, temp; 3460 3461 3462 if (!intel_crtc->active) 3463 return; 3464 3465 for_each_encoder_on_crtc(dev, crtc, encoder) 3466 encoder->disable(encoder); 3467 3468 intel_crtc_wait_for_pending_flips(crtc); 3469 drm_vblank_off(dev, pipe); 3470 intel_crtc_update_cursor(crtc, false); 3471 3472 intel_disable_plane(dev_priv, plane, pipe); 3473 3474 if (dev_priv->cfb_plane == plane) 3475 intel_disable_fbc(dev); 3476 3477 intel_disable_pipe(dev_priv, pipe); 3478 3479 /* Disable PF */ 3480 I915_WRITE(PF_CTL(pipe), 0); 3481 I915_WRITE(PF_WIN_SZ(pipe), 0); 3482 3483 for_each_encoder_on_crtc(dev, crtc, encoder) 3484 if (encoder->post_disable) 3485 encoder->post_disable(encoder); 3486 3487 ironlake_fdi_disable(crtc); 3488 3489 ironlake_disable_pch_transcoder(dev_priv, pipe); 3490 3491 if (HAS_PCH_CPT(dev)) { 3492 /* disable TRANS_DP_CTL */ 3493 reg = TRANS_DP_CTL(pipe); 3494 temp = I915_READ(reg); 3495 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK); 3496 temp |= TRANS_DP_PORT_SEL_NONE; 3497 I915_WRITE(reg, temp); 3498 3499 /* disable DPLL_SEL */ 3500 temp = I915_READ(PCH_DPLL_SEL); 3501 switch (pipe) { 3502 case 0: 3503 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL); 3504 break; 3505 case 1: 3506 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL); 3507 break; 3508 case 2: 3509 /* C shares PLL A or B */ 3510 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL); 3511 break; 3512 default: 3513 BUG(); /* wtf */ 3514 } 3515 I915_WRITE(PCH_DPLL_SEL, temp); 3516 } 3517 3518 /* disable PCH DPLL */ 3519 intel_disable_pch_pll(intel_crtc); 3520 3521 ironlake_fdi_pll_disable(intel_crtc); 3522 3523 intel_crtc->active = false; 3524 intel_update_watermarks(dev); 3525 3526 mutex_lock(&dev->struct_mutex); 3527 intel_update_fbc(dev); 3528 mutex_unlock(&dev->struct_mutex); 3529 } 3530 3531 static void haswell_crtc_disable(struct drm_crtc *crtc) 3532 { 3533 struct drm_device *dev = crtc->dev; 3534 struct drm_i915_private *dev_priv = dev->dev_private; 3535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3536 struct intel_encoder *encoder; 3537 int pipe = intel_crtc->pipe; 3538 int plane = intel_crtc->plane; 3539 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 3540 bool is_pch_port; 3541 3542 if (!intel_crtc->active) 3543 return; 3544 3545 is_pch_port = haswell_crtc_driving_pch(crtc); 3546 3547 for_each_encoder_on_crtc(dev, crtc, encoder) 3548 encoder->disable(encoder); 3549 3550 intel_crtc_wait_for_pending_flips(crtc); 3551 drm_vblank_off(dev, pipe); 3552 intel_crtc_update_cursor(crtc, false); 3553 3554 intel_disable_plane(dev_priv, plane, pipe); 3555 3556 if (dev_priv->cfb_plane == plane) 3557 intel_disable_fbc(dev); 3558 3559 intel_disable_pipe(dev_priv, pipe); 3560 3561 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); 3562 3563 /* Disable PF */ 3564 I915_WRITE(PF_CTL(pipe), 0); 3565 I915_WRITE(PF_WIN_SZ(pipe), 0); 3566 3567 intel_ddi_disable_pipe_clock(intel_crtc); 3568 3569 for_each_encoder_on_crtc(dev, crtc, encoder) 3570 if (encoder->post_disable) 3571 encoder->post_disable(encoder); 3572 3573 if (is_pch_port) { 3574 lpt_disable_pch_transcoder(dev_priv); 3575 intel_ddi_fdi_disable(crtc); 3576 } 3577 3578 intel_crtc->active = false; 3579 intel_update_watermarks(dev); 3580 3581 mutex_lock(&dev->struct_mutex); 3582 intel_update_fbc(dev); 3583 mutex_unlock(&dev->struct_mutex); 3584 } 3585 3586 static void ironlake_crtc_off(struct drm_crtc *crtc) 3587 { 3588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3589 intel_put_pch_pll(intel_crtc); 3590 } 3591 3592 static void haswell_crtc_off(struct drm_crtc *crtc) 3593 { 3594 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3595 3596 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might 3597 * start using it. */ 3598 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe; 3599 3600 intel_ddi_put_crtc_pll(crtc); 3601 } 3602 3603 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) 3604 { 3605 if (!enable && intel_crtc->overlay) { 3606 struct drm_device *dev = intel_crtc->base.dev; 3607 struct drm_i915_private *dev_priv = dev->dev_private; 3608 3609 mutex_lock(&dev->struct_mutex); 3610 dev_priv->mm.interruptible = false; 3611 (void) intel_overlay_switch_off(intel_crtc->overlay); 3612 dev_priv->mm.interruptible = true; 3613 mutex_unlock(&dev->struct_mutex); 3614 } 3615 3616 /* Let userspace switch the overlay on again. In most cases userspace 3617 * has to recompute where to put it anyway. 3618 */ 3619 } 3620 3621 /** 3622 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware 3623 * cursor plane briefly if not already running after enabling the display 3624 * plane. 3625 * This workaround avoids occasional blank screens when self refresh is 3626 * enabled. 3627 */ 3628 static void 3629 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum i915_pipe pipe) 3630 { 3631 u32 cntl = I915_READ(CURCNTR(pipe)); 3632 3633 if ((cntl & CURSOR_MODE) == 0) { 3634 u32 fw_bcl_self = I915_READ(FW_BLC_SELF); 3635 3636 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN); 3637 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX); 3638 intel_wait_for_vblank(dev_priv->dev, pipe); 3639 I915_WRITE(CURCNTR(pipe), cntl); 3640 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); 3641 I915_WRITE(FW_BLC_SELF, fw_bcl_self); 3642 } 3643 } 3644 3645 static void i9xx_crtc_enable(struct drm_crtc *crtc) 3646 { 3647 struct drm_device *dev = crtc->dev; 3648 struct drm_i915_private *dev_priv = dev->dev_private; 3649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3650 struct intel_encoder *encoder; 3651 int pipe = intel_crtc->pipe; 3652 int plane = intel_crtc->plane; 3653 3654 WARN_ON(!crtc->enabled); 3655 3656 if (intel_crtc->active) 3657 return; 3658 3659 intel_crtc->active = true; 3660 intel_update_watermarks(dev); 3661 3662 intel_enable_pll(dev_priv, pipe); 3663 3664 for_each_encoder_on_crtc(dev, crtc, encoder) 3665 if (encoder->pre_enable) 3666 encoder->pre_enable(encoder); 3667 3668 intel_enable_pipe(dev_priv, pipe, false); 3669 intel_enable_plane(dev_priv, plane, pipe); 3670 if (IS_G4X(dev)) 3671 g4x_fixup_plane(dev_priv, pipe); 3672 3673 intel_crtc_load_lut(crtc); 3674 intel_update_fbc(dev); 3675 3676 /* Give the overlay scaler a chance to enable if it's on this pipe */ 3677 intel_crtc_dpms_overlay(intel_crtc, true); 3678 intel_crtc_update_cursor(crtc, true); 3679 3680 for_each_encoder_on_crtc(dev, crtc, encoder) 3681 encoder->enable(encoder); 3682 } 3683 3684 static void i9xx_crtc_disable(struct drm_crtc *crtc) 3685 { 3686 struct drm_device *dev = crtc->dev; 3687 struct drm_i915_private *dev_priv = dev->dev_private; 3688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3689 struct intel_encoder *encoder; 3690 int pipe = intel_crtc->pipe; 3691 int plane = intel_crtc->plane; 3692 u32 pctl; 3693 3694 3695 if (!intel_crtc->active) 3696 return; 3697 3698 for_each_encoder_on_crtc(dev, crtc, encoder) 3699 encoder->disable(encoder); 3700 3701 /* Give the overlay scaler a chance to disable if it's on this pipe */ 3702 intel_crtc_wait_for_pending_flips(crtc); 3703 drm_vblank_off(dev, pipe); 3704 intel_crtc_dpms_overlay(intel_crtc, false); 3705 intel_crtc_update_cursor(crtc, false); 3706 3707 if (dev_priv->cfb_plane == plane) 3708 intel_disable_fbc(dev); 3709 3710 intel_disable_plane(dev_priv, plane, pipe); 3711 intel_disable_pipe(dev_priv, pipe); 3712 3713 /* Disable pannel fitter if it is on this pipe. */ 3714 pctl = I915_READ(PFIT_CONTROL); 3715 if ((pctl & PFIT_ENABLE) && 3716 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe) 3717 I915_WRITE(PFIT_CONTROL, 0); 3718 3719 intel_disable_pll(dev_priv, pipe); 3720 3721 intel_crtc->active = false; 3722 intel_update_fbc(dev); 3723 intel_update_watermarks(dev); 3724 } 3725 3726 static void i9xx_crtc_off(struct drm_crtc *crtc) 3727 { 3728 } 3729 3730 static void intel_crtc_update_sarea(struct drm_crtc *crtc, 3731 bool enabled) 3732 { 3733 struct drm_device *dev = crtc->dev; 3734 struct drm_i915_private *dev_priv = dev->dev_private; 3735 #if 0 3736 struct drm_i915_master_private *master_priv; 3737 #endif 3738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3739 int pipe = intel_crtc->pipe; 3740 3741 #if 0 3742 if (!dev->primary->master) 3743 return; 3744 3745 master_priv = dev->primary->master->driver_priv; 3746 if (!master_priv->sarea_priv) 3747 return; 3748 #else 3749 if (!dev_priv->sarea_priv) 3750 return; 3751 #endif 3752 3753 switch (pipe) { 3754 case 0: 3755 #if 0 3756 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; 3757 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; 3758 #else 3759 dev_priv->sarea_priv->planeA_w = enabled ? crtc->mode.hdisplay : 0; 3760 dev_priv->sarea_priv->planeA_h = enabled ? crtc->mode.vdisplay : 0; 3761 #endif 3762 break; 3763 case 1: 3764 #if 0 3765 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; 3766 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; 3767 #else 3768 dev_priv->sarea_priv->planeB_w = enabled ? crtc->mode.hdisplay : 0; 3769 dev_priv->sarea_priv->planeB_h = enabled ? crtc->mode.vdisplay : 0; 3770 #endif 3771 break; 3772 default: 3773 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); 3774 break; 3775 } 3776 } 3777 3778 /** 3779 * Sets the power management mode of the pipe and plane. 3780 */ 3781 void intel_crtc_update_dpms(struct drm_crtc *crtc) 3782 { 3783 struct drm_device *dev = crtc->dev; 3784 struct drm_i915_private *dev_priv = dev->dev_private; 3785 struct intel_encoder *intel_encoder; 3786 bool enable = false; 3787 3788 for_each_encoder_on_crtc(dev, crtc, intel_encoder) 3789 enable |= intel_encoder->connectors_active; 3790 3791 if (enable) 3792 dev_priv->display.crtc_enable(crtc); 3793 else 3794 dev_priv->display.crtc_disable(crtc); 3795 3796 intel_crtc_update_sarea(crtc, enable); 3797 } 3798 3799 static void intel_crtc_noop(struct drm_crtc *crtc) 3800 { 3801 } 3802 3803 static void intel_crtc_disable(struct drm_crtc *crtc) 3804 { 3805 struct drm_device *dev = crtc->dev; 3806 struct drm_connector *connector; 3807 struct drm_i915_private *dev_priv = dev->dev_private; 3808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 3809 3810 /* crtc should still be enabled when we disable it. */ 3811 WARN_ON(!crtc->enabled); 3812 3813 intel_crtc->eld_vld = false; 3814 dev_priv->display.crtc_disable(crtc); 3815 intel_crtc_update_sarea(crtc, false); 3816 dev_priv->display.off(crtc); 3817 3818 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane); 3819 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe); 3820 3821 if (crtc->fb) { 3822 mutex_lock(&dev->struct_mutex); 3823 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj); 3824 mutex_unlock(&dev->struct_mutex); 3825 crtc->fb = NULL; 3826 } 3827 3828 /* Update computed state. */ 3829 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 3830 if (!connector->encoder || !connector->encoder->crtc) 3831 continue; 3832 3833 if (connector->encoder->crtc != crtc) 3834 continue; 3835 3836 connector->dpms = DRM_MODE_DPMS_OFF; 3837 to_intel_encoder(connector->encoder)->connectors_active = false; 3838 } 3839 } 3840 3841 void intel_modeset_disable(struct drm_device *dev) 3842 { 3843 struct drm_crtc *crtc; 3844 3845 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 3846 if (crtc->enabled) 3847 intel_crtc_disable(crtc); 3848 } 3849 } 3850 3851 void intel_encoder_noop(struct drm_encoder *encoder) 3852 { 3853 } 3854 3855 void intel_encoder_destroy(struct drm_encoder *encoder) 3856 { 3857 struct intel_encoder *intel_encoder = to_intel_encoder(encoder); 3858 3859 drm_encoder_cleanup(encoder); 3860 drm_free(intel_encoder, M_DRM); 3861 } 3862 3863 /* Simple dpms helper for encodres with just one connector, no cloning and only 3864 * one kind of off state. It clamps all !ON modes to fully OFF and changes the 3865 * state of the entire output pipe. */ 3866 void intel_encoder_dpms(struct intel_encoder *encoder, int mode) 3867 { 3868 if (mode == DRM_MODE_DPMS_ON) { 3869 encoder->connectors_active = true; 3870 3871 intel_crtc_update_dpms(encoder->base.crtc); 3872 } else { 3873 encoder->connectors_active = false; 3874 3875 intel_crtc_update_dpms(encoder->base.crtc); 3876 } 3877 } 3878 3879 /* Cross check the actual hw state with our own modeset state tracking (and it's 3880 * internal consistency). */ 3881 static void intel_connector_check_state(struct intel_connector *connector) 3882 { 3883 if (connector->get_hw_state(connector)) { 3884 struct intel_encoder *encoder = connector->encoder; 3885 struct drm_crtc *crtc; 3886 bool encoder_enabled; 3887 enum i915_pipe pipe; 3888 3889 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 3890 connector->base.base.id, 3891 drm_get_connector_name(&connector->base)); 3892 3893 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, 3894 "wrong connector dpms state\n"); 3895 WARN(connector->base.encoder != &encoder->base, 3896 "active connector not linked to encoder\n"); 3897 WARN(!encoder->connectors_active, 3898 "encoder->connectors_active not set\n"); 3899 3900 encoder_enabled = encoder->get_hw_state(encoder, &pipe); 3901 WARN(!encoder_enabled, "encoder not enabled\n"); 3902 if (WARN_ON(!encoder->base.crtc)) 3903 return; 3904 3905 crtc = encoder->base.crtc; 3906 3907 WARN(!crtc->enabled, "crtc not enabled\n"); 3908 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); 3909 WARN(pipe != to_intel_crtc(crtc)->pipe, 3910 "encoder active on the wrong pipe\n"); 3911 } 3912 } 3913 3914 /* Even simpler default implementation, if there's really no special case to 3915 * consider. */ 3916 void intel_connector_dpms(struct drm_connector *connector, int mode) 3917 { 3918 struct intel_encoder *encoder = intel_attached_encoder(connector); 3919 3920 /* All the simple cases only support two dpms states. */ 3921 if (mode != DRM_MODE_DPMS_ON) 3922 mode = DRM_MODE_DPMS_OFF; 3923 3924 if (mode == connector->dpms) 3925 return; 3926 3927 connector->dpms = mode; 3928 3929 /* Only need to change hw state when actually enabled */ 3930 if (encoder->base.crtc) 3931 intel_encoder_dpms(encoder, mode); 3932 else 3933 WARN_ON(encoder->connectors_active != false); 3934 3935 intel_modeset_check_state(connector->dev); 3936 } 3937 3938 /* Simple connector->get_hw_state implementation for encoders that support only 3939 * one connector and no cloning and hence the encoder state determines the state 3940 * of the connector. */ 3941 bool intel_connector_get_hw_state(struct intel_connector *connector) 3942 { 3943 enum i915_pipe pipe = 0; 3944 struct intel_encoder *encoder = connector->encoder; 3945 3946 return encoder->get_hw_state(encoder, &pipe); 3947 } 3948 3949 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, 3950 const struct drm_display_mode *mode, 3951 struct drm_display_mode *adjusted_mode) 3952 { 3953 struct drm_device *dev = crtc->dev; 3954 3955 if (HAS_PCH_SPLIT(dev)) { 3956 /* FDI link clock is fixed at 2.7G */ 3957 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) 3958 return false; 3959 } 3960 3961 /* All interlaced capable intel hw wants timings in frames. Note though 3962 * that intel_lvds_mode_fixup does some funny tricks with the crtc 3963 * timings, so we need to be careful not to clobber these.*/ 3964 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET)) 3965 drm_mode_set_crtcinfo(adjusted_mode, 0); 3966 3967 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes 3968 * with a hsync front porch of 0. 3969 */ 3970 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && 3971 adjusted_mode->hsync_start == adjusted_mode->hdisplay) 3972 return false; 3973 3974 return true; 3975 } 3976 3977 static int valleyview_get_display_clock_speed(struct drm_device *dev) 3978 { 3979 return 400000; /* FIXME */ 3980 } 3981 3982 static int i945_get_display_clock_speed(struct drm_device *dev) 3983 { 3984 return 400000; 3985 } 3986 3987 static int i915_get_display_clock_speed(struct drm_device *dev) 3988 { 3989 return 333000; 3990 } 3991 3992 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) 3993 { 3994 return 200000; 3995 } 3996 3997 static int i915gm_get_display_clock_speed(struct drm_device *dev) 3998 { 3999 u16 gcfgc = 0; 4000 4001 pci_read_config_word(dev->pdev, GCFGC, &gcfgc); 4002 4003 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) 4004 return 133000; 4005 else { 4006 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { 4007 case GC_DISPLAY_CLOCK_333_MHZ: 4008 return 333000; 4009 default: 4010 case GC_DISPLAY_CLOCK_190_200_MHZ: 4011 return 190000; 4012 } 4013 } 4014 } 4015 4016 static int i865_get_display_clock_speed(struct drm_device *dev) 4017 { 4018 return 266000; 4019 } 4020 4021 static int i855_get_display_clock_speed(struct drm_device *dev) 4022 { 4023 u16 hpllcc = 0; 4024 /* Assume that the hardware is in the high speed state. This 4025 * should be the default. 4026 */ 4027 switch (hpllcc & GC_CLOCK_CONTROL_MASK) { 4028 case GC_CLOCK_133_200: 4029 case GC_CLOCK_100_200: 4030 return 200000; 4031 case GC_CLOCK_166_250: 4032 return 250000; 4033 case GC_CLOCK_100_133: 4034 return 133000; 4035 } 4036 4037 /* Shouldn't happen */ 4038 return 0; 4039 } 4040 4041 static int i830_get_display_clock_speed(struct drm_device *dev) 4042 { 4043 return 133000; 4044 } 4045 4046 static void 4047 intel_reduce_ratio(uint32_t *num, uint32_t *den) 4048 { 4049 while (*num > 0xffffff || *den > 0xffffff) { 4050 *num >>= 1; 4051 *den >>= 1; 4052 } 4053 } 4054 4055 void 4056 intel_link_compute_m_n(int bits_per_pixel, int nlanes, 4057 int pixel_clock, int link_clock, 4058 struct intel_link_m_n *m_n) 4059 { 4060 m_n->tu = 64; 4061 m_n->gmch_m = bits_per_pixel * pixel_clock; 4062 m_n->gmch_n = link_clock * nlanes * 8; 4063 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 4064 m_n->link_m = pixel_clock; 4065 m_n->link_n = link_clock; 4066 intel_reduce_ratio(&m_n->link_m, &m_n->link_n); 4067 } 4068 4069 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) 4070 { 4071 if (i915_panel_use_ssc >= 0) 4072 return i915_panel_use_ssc != 0; 4073 return dev_priv->lvds_use_ssc 4074 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); 4075 } 4076 4077 /** 4078 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send 4079 * @crtc: CRTC structure 4080 * @mode: requested mode 4081 * 4082 * A pipe may be connected to one or more outputs. Based on the depth of the 4083 * attached framebuffer, choose a good color depth to use on the pipe. 4084 * 4085 * If possible, match the pipe depth to the fb depth. In some cases, this 4086 * isn't ideal, because the connected output supports a lesser or restricted 4087 * set of depths. Resolve that here: 4088 * LVDS typically supports only 6bpc, so clamp down in that case 4089 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc 4090 * Displays may support a restricted set as well, check EDID and clamp as 4091 * appropriate. 4092 * DP may want to dither down to 6bpc to fit larger modes 4093 * 4094 * RETURNS: 4095 * Dithering requirement (i.e. false if display bpc and pipe bpc match, 4096 * true if they don't match). 4097 */ 4098 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, 4099 struct drm_framebuffer *fb, 4100 unsigned int *pipe_bpp, 4101 struct drm_display_mode *mode) 4102 { 4103 struct drm_device *dev = crtc->dev; 4104 struct drm_i915_private *dev_priv = dev->dev_private; 4105 struct drm_connector *connector; 4106 struct intel_encoder *intel_encoder; 4107 unsigned int display_bpc = UINT_MAX, bpc; 4108 4109 /* Walk the encoders & connectors on this crtc, get min bpc */ 4110 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 4111 4112 if (intel_encoder->type == INTEL_OUTPUT_LVDS) { 4113 unsigned int lvds_bpc; 4114 4115 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == 4116 LVDS_A3_POWER_UP) 4117 lvds_bpc = 8; 4118 else 4119 lvds_bpc = 6; 4120 4121 if (lvds_bpc < display_bpc) { 4122 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc); 4123 display_bpc = lvds_bpc; 4124 } 4125 continue; 4126 } 4127 4128 /* Not one of the known troublemakers, check the EDID */ 4129 list_for_each_entry(connector, &dev->mode_config.connector_list, 4130 head) { 4131 if (connector->encoder != &intel_encoder->base) 4132 continue; 4133 4134 /* Don't use an invalid EDID bpc value */ 4135 if (connector->display_info.bpc && 4136 connector->display_info.bpc < display_bpc) { 4137 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc); 4138 display_bpc = connector->display_info.bpc; 4139 } 4140 } 4141 4142 if (intel_encoder->type == INTEL_OUTPUT_EDP) { 4143 /* Use VBT settings if we have an eDP panel */ 4144 unsigned int edp_bpc = dev_priv->edp.bpp / 3; 4145 4146 if (edp_bpc && edp_bpc < display_bpc) { 4147 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc); 4148 display_bpc = edp_bpc; 4149 } 4150 continue; 4151 } 4152 4153 /* 4154 * HDMI is either 12 or 8, so if the display lets 10bpc sneak 4155 * through, clamp it down. (Note: >12bpc will be caught below.) 4156 */ 4157 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 4158 if (display_bpc > 8 && display_bpc < 12) { 4159 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n"); 4160 display_bpc = 12; 4161 } else { 4162 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n"); 4163 display_bpc = 8; 4164 } 4165 } 4166 } 4167 4168 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 4169 DRM_DEBUG_KMS("Dithering DP to 6bpc\n"); 4170 display_bpc = 6; 4171 } 4172 4173 /* 4174 * We could just drive the pipe at the highest bpc all the time and 4175 * enable dithering as needed, but that costs bandwidth. So choose 4176 * the minimum value that expresses the full color range of the fb but 4177 * also stays within the max display bpc discovered above. 4178 */ 4179 4180 switch (fb->depth) { 4181 case 8: 4182 bpc = 8; /* since we go through a colormap */ 4183 break; 4184 case 15: 4185 case 16: 4186 bpc = 6; /* min is 18bpp */ 4187 break; 4188 case 24: 4189 bpc = 8; 4190 break; 4191 case 30: 4192 bpc = 10; 4193 break; 4194 case 48: 4195 bpc = 12; 4196 break; 4197 default: 4198 DRM_DEBUG("unsupported depth, assuming 24 bits\n"); 4199 bpc = min((unsigned int)8, display_bpc); 4200 break; 4201 } 4202 4203 display_bpc = min(display_bpc, bpc); 4204 4205 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n", 4206 bpc, display_bpc); 4207 4208 *pipe_bpp = display_bpc * 3; 4209 4210 return display_bpc != bpc; 4211 } 4212 4213 static int vlv_get_refclk(struct drm_crtc *crtc) 4214 { 4215 struct drm_device *dev = crtc->dev; 4216 struct drm_i915_private *dev_priv = dev->dev_private; 4217 int refclk = 27000; /* for DP & HDMI */ 4218 4219 return 100000; /* only one validated so far */ 4220 4221 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { 4222 refclk = 96000; 4223 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 4224 if (intel_panel_use_ssc(dev_priv)) 4225 refclk = 100000; 4226 else 4227 refclk = 96000; 4228 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { 4229 refclk = 100000; 4230 } 4231 4232 return refclk; 4233 } 4234 4235 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) 4236 { 4237 struct drm_device *dev = crtc->dev; 4238 struct drm_i915_private *dev_priv = dev->dev_private; 4239 int refclk; 4240 4241 if (IS_VALLEYVIEW(dev)) { 4242 refclk = vlv_get_refclk(crtc); 4243 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4244 intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 4245 refclk = dev_priv->lvds_ssc_freq * 1000; 4246 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 4247 refclk / 1000); 4248 } else if (!IS_GEN2(dev)) { 4249 refclk = 96000; 4250 } else { 4251 refclk = 48000; 4252 } 4253 4254 return refclk; 4255 } 4256 4257 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, 4258 intel_clock_t *clock) 4259 { 4260 /* SDVO TV has fixed PLL values depend on its clock range, 4261 this mirrors vbios setting. */ 4262 if (adjusted_mode->clock >= 100000 4263 && adjusted_mode->clock < 140500) { 4264 clock->p1 = 2; 4265 clock->p2 = 10; 4266 clock->n = 3; 4267 clock->m1 = 16; 4268 clock->m2 = 8; 4269 } else if (adjusted_mode->clock >= 140500 4270 && adjusted_mode->clock <= 200000) { 4271 clock->p1 = 1; 4272 clock->p2 = 10; 4273 clock->n = 6; 4274 clock->m1 = 12; 4275 clock->m2 = 8; 4276 } 4277 } 4278 4279 static void i9xx_update_pll_dividers(struct drm_crtc *crtc, 4280 intel_clock_t *clock, 4281 intel_clock_t *reduced_clock) 4282 { 4283 struct drm_device *dev = crtc->dev; 4284 struct drm_i915_private *dev_priv = dev->dev_private; 4285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4286 int pipe = intel_crtc->pipe; 4287 u32 fp, fp2 = 0; 4288 4289 if (IS_PINEVIEW(dev)) { 4290 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2; 4291 if (reduced_clock) 4292 fp2 = (1 << reduced_clock->n) << 16 | 4293 reduced_clock->m1 << 8 | reduced_clock->m2; 4294 } else { 4295 fp = clock->n << 16 | clock->m1 << 8 | clock->m2; 4296 if (reduced_clock) 4297 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 | 4298 reduced_clock->m2; 4299 } 4300 4301 I915_WRITE(FP0(pipe), fp); 4302 4303 intel_crtc->lowfreq_avail = false; 4304 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4305 reduced_clock && i915_powersave) { 4306 I915_WRITE(FP1(pipe), fp2); 4307 intel_crtc->lowfreq_avail = true; 4308 } else { 4309 I915_WRITE(FP1(pipe), fp); 4310 } 4311 } 4312 4313 static void vlv_update_pll(struct drm_crtc *crtc, 4314 struct drm_display_mode *mode, 4315 struct drm_display_mode *adjusted_mode, 4316 intel_clock_t *clock, intel_clock_t *reduced_clock, 4317 int num_connectors) 4318 { 4319 struct drm_device *dev = crtc->dev; 4320 struct drm_i915_private *dev_priv = dev->dev_private; 4321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4322 int pipe = intel_crtc->pipe; 4323 u32 dpll, mdiv, pdiv; 4324 u32 bestn, bestm1, bestm2, bestp1, bestp2; 4325 bool is_sdvo; 4326 u32 temp; 4327 4328 lockmgr(&dev_priv->dpio_lock, LK_EXCLUSIVE); 4329 4330 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || 4331 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); 4332 4333 dpll = DPLL_VGA_MODE_DIS; 4334 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV; 4335 dpll |= DPLL_REFA_CLK_ENABLE_VLV; 4336 dpll |= DPLL_INTEGRATED_CLOCK_VLV; 4337 4338 I915_WRITE(DPLL(pipe), dpll); 4339 POSTING_READ(DPLL(pipe)); 4340 4341 bestn = clock->n; 4342 bestm1 = clock->m1; 4343 bestm2 = clock->m2; 4344 bestp1 = clock->p1; 4345 bestp2 = clock->p2; 4346 4347 /* 4348 * In Valleyview PLL and program lane counter registers are exposed 4349 * through DPIO interface 4350 */ 4351 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 4352 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 4353 mdiv |= ((bestn << DPIO_N_SHIFT)); 4354 mdiv |= (1 << DPIO_POST_DIV_SHIFT); 4355 mdiv |= (1 << DPIO_K_SHIFT); 4356 mdiv |= DPIO_ENABLE_CALIBRATION; 4357 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv); 4358 4359 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000); 4360 4361 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) | 4362 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) | 4363 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) | 4364 (5 << DPIO_CLK_BIAS_CTL_SHIFT); 4365 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv); 4366 4367 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b); 4368 4369 dpll |= DPLL_VCO_ENABLE; 4370 I915_WRITE(DPLL(pipe), dpll); 4371 POSTING_READ(DPLL(pipe)); 4372 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) 4373 DRM_ERROR("DPLL %d failed to lock\n", pipe); 4374 4375 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620); 4376 4377 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 4378 intel_dp_set_m_n(crtc, mode, adjusted_mode); 4379 4380 I915_WRITE(DPLL(pipe), dpll); 4381 4382 /* Wait for the clocks to stabilize. */ 4383 POSTING_READ(DPLL(pipe)); 4384 udelay(150); 4385 4386 temp = 0; 4387 if (is_sdvo) { 4388 temp = intel_mode_get_pixel_multiplier(adjusted_mode); 4389 if (temp > 1) 4390 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 4391 else 4392 temp = 0; 4393 } 4394 I915_WRITE(DPLL_MD(pipe), temp); 4395 POSTING_READ(DPLL_MD(pipe)); 4396 4397 /* Now program lane control registers */ 4398 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) 4399 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 4400 { 4401 temp = 0x1000C4; 4402 if(pipe == 1) 4403 temp |= (1 << 21); 4404 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp); 4405 } 4406 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP)) 4407 { 4408 temp = 0x1000C4; 4409 if(pipe == 1) 4410 temp |= (1 << 21); 4411 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp); 4412 } 4413 4414 lockmgr(&dev_priv->dpio_lock, LK_RELEASE); 4415 } 4416 4417 static void i9xx_update_pll(struct drm_crtc *crtc, 4418 struct drm_display_mode *mode, 4419 struct drm_display_mode *adjusted_mode, 4420 intel_clock_t *clock, intel_clock_t *reduced_clock, 4421 int num_connectors) 4422 { 4423 struct drm_device *dev = crtc->dev; 4424 struct drm_i915_private *dev_priv = dev->dev_private; 4425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4426 struct intel_encoder *encoder; 4427 int pipe = intel_crtc->pipe; 4428 u32 dpll; 4429 bool is_sdvo; 4430 4431 i9xx_update_pll_dividers(crtc, clock, reduced_clock); 4432 4433 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) || 4434 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI); 4435 4436 dpll = DPLL_VGA_MODE_DIS; 4437 4438 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) 4439 dpll |= DPLLB_MODE_LVDS; 4440 else 4441 dpll |= DPLLB_MODE_DAC_SERIAL; 4442 if (is_sdvo) { 4443 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 4444 if (pixel_multiplier > 1) { 4445 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 4446 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES; 4447 } 4448 dpll |= DPLL_DVO_HIGH_SPEED; 4449 } 4450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 4451 dpll |= DPLL_DVO_HIGH_SPEED; 4452 4453 /* compute bitmask from p1 value */ 4454 if (IS_PINEVIEW(dev)) 4455 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 4456 else { 4457 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4458 if (IS_G4X(dev) && reduced_clock) 4459 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 4460 } 4461 switch (clock->p2) { 4462 case 5: 4463 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 4464 break; 4465 case 7: 4466 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 4467 break; 4468 case 10: 4469 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 4470 break; 4471 case 14: 4472 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 4473 break; 4474 } 4475 if (INTEL_INFO(dev)->gen >= 4) 4476 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 4477 4478 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) 4479 dpll |= PLL_REF_INPUT_TVCLKINBC; 4480 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) 4481 /* XXX: just matching BIOS for now */ 4482 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 4483 dpll |= 3; 4484 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4485 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4486 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4487 else 4488 dpll |= PLL_REF_INPUT_DREFCLK; 4489 4490 dpll |= DPLL_VCO_ENABLE; 4491 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 4492 POSTING_READ(DPLL(pipe)); 4493 udelay(150); 4494 4495 for_each_encoder_on_crtc(dev, crtc, encoder) 4496 if (encoder->pre_pll_enable) 4497 encoder->pre_pll_enable(encoder); 4498 4499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) 4500 intel_dp_set_m_n(crtc, mode, adjusted_mode); 4501 4502 I915_WRITE(DPLL(pipe), dpll); 4503 4504 /* Wait for the clocks to stabilize. */ 4505 POSTING_READ(DPLL(pipe)); 4506 udelay(150); 4507 4508 if (INTEL_INFO(dev)->gen >= 4) { 4509 u32 temp = 0; 4510 if (is_sdvo) { 4511 temp = intel_mode_get_pixel_multiplier(adjusted_mode); 4512 if (temp > 1) 4513 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 4514 else 4515 temp = 0; 4516 } 4517 I915_WRITE(DPLL_MD(pipe), temp); 4518 } else { 4519 /* The pixel multiplier can only be updated once the 4520 * DPLL is enabled and the clocks are stable. 4521 * 4522 * So write it again. 4523 */ 4524 I915_WRITE(DPLL(pipe), dpll); 4525 } 4526 } 4527 4528 static void i8xx_update_pll(struct drm_crtc *crtc, 4529 struct drm_display_mode *adjusted_mode, 4530 intel_clock_t *clock, intel_clock_t *reduced_clock, 4531 int num_connectors) 4532 { 4533 struct drm_device *dev = crtc->dev; 4534 struct drm_i915_private *dev_priv = dev->dev_private; 4535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4536 struct intel_encoder *encoder; 4537 int pipe = intel_crtc->pipe; 4538 u32 dpll; 4539 4540 i9xx_update_pll_dividers(crtc, clock, reduced_clock); 4541 4542 dpll = DPLL_VGA_MODE_DIS; 4543 4544 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 4545 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4546 } else { 4547 if (clock->p1 == 2) 4548 dpll |= PLL_P1_DIVIDE_BY_TWO; 4549 else 4550 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 4551 if (clock->p2 == 4) 4552 dpll |= PLL_P2_DIVIDE_BY_4; 4553 } 4554 4555 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT)) 4556 /* XXX: just matching BIOS for now */ 4557 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 4558 dpll |= 3; 4559 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && 4560 intel_panel_use_ssc(dev_priv) && num_connectors < 2) 4561 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 4562 else 4563 dpll |= PLL_REF_INPUT_DREFCLK; 4564 4565 dpll |= DPLL_VCO_ENABLE; 4566 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); 4567 POSTING_READ(DPLL(pipe)); 4568 udelay(150); 4569 4570 for_each_encoder_on_crtc(dev, crtc, encoder) 4571 if (encoder->pre_pll_enable) 4572 encoder->pre_pll_enable(encoder); 4573 4574 I915_WRITE(DPLL(pipe), dpll); 4575 4576 /* Wait for the clocks to stabilize. */ 4577 POSTING_READ(DPLL(pipe)); 4578 udelay(150); 4579 4580 /* The pixel multiplier can only be updated once the 4581 * DPLL is enabled and the clocks are stable. 4582 * 4583 * So write it again. 4584 */ 4585 I915_WRITE(DPLL(pipe), dpll); 4586 } 4587 4588 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, 4589 struct drm_display_mode *mode, 4590 struct drm_display_mode *adjusted_mode) 4591 { 4592 struct drm_device *dev = intel_crtc->base.dev; 4593 struct drm_i915_private *dev_priv = dev->dev_private; 4594 enum i915_pipe pipe = intel_crtc->pipe; 4595 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 4596 uint32_t vsyncshift; 4597 4598 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 4599 /* the chip adds 2 halflines automatically */ 4600 adjusted_mode->crtc_vtotal -= 1; 4601 adjusted_mode->crtc_vblank_end -= 1; 4602 vsyncshift = adjusted_mode->crtc_hsync_start 4603 - adjusted_mode->crtc_htotal / 2; 4604 } else { 4605 vsyncshift = 0; 4606 } 4607 4608 if (INTEL_INFO(dev)->gen > 3) 4609 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); 4610 4611 I915_WRITE(HTOTAL(cpu_transcoder), 4612 (adjusted_mode->crtc_hdisplay - 1) | 4613 ((adjusted_mode->crtc_htotal - 1) << 16)); 4614 I915_WRITE(HBLANK(cpu_transcoder), 4615 (adjusted_mode->crtc_hblank_start - 1) | 4616 ((adjusted_mode->crtc_hblank_end - 1) << 16)); 4617 I915_WRITE(HSYNC(cpu_transcoder), 4618 (adjusted_mode->crtc_hsync_start - 1) | 4619 ((adjusted_mode->crtc_hsync_end - 1) << 16)); 4620 4621 I915_WRITE(VTOTAL(cpu_transcoder), 4622 (adjusted_mode->crtc_vdisplay - 1) | 4623 ((adjusted_mode->crtc_vtotal - 1) << 16)); 4624 I915_WRITE(VBLANK(cpu_transcoder), 4625 (adjusted_mode->crtc_vblank_start - 1) | 4626 ((adjusted_mode->crtc_vblank_end - 1) << 16)); 4627 I915_WRITE(VSYNC(cpu_transcoder), 4628 (adjusted_mode->crtc_vsync_start - 1) | 4629 ((adjusted_mode->crtc_vsync_end - 1) << 16)); 4630 4631 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be 4632 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is 4633 * documented on the DDI_FUNC_CTL register description, EDP Input Select 4634 * bits. */ 4635 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && 4636 (pipe == PIPE_B || pipe == PIPE_C)) 4637 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); 4638 4639 /* pipesrc controls the size that is scaled from, which should 4640 * always be the user's requested size. 4641 */ 4642 I915_WRITE(PIPESRC(pipe), 4643 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); 4644 } 4645 4646 static int i9xx_crtc_mode_set(struct drm_crtc *crtc, 4647 struct drm_display_mode *mode, 4648 struct drm_display_mode *adjusted_mode, 4649 int x, int y, 4650 struct drm_framebuffer *fb) 4651 { 4652 struct drm_device *dev = crtc->dev; 4653 struct drm_i915_private *dev_priv = dev->dev_private; 4654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 4655 int pipe = intel_crtc->pipe; 4656 int plane = intel_crtc->plane; 4657 int refclk, num_connectors = 0; 4658 intel_clock_t clock, reduced_clock; 4659 u32 dspcntr, pipeconf; 4660 bool ok, has_reduced_clock = false, is_sdvo = false; 4661 bool is_lvds = false, is_tv = false, is_dp = false; 4662 struct intel_encoder *encoder; 4663 const intel_limit_t *limit; 4664 int ret; 4665 4666 for_each_encoder_on_crtc(dev, crtc, encoder) { 4667 switch (encoder->type) { 4668 case INTEL_OUTPUT_LVDS: 4669 is_lvds = true; 4670 break; 4671 case INTEL_OUTPUT_SDVO: 4672 case INTEL_OUTPUT_HDMI: 4673 is_sdvo = true; 4674 if (encoder->needs_tv_clock) 4675 is_tv = true; 4676 break; 4677 case INTEL_OUTPUT_TVOUT: 4678 is_tv = true; 4679 break; 4680 case INTEL_OUTPUT_DISPLAYPORT: 4681 is_dp = true; 4682 break; 4683 } 4684 4685 num_connectors++; 4686 } 4687 4688 refclk = i9xx_get_refclk(crtc, num_connectors); 4689 4690 /* 4691 * Returns a set of divisors for the desired target clock with the given 4692 * refclk, or FALSE. The returned values represent the clock equation: 4693 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 4694 */ 4695 limit = intel_limit(crtc, refclk); 4696 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 4697 &clock); 4698 if (!ok) { 4699 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 4700 return -EINVAL; 4701 } 4702 4703 /* Ensure that the cursor is valid for the new mode before changing... */ 4704 intel_crtc_update_cursor(crtc, true); 4705 4706 if (is_lvds && dev_priv->lvds_downclock_avail) { 4707 /* 4708 * Ensure we match the reduced clock's P to the target clock. 4709 * If the clocks don't match, we can't switch the display clock 4710 * by using the FP0/FP1. In such case we will disable the LVDS 4711 * downclock feature. 4712 */ 4713 has_reduced_clock = limit->find_pll(limit, crtc, 4714 dev_priv->lvds_downclock, 4715 refclk, 4716 &clock, 4717 &reduced_clock); 4718 } 4719 4720 if (is_sdvo && is_tv) 4721 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock); 4722 4723 if (IS_GEN2(dev)) 4724 i8xx_update_pll(crtc, adjusted_mode, &clock, 4725 has_reduced_clock ? &reduced_clock : NULL, 4726 num_connectors); 4727 else if (IS_VALLEYVIEW(dev)) 4728 vlv_update_pll(crtc, mode, adjusted_mode, &clock, 4729 has_reduced_clock ? &reduced_clock : NULL, 4730 num_connectors); 4731 else 4732 i9xx_update_pll(crtc, mode, adjusted_mode, &clock, 4733 has_reduced_clock ? &reduced_clock : NULL, 4734 num_connectors); 4735 4736 /* setup pipeconf */ 4737 pipeconf = I915_READ(PIPECONF(pipe)); 4738 4739 /* Set up the display plane register */ 4740 dspcntr = DISPPLANE_GAMMA_ENABLE; 4741 4742 if (pipe == 0) 4743 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; 4744 else 4745 dspcntr |= DISPPLANE_SEL_PIPE_B; 4746 4747 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) { 4748 /* Enable pixel doubling when the dot clock is > 90% of the (display) 4749 * core speed. 4750 * 4751 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the 4752 * pipe == 0 check? 4753 */ 4754 if (mode->clock > 4755 dev_priv->display.get_display_clock_speed(dev) * 9 / 10) 4756 pipeconf |= PIPECONF_DOUBLE_WIDE; 4757 else 4758 pipeconf &= ~PIPECONF_DOUBLE_WIDE; 4759 } 4760 4761 /* default to 8bpc */ 4762 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); 4763 if (is_dp) { 4764 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 4765 pipeconf |= PIPECONF_6BPC | 4766 PIPECONF_DITHER_EN | 4767 PIPECONF_DITHER_TYPE_SP; 4768 } 4769 } 4770 4771 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) { 4772 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) { 4773 pipeconf |= PIPECONF_6BPC | 4774 PIPECONF_ENABLE | 4775 I965_PIPECONF_ACTIVE; 4776 } 4777 } 4778 4779 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); 4780 drm_mode_debug_printmodeline(mode); 4781 4782 if (HAS_PIPE_CXSR(dev)) { 4783 if (intel_crtc->lowfreq_avail) { 4784 DRM_DEBUG_KMS("enabling CxSR downclocking\n"); 4785 pipeconf |= PIPECONF_CXSR_DOWNCLOCK; 4786 } else { 4787 DRM_DEBUG_KMS("disabling CxSR downclocking\n"); 4788 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK; 4789 } 4790 } 4791 4792 pipeconf &= ~PIPECONF_INTERLACE_MASK; 4793 if (!IS_GEN2(dev) && 4794 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 4795 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 4796 else 4797 pipeconf |= PIPECONF_PROGRESSIVE; 4798 4799 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 4800 4801 /* pipesrc and dspsize control the size that is scaled from, 4802 * which should always be the user's requested size. 4803 */ 4804 I915_WRITE(DSPSIZE(plane), 4805 ((mode->vdisplay - 1) << 16) | 4806 (mode->hdisplay - 1)); 4807 I915_WRITE(DSPPOS(plane), 0); 4808 4809 I915_WRITE(PIPECONF(pipe), pipeconf); 4810 POSTING_READ(PIPECONF(pipe)); 4811 intel_enable_pipe(dev_priv, pipe, false); 4812 4813 intel_wait_for_vblank(dev, pipe); 4814 4815 I915_WRITE(DSPCNTR(plane), dspcntr); 4816 POSTING_READ(DSPCNTR(plane)); 4817 4818 ret = intel_pipe_set_base(crtc, x, y, fb); 4819 4820 intel_update_watermarks(dev); 4821 4822 return ret; 4823 } 4824 4825 static void ironlake_init_pch_refclk(struct drm_device *dev) 4826 { 4827 struct drm_i915_private *dev_priv = dev->dev_private; 4828 struct drm_mode_config *mode_config = &dev->mode_config; 4829 struct intel_encoder *encoder; 4830 u32 temp; 4831 bool has_lvds = false; 4832 bool has_cpu_edp = false; 4833 bool has_pch_edp = false; 4834 bool has_panel = false; 4835 bool has_ck505 = false; 4836 bool can_ssc = false; 4837 4838 /* We need to take the global config into account */ 4839 list_for_each_entry(encoder, &mode_config->encoder_list, 4840 base.head) { 4841 switch (encoder->type) { 4842 case INTEL_OUTPUT_LVDS: 4843 has_panel = true; 4844 has_lvds = true; 4845 break; 4846 case INTEL_OUTPUT_EDP: 4847 has_panel = true; 4848 if (intel_encoder_is_pch_edp(&encoder->base)) 4849 has_pch_edp = true; 4850 else 4851 has_cpu_edp = true; 4852 break; 4853 } 4854 } 4855 4856 if (HAS_PCH_IBX(dev)) { 4857 has_ck505 = dev_priv->display_clock_mode; 4858 can_ssc = has_ck505; 4859 } else { 4860 has_ck505 = false; 4861 can_ssc = true; 4862 } 4863 4864 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n", 4865 has_panel, has_lvds, has_pch_edp, has_cpu_edp, 4866 has_ck505); 4867 4868 /* Ironlake: try to setup display ref clock before DPLL 4869 * enabling. This is only under driver's control after 4870 * PCH B stepping, previous chipset stepping should be 4871 * ignoring this setting. 4872 */ 4873 temp = I915_READ(PCH_DREF_CONTROL); 4874 /* Always enable nonspread source */ 4875 temp &= ~DREF_NONSPREAD_SOURCE_MASK; 4876 4877 if (has_ck505) 4878 temp |= DREF_NONSPREAD_CK505_ENABLE; 4879 else 4880 temp |= DREF_NONSPREAD_SOURCE_ENABLE; 4881 4882 if (has_panel) { 4883 temp &= ~DREF_SSC_SOURCE_MASK; 4884 temp |= DREF_SSC_SOURCE_ENABLE; 4885 4886 /* SSC must be turned on before enabling the CPU output */ 4887 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 4888 DRM_DEBUG_KMS("Using SSC on panel\n"); 4889 temp |= DREF_SSC1_ENABLE; 4890 } else 4891 temp &= ~DREF_SSC1_ENABLE; 4892 4893 /* Get SSC going before enabling the outputs */ 4894 I915_WRITE(PCH_DREF_CONTROL, temp); 4895 POSTING_READ(PCH_DREF_CONTROL); 4896 udelay(200); 4897 4898 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 4899 4900 /* Enable CPU source on CPU attached eDP */ 4901 if (has_cpu_edp) { 4902 if (intel_panel_use_ssc(dev_priv) && can_ssc) { 4903 DRM_DEBUG_KMS("Using SSC on eDP\n"); 4904 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; 4905 } 4906 else 4907 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; 4908 } else 4909 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 4910 4911 I915_WRITE(PCH_DREF_CONTROL, temp); 4912 POSTING_READ(PCH_DREF_CONTROL); 4913 udelay(200); 4914 } else { 4915 DRM_DEBUG_KMS("Disabling SSC entirely\n"); 4916 4917 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK; 4918 4919 /* Turn off CPU output */ 4920 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE; 4921 4922 I915_WRITE(PCH_DREF_CONTROL, temp); 4923 POSTING_READ(PCH_DREF_CONTROL); 4924 udelay(200); 4925 4926 /* Turn off the SSC source */ 4927 temp &= ~DREF_SSC_SOURCE_MASK; 4928 temp |= DREF_SSC_SOURCE_DISABLE; 4929 4930 /* Turn off SSC1 */ 4931 temp &= ~ DREF_SSC1_ENABLE; 4932 4933 I915_WRITE(PCH_DREF_CONTROL, temp); 4934 POSTING_READ(PCH_DREF_CONTROL); 4935 udelay(200); 4936 } 4937 } 4938 4939 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */ 4940 static void lpt_init_pch_refclk(struct drm_device *dev) 4941 { 4942 struct drm_i915_private *dev_priv = dev->dev_private; 4943 struct drm_mode_config *mode_config = &dev->mode_config; 4944 struct intel_encoder *encoder; 4945 bool has_vga = false; 4946 bool is_sdv = false; 4947 u32 tmp; 4948 4949 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) { 4950 switch (encoder->type) { 4951 case INTEL_OUTPUT_ANALOG: 4952 has_vga = true; 4953 break; 4954 } 4955 } 4956 4957 if (!has_vga) 4958 return; 4959 4960 mutex_lock(&dev_priv->dpio_lock); 4961 4962 /* XXX: Rip out SDV support once Haswell ships for real. */ 4963 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00) 4964 is_sdv = true; 4965 4966 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 4967 tmp &= ~SBI_SSCCTL_DISABLE; 4968 tmp |= SBI_SSCCTL_PATHALT; 4969 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 4970 4971 udelay(24); 4972 4973 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); 4974 tmp &= ~SBI_SSCCTL_PATHALT; 4975 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); 4976 4977 if (!is_sdv) { 4978 tmp = I915_READ(SOUTH_CHICKEN2); 4979 tmp |= FDI_MPHY_IOSFSB_RESET_CTL; 4980 I915_WRITE(SOUTH_CHICKEN2, tmp); 4981 4982 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & 4983 FDI_MPHY_IOSFSB_RESET_STATUS, 100)) 4984 DRM_ERROR("FDI mPHY reset assert timeout\n"); 4985 4986 tmp = I915_READ(SOUTH_CHICKEN2); 4987 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; 4988 I915_WRITE(SOUTH_CHICKEN2, tmp); 4989 4990 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & 4991 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 4992 100)) 4993 DRM_ERROR("FDI mPHY reset de-assert timeout\n"); 4994 } 4995 4996 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); 4997 tmp &= ~(0xFF << 24); 4998 tmp |= (0x12 << 24); 4999 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); 5000 5001 if (!is_sdv) { 5002 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY); 5003 tmp &= ~(0x3 << 6); 5004 tmp |= (1 << 6) | (1 << 0); 5005 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY); 5006 } 5007 5008 if (is_sdv) { 5009 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY); 5010 tmp |= 0x7FFF; 5011 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY); 5012 } 5013 5014 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); 5015 tmp |= (1 << 11); 5016 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); 5017 5018 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); 5019 tmp |= (1 << 11); 5020 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); 5021 5022 if (is_sdv) { 5023 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY); 5024 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); 5025 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY); 5026 5027 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY); 5028 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16); 5029 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY); 5030 5031 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY); 5032 tmp |= (0x3F << 8); 5033 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY); 5034 5035 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY); 5036 tmp |= (0x3F << 8); 5037 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY); 5038 } 5039 5040 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); 5041 tmp |= (1 << 24) | (1 << 21) | (1 << 18); 5042 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); 5043 5044 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); 5045 tmp |= (1 << 24) | (1 << 21) | (1 << 18); 5046 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); 5047 5048 if (!is_sdv) { 5049 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); 5050 tmp &= ~(7 << 13); 5051 tmp |= (5 << 13); 5052 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); 5053 5054 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); 5055 tmp &= ~(7 << 13); 5056 tmp |= (5 << 13); 5057 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); 5058 } 5059 5060 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); 5061 tmp &= ~0xFF; 5062 tmp |= 0x1C; 5063 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); 5064 5065 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); 5066 tmp &= ~0xFF; 5067 tmp |= 0x1C; 5068 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); 5069 5070 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); 5071 tmp &= ~(0xFF << 16); 5072 tmp |= (0x1C << 16); 5073 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); 5074 5075 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); 5076 tmp &= ~(0xFF << 16); 5077 tmp |= (0x1C << 16); 5078 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); 5079 5080 if (!is_sdv) { 5081 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); 5082 tmp |= (1 << 27); 5083 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); 5084 5085 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); 5086 tmp |= (1 << 27); 5087 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); 5088 5089 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); 5090 tmp &= ~(0xF << 28); 5091 tmp |= (4 << 28); 5092 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); 5093 5094 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); 5095 tmp &= ~(0xF << 28); 5096 tmp |= (4 << 28); 5097 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); 5098 } 5099 5100 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */ 5101 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK); 5102 tmp |= SBI_DBUFF0_ENABLE; 5103 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK); 5104 5105 mutex_unlock(&dev_priv->dpio_lock); 5106 } 5107 5108 /* 5109 * Initialize reference clocks when the driver loads 5110 */ 5111 void intel_init_pch_refclk(struct drm_device *dev) 5112 { 5113 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 5114 ironlake_init_pch_refclk(dev); 5115 else if (HAS_PCH_LPT(dev)) 5116 lpt_init_pch_refclk(dev); 5117 } 5118 5119 static int ironlake_get_refclk(struct drm_crtc *crtc) 5120 { 5121 struct drm_device *dev = crtc->dev; 5122 struct drm_i915_private *dev_priv = dev->dev_private; 5123 struct intel_encoder *encoder; 5124 struct intel_encoder *edp_encoder = NULL; 5125 int num_connectors = 0; 5126 bool is_lvds = false; 5127 5128 for_each_encoder_on_crtc(dev, crtc, encoder) { 5129 switch (encoder->type) { 5130 case INTEL_OUTPUT_LVDS: 5131 is_lvds = true; 5132 break; 5133 case INTEL_OUTPUT_EDP: 5134 edp_encoder = encoder; 5135 break; 5136 } 5137 num_connectors++; 5138 } 5139 5140 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { 5141 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n", 5142 dev_priv->lvds_ssc_freq); 5143 return dev_priv->lvds_ssc_freq * 1000; 5144 } 5145 5146 return 120000; 5147 } 5148 5149 static void ironlake_set_pipeconf(struct drm_crtc *crtc, 5150 struct drm_display_mode *adjusted_mode, 5151 bool dither) 5152 { 5153 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 5154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5155 int pipe = intel_crtc->pipe; 5156 uint32_t val; 5157 5158 val = I915_READ(PIPECONF(pipe)); 5159 5160 val &= ~PIPECONF_BPC_MASK; 5161 switch (intel_crtc->bpp) { 5162 case 18: 5163 val |= PIPECONF_6BPC; 5164 break; 5165 case 24: 5166 val |= PIPECONF_8BPC; 5167 break; 5168 case 30: 5169 val |= PIPECONF_10BPC; 5170 break; 5171 case 36: 5172 val |= PIPECONF_12BPC; 5173 break; 5174 default: 5175 /* Case prevented by intel_choose_pipe_bpp_dither. */ 5176 BUG(); 5177 } 5178 5179 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); 5180 if (dither) 5181 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 5182 5183 val &= ~PIPECONF_INTERLACE_MASK; 5184 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 5185 val |= PIPECONF_INTERLACED_ILK; 5186 else 5187 val |= PIPECONF_PROGRESSIVE; 5188 5189 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 5190 val |= PIPECONF_COLOR_RANGE_SELECT; 5191 else 5192 val &= ~PIPECONF_COLOR_RANGE_SELECT; 5193 5194 I915_WRITE(PIPECONF(pipe), val); 5195 POSTING_READ(PIPECONF(pipe)); 5196 } 5197 5198 /* 5199 * Set up the pipe CSC unit. 5200 * 5201 * Currently only full range RGB to limited range RGB conversion 5202 * is supported, but eventually this should handle various 5203 * RGB<->YCbCr scenarios as well. 5204 */ 5205 static void intel_set_pipe_csc(struct drm_crtc *crtc, 5206 const struct drm_display_mode *adjusted_mode) 5207 { 5208 struct drm_device *dev = crtc->dev; 5209 struct drm_i915_private *dev_priv = dev->dev_private; 5210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5211 int pipe = intel_crtc->pipe; 5212 uint16_t coeff = 0x7800; /* 1.0 */ 5213 5214 /* 5215 * TODO: Check what kind of values actually come out of the pipe 5216 * with these coeff/postoff values and adjust to get the best 5217 * accuracy. Perhaps we even need to take the bpc value into 5218 * consideration. 5219 */ 5220 5221 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 5222 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ 5223 5224 /* 5225 * GY/GU and RY/RU should be the other way around according 5226 * to BSpec, but reality doesn't agree. Just set them up in 5227 * a way that results in the correct picture. 5228 */ 5229 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); 5230 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); 5231 5232 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); 5233 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); 5234 5235 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); 5236 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); 5237 5238 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); 5239 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); 5240 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); 5241 5242 if (INTEL_INFO(dev)->gen > 6) { 5243 uint16_t postoff = 0; 5244 5245 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 5246 postoff = (16 * (1 << 13) / 255) & 0x1fff; 5247 5248 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); 5249 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); 5250 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); 5251 5252 I915_WRITE(PIPE_CSC_MODE(pipe), 0); 5253 } else { 5254 uint32_t mode = CSC_MODE_YUV_TO_RGB; 5255 5256 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) 5257 mode |= CSC_BLACK_SCREEN_OFFSET; 5258 5259 I915_WRITE(PIPE_CSC_MODE(pipe), mode); 5260 } 5261 } 5262 5263 static void haswell_set_pipeconf(struct drm_crtc *crtc, 5264 struct drm_display_mode *adjusted_mode, 5265 bool dither) 5266 { 5267 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 5268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5269 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 5270 uint32_t val; 5271 5272 val = I915_READ(PIPECONF(cpu_transcoder)); 5273 5274 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); 5275 if (dither) 5276 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); 5277 5278 val &= ~PIPECONF_INTERLACE_MASK_HSW; 5279 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 5280 val |= PIPECONF_INTERLACED_ILK; 5281 else 5282 val |= PIPECONF_PROGRESSIVE; 5283 5284 I915_WRITE(PIPECONF(cpu_transcoder), val); 5285 POSTING_READ(PIPECONF(cpu_transcoder)); 5286 } 5287 5288 static bool ironlake_compute_clocks(struct drm_crtc *crtc, 5289 struct drm_display_mode *adjusted_mode, 5290 intel_clock_t *clock, 5291 bool *has_reduced_clock, 5292 intel_clock_t *reduced_clock) 5293 { 5294 struct drm_device *dev = crtc->dev; 5295 struct drm_i915_private *dev_priv = dev->dev_private; 5296 struct intel_encoder *intel_encoder; 5297 int refclk; 5298 const intel_limit_t *limit; 5299 bool ret, is_sdvo = false, is_tv = false, is_lvds = false; 5300 5301 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5302 switch (intel_encoder->type) { 5303 case INTEL_OUTPUT_LVDS: 5304 is_lvds = true; 5305 break; 5306 case INTEL_OUTPUT_SDVO: 5307 case INTEL_OUTPUT_HDMI: 5308 is_sdvo = true; 5309 if (intel_encoder->needs_tv_clock) 5310 is_tv = true; 5311 break; 5312 case INTEL_OUTPUT_TVOUT: 5313 is_tv = true; 5314 break; 5315 } 5316 } 5317 5318 refclk = ironlake_get_refclk(crtc); 5319 5320 /* 5321 * Returns a set of divisors for the desired target clock with the given 5322 * refclk, or FALSE. The returned values represent the clock equation: 5323 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 5324 */ 5325 limit = intel_limit(crtc, refclk); 5326 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL, 5327 clock); 5328 if (!ret) 5329 return false; 5330 5331 if (is_lvds && dev_priv->lvds_downclock_avail) { 5332 /* 5333 * Ensure we match the reduced clock's P to the target clock. 5334 * If the clocks don't match, we can't switch the display clock 5335 * by using the FP0/FP1. In such case we will disable the LVDS 5336 * downclock feature. 5337 */ 5338 *has_reduced_clock = limit->find_pll(limit, crtc, 5339 dev_priv->lvds_downclock, 5340 refclk, 5341 clock, 5342 reduced_clock); 5343 } 5344 5345 if (is_sdvo && is_tv) 5346 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock); 5347 5348 return true; 5349 } 5350 5351 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) 5352 { 5353 struct drm_i915_private *dev_priv = dev->dev_private; 5354 uint32_t temp; 5355 5356 temp = I915_READ(SOUTH_CHICKEN1); 5357 if (temp & FDI_BC_BIFURCATION_SELECT) 5358 return; 5359 5360 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); 5361 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); 5362 5363 temp |= FDI_BC_BIFURCATION_SELECT; 5364 DRM_DEBUG_KMS("enabling fdi C rx\n"); 5365 I915_WRITE(SOUTH_CHICKEN1, temp); 5366 POSTING_READ(SOUTH_CHICKEN1); 5367 } 5368 5369 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) 5370 { 5371 struct drm_device *dev = intel_crtc->base.dev; 5372 struct drm_i915_private *dev_priv = dev->dev_private; 5373 struct intel_crtc *pipe_B_crtc = 5374 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); 5375 5376 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n", 5377 intel_crtc->pipe, intel_crtc->fdi_lanes); 5378 if (intel_crtc->fdi_lanes > 4) { 5379 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n", 5380 intel_crtc->pipe, intel_crtc->fdi_lanes); 5381 /* Clamp lanes to avoid programming the hw with bogus values. */ 5382 intel_crtc->fdi_lanes = 4; 5383 5384 return false; 5385 } 5386 5387 if (dev_priv->num_pipe == 2) 5388 return true; 5389 5390 switch (intel_crtc->pipe) { 5391 case PIPE_A: 5392 return true; 5393 case PIPE_B: 5394 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && 5395 intel_crtc->fdi_lanes > 2) { 5396 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", 5397 intel_crtc->pipe, intel_crtc->fdi_lanes); 5398 /* Clamp lanes to avoid programming the hw with bogus values. */ 5399 intel_crtc->fdi_lanes = 2; 5400 5401 return false; 5402 } 5403 5404 if (intel_crtc->fdi_lanes > 2) 5405 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); 5406 else 5407 cpt_enable_fdi_bc_bifurcation(dev); 5408 5409 return true; 5410 case PIPE_C: 5411 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) { 5412 if (intel_crtc->fdi_lanes > 2) { 5413 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n", 5414 intel_crtc->pipe, intel_crtc->fdi_lanes); 5415 /* Clamp lanes to avoid programming the hw with bogus values. */ 5416 intel_crtc->fdi_lanes = 2; 5417 5418 return false; 5419 } 5420 } else { 5421 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); 5422 return false; 5423 } 5424 5425 cpt_enable_fdi_bc_bifurcation(dev); 5426 5427 return true; 5428 default: 5429 BUG(); 5430 } 5431 } 5432 5433 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) 5434 { 5435 /* 5436 * Account for spread spectrum to avoid 5437 * oversubscribing the link. Max center spread 5438 * is 2.5%; use 5% for safety's sake. 5439 */ 5440 u32 bps = target_clock * bpp * 21 / 20; 5441 return bps / (link_bw * 8) + 1; 5442 } 5443 5444 static void ironlake_set_m_n(struct drm_crtc *crtc, 5445 struct drm_display_mode *mode, 5446 struct drm_display_mode *adjusted_mode) 5447 { 5448 struct drm_device *dev = crtc->dev; 5449 struct drm_i915_private *dev_priv = dev->dev_private; 5450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5451 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 5452 struct intel_encoder *intel_encoder, *edp_encoder = NULL; 5453 struct intel_link_m_n m_n = {0}; 5454 int target_clock, pixel_multiplier, lane, link_bw; 5455 bool is_dp = false, is_cpu_edp = false; 5456 5457 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5458 switch (intel_encoder->type) { 5459 case INTEL_OUTPUT_DISPLAYPORT: 5460 is_dp = true; 5461 break; 5462 case INTEL_OUTPUT_EDP: 5463 is_dp = true; 5464 if (!intel_encoder_is_pch_edp(&intel_encoder->base)) 5465 is_cpu_edp = true; 5466 edp_encoder = intel_encoder; 5467 break; 5468 } 5469 } 5470 5471 /* FDI link */ 5472 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 5473 lane = 0; 5474 /* CPU eDP doesn't require FDI link, so just set DP M/N 5475 according to current link config */ 5476 if (is_cpu_edp) { 5477 intel_edp_link_config(edp_encoder, &lane, &link_bw); 5478 } else { 5479 /* FDI is a binary signal running at ~2.7GHz, encoding 5480 * each output octet as 10 bits. The actual frequency 5481 * is stored as a divider into a 100MHz clock, and the 5482 * mode pixel clock is stored in units of 1KHz. 5483 * Hence the bw of each lane in terms of the mode signal 5484 * is: 5485 */ 5486 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; 5487 } 5488 5489 /* [e]DP over FDI requires target mode clock instead of link clock. */ 5490 if (edp_encoder) 5491 target_clock = intel_edp_target_clock(edp_encoder, mode); 5492 else if (is_dp) 5493 target_clock = mode->clock; 5494 else 5495 target_clock = adjusted_mode->clock; 5496 5497 if (!lane) 5498 lane = ironlake_get_lanes_required(target_clock, link_bw, 5499 intel_crtc->bpp); 5500 5501 intel_crtc->fdi_lanes = lane; 5502 5503 if (pixel_multiplier > 1) 5504 link_bw *= pixel_multiplier; 5505 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n); 5506 5507 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m); 5508 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); 5509 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); 5510 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); 5511 } 5512 5513 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, 5514 struct drm_display_mode *adjusted_mode, 5515 intel_clock_t *clock, u32 fp) 5516 { 5517 struct drm_crtc *crtc = &intel_crtc->base; 5518 struct drm_device *dev = crtc->dev; 5519 struct drm_i915_private *dev_priv = dev->dev_private; 5520 struct intel_encoder *intel_encoder; 5521 uint32_t dpll; 5522 int factor, pixel_multiplier, num_connectors = 0; 5523 bool is_lvds = false, is_sdvo = false, is_tv = false; 5524 bool is_dp = false, is_cpu_edp = false; 5525 5526 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 5527 switch (intel_encoder->type) { 5528 case INTEL_OUTPUT_LVDS: 5529 is_lvds = true; 5530 break; 5531 case INTEL_OUTPUT_SDVO: 5532 case INTEL_OUTPUT_HDMI: 5533 is_sdvo = true; 5534 if (intel_encoder->needs_tv_clock) 5535 is_tv = true; 5536 break; 5537 case INTEL_OUTPUT_TVOUT: 5538 is_tv = true; 5539 break; 5540 case INTEL_OUTPUT_DISPLAYPORT: 5541 is_dp = true; 5542 break; 5543 case INTEL_OUTPUT_EDP: 5544 is_dp = true; 5545 if (!intel_encoder_is_pch_edp(&intel_encoder->base)) 5546 is_cpu_edp = true; 5547 break; 5548 } 5549 5550 num_connectors++; 5551 } 5552 5553 /* Enable autotuning of the PLL clock (if permissible) */ 5554 factor = 21; 5555 if (is_lvds) { 5556 if ((intel_panel_use_ssc(dev_priv) && 5557 dev_priv->lvds_ssc_freq == 100) || 5558 intel_is_dual_link_lvds(dev)) 5559 factor = 25; 5560 } else if (is_sdvo && is_tv) 5561 factor = 20; 5562 5563 if (clock->m < factor * clock->n) 5564 fp |= FP_CB_TUNE; 5565 5566 dpll = 0; 5567 5568 if (is_lvds) 5569 dpll |= DPLLB_MODE_LVDS; 5570 else 5571 dpll |= DPLLB_MODE_DAC_SERIAL; 5572 if (is_sdvo) { 5573 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); 5574 if (pixel_multiplier > 1) { 5575 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 5576 } 5577 dpll |= DPLL_DVO_HIGH_SPEED; 5578 } 5579 if (is_dp && !is_cpu_edp) 5580 dpll |= DPLL_DVO_HIGH_SPEED; 5581 5582 /* compute bitmask from p1 value */ 5583 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 5584 /* also FPA1 */ 5585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 5586 5587 switch (clock->p2) { 5588 case 5: 5589 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 5590 break; 5591 case 7: 5592 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 5593 break; 5594 case 10: 5595 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 5596 break; 5597 case 14: 5598 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 5599 break; 5600 } 5601 5602 if (is_sdvo && is_tv) 5603 dpll |= PLL_REF_INPUT_TVCLKINBC; 5604 else if (is_tv) 5605 /* XXX: just matching BIOS for now */ 5606 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */ 5607 dpll |= 3; 5608 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) 5609 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 5610 else 5611 dpll |= PLL_REF_INPUT_DREFCLK; 5612 5613 return dpll; 5614 } 5615 5616 static int ironlake_crtc_mode_set(struct drm_crtc *crtc, 5617 struct drm_display_mode *mode, 5618 struct drm_display_mode *adjusted_mode, 5619 int x, int y, 5620 struct drm_framebuffer *fb) 5621 { 5622 struct drm_device *dev = crtc->dev; 5623 struct drm_i915_private *dev_priv = dev->dev_private; 5624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5625 int pipe = intel_crtc->pipe; 5626 int plane = intel_crtc->plane; 5627 int num_connectors = 0; 5628 intel_clock_t clock, reduced_clock; 5629 u32 dpll, fp = 0, fp2 = 0; 5630 bool ok, has_reduced_clock = false; 5631 bool is_lvds = false, is_dp = false, is_cpu_edp = false; 5632 struct intel_encoder *encoder; 5633 int ret; 5634 bool dither, fdi_config_ok; 5635 5636 for_each_encoder_on_crtc(dev, crtc, encoder) { 5637 switch (encoder->type) { 5638 case INTEL_OUTPUT_LVDS: 5639 is_lvds = true; 5640 break; 5641 case INTEL_OUTPUT_DISPLAYPORT: 5642 is_dp = true; 5643 break; 5644 case INTEL_OUTPUT_EDP: 5645 is_dp = true; 5646 if (!intel_encoder_is_pch_edp(&encoder->base)) 5647 is_cpu_edp = true; 5648 break; 5649 } 5650 5651 num_connectors++; 5652 } 5653 5654 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), 5655 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); 5656 5657 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock, 5658 &has_reduced_clock, &reduced_clock); 5659 if (!ok) { 5660 DRM_ERROR("Couldn't find PLL settings for mode!\n"); 5661 return -EINVAL; 5662 } 5663 5664 /* Ensure that the cursor is valid for the new mode before changing... */ 5665 intel_crtc_update_cursor(crtc, true); 5666 5667 /* determine panel color depth */ 5668 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, 5669 adjusted_mode); 5670 if (is_lvds && dev_priv->lvds_dither) 5671 dither = true; 5672 5673 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; 5674 if (has_reduced_clock) 5675 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 | 5676 reduced_clock.m2; 5677 5678 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp); 5679 5680 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 5681 drm_mode_debug_printmodeline(mode); 5682 5683 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 5684 if (!is_cpu_edp) { 5685 struct intel_pch_pll *pll; 5686 5687 pll = intel_get_pch_pll(intel_crtc, dpll, fp); 5688 if (pll == NULL) { 5689 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n", 5690 pipe); 5691 return -EINVAL; 5692 } 5693 } else 5694 intel_put_pch_pll(intel_crtc); 5695 5696 if (is_dp && !is_cpu_edp) 5697 intel_dp_set_m_n(crtc, mode, adjusted_mode); 5698 5699 for_each_encoder_on_crtc(dev, crtc, encoder) 5700 if (encoder->pre_pll_enable) 5701 encoder->pre_pll_enable(encoder); 5702 5703 if (intel_crtc->pch_pll) { 5704 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); 5705 5706 /* Wait for the clocks to stabilize. */ 5707 POSTING_READ(intel_crtc->pch_pll->pll_reg); 5708 udelay(150); 5709 5710 /* The pixel multiplier can only be updated once the 5711 * DPLL is enabled and the clocks are stable. 5712 * 5713 * So write it again. 5714 */ 5715 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll); 5716 } 5717 5718 intel_crtc->lowfreq_avail = false; 5719 if (intel_crtc->pch_pll) { 5720 if (is_lvds && has_reduced_clock && i915_powersave) { 5721 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2); 5722 intel_crtc->lowfreq_avail = true; 5723 } else { 5724 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp); 5725 } 5726 } 5727 5728 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5729 5730 /* Note, this also computes intel_crtc->fdi_lanes which is used below in 5731 * ironlake_check_fdi_lanes. */ 5732 5733 ironlake_set_m_n(crtc, mode, adjusted_mode); 5734 5735 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc); 5736 5737 ironlake_set_pipeconf(crtc, adjusted_mode, dither); 5738 5739 intel_wait_for_vblank(dev, pipe); 5740 5741 /* Set up the display plane register */ 5742 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE); 5743 POSTING_READ(DSPCNTR(plane)); 5744 5745 ret = intel_pipe_set_base(crtc, x, y, fb); 5746 5747 intel_update_watermarks(dev); 5748 5749 intel_update_linetime_watermarks(dev, pipe, adjusted_mode); 5750 5751 return fdi_config_ok ? ret : -EINVAL; 5752 } 5753 5754 static void haswell_modeset_global_resources(struct drm_device *dev) 5755 { 5756 struct drm_i915_private *dev_priv = dev->dev_private; 5757 bool enable = false; 5758 struct intel_crtc *crtc; 5759 struct intel_encoder *encoder; 5760 5761 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { 5762 if (crtc->pipe != PIPE_A && crtc->base.enabled) 5763 enable = true; 5764 /* XXX: Should check for edp transcoder here, but thanks to init 5765 * sequence that's not yet available. Just in case desktop eDP 5766 * on PORT D is possible on haswell, too. */ 5767 } 5768 5769 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 5770 base.head) { 5771 if (encoder->type != INTEL_OUTPUT_EDP && 5772 encoder->connectors_active) 5773 enable = true; 5774 } 5775 5776 /* Even the eDP panel fitter is outside the always-on well. */ 5777 if (dev_priv->pch_pf_size) 5778 enable = true; 5779 5780 intel_set_power_well(dev, enable); 5781 } 5782 5783 static int haswell_crtc_mode_set(struct drm_crtc *crtc, 5784 struct drm_display_mode *mode, 5785 struct drm_display_mode *adjusted_mode, 5786 int x, int y, 5787 struct drm_framebuffer *fb) 5788 { 5789 struct drm_device *dev = crtc->dev; 5790 struct drm_i915_private *dev_priv = dev->dev_private; 5791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5792 int pipe = intel_crtc->pipe; 5793 int plane = intel_crtc->plane; 5794 int num_connectors = 0; 5795 bool is_dp = false, is_cpu_edp = false; 5796 struct intel_encoder *encoder; 5797 int ret; 5798 bool dither; 5799 5800 for_each_encoder_on_crtc(dev, crtc, encoder) { 5801 switch (encoder->type) { 5802 case INTEL_OUTPUT_DISPLAYPORT: 5803 is_dp = true; 5804 break; 5805 case INTEL_OUTPUT_EDP: 5806 is_dp = true; 5807 if (!intel_encoder_is_pch_edp(&encoder->base)) 5808 is_cpu_edp = true; 5809 break; 5810 } 5811 5812 num_connectors++; 5813 } 5814 5815 if (is_cpu_edp) 5816 intel_crtc->cpu_transcoder = TRANSCODER_EDP; 5817 else 5818 intel_crtc->cpu_transcoder = pipe; 5819 5820 /* We are not sure yet this won't happen. */ 5821 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n", 5822 INTEL_PCH_TYPE(dev)); 5823 5824 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", 5825 num_connectors, pipe_name(pipe)); 5826 5827 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) & 5828 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); 5829 5830 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); 5831 5832 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock)) 5833 return -EINVAL; 5834 5835 /* Ensure that the cursor is valid for the new mode before changing... */ 5836 intel_crtc_update_cursor(crtc, true); 5837 5838 /* determine panel color depth */ 5839 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, 5840 adjusted_mode); 5841 5842 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe); 5843 drm_mode_debug_printmodeline(mode); 5844 5845 if (is_dp && !is_cpu_edp) 5846 intel_dp_set_m_n(crtc, mode, adjusted_mode); 5847 5848 intel_crtc->lowfreq_avail = false; 5849 5850 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode); 5851 5852 if (!is_dp || is_cpu_edp) 5853 ironlake_set_m_n(crtc, mode, adjusted_mode); 5854 5855 haswell_set_pipeconf(crtc, adjusted_mode, dither); 5856 5857 intel_set_pipe_csc(crtc, adjusted_mode); 5858 5859 /* Set up the display plane register */ 5860 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE); 5861 POSTING_READ(DSPCNTR(plane)); 5862 5863 ret = intel_pipe_set_base(crtc, x, y, fb); 5864 5865 intel_update_watermarks(dev); 5866 5867 intel_update_linetime_watermarks(dev, pipe, adjusted_mode); 5868 5869 return ret; 5870 } 5871 5872 static int intel_crtc_mode_set(struct drm_crtc *crtc, 5873 struct drm_display_mode *mode, 5874 struct drm_display_mode *adjusted_mode, 5875 int x, int y, 5876 struct drm_framebuffer *fb) 5877 { 5878 struct drm_device *dev = crtc->dev; 5879 struct drm_i915_private *dev_priv = dev->dev_private; 5880 struct drm_encoder_helper_funcs *encoder_funcs; 5881 struct intel_encoder *encoder; 5882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5883 int pipe = intel_crtc->pipe; 5884 int ret; 5885 5886 drm_vblank_pre_modeset(dev, pipe); 5887 5888 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, 5889 x, y, fb); 5890 drm_vblank_post_modeset(dev, pipe); 5891 5892 if (ret != 0) 5893 return ret; 5894 5895 for_each_encoder_on_crtc(dev, crtc, encoder) { 5896 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n", 5897 encoder->base.base.id, 5898 drm_get_encoder_name(&encoder->base), 5899 mode->base.id, mode->name); 5900 encoder_funcs = encoder->base.helper_private; 5901 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode); 5902 } 5903 5904 return 0; 5905 } 5906 5907 static bool intel_eld_uptodate(struct drm_connector *connector, 5908 int reg_eldv, uint32_t bits_eldv, 5909 int reg_elda, uint32_t bits_elda, 5910 int reg_edid) 5911 { 5912 struct drm_i915_private *dev_priv = connector->dev->dev_private; 5913 uint8_t *eld = connector->eld; 5914 uint32_t i; 5915 5916 i = I915_READ(reg_eldv); 5917 i &= bits_eldv; 5918 5919 if (!eld[0]) 5920 return !i; 5921 5922 if (!i) 5923 return false; 5924 5925 i = I915_READ(reg_elda); 5926 i &= ~bits_elda; 5927 I915_WRITE(reg_elda, i); 5928 5929 for (i = 0; i < eld[2]; i++) 5930 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 5931 return false; 5932 5933 return true; 5934 } 5935 5936 static void g4x_write_eld(struct drm_connector *connector, 5937 struct drm_crtc *crtc) 5938 { 5939 struct drm_i915_private *dev_priv = connector->dev->dev_private; 5940 uint8_t *eld = connector->eld; 5941 uint32_t eldv; 5942 uint32_t len; 5943 uint32_t i; 5944 5945 i = I915_READ(G4X_AUD_VID_DID); 5946 5947 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) 5948 eldv = G4X_ELDV_DEVCL_DEVBLC; 5949 else 5950 eldv = G4X_ELDV_DEVCTG; 5951 5952 if (intel_eld_uptodate(connector, 5953 G4X_AUD_CNTL_ST, eldv, 5954 G4X_AUD_CNTL_ST, G4X_ELD_ADDR, 5955 G4X_HDMIW_HDMIEDID)) 5956 return; 5957 5958 i = I915_READ(G4X_AUD_CNTL_ST); 5959 i &= ~(eldv | G4X_ELD_ADDR); 5960 len = (i >> 9) & 0x1f; /* ELD buffer size */ 5961 I915_WRITE(G4X_AUD_CNTL_ST, i); 5962 5963 if (!eld[0]) 5964 return; 5965 5966 len = min_t(uint8_t, eld[2], len); 5967 DRM_DEBUG_DRIVER("ELD size %d\n", len); 5968 for (i = 0; i < len; i++) 5969 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 5970 5971 i = I915_READ(G4X_AUD_CNTL_ST); 5972 i |= eldv; 5973 I915_WRITE(G4X_AUD_CNTL_ST, i); 5974 } 5975 5976 static void haswell_write_eld(struct drm_connector *connector, 5977 struct drm_crtc *crtc) 5978 { 5979 struct drm_i915_private *dev_priv = connector->dev->dev_private; 5980 uint8_t *eld = connector->eld; 5981 struct drm_device *dev = crtc->dev; 5982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 5983 uint32_t eldv; 5984 uint32_t i; 5985 int len; 5986 int pipe = to_intel_crtc(crtc)->pipe; 5987 int tmp; 5988 5989 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); 5990 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); 5991 int aud_config = HSW_AUD_CFG(pipe); 5992 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; 5993 5994 5995 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n"); 5996 5997 /* Audio output enable */ 5998 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); 5999 tmp = I915_READ(aud_cntrl_st2); 6000 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); 6001 I915_WRITE(aud_cntrl_st2, tmp); 6002 6003 /* Wait for 1 vertical blank */ 6004 intel_wait_for_vblank(dev, pipe); 6005 6006 /* Set ELD valid state */ 6007 tmp = I915_READ(aud_cntrl_st2); 6008 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp); 6009 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); 6010 I915_WRITE(aud_cntrl_st2, tmp); 6011 tmp = I915_READ(aud_cntrl_st2); 6012 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp); 6013 6014 /* Enable HDMI mode */ 6015 tmp = I915_READ(aud_config); 6016 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp); 6017 /* clear N_programing_enable and N_value_index */ 6018 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); 6019 I915_WRITE(aud_config, tmp); 6020 6021 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); 6022 6023 eldv = AUDIO_ELD_VALID_A << (pipe * 4); 6024 intel_crtc->eld_vld = true; 6025 6026 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 6027 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); 6028 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ 6029 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ 6030 } else 6031 I915_WRITE(aud_config, 0); 6032 6033 if (intel_eld_uptodate(connector, 6034 aud_cntrl_st2, eldv, 6035 aud_cntl_st, IBX_ELD_ADDRESS, 6036 hdmiw_hdmiedid)) 6037 return; 6038 6039 i = I915_READ(aud_cntrl_st2); 6040 i &= ~eldv; 6041 I915_WRITE(aud_cntrl_st2, i); 6042 6043 if (!eld[0]) 6044 return; 6045 6046 i = I915_READ(aud_cntl_st); 6047 i &= ~IBX_ELD_ADDRESS; 6048 I915_WRITE(aud_cntl_st, i); 6049 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ 6050 DRM_DEBUG_DRIVER("port num:%d\n", i); 6051 6052 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ 6053 DRM_DEBUG_DRIVER("ELD size %d\n", len); 6054 for (i = 0; i < len; i++) 6055 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 6056 6057 i = I915_READ(aud_cntrl_st2); 6058 i |= eldv; 6059 I915_WRITE(aud_cntrl_st2, i); 6060 6061 } 6062 6063 static void ironlake_write_eld(struct drm_connector *connector, 6064 struct drm_crtc *crtc) 6065 { 6066 struct drm_i915_private *dev_priv = connector->dev->dev_private; 6067 uint8_t *eld = connector->eld; 6068 uint32_t eldv; 6069 uint32_t i; 6070 int len; 6071 int hdmiw_hdmiedid; 6072 int aud_config; 6073 int aud_cntl_st; 6074 int aud_cntrl_st2; 6075 int pipe = to_intel_crtc(crtc)->pipe; 6076 6077 if (HAS_PCH_IBX(connector->dev)) { 6078 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 6079 aud_config = IBX_AUD_CFG(pipe); 6080 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 6081 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 6082 } else { 6083 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 6084 aud_config = CPT_AUD_CFG(pipe); 6085 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 6086 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 6087 } 6088 6089 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); 6090 6091 i = I915_READ(aud_cntl_st); 6092 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ 6093 if (!i) { 6094 DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); 6095 /* operate blindly on all ports */ 6096 eldv = IBX_ELD_VALIDB; 6097 eldv |= IBX_ELD_VALIDB << 4; 6098 eldv |= IBX_ELD_VALIDB << 8; 6099 } else { 6100 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i); 6101 eldv = IBX_ELD_VALIDB << ((i - 1) * 4); 6102 } 6103 6104 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { 6105 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); 6106 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ 6107 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ 6108 } else 6109 I915_WRITE(aud_config, 0); 6110 6111 if (intel_eld_uptodate(connector, 6112 aud_cntrl_st2, eldv, 6113 aud_cntl_st, IBX_ELD_ADDRESS, 6114 hdmiw_hdmiedid)) 6115 return; 6116 6117 i = I915_READ(aud_cntrl_st2); 6118 i &= ~eldv; 6119 I915_WRITE(aud_cntrl_st2, i); 6120 6121 if (!eld[0]) 6122 return; 6123 6124 i = I915_READ(aud_cntl_st); 6125 i &= ~IBX_ELD_ADDRESS; 6126 I915_WRITE(aud_cntl_st, i); 6127 6128 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ 6129 DRM_DEBUG_DRIVER("ELD size %d\n", len); 6130 for (i = 0; i < len; i++) 6131 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 6132 6133 i = I915_READ(aud_cntrl_st2); 6134 i |= eldv; 6135 I915_WRITE(aud_cntrl_st2, i); 6136 } 6137 6138 void intel_write_eld(struct drm_encoder *encoder, 6139 struct drm_display_mode *mode) 6140 { 6141 struct drm_crtc *crtc = encoder->crtc; 6142 struct drm_connector *connector; 6143 struct drm_device *dev = encoder->dev; 6144 struct drm_i915_private *dev_priv = dev->dev_private; 6145 6146 connector = drm_select_eld(encoder, mode); 6147 if (!connector) 6148 return; 6149 6150 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 6151 connector->base.id, 6152 drm_get_connector_name(connector), 6153 connector->encoder->base.id, 6154 drm_get_encoder_name(connector->encoder)); 6155 6156 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; 6157 6158 if (dev_priv->display.write_eld) 6159 dev_priv->display.write_eld(connector, crtc); 6160 } 6161 6162 /** Loads the palette/gamma unit for the CRTC with the prepared values */ 6163 void intel_crtc_load_lut(struct drm_crtc *crtc) 6164 { 6165 struct drm_device *dev = crtc->dev; 6166 struct drm_i915_private *dev_priv = dev->dev_private; 6167 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6168 int palreg = PALETTE(intel_crtc->pipe); 6169 int i; 6170 6171 /* The clocks have to be on to load the palette. */ 6172 if (!crtc->enabled || !intel_crtc->active) 6173 return; 6174 6175 /* use legacy palette for Ironlake */ 6176 if (HAS_PCH_SPLIT(dev)) 6177 palreg = LGC_PALETTE(intel_crtc->pipe); 6178 6179 for (i = 0; i < 256; i++) { 6180 I915_WRITE(palreg + 4 * i, 6181 (intel_crtc->lut_r[i] << 16) | 6182 (intel_crtc->lut_g[i] << 8) | 6183 intel_crtc->lut_b[i]); 6184 } 6185 } 6186 6187 static void i845_update_cursor(struct drm_crtc *crtc, u32 base) 6188 { 6189 struct drm_device *dev = crtc->dev; 6190 struct drm_i915_private *dev_priv = dev->dev_private; 6191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6192 bool visible = base != 0; 6193 u32 cntl; 6194 6195 if (intel_crtc->cursor_visible == visible) 6196 return; 6197 6198 cntl = I915_READ(_CURACNTR); 6199 if (visible) { 6200 /* On these chipsets we can only modify the base whilst 6201 * the cursor is disabled. 6202 */ 6203 I915_WRITE(_CURABASE, base); 6204 6205 cntl &= ~(CURSOR_FORMAT_MASK); 6206 /* XXX width must be 64, stride 256 => 0x00 << 28 */ 6207 cntl |= CURSOR_ENABLE | 6208 CURSOR_GAMMA_ENABLE | 6209 CURSOR_FORMAT_ARGB; 6210 } else 6211 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE); 6212 I915_WRITE(_CURACNTR, cntl); 6213 6214 intel_crtc->cursor_visible = visible; 6215 } 6216 6217 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) 6218 { 6219 struct drm_device *dev = crtc->dev; 6220 struct drm_i915_private *dev_priv = dev->dev_private; 6221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6222 int pipe = intel_crtc->pipe; 6223 bool visible = base != 0; 6224 6225 if (intel_crtc->cursor_visible != visible) { 6226 uint32_t cntl = I915_READ(CURCNTR(pipe)); 6227 if (base) { 6228 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); 6229 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 6230 cntl |= pipe << 28; /* Connect to correct pipe */ 6231 } else { 6232 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 6233 cntl |= CURSOR_MODE_DISABLE; 6234 } 6235 I915_WRITE(CURCNTR(pipe), cntl); 6236 6237 intel_crtc->cursor_visible = visible; 6238 } 6239 /* and commit changes on next vblank */ 6240 I915_WRITE(CURBASE(pipe), base); 6241 } 6242 6243 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base) 6244 { 6245 struct drm_device *dev = crtc->dev; 6246 struct drm_i915_private *dev_priv = dev->dev_private; 6247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6248 int pipe = intel_crtc->pipe; 6249 bool visible = base != 0; 6250 6251 if (intel_crtc->cursor_visible != visible) { 6252 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe)); 6253 if (base) { 6254 cntl &= ~CURSOR_MODE; 6255 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; 6256 } else { 6257 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE); 6258 cntl |= CURSOR_MODE_DISABLE; 6259 } 6260 if (IS_HASWELL(dev)) 6261 cntl |= CURSOR_PIPE_CSC_ENABLE; 6262 I915_WRITE(CURCNTR_IVB(pipe), cntl); 6263 6264 intel_crtc->cursor_visible = visible; 6265 } 6266 /* and commit changes on next vblank */ 6267 I915_WRITE(CURBASE_IVB(pipe), base); 6268 } 6269 6270 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ 6271 static void intel_crtc_update_cursor(struct drm_crtc *crtc, 6272 bool on) 6273 { 6274 struct drm_device *dev = crtc->dev; 6275 struct drm_i915_private *dev_priv = dev->dev_private; 6276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6277 int pipe = intel_crtc->pipe; 6278 int x = intel_crtc->cursor_x; 6279 int y = intel_crtc->cursor_y; 6280 u32 base, pos; 6281 bool visible; 6282 6283 pos = 0; 6284 6285 if (on && crtc->enabled && crtc->fb) { 6286 base = intel_crtc->cursor_addr; 6287 if (x > (int) crtc->fb->width) 6288 base = 0; 6289 6290 if (y > (int) crtc->fb->height) 6291 base = 0; 6292 } else 6293 base = 0; 6294 6295 if (x < 0) { 6296 if (x + intel_crtc->cursor_width < 0) 6297 base = 0; 6298 6299 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; 6300 x = -x; 6301 } 6302 pos |= x << CURSOR_X_SHIFT; 6303 6304 if (y < 0) { 6305 if (y + intel_crtc->cursor_height < 0) 6306 base = 0; 6307 6308 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; 6309 y = -y; 6310 } 6311 pos |= y << CURSOR_Y_SHIFT; 6312 6313 visible = base != 0; 6314 if (!visible && !intel_crtc->cursor_visible) 6315 return; 6316 6317 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { 6318 I915_WRITE(CURPOS_IVB(pipe), pos); 6319 ivb_update_cursor(crtc, base); 6320 } else { 6321 I915_WRITE(CURPOS(pipe), pos); 6322 if (IS_845G(dev) || IS_I865G(dev)) 6323 i845_update_cursor(crtc, base); 6324 else 6325 i9xx_update_cursor(crtc, base); 6326 } 6327 } 6328 6329 static int intel_crtc_cursor_set(struct drm_crtc *crtc, 6330 struct drm_file *file, 6331 uint32_t handle, 6332 uint32_t width, uint32_t height) 6333 { 6334 struct drm_device *dev = crtc->dev; 6335 struct drm_i915_private *dev_priv = dev->dev_private; 6336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6337 struct drm_i915_gem_object *obj; 6338 uint32_t addr; 6339 int ret; 6340 6341 /* if we want to turn off the cursor ignore width and height */ 6342 if (!handle) { 6343 DRM_DEBUG_KMS("cursor off\n"); 6344 addr = 0; 6345 obj = NULL; 6346 mutex_lock(&dev->struct_mutex); 6347 goto finish; 6348 } 6349 6350 /* Currently we only support 64x64 cursors */ 6351 if (width != 64 || height != 64) { 6352 DRM_ERROR("we currently only support 64x64 cursors\n"); 6353 return -EINVAL; 6354 } 6355 6356 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); 6357 if (&obj->base == NULL) 6358 return -ENOENT; 6359 6360 if (obj->base.size < width * height * 4) { 6361 DRM_ERROR("buffer is to small\n"); 6362 ret = -ENOMEM; 6363 goto fail; 6364 } 6365 6366 /* we only need to pin inside GTT if cursor is non-phy */ 6367 mutex_lock(&dev->struct_mutex); 6368 if (!dev_priv->info->cursor_needs_physical) { 6369 if (obj->tiling_mode) { 6370 DRM_ERROR("cursor cannot be tiled\n"); 6371 ret = -EINVAL; 6372 goto fail_locked; 6373 } 6374 6375 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL); 6376 if (ret) { 6377 DRM_ERROR("failed to move cursor bo into the GTT\n"); 6378 goto fail_locked; 6379 } 6380 6381 ret = i915_gem_object_put_fence(obj); 6382 if (ret) { 6383 DRM_ERROR("failed to release fence for cursor"); 6384 goto fail_unpin; 6385 } 6386 6387 addr = obj->gtt_offset; 6388 } else { 6389 int align = IS_I830(dev) ? 16 * 1024 : 256; 6390 ret = i915_gem_attach_phys_object(dev, obj, 6391 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1, 6392 align); 6393 if (ret) { 6394 DRM_ERROR("failed to attach phys object\n"); 6395 goto fail_locked; 6396 } 6397 addr = obj->phys_obj->handle->busaddr; 6398 } 6399 6400 if (IS_GEN2(dev)) 6401 I915_WRITE(CURSIZE, (height << 12) | width); 6402 6403 finish: 6404 if (intel_crtc->cursor_bo) { 6405 if (dev_priv->info->cursor_needs_physical) { 6406 if (intel_crtc->cursor_bo != obj) 6407 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo); 6408 } else 6409 i915_gem_object_unpin(intel_crtc->cursor_bo); 6410 drm_gem_object_unreference(&intel_crtc->cursor_bo->base); 6411 } 6412 6413 mutex_unlock(&dev->struct_mutex); 6414 6415 intel_crtc->cursor_addr = addr; 6416 intel_crtc->cursor_bo = obj; 6417 intel_crtc->cursor_width = width; 6418 intel_crtc->cursor_height = height; 6419 6420 intel_crtc_update_cursor(crtc, true); 6421 6422 return 0; 6423 fail_unpin: 6424 i915_gem_object_unpin(obj); 6425 fail_locked: 6426 mutex_unlock(&dev->struct_mutex); 6427 fail: 6428 drm_gem_object_unreference_unlocked(&obj->base); 6429 return ret; 6430 } 6431 6432 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 6433 { 6434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6435 6436 intel_crtc->cursor_x = x; 6437 intel_crtc->cursor_y = y; 6438 6439 intel_crtc_update_cursor(crtc, true); 6440 6441 return 0; 6442 } 6443 6444 /** Sets the color ramps on behalf of RandR */ 6445 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, 6446 u16 blue, int regno) 6447 { 6448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6449 6450 intel_crtc->lut_r[regno] = red >> 8; 6451 intel_crtc->lut_g[regno] = green >> 8; 6452 intel_crtc->lut_b[regno] = blue >> 8; 6453 } 6454 6455 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, 6456 u16 *blue, int regno) 6457 { 6458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6459 6460 *red = intel_crtc->lut_r[regno] << 8; 6461 *green = intel_crtc->lut_g[regno] << 8; 6462 *blue = intel_crtc->lut_b[regno] << 8; 6463 } 6464 6465 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 6466 u16 *blue, uint32_t start, uint32_t size) 6467 { 6468 int end = (start + size > 256) ? 256 : start + size, i; 6469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6470 6471 for (i = start; i < end; i++) { 6472 intel_crtc->lut_r[i] = red[i] >> 8; 6473 intel_crtc->lut_g[i] = green[i] >> 8; 6474 intel_crtc->lut_b[i] = blue[i] >> 8; 6475 } 6476 6477 intel_crtc_load_lut(crtc); 6478 } 6479 6480 /** 6481 * Get a pipe with a simple mode set on it for doing load-based monitor 6482 * detection. 6483 * 6484 * It will be up to the load-detect code to adjust the pipe as appropriate for 6485 * its requirements. The pipe will be connected to no other encoders. 6486 * 6487 * Currently this code will only succeed if there is a pipe with no encoders 6488 * configured for it. In the future, it could choose to temporarily disable 6489 * some outputs to free up a pipe for its use. 6490 * 6491 * \return crtc, or NULL if no pipes are available. 6492 */ 6493 6494 /* VESA 640x480x72Hz mode to set on the pipe */ 6495 static struct drm_display_mode load_detect_mode = { 6496 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, 6497 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 6498 }; 6499 6500 static struct drm_framebuffer * 6501 intel_framebuffer_create(struct drm_device *dev, 6502 struct drm_mode_fb_cmd2 *mode_cmd, 6503 struct drm_i915_gem_object *obj) 6504 { 6505 struct intel_framebuffer *intel_fb; 6506 int ret; 6507 6508 intel_fb = kmalloc(sizeof(*intel_fb), M_DRM, M_WAITOK | M_ZERO); 6509 if (!intel_fb) { 6510 drm_gem_object_unreference_unlocked(&obj->base); 6511 return ERR_PTR(-ENOMEM); 6512 } 6513 6514 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); 6515 if (ret) { 6516 drm_gem_object_unreference_unlocked(&obj->base); 6517 kfree(intel_fb, M_DRM); 6518 return ERR_PTR(ret); 6519 } 6520 6521 return &intel_fb->base; 6522 } 6523 6524 static u32 6525 intel_framebuffer_pitch_for_width(int width, int bpp) 6526 { 6527 u32 pitch = DIV_ROUND_UP(width * bpp, 8); 6528 return ALIGN(pitch, 64); 6529 } 6530 6531 static u32 6532 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) 6533 { 6534 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); 6535 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE); 6536 } 6537 6538 static struct drm_framebuffer * 6539 intel_framebuffer_create_for_mode(struct drm_device *dev, 6540 struct drm_display_mode *mode, 6541 int depth, int bpp) 6542 { 6543 struct drm_i915_gem_object *obj; 6544 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 6545 6546 obj = i915_gem_alloc_object(dev, 6547 intel_framebuffer_size_for_mode(mode, bpp)); 6548 if (obj == NULL) 6549 return ERR_PTR(-ENOMEM); 6550 6551 mode_cmd.width = mode->hdisplay; 6552 mode_cmd.height = mode->vdisplay; 6553 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, 6554 bpp); 6555 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); 6556 6557 return intel_framebuffer_create(dev, &mode_cmd, obj); 6558 } 6559 6560 static struct drm_framebuffer * 6561 mode_fits_in_fbdev(struct drm_device *dev, 6562 struct drm_display_mode *mode) 6563 { 6564 struct drm_i915_private *dev_priv = dev->dev_private; 6565 struct drm_i915_gem_object *obj; 6566 struct drm_framebuffer *fb; 6567 6568 if (dev_priv->fbdev == NULL) 6569 return NULL; 6570 6571 obj = dev_priv->fbdev->ifb.obj; 6572 if (obj == NULL) 6573 return NULL; 6574 6575 fb = &dev_priv->fbdev->ifb.base; 6576 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, 6577 fb->bits_per_pixel)) 6578 return NULL; 6579 6580 if (obj->base.size < mode->vdisplay * fb->pitches[0]) 6581 return NULL; 6582 6583 return fb; 6584 } 6585 6586 bool intel_get_load_detect_pipe(struct drm_connector *connector, 6587 struct drm_display_mode *mode, 6588 struct intel_load_detect_pipe *old) 6589 { 6590 struct intel_crtc *intel_crtc; 6591 struct intel_encoder *intel_encoder = 6592 intel_attached_encoder(connector); 6593 struct drm_crtc *possible_crtc; 6594 struct drm_encoder *encoder = &intel_encoder->base; 6595 struct drm_crtc *crtc = NULL; 6596 struct drm_device *dev = encoder->dev; 6597 struct drm_framebuffer *fb; 6598 int i = -1; 6599 6600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 6601 connector->base.id, drm_get_connector_name(connector), 6602 encoder->base.id, drm_get_encoder_name(encoder)); 6603 6604 /* 6605 * Algorithm gets a little messy: 6606 * 6607 * - if the connector already has an assigned crtc, use it (but make 6608 * sure it's on first) 6609 * 6610 * - try to find the first unused crtc that can drive this connector, 6611 * and use that if we find one 6612 */ 6613 6614 /* See if we already have a CRTC for this connector */ 6615 if (encoder->crtc) { 6616 crtc = encoder->crtc; 6617 6618 mutex_lock(&crtc->mutex); 6619 6620 old->dpms_mode = connector->dpms; 6621 old->load_detect_temp = false; 6622 6623 /* Make sure the crtc and connector are running */ 6624 if (connector->dpms != DRM_MODE_DPMS_ON) 6625 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); 6626 6627 return true; 6628 } 6629 6630 /* Find an unused one (if possible) */ 6631 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) { 6632 i++; 6633 if (!(encoder->possible_crtcs & (1 << i))) 6634 continue; 6635 if (!possible_crtc->enabled) { 6636 crtc = possible_crtc; 6637 break; 6638 } 6639 } 6640 6641 /* 6642 * If we didn't find an unused CRTC, don't use any. 6643 */ 6644 if (!crtc) { 6645 DRM_DEBUG_KMS("no pipe available for load-detect\n"); 6646 return false; 6647 } 6648 6649 mutex_lock(&crtc->mutex); 6650 intel_encoder->new_crtc = to_intel_crtc(crtc); 6651 to_intel_connector(connector)->new_encoder = intel_encoder; 6652 6653 intel_crtc = to_intel_crtc(crtc); 6654 old->dpms_mode = connector->dpms; 6655 old->load_detect_temp = true; 6656 old->release_fb = NULL; 6657 6658 if (!mode) 6659 mode = &load_detect_mode; 6660 6661 /* We need a framebuffer large enough to accommodate all accesses 6662 * that the plane may generate whilst we perform load detection. 6663 * We can not rely on the fbcon either being present (we get called 6664 * during its initialisation to detect all boot displays, or it may 6665 * not even exist) or that it is large enough to satisfy the 6666 * requested mode. 6667 */ 6668 fb = mode_fits_in_fbdev(dev, mode); 6669 if (fb == NULL) { 6670 DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); 6671 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); 6672 old->release_fb = fb; 6673 } else 6674 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); 6675 if (IS_ERR(fb)) { 6676 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); 6677 mutex_unlock(&crtc->mutex); 6678 return false; 6679 } 6680 6681 if (intel_set_mode(crtc, mode, 0, 0, fb)) { 6682 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); 6683 if (old->release_fb) 6684 old->release_fb->funcs->destroy(old->release_fb); 6685 mutex_unlock(&crtc->mutex); 6686 return false; 6687 } 6688 6689 /* let the connector get through one full cycle before testing */ 6690 intel_wait_for_vblank(dev, intel_crtc->pipe); 6691 return true; 6692 } 6693 6694 void intel_release_load_detect_pipe(struct drm_connector *connector, 6695 struct intel_load_detect_pipe *old) 6696 { 6697 struct intel_encoder *intel_encoder = 6698 intel_attached_encoder(connector); 6699 struct drm_encoder *encoder = &intel_encoder->base; 6700 struct drm_crtc *crtc = encoder->crtc; 6701 6702 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 6703 connector->base.id, drm_get_connector_name(connector), 6704 encoder->base.id, drm_get_encoder_name(encoder)); 6705 6706 if (old->load_detect_temp) { 6707 to_intel_connector(connector)->new_encoder = NULL; 6708 intel_encoder->new_crtc = NULL; 6709 intel_set_mode(crtc, NULL, 0, 0, NULL); 6710 6711 if (old->release_fb) { 6712 drm_framebuffer_unregister_private(old->release_fb); 6713 drm_framebuffer_unreference(old->release_fb); 6714 } 6715 6716 mutex_unlock(&crtc->mutex); 6717 return; 6718 } 6719 6720 /* Switch crtc and encoder back off if necessary */ 6721 if (old->dpms_mode != DRM_MODE_DPMS_ON) 6722 connector->funcs->dpms(connector, old->dpms_mode); 6723 6724 mutex_unlock(&crtc->mutex); 6725 } 6726 6727 /* Returns the clock of the currently programmed mode of the given pipe. */ 6728 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc) 6729 { 6730 struct drm_i915_private *dev_priv = dev->dev_private; 6731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6732 int pipe = intel_crtc->pipe; 6733 u32 dpll = I915_READ(DPLL(pipe)); 6734 u32 fp; 6735 intel_clock_t clock; 6736 6737 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) 6738 fp = I915_READ(FP0(pipe)); 6739 else 6740 fp = I915_READ(FP1(pipe)); 6741 6742 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; 6743 if (IS_PINEVIEW(dev)) { 6744 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; 6745 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; 6746 } else { 6747 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; 6748 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; 6749 } 6750 6751 if (!IS_GEN2(dev)) { 6752 if (IS_PINEVIEW(dev)) 6753 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> 6754 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); 6755 else 6756 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> 6757 DPLL_FPA01_P1_POST_DIV_SHIFT); 6758 6759 switch (dpll & DPLL_MODE_MASK) { 6760 case DPLLB_MODE_DAC_SERIAL: 6761 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 6762 5 : 10; 6763 break; 6764 case DPLLB_MODE_LVDS: 6765 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 6766 7 : 14; 6767 break; 6768 default: 6769 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " 6770 "mode\n", (int)(dpll & DPLL_MODE_MASK)); 6771 return 0; 6772 } 6773 6774 /* XXX: Handle the 100Mhz refclk */ 6775 intel_clock(dev, 96000, &clock); 6776 } else { 6777 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN); 6778 6779 if (is_lvds) { 6780 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> 6781 DPLL_FPA01_P1_POST_DIV_SHIFT); 6782 clock.p2 = 14; 6783 6784 if ((dpll & PLL_REF_INPUT_MASK) == 6785 PLLB_REF_INPUT_SPREADSPECTRUMIN) { 6786 /* XXX: might not be 66MHz */ 6787 intel_clock(dev, 66000, &clock); 6788 } else 6789 intel_clock(dev, 48000, &clock); 6790 } else { 6791 if (dpll & PLL_P1_DIVIDE_BY_TWO) 6792 clock.p1 = 2; 6793 else { 6794 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> 6795 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; 6796 } 6797 if (dpll & PLL_P2_DIVIDE_BY_4) 6798 clock.p2 = 4; 6799 else 6800 clock.p2 = 2; 6801 6802 intel_clock(dev, 48000, &clock); 6803 } 6804 } 6805 6806 /* XXX: It would be nice to validate the clocks, but we can't reuse 6807 * i830PllIsValid() because it relies on the xf86_config connector 6808 * configuration being accurate, which it isn't necessarily. 6809 */ 6810 6811 return clock.dot; 6812 } 6813 6814 /** Returns the currently programmed mode of the given pipe. */ 6815 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, 6816 struct drm_crtc *crtc) 6817 { 6818 struct drm_i915_private *dev_priv = dev->dev_private; 6819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6820 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; 6821 struct drm_display_mode *mode; 6822 int htot = I915_READ(HTOTAL(cpu_transcoder)); 6823 int hsync = I915_READ(HSYNC(cpu_transcoder)); 6824 int vtot = I915_READ(VTOTAL(cpu_transcoder)); 6825 int vsync = I915_READ(VSYNC(cpu_transcoder)); 6826 6827 mode = kmalloc(sizeof(*mode), M_DRM, M_WAITOK | M_ZERO); 6828 if (!mode) 6829 return NULL; 6830 6831 mode->clock = intel_crtc_clock_get(dev, crtc); 6832 mode->hdisplay = (htot & 0xffff) + 1; 6833 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; 6834 mode->hsync_start = (hsync & 0xffff) + 1; 6835 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; 6836 mode->vdisplay = (vtot & 0xffff) + 1; 6837 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; 6838 mode->vsync_start = (vsync & 0xffff) + 1; 6839 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; 6840 6841 drm_mode_set_name(mode); 6842 6843 return mode; 6844 } 6845 6846 static void intel_increase_pllclock(struct drm_crtc *crtc) 6847 { 6848 struct drm_device *dev = crtc->dev; 6849 drm_i915_private_t *dev_priv = dev->dev_private; 6850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6851 int pipe = intel_crtc->pipe; 6852 int dpll_reg = DPLL(pipe); 6853 int dpll; 6854 6855 if (HAS_PCH_SPLIT(dev)) 6856 return; 6857 6858 if (!dev_priv->lvds_downclock_avail) 6859 return; 6860 6861 dpll = I915_READ(dpll_reg); 6862 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { 6863 DRM_DEBUG_DRIVER("upclocking LVDS\n"); 6864 6865 assert_panel_unlocked(dev_priv, pipe); 6866 6867 dpll &= ~DISPLAY_RATE_SELECT_FPA1; 6868 I915_WRITE(dpll_reg, dpll); 6869 intel_wait_for_vblank(dev, pipe); 6870 6871 dpll = I915_READ(dpll_reg); 6872 if (dpll & DISPLAY_RATE_SELECT_FPA1) 6873 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); 6874 } 6875 } 6876 6877 static void intel_decrease_pllclock(struct drm_crtc *crtc) 6878 { 6879 struct drm_device *dev = crtc->dev; 6880 drm_i915_private_t *dev_priv = dev->dev_private; 6881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6882 6883 if (HAS_PCH_SPLIT(dev)) 6884 return; 6885 6886 if (!dev_priv->lvds_downclock_avail) 6887 return; 6888 6889 /* 6890 * Since this is called by a timer, we should never get here in 6891 * the manual case. 6892 */ 6893 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { 6894 int pipe = intel_crtc->pipe; 6895 int dpll_reg = DPLL(pipe); 6896 int dpll; 6897 6898 DRM_DEBUG_DRIVER("downclocking LVDS\n"); 6899 6900 assert_panel_unlocked(dev_priv, pipe); 6901 6902 dpll = I915_READ(dpll_reg); 6903 dpll |= DISPLAY_RATE_SELECT_FPA1; 6904 I915_WRITE(dpll_reg, dpll); 6905 intel_wait_for_vblank(dev, pipe); 6906 dpll = I915_READ(dpll_reg); 6907 if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) 6908 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); 6909 } 6910 } 6911 6912 void intel_mark_busy(struct drm_device *dev) 6913 { 6914 i915_update_gfx_val(dev->dev_private); 6915 } 6916 6917 void intel_mark_idle(struct drm_device *dev) 6918 { 6919 struct drm_crtc *crtc; 6920 6921 if (!i915_powersave) 6922 return; 6923 6924 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6925 if (!crtc->fb) 6926 continue; 6927 6928 intel_decrease_pllclock(crtc); 6929 } 6930 } 6931 6932 void intel_mark_fb_busy(struct drm_i915_gem_object *obj) 6933 { 6934 struct drm_device *dev = obj->base.dev; 6935 struct drm_crtc *crtc; 6936 6937 if (!i915_powersave) 6938 return; 6939 6940 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 6941 if (!crtc->fb) 6942 continue; 6943 6944 if (to_intel_framebuffer(crtc->fb)->obj == obj) 6945 intel_increase_pllclock(crtc); 6946 } 6947 } 6948 6949 static void intel_crtc_destroy(struct drm_crtc *crtc) 6950 { 6951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6952 struct drm_device *dev = crtc->dev; 6953 struct intel_unpin_work *work; 6954 6955 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 6956 work = intel_crtc->unpin_work; 6957 intel_crtc->unpin_work = NULL; 6958 lockmgr(&dev->event_lock, LK_RELEASE); 6959 6960 if (work) { 6961 cancel_work_sync(&work->work); 6962 kfree(work, M_DRM); 6963 } 6964 6965 drm_crtc_cleanup(crtc); 6966 6967 drm_free(intel_crtc, M_DRM); 6968 } 6969 6970 static void intel_unpin_work_fn(struct work_struct *__work) 6971 { 6972 struct intel_unpin_work *work = 6973 container_of(__work, struct intel_unpin_work, work); 6974 struct drm_device *dev = work->crtc->dev; 6975 6976 mutex_lock(&dev->struct_mutex); 6977 intel_unpin_fb_obj(work->old_fb_obj); 6978 drm_gem_object_unreference(&work->pending_flip_obj->base); 6979 drm_gem_object_unreference(&work->old_fb_obj->base); 6980 6981 intel_update_fbc(dev); 6982 mutex_unlock(&dev->struct_mutex); 6983 6984 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); 6985 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); 6986 6987 drm_free(work, M_DRM); 6988 } 6989 6990 static void do_intel_finish_page_flip(struct drm_device *dev, 6991 struct drm_crtc *crtc) 6992 { 6993 drm_i915_private_t *dev_priv = dev->dev_private; 6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 6995 struct intel_unpin_work *work; 6996 struct drm_i915_gem_object *obj; 6997 6998 /* Ignore early vblank irqs */ 6999 if (intel_crtc == NULL) 7000 return; 7001 7002 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7003 work = intel_crtc->unpin_work; 7004 7005 /* Ensure we don't miss a work->pending update ... */ 7006 cpu_lfence(); 7007 7008 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { 7009 lockmgr(&dev->event_lock, LK_RELEASE); 7010 return; 7011 } 7012 7013 /* and that the unpin work is consistent wrt ->pending. */ 7014 cpu_lfence(); 7015 7016 intel_crtc->unpin_work = NULL; 7017 7018 if (work->event) 7019 drm_send_vblank_event(dev, intel_crtc->pipe, work->event); 7020 7021 drm_vblank_put(dev, intel_crtc->pipe); 7022 7023 lockmgr(&dev->event_lock, LK_RELEASE); 7024 7025 obj = work->old_fb_obj; 7026 7027 wake_up_all(&dev_priv->pending_flip_queue); 7028 7029 queue_work(dev_priv->wq, &work->work); 7030 } 7031 7032 void intel_finish_page_flip(struct drm_device *dev, int pipe) 7033 { 7034 drm_i915_private_t *dev_priv = dev->dev_private; 7035 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 7036 7037 do_intel_finish_page_flip(dev, crtc); 7038 } 7039 7040 void intel_finish_page_flip_plane(struct drm_device *dev, int plane) 7041 { 7042 drm_i915_private_t *dev_priv = dev->dev_private; 7043 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; 7044 7045 do_intel_finish_page_flip(dev, crtc); 7046 } 7047 7048 void intel_prepare_page_flip(struct drm_device *dev, int plane) 7049 { 7050 drm_i915_private_t *dev_priv = dev->dev_private; 7051 struct intel_crtc *intel_crtc = 7052 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); 7053 7054 /* NB: An MMIO update of the plane base pointer will also 7055 * generate a page-flip completion irq, i.e. every modeset 7056 * is also accompanied by a spurious intel_prepare_page_flip(). 7057 */ 7058 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7059 if (intel_crtc->unpin_work) 7060 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); 7061 lockmgr(&dev->event_lock, LK_RELEASE); 7062 } 7063 7064 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) 7065 { 7066 /* Ensure that the work item is consistent when activating it ... */ 7067 cpu_sfence(); 7068 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); 7069 /* and that it is marked active as soon as the irq could fire. */ 7070 cpu_sfence(); 7071 } 7072 7073 static int intel_gen2_queue_flip(struct drm_device *dev, 7074 struct drm_crtc *crtc, 7075 struct drm_framebuffer *fb, 7076 struct drm_i915_gem_object *obj) 7077 { 7078 struct drm_i915_private *dev_priv = dev->dev_private; 7079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7080 u32 flip_mask; 7081 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 7082 int ret; 7083 7084 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7085 if (ret) 7086 goto err; 7087 7088 ret = intel_ring_begin(ring, 6); 7089 if (ret) 7090 goto err_unpin; 7091 7092 /* Can't queue multiple flips, so wait for the previous 7093 * one to finish before executing the next. 7094 */ 7095 if (intel_crtc->plane) 7096 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 7097 else 7098 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 7099 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); 7100 intel_ring_emit(ring, MI_NOOP); 7101 intel_ring_emit(ring, MI_DISPLAY_FLIP | 7102 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 7103 intel_ring_emit(ring, fb->pitches[0]); 7104 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); 7105 intel_ring_emit(ring, 0); /* aux display base address, unused */ 7106 7107 intel_mark_page_flip_active(intel_crtc); 7108 intel_ring_advance(ring); 7109 return 0; 7110 7111 err_unpin: 7112 intel_unpin_fb_obj(obj); 7113 err: 7114 return ret; 7115 } 7116 7117 static int intel_gen3_queue_flip(struct drm_device *dev, 7118 struct drm_crtc *crtc, 7119 struct drm_framebuffer *fb, 7120 struct drm_i915_gem_object *obj) 7121 { 7122 struct drm_i915_private *dev_priv = dev->dev_private; 7123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7124 u32 flip_mask; 7125 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 7126 int ret; 7127 7128 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7129 if (ret) 7130 goto err; 7131 7132 ret = intel_ring_begin(ring, 6); 7133 if (ret) 7134 goto err_unpin; 7135 7136 if (intel_crtc->plane) 7137 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; 7138 else 7139 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; 7140 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); 7141 intel_ring_emit(ring, MI_NOOP); 7142 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | 7143 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 7144 intel_ring_emit(ring, fb->pitches[0]); 7145 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); 7146 intel_ring_emit(ring, MI_NOOP); 7147 7148 intel_mark_page_flip_active(intel_crtc); 7149 intel_ring_advance(ring); 7150 return 0; 7151 7152 err_unpin: 7153 intel_unpin_fb_obj(obj); 7154 err: 7155 return ret; 7156 } 7157 7158 static int intel_gen4_queue_flip(struct drm_device *dev, 7159 struct drm_crtc *crtc, 7160 struct drm_framebuffer *fb, 7161 struct drm_i915_gem_object *obj) 7162 { 7163 struct drm_i915_private *dev_priv = dev->dev_private; 7164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7165 uint32_t pf, pipesrc; 7166 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 7167 int ret; 7168 7169 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7170 if (ret) 7171 goto err; 7172 7173 ret = intel_ring_begin(ring, 4); 7174 if (ret) 7175 goto err_unpin; 7176 7177 /* i965+ uses the linear or tiled offsets from the 7178 * Display Registers (which do not change across a page-flip) 7179 * so we need only reprogram the base address. 7180 */ 7181 intel_ring_emit(ring, MI_DISPLAY_FLIP | 7182 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 7183 intel_ring_emit(ring, fb->pitches[0]); 7184 intel_ring_emit(ring, 7185 (obj->gtt_offset + intel_crtc->dspaddr_offset) | 7186 obj->tiling_mode); 7187 7188 /* XXX Enabling the panel-fitter across page-flip is so far 7189 * untested on non-native modes, so ignore it for now. 7190 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; 7191 */ 7192 pf = 0; 7193 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 7194 intel_ring_emit(ring, pf | pipesrc); 7195 7196 intel_mark_page_flip_active(intel_crtc); 7197 intel_ring_advance(ring); 7198 return 0; 7199 7200 err_unpin: 7201 intel_unpin_fb_obj(obj); 7202 err: 7203 return ret; 7204 } 7205 7206 static int intel_gen6_queue_flip(struct drm_device *dev, 7207 struct drm_crtc *crtc, 7208 struct drm_framebuffer *fb, 7209 struct drm_i915_gem_object *obj) 7210 { 7211 struct drm_i915_private *dev_priv = dev->dev_private; 7212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7213 struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; 7214 uint32_t pf, pipesrc; 7215 int ret; 7216 7217 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7218 if (ret) 7219 goto err; 7220 7221 ret = intel_ring_begin(ring, 4); 7222 if (ret) 7223 goto err_unpin; 7224 7225 intel_ring_emit(ring, MI_DISPLAY_FLIP | 7226 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); 7227 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); 7228 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); 7229 7230 /* Contrary to the suggestions in the documentation, 7231 * "Enable Panel Fitter" does not seem to be required when page 7232 * flipping with a non-native mode, and worse causes a normal 7233 * modeset to fail. 7234 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; 7235 */ 7236 pf = 0; 7237 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; 7238 intel_ring_emit(ring, pf | pipesrc); 7239 7240 intel_mark_page_flip_active(intel_crtc); 7241 intel_ring_advance(ring); 7242 return 0; 7243 7244 err_unpin: 7245 intel_unpin_fb_obj(obj); 7246 err: 7247 return ret; 7248 } 7249 7250 /* 7251 * On gen7 we currently use the blit ring because (in early silicon at least) 7252 * the render ring doesn't give us interrpts for page flip completion, which 7253 * means clients will hang after the first flip is queued. Fortunately the 7254 * blit ring generates interrupts properly, so use it instead. 7255 */ 7256 static int intel_gen7_queue_flip(struct drm_device *dev, 7257 struct drm_crtc *crtc, 7258 struct drm_framebuffer *fb, 7259 struct drm_i915_gem_object *obj) 7260 { 7261 struct drm_i915_private *dev_priv = dev->dev_private; 7262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7263 struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; 7264 uint32_t plane_bit = 0; 7265 int ret; 7266 7267 ret = intel_pin_and_fence_fb_obj(dev, obj, ring); 7268 if (ret) 7269 goto err; 7270 7271 switch(intel_crtc->plane) { 7272 case PLANE_A: 7273 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; 7274 break; 7275 case PLANE_B: 7276 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; 7277 break; 7278 case PLANE_C: 7279 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; 7280 break; 7281 default: 7282 WARN_ONCE(1, "unknown plane in flip command\n"); 7283 ret = -ENODEV; 7284 goto err_unpin; 7285 } 7286 7287 ret = intel_ring_begin(ring, 4); 7288 if (ret) 7289 goto err_unpin; 7290 7291 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); 7292 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); 7293 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); 7294 intel_ring_emit(ring, (MI_NOOP)); 7295 7296 intel_mark_page_flip_active(intel_crtc); 7297 intel_ring_advance(ring); 7298 return 0; 7299 7300 err_unpin: 7301 intel_unpin_fb_obj(obj); 7302 err: 7303 return ret; 7304 } 7305 7306 static int intel_default_queue_flip(struct drm_device *dev, 7307 struct drm_crtc *crtc, 7308 struct drm_framebuffer *fb, 7309 struct drm_i915_gem_object *obj) 7310 { 7311 return -ENODEV; 7312 } 7313 7314 static int intel_crtc_page_flip(struct drm_crtc *crtc, 7315 struct drm_framebuffer *fb, 7316 struct drm_pending_vblank_event *event) 7317 { 7318 struct drm_device *dev = crtc->dev; 7319 struct drm_i915_private *dev_priv = dev->dev_private; 7320 struct drm_framebuffer *old_fb = crtc->fb; 7321 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj; 7322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 7323 struct intel_unpin_work *work; 7324 int ret; 7325 7326 /* Can't change pixel format via MI display flips. */ 7327 if (fb->pixel_format != crtc->fb->pixel_format) 7328 return -EINVAL; 7329 7330 /* 7331 * TILEOFF/LINOFF registers can't be changed via MI display flips. 7332 * Note that pitch changes could also affect these register. 7333 */ 7334 if (INTEL_INFO(dev)->gen > 3 && 7335 (fb->offsets[0] != crtc->fb->offsets[0] || 7336 fb->pitches[0] != crtc->fb->pitches[0])) 7337 return -EINVAL; 7338 7339 work = kmalloc(sizeof *work, M_DRM, M_WAITOK | M_ZERO); 7340 if (work == NULL) 7341 return -ENOMEM; 7342 7343 work->event = event; 7344 work->crtc = crtc; 7345 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj; 7346 INIT_WORK(&work->work, intel_unpin_work_fn); 7347 7348 ret = drm_vblank_get(dev, intel_crtc->pipe); 7349 if (ret) 7350 goto free_work; 7351 7352 /* We borrow the event spin lock for protecting unpin_work */ 7353 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7354 if (intel_crtc->unpin_work) { 7355 lockmgr(&dev->event_lock, LK_RELEASE); 7356 drm_free(work, M_DRM); 7357 drm_vblank_put(dev, intel_crtc->pipe); 7358 7359 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 7360 return -EBUSY; 7361 } 7362 intel_crtc->unpin_work = work; 7363 lockmgr(&dev->event_lock, LK_RELEASE); 7364 7365 if (atomic_read(&intel_crtc->unpin_work_count) >= 2) 7366 flush_workqueue(dev_priv->wq); 7367 7368 ret = i915_mutex_lock_interruptible(dev); 7369 if (ret) 7370 goto cleanup; 7371 7372 /* Reference the objects for the scheduled work. */ 7373 drm_gem_object_reference(&work->old_fb_obj->base); 7374 drm_gem_object_reference(&obj->base); 7375 7376 crtc->fb = fb; 7377 7378 work->pending_flip_obj = obj; 7379 7380 work->enable_stall_check = true; 7381 7382 atomic_inc(&intel_crtc->unpin_work_count); 7383 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); 7384 7385 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj); 7386 if (ret) 7387 goto cleanup_pending; 7388 7389 intel_disable_fbc(dev); 7390 intel_mark_fb_busy(obj); 7391 mutex_unlock(&dev->struct_mutex); 7392 7393 return 0; 7394 7395 cleanup_pending: 7396 atomic_dec(&intel_crtc->unpin_work_count); 7397 crtc->fb = old_fb; 7398 drm_gem_object_unreference(&work->old_fb_obj->base); 7399 drm_gem_object_unreference(&obj->base); 7400 mutex_unlock(&dev->struct_mutex); 7401 7402 cleanup: 7403 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 7404 intel_crtc->unpin_work = NULL; 7405 lockmgr(&dev->event_lock, LK_RELEASE); 7406 7407 drm_vblank_put(dev, intel_crtc->pipe); 7408 free_work: 7409 drm_free(work, M_DRM); 7410 7411 return ret; 7412 } 7413 7414 static struct drm_crtc_helper_funcs intel_helper_funcs = { 7415 .mode_set_base_atomic = intel_pipe_set_base_atomic, 7416 .load_lut = intel_crtc_load_lut, 7417 .disable = intel_crtc_noop, 7418 }; 7419 7420 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder) 7421 { 7422 struct intel_encoder *other_encoder; 7423 struct drm_crtc *crtc = &encoder->new_crtc->base; 7424 7425 if (WARN_ON(!crtc)) 7426 return false; 7427 7428 list_for_each_entry(other_encoder, 7429 &crtc->dev->mode_config.encoder_list, 7430 base.head) { 7431 7432 if (&other_encoder->new_crtc->base != crtc || 7433 encoder == other_encoder) 7434 continue; 7435 else 7436 return true; 7437 } 7438 7439 return false; 7440 } 7441 7442 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder, 7443 struct drm_crtc *crtc) 7444 { 7445 struct drm_device *dev; 7446 struct drm_crtc *tmp; 7447 int crtc_mask = 1; 7448 7449 WARN(!crtc, "checking null crtc?\n"); 7450 /* profmakx: this is to prevent the kernel from panicing */ 7451 if(!crtc) { 7452 return false; 7453 } 7454 7455 dev = crtc->dev; 7456 7457 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) { 7458 if (tmp == crtc) 7459 break; 7460 crtc_mask <<= 1; 7461 } 7462 7463 if (encoder->possible_crtcs & crtc_mask) 7464 return true; 7465 return false; 7466 } 7467 7468 /** 7469 * intel_modeset_update_staged_output_state 7470 * 7471 * Updates the staged output configuration state, e.g. after we've read out the 7472 * current hw state. 7473 */ 7474 static void intel_modeset_update_staged_output_state(struct drm_device *dev) 7475 { 7476 struct intel_encoder *encoder; 7477 struct intel_connector *connector; 7478 7479 list_for_each_entry(connector, &dev->mode_config.connector_list, 7480 base.head) { 7481 connector->new_encoder = 7482 to_intel_encoder(connector->base.encoder); 7483 } 7484 7485 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7486 base.head) { 7487 encoder->new_crtc = 7488 to_intel_crtc(encoder->base.crtc); 7489 } 7490 } 7491 7492 /** 7493 * intel_modeset_commit_output_state 7494 * 7495 * This function copies the stage display pipe configuration to the real one. 7496 */ 7497 static void intel_modeset_commit_output_state(struct drm_device *dev) 7498 { 7499 struct intel_encoder *encoder; 7500 struct intel_connector *connector; 7501 7502 list_for_each_entry(connector, &dev->mode_config.connector_list, 7503 base.head) { 7504 connector->base.encoder = &connector->new_encoder->base; 7505 } 7506 7507 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7508 base.head) { 7509 encoder->base.crtc = &encoder->new_crtc->base; 7510 } 7511 } 7512 7513 static struct drm_display_mode * 7514 intel_modeset_adjusted_mode(struct drm_crtc *crtc, 7515 struct drm_display_mode *mode) 7516 { 7517 struct drm_device *dev = crtc->dev; 7518 struct drm_display_mode *adjusted_mode; 7519 struct drm_encoder_helper_funcs *encoder_funcs; 7520 struct intel_encoder *encoder; 7521 7522 adjusted_mode = drm_mode_duplicate(dev, mode); 7523 if (!adjusted_mode) 7524 return ERR_PTR(-ENOMEM); 7525 7526 /* Pass our mode to the connectors and the CRTC to give them a chance to 7527 * adjust it according to limitations or connector properties, and also 7528 * a chance to reject the mode entirely. 7529 */ 7530 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7531 base.head) { 7532 7533 if (&encoder->new_crtc->base != crtc) 7534 continue; 7535 encoder_funcs = encoder->base.helper_private; 7536 if (!(encoder_funcs->mode_fixup(&encoder->base, mode, 7537 adjusted_mode))) { 7538 DRM_DEBUG_KMS("Encoder fixup failed\n"); 7539 goto fail; 7540 } 7541 } 7542 7543 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) { 7544 DRM_DEBUG_KMS("CRTC fixup failed\n"); 7545 goto fail; 7546 } 7547 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); 7548 7549 return adjusted_mode; 7550 fail: 7551 drm_mode_destroy(dev, adjusted_mode); 7552 return ERR_PTR(-EINVAL); 7553 } 7554 7555 /* Computes which crtcs are affected and sets the relevant bits in the mask. For 7556 * simplicity we use the crtc's pipe number (because it's easier to obtain). */ 7557 static void 7558 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, 7559 unsigned *prepare_pipes, unsigned *disable_pipes) 7560 { 7561 struct intel_crtc *intel_crtc; 7562 struct drm_device *dev = crtc->dev; 7563 struct intel_encoder *encoder; 7564 struct intel_connector *connector; 7565 struct drm_crtc *tmp_crtc; 7566 7567 *disable_pipes = *modeset_pipes = *prepare_pipes = 0; 7568 7569 /* Check which crtcs have changed outputs connected to them, these need 7570 * to be part of the prepare_pipes mask. We don't (yet) support global 7571 * modeset across multiple crtcs, so modeset_pipes will only have one 7572 * bit set at most. */ 7573 list_for_each_entry(connector, &dev->mode_config.connector_list, 7574 base.head) { 7575 if (connector->base.encoder == &connector->new_encoder->base) 7576 continue; 7577 7578 if (connector->base.encoder) { 7579 tmp_crtc = connector->base.encoder->crtc; 7580 7581 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; 7582 } 7583 7584 if (connector->new_encoder) 7585 *prepare_pipes |= 7586 1 << connector->new_encoder->new_crtc->pipe; 7587 } 7588 7589 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7590 base.head) { 7591 if (encoder->base.crtc == &encoder->new_crtc->base) 7592 continue; 7593 7594 if (encoder->base.crtc) { 7595 tmp_crtc = encoder->base.crtc; 7596 7597 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; 7598 } 7599 7600 if (encoder->new_crtc) 7601 *prepare_pipes |= 1 << encoder->new_crtc->pipe; 7602 } 7603 7604 /* Check for any pipes that will be fully disabled ... */ 7605 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 7606 base.head) { 7607 bool used = false; 7608 7609 /* Don't try to disable disabled crtcs. */ 7610 if (!intel_crtc->base.enabled) 7611 continue; 7612 7613 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7614 base.head) { 7615 if (encoder->new_crtc == intel_crtc) 7616 used = true; 7617 } 7618 7619 if (!used) 7620 *disable_pipes |= 1 << intel_crtc->pipe; 7621 } 7622 7623 7624 /* set_mode is also used to update properties on life display pipes. */ 7625 intel_crtc = to_intel_crtc(crtc); 7626 if (crtc->enabled) 7627 *prepare_pipes |= 1 << intel_crtc->pipe; 7628 7629 /* 7630 * For simplicity do a full modeset on any pipe where the output routing 7631 * changed. We could be more clever, but that would require us to be 7632 * more careful with calling the relevant encoder->mode_set functions. 7633 */ 7634 if (*prepare_pipes) 7635 *modeset_pipes = *prepare_pipes; 7636 7637 /* ... and mask these out. */ 7638 *modeset_pipes &= ~(*disable_pipes); 7639 *prepare_pipes &= ~(*disable_pipes); 7640 7641 /* 7642 * HACK: We don't (yet) fully support global modesets. intel_set_config 7643 * obies this rule, but the modeset restore mode of 7644 * intel_modeset_setup_hw_state does not. 7645 */ 7646 *modeset_pipes &= 1 << intel_crtc->pipe; 7647 *prepare_pipes &= 1 << intel_crtc->pipe; 7648 } 7649 7650 static bool intel_crtc_in_use(struct drm_crtc *crtc) 7651 { 7652 struct drm_encoder *encoder; 7653 struct drm_device *dev = crtc->dev; 7654 7655 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) 7656 if (encoder->crtc == crtc) 7657 return true; 7658 7659 return false; 7660 } 7661 7662 static void 7663 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) 7664 { 7665 struct intel_encoder *intel_encoder; 7666 struct intel_crtc *intel_crtc; 7667 struct drm_connector *connector; 7668 7669 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list, 7670 base.head) { 7671 if (!intel_encoder->base.crtc) 7672 continue; 7673 7674 intel_crtc = to_intel_crtc(intel_encoder->base.crtc); 7675 7676 if (prepare_pipes & (1 << intel_crtc->pipe)) 7677 intel_encoder->connectors_active = false; 7678 } 7679 7680 intel_modeset_commit_output_state(dev); 7681 7682 /* Update computed state. */ 7683 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, 7684 base.head) { 7685 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base); 7686 } 7687 7688 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 7689 if (!connector->encoder || !connector->encoder->crtc) 7690 continue; 7691 7692 intel_crtc = to_intel_crtc(connector->encoder->crtc); 7693 7694 if (prepare_pipes & (1 << intel_crtc->pipe)) { 7695 struct drm_property *dpms_property = 7696 dev->mode_config.dpms_property; 7697 7698 connector->dpms = DRM_MODE_DPMS_ON; 7699 drm_object_property_set_value(&connector->base, 7700 dpms_property, 7701 DRM_MODE_DPMS_ON); 7702 7703 intel_encoder = to_intel_encoder(connector->encoder); 7704 intel_encoder->connectors_active = true; 7705 } 7706 } 7707 7708 } 7709 7710 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ 7711 list_for_each_entry((intel_crtc), \ 7712 &(dev)->mode_config.crtc_list, \ 7713 base.head) \ 7714 if (mask & (1 <<(intel_crtc)->pipe)) \ 7715 7716 void 7717 intel_modeset_check_state(struct drm_device *dev) 7718 { 7719 struct intel_crtc *crtc; 7720 struct intel_encoder *encoder; 7721 struct intel_connector *connector; 7722 7723 list_for_each_entry(connector, &dev->mode_config.connector_list, 7724 base.head) { 7725 /* This also checks the encoder/connector hw state with the 7726 * ->get_hw_state callbacks. */ 7727 intel_connector_check_state(connector); 7728 7729 WARN(&connector->new_encoder->base != connector->base.encoder, 7730 "connector's staged encoder doesn't match current encoder\n"); 7731 } 7732 7733 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7734 base.head) { 7735 bool enabled = false; 7736 bool active = false; 7737 enum i915_pipe pipe, tracked_pipe; 7738 7739 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", 7740 encoder->base.base.id, 7741 drm_get_encoder_name(&encoder->base)); 7742 7743 WARN(&encoder->new_crtc->base != encoder->base.crtc, 7744 "encoder's stage crtc doesn't match current crtc\n"); 7745 WARN(encoder->connectors_active && !encoder->base.crtc, 7746 "encoder's active_connectors set, but no crtc\n"); 7747 7748 list_for_each_entry(connector, &dev->mode_config.connector_list, 7749 base.head) { 7750 if (connector->base.encoder != &encoder->base) 7751 continue; 7752 enabled = true; 7753 if (connector->base.dpms != DRM_MODE_DPMS_OFF) 7754 active = true; 7755 } 7756 WARN(!!encoder->base.crtc != enabled, 7757 "encoder's enabled state mismatch " 7758 "(expected %i, found %i)\n", 7759 !!encoder->base.crtc, enabled); 7760 WARN(active && !encoder->base.crtc, 7761 "active encoder with no crtc\n"); 7762 7763 WARN(encoder->connectors_active != active, 7764 "encoder's computed active state doesn't match tracked active state " 7765 "(expected %i, found %i)\n", active, encoder->connectors_active); 7766 7767 active = encoder->get_hw_state(encoder, &pipe); 7768 WARN(active != encoder->connectors_active, 7769 "encoder's hw state doesn't match sw tracking " 7770 "(expected %i, found %i)\n", 7771 encoder->connectors_active, active); 7772 7773 if (!encoder->base.crtc) 7774 continue; 7775 7776 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; 7777 WARN(active && pipe != tracked_pipe, 7778 "active encoder's pipe doesn't match" 7779 "(expected %i, found %i)\n", 7780 tracked_pipe, pipe); 7781 7782 } 7783 7784 list_for_each_entry(crtc, &dev->mode_config.crtc_list, 7785 base.head) { 7786 bool enabled = false; 7787 bool active = false; 7788 7789 DRM_DEBUG_KMS("[CRTC:%d]\n", 7790 crtc->base.base.id); 7791 7792 WARN(crtc->active && !crtc->base.enabled, 7793 "active crtc, but not enabled in sw tracking\n"); 7794 7795 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 7796 base.head) { 7797 if (encoder->base.crtc != &crtc->base) 7798 continue; 7799 enabled = true; 7800 if (encoder->connectors_active) 7801 active = true; 7802 } 7803 WARN(active != crtc->active, 7804 "crtc's computed active state doesn't match tracked active state " 7805 "(expected %i, found %i)\n", active, crtc->active); 7806 WARN(enabled != crtc->base.enabled, 7807 "crtc's computed enabled state doesn't match tracked enabled state " 7808 "(expected %i, found %i)\n", enabled, crtc->base.enabled); 7809 7810 assert_pipe(dev->dev_private, crtc->pipe, crtc->active); 7811 } 7812 } 7813 7814 static int __intel_set_mode(struct drm_crtc *crtc, 7815 struct drm_display_mode *mode, 7816 int x, int y, struct drm_framebuffer *fb) 7817 { 7818 struct drm_device *dev = crtc->dev; 7819 drm_i915_private_t *dev_priv = dev->dev_private; 7820 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode; 7821 struct intel_crtc *intel_crtc; 7822 unsigned disable_pipes, prepare_pipes, modeset_pipes; 7823 int ret = 0; 7824 7825 saved_mode = kmalloc(2 * sizeof(*saved_mode), M_DRM, M_WAITOK); 7826 if (!saved_mode) 7827 return -ENOMEM; 7828 saved_hwmode = saved_mode + 1; 7829 7830 intel_modeset_affected_pipes(crtc, &modeset_pipes, 7831 &prepare_pipes, &disable_pipes); 7832 7833 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", 7834 modeset_pipes, prepare_pipes, disable_pipes); 7835 7836 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) 7837 intel_crtc_disable(&intel_crtc->base); 7838 7839 *saved_hwmode = crtc->hwmode; 7840 *saved_mode = crtc->mode; 7841 7842 /* Hack: Because we don't (yet) support global modeset on multiple 7843 * crtcs, we don't keep track of the new mode for more than one crtc. 7844 * Hence simply check whether any bit is set in modeset_pipes in all the 7845 * pieces of code that are not yet converted to deal with mutliple crtcs 7846 * changing their mode at the same time. */ 7847 adjusted_mode = NULL; 7848 if (modeset_pipes) { 7849 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode); 7850 if (IS_ERR(adjusted_mode)) { 7851 ret = PTR_ERR(adjusted_mode); 7852 goto out; 7853 } 7854 } 7855 7856 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { 7857 if (intel_crtc->base.enabled) 7858 dev_priv->display.crtc_disable(&intel_crtc->base); 7859 } 7860 7861 /* crtc->mode is already used by the ->mode_set callbacks, hence we need 7862 * to set it here already despite that we pass it down the callchain. 7863 */ 7864 if (modeset_pipes) 7865 crtc->mode = *mode; 7866 7867 /* Only after disabling all output pipelines that will be changed can we 7868 * update the the output configuration. */ 7869 intel_modeset_update_state(dev, prepare_pipes); 7870 7871 if (dev_priv->display.modeset_global_resources) 7872 dev_priv->display.modeset_global_resources(dev); 7873 7874 /* Set up the DPLL and any encoders state that needs to adjust or depend 7875 * on the DPLL. 7876 */ 7877 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { 7878 ret = intel_crtc_mode_set(&intel_crtc->base, 7879 mode, adjusted_mode, 7880 x, y, fb); 7881 if (ret) 7882 goto done; 7883 } 7884 7885 /* Now enable the clocks, plane, pipe, and connectors that we set up. */ 7886 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) 7887 dev_priv->display.crtc_enable(&intel_crtc->base); 7888 7889 if (modeset_pipes) { 7890 /* Store real post-adjustment hardware mode. */ 7891 crtc->hwmode = *adjusted_mode; 7892 7893 /* Calculate and store various constants which 7894 * are later needed by vblank and swap-completion 7895 * timestamping. They are derived from true hwmode. 7896 */ 7897 drm_calc_timestamping_constants(crtc); 7898 } 7899 7900 /* FIXME: add subpixel order */ 7901 done: 7902 drm_mode_destroy(dev, adjusted_mode); 7903 if (ret && crtc->enabled) { 7904 crtc->hwmode = *saved_hwmode; 7905 crtc->mode = *saved_mode; 7906 } 7907 7908 out: 7909 kfree(saved_mode, M_DRM); 7910 return ret; 7911 } 7912 7913 int intel_set_mode(struct drm_crtc *crtc, 7914 struct drm_display_mode *mode, 7915 int x, int y, struct drm_framebuffer *fb) 7916 { 7917 int ret; 7918 7919 ret = __intel_set_mode(crtc, mode, x, y, fb); 7920 7921 if (ret == 0) 7922 intel_modeset_check_state(crtc->dev); 7923 7924 return ret; 7925 } 7926 7927 void intel_crtc_restore_mode(struct drm_crtc *crtc) 7928 { 7929 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb); 7930 } 7931 7932 #undef for_each_intel_crtc_masked 7933 7934 static void intel_set_config_free(struct intel_set_config *config) 7935 { 7936 if (!config) 7937 return; 7938 7939 drm_free(config->save_connector_encoders, M_DRM); 7940 drm_free(config->save_encoder_crtcs, M_DRM); 7941 drm_free(config, M_DRM); 7942 } 7943 7944 static int intel_set_config_save_state(struct drm_device *dev, 7945 struct intel_set_config *config) 7946 { 7947 struct drm_encoder *encoder; 7948 struct drm_connector *connector; 7949 int count; 7950 7951 config->save_encoder_crtcs = 7952 kmalloc(dev->mode_config.num_encoder * 7953 sizeof(struct drm_crtc *), M_DRM, M_WAITOK | M_ZERO ); 7954 if (!config->save_encoder_crtcs) 7955 return -ENOMEM; 7956 7957 config->save_connector_encoders = 7958 kmalloc(dev->mode_config.num_connector * 7959 sizeof(struct drm_encoder *), M_DRM, M_WAITOK | M_ZERO ); 7960 if (!config->save_connector_encoders) 7961 return -ENOMEM; 7962 7963 /* Copy data. Note that driver private data is not affected. 7964 * Should anything bad happen only the expected state is 7965 * restored, not the drivers personal bookkeeping. 7966 */ 7967 count = 0; 7968 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 7969 config->save_encoder_crtcs[count++] = encoder->crtc; 7970 } 7971 7972 count = 0; 7973 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 7974 config->save_connector_encoders[count++] = connector->encoder; 7975 } 7976 7977 return 0; 7978 } 7979 7980 static void intel_set_config_restore_state(struct drm_device *dev, 7981 struct intel_set_config *config) 7982 { 7983 struct intel_encoder *encoder; 7984 struct intel_connector *connector; 7985 int count; 7986 7987 count = 0; 7988 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 7989 encoder->new_crtc = 7990 to_intel_crtc(config->save_encoder_crtcs[count++]); 7991 } 7992 7993 count = 0; 7994 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { 7995 connector->new_encoder = 7996 to_intel_encoder(config->save_connector_encoders[count++]); 7997 } 7998 } 7999 8000 static bool 8001 is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors, 8002 int num_connectors) 8003 { 8004 int i; 8005 8006 for (i = 0; i < num_connectors; i++) 8007 if (connectors[i].encoder && 8008 connectors[i].encoder->crtc == crtc && 8009 connectors[i].dpms != DRM_MODE_DPMS_ON) 8010 return true; 8011 8012 return false; 8013 } 8014 8015 static void 8016 intel_set_config_compute_mode_changes(struct drm_mode_set *set, 8017 struct intel_set_config *config) 8018 { 8019 8020 /* We should be able to check here if the fb has the same properties 8021 * and then just flip_or_move it */ 8022 if (set->connectors != NULL && 8023 is_crtc_connector_off(set->crtc, *set->connectors, 8024 set->num_connectors)) { 8025 config->mode_changed = true; 8026 } else if (set->crtc->fb != set->fb) { 8027 /* If we have no fb then treat it as a full mode set */ 8028 if (set->crtc->fb == NULL) { 8029 DRM_DEBUG_KMS("crtc has no fb, full mode set\n"); 8030 config->mode_changed = true; 8031 } else if (set->fb == NULL) { 8032 config->mode_changed = true; 8033 } else if (set->fb->depth != set->crtc->fb->depth) { 8034 config->mode_changed = true; 8035 } else if (set->fb->bits_per_pixel != 8036 set->crtc->fb->bits_per_pixel) { 8037 config->mode_changed = true; 8038 } else { 8039 config->fb_changed = true; 8040 } 8041 } 8042 8043 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) 8044 config->fb_changed = true; 8045 8046 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { 8047 DRM_DEBUG_KMS("modes are different, full mode set\n"); 8048 drm_mode_debug_printmodeline(&set->crtc->mode); 8049 drm_mode_debug_printmodeline(set->mode); 8050 config->mode_changed = true; 8051 } 8052 } 8053 8054 static int 8055 intel_modeset_stage_output_state(struct drm_device *dev, 8056 struct drm_mode_set *set, 8057 struct intel_set_config *config) 8058 { 8059 struct drm_crtc *new_crtc; 8060 struct intel_connector *connector; 8061 struct intel_encoder *encoder; 8062 int count, ro; 8063 8064 /* The upper layers ensure that we either disable a crtc or have a list 8065 * of connectors. For paranoia, double-check this. */ 8066 WARN_ON(!set->fb && (set->num_connectors != 0)); 8067 WARN_ON(set->fb && (set->num_connectors == 0)); 8068 8069 count = 0; 8070 list_for_each_entry(connector, &dev->mode_config.connector_list, 8071 base.head) { 8072 /* Otherwise traverse passed in connector list and get encoders 8073 * for them. */ 8074 for (ro = 0; ro < set->num_connectors; ro++) { 8075 if (set->connectors[ro] == &connector->base) { 8076 connector->new_encoder = connector->encoder; 8077 break; 8078 } 8079 } 8080 8081 /* If we disable the crtc, disable all its connectors. Also, if 8082 * the connector is on the changing crtc but not on the new 8083 * connector list, disable it. */ 8084 if ((!set->fb || ro == set->num_connectors) && 8085 connector->base.encoder && 8086 connector->base.encoder->crtc == set->crtc) { 8087 connector->new_encoder = NULL; 8088 8089 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", 8090 connector->base.base.id, 8091 drm_get_connector_name(&connector->base)); 8092 } 8093 8094 8095 if (&connector->new_encoder->base != connector->base.encoder) { 8096 DRM_DEBUG_KMS("encoder changed, full mode switch\n"); 8097 config->mode_changed = true; 8098 } 8099 } 8100 /* connector->new_encoder is now updated for all connectors. */ 8101 8102 /* Update crtc of enabled connectors. */ 8103 count = 0; 8104 list_for_each_entry(connector, &dev->mode_config.connector_list, 8105 base.head) { 8106 if (!connector->new_encoder) 8107 continue; 8108 8109 new_crtc = connector->new_encoder->base.crtc; 8110 8111 for (ro = 0; ro < set->num_connectors; ro++) { 8112 if (set->connectors[ro] == &connector->base) 8113 new_crtc = set->crtc; 8114 } 8115 8116 /* Make sure the new CRTC will work with the encoder */ 8117 if (!intel_encoder_crtc_ok(&connector->new_encoder->base, 8118 new_crtc)) { 8119 return -EINVAL; 8120 } 8121 connector->encoder->new_crtc = to_intel_crtc(new_crtc); 8122 8123 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", 8124 connector->base.base.id, 8125 drm_get_connector_name(&connector->base), 8126 new_crtc->base.id); 8127 } 8128 8129 /* Check for any encoders that needs to be disabled. */ 8130 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 8131 base.head) { 8132 list_for_each_entry(connector, 8133 &dev->mode_config.connector_list, 8134 base.head) { 8135 if (connector->new_encoder == encoder) { 8136 WARN_ON(!connector->new_encoder->new_crtc); 8137 8138 goto next_encoder; 8139 } 8140 } 8141 encoder->new_crtc = NULL; 8142 next_encoder: 8143 /* Only now check for crtc changes so we don't miss encoders 8144 * that will be disabled. */ 8145 if (&encoder->new_crtc->base != encoder->base.crtc) { 8146 DRM_DEBUG_KMS("crtc changed, full mode switch\n"); 8147 config->mode_changed = true; 8148 } 8149 } 8150 /* Now we've also updated encoder->new_crtc for all encoders. */ 8151 8152 return 0; 8153 } 8154 8155 static int intel_crtc_set_config(struct drm_mode_set *set) 8156 { 8157 struct drm_device *dev; 8158 struct drm_mode_set save_set; 8159 struct intel_set_config *config; 8160 int ret; 8161 8162 BUG_ON(!set); 8163 BUG_ON(!set->crtc); 8164 BUG_ON(!set->crtc->helper_private); 8165 8166 /* Enforce sane interface api - has been abused by the fb helper. */ 8167 BUG_ON(!set->mode && set->fb); 8168 BUG_ON(set->fb && set->num_connectors == 0); 8169 8170 if (set->fb) { 8171 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", 8172 set->crtc->base.id, set->fb->base.id, 8173 (int)set->num_connectors, set->x, set->y); 8174 } else { 8175 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); 8176 } 8177 8178 dev = set->crtc->dev; 8179 8180 ret = -ENOMEM; 8181 config = kmalloc(sizeof(*config), M_DRM, M_WAITOK | M_ZERO); 8182 if (!config) 8183 goto out_config; 8184 8185 ret = intel_set_config_save_state(dev, config); 8186 if (ret) 8187 goto out_config; 8188 8189 save_set.crtc = set->crtc; 8190 save_set.mode = &set->crtc->mode; 8191 save_set.x = set->crtc->x; 8192 save_set.y = set->crtc->y; 8193 save_set.fb = set->crtc->fb; 8194 8195 /* Compute whether we need a full modeset, only an fb base update or no 8196 * change at all. In the future we might also check whether only the 8197 * mode changed, e.g. for LVDS where we only change the panel fitter in 8198 * such cases. */ 8199 intel_set_config_compute_mode_changes(set, config); 8200 8201 ret = intel_modeset_stage_output_state(dev, set, config); 8202 if (ret) 8203 goto fail; 8204 8205 if (config->mode_changed) { 8206 if (set->mode) { 8207 DRM_DEBUG_KMS("attempting to set mode from" 8208 " userspace\n"); 8209 drm_mode_debug_printmodeline(set->mode); 8210 } 8211 8212 ret = intel_set_mode(set->crtc, set->mode, 8213 set->x, set->y, set->fb); 8214 if (ret) { 8215 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n", 8216 set->crtc->base.id, ret); 8217 goto fail; 8218 } 8219 } else if (config->fb_changed) { 8220 ret = intel_pipe_set_base(set->crtc, 8221 set->x, set->y, set->fb); 8222 } 8223 8224 intel_set_config_free(config); 8225 8226 return 0; 8227 8228 fail: 8229 intel_set_config_restore_state(dev, config); 8230 8231 /* Try to restore the config */ 8232 if (config->mode_changed && 8233 intel_set_mode(save_set.crtc, save_set.mode, 8234 save_set.x, save_set.y, save_set.fb)) 8235 DRM_ERROR("failed to restore config after modeset failure\n"); 8236 8237 out_config: 8238 intel_set_config_free(config); 8239 return ret; 8240 } 8241 8242 static const struct drm_crtc_funcs intel_crtc_funcs = { 8243 .cursor_set = intel_crtc_cursor_set, 8244 .cursor_move = intel_crtc_cursor_move, 8245 .gamma_set = intel_crtc_gamma_set, 8246 .set_config = intel_crtc_set_config, 8247 .destroy = intel_crtc_destroy, 8248 .page_flip = intel_crtc_page_flip, 8249 }; 8250 8251 static void intel_cpu_pll_init(struct drm_device *dev) 8252 { 8253 if (HAS_DDI(dev)) 8254 intel_ddi_pll_init(dev); 8255 } 8256 8257 static void intel_pch_pll_init(struct drm_device *dev) 8258 { 8259 drm_i915_private_t *dev_priv = dev->dev_private; 8260 int i; 8261 8262 if (dev_priv->num_pch_pll == 0) { 8263 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n"); 8264 return; 8265 } 8266 8267 for (i = 0; i < dev_priv->num_pch_pll; i++) { 8268 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i); 8269 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i); 8270 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i); 8271 } 8272 } 8273 8274 static void intel_crtc_init(struct drm_device *dev, int pipe) 8275 { 8276 drm_i915_private_t *dev_priv = dev->dev_private; 8277 struct intel_crtc *intel_crtc; 8278 int i; 8279 8280 intel_crtc = kmalloc(sizeof(struct intel_crtc) + 8281 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), 8282 M_DRM, M_WAITOK | M_ZERO); 8283 if (intel_crtc == NULL) 8284 return; 8285 8286 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs); 8287 8288 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); 8289 for (i = 0; i < 256; i++) { 8290 intel_crtc->lut_r[i] = i; 8291 intel_crtc->lut_g[i] = i; 8292 intel_crtc->lut_b[i] = i; 8293 } 8294 8295 /* Swap pipes & planes for FBC on pre-965 */ 8296 intel_crtc->pipe = pipe; 8297 intel_crtc->plane = pipe; 8298 intel_crtc->cpu_transcoder = pipe; 8299 if (IS_MOBILE(dev) && IS_GEN3(dev)) { 8300 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); 8301 intel_crtc->plane = !pipe; 8302 } 8303 8304 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || 8305 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); 8306 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; 8307 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; 8308 8309 intel_crtc->bpp = 24; /* default for pre-Ironlake */ 8310 8311 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); 8312 } 8313 8314 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, 8315 struct drm_file *file) 8316 { 8317 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; 8318 struct drm_mode_object *drmmode_obj; 8319 struct intel_crtc *crtc; 8320 8321 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 8322 return -ENODEV; 8323 8324 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id, 8325 DRM_MODE_OBJECT_CRTC); 8326 8327 if (!drmmode_obj) { 8328 DRM_ERROR("no such CRTC id\n"); 8329 return -EINVAL; 8330 } 8331 8332 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj)); 8333 pipe_from_crtc_id->pipe = crtc->pipe; 8334 8335 return 0; 8336 } 8337 8338 static int intel_encoder_clones(struct intel_encoder *encoder) 8339 { 8340 struct drm_device *dev = encoder->base.dev; 8341 struct intel_encoder *source_encoder; 8342 int index_mask = 0; 8343 int entry = 0; 8344 8345 list_for_each_entry(source_encoder, 8346 &dev->mode_config.encoder_list, base.head) { 8347 8348 if (encoder == source_encoder) 8349 index_mask |= (1 << entry); 8350 8351 /* Intel hw has only one MUX where enocoders could be cloned. */ 8352 if (encoder->cloneable && source_encoder->cloneable) 8353 index_mask |= (1 << entry); 8354 8355 entry++; 8356 } 8357 8358 return index_mask; 8359 } 8360 8361 static bool has_edp_a(struct drm_device *dev) 8362 { 8363 struct drm_i915_private *dev_priv = dev->dev_private; 8364 8365 if (!IS_MOBILE(dev)) 8366 return false; 8367 8368 if ((I915_READ(DP_A) & DP_DETECTED) == 0) 8369 return false; 8370 8371 if (IS_GEN5(dev) && 8372 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE)) 8373 return false; 8374 8375 return true; 8376 } 8377 8378 static void intel_setup_outputs(struct drm_device *dev) 8379 { 8380 struct drm_i915_private *dev_priv = dev->dev_private; 8381 struct intel_encoder *encoder; 8382 bool dpd_is_edp = false; 8383 bool has_lvds; 8384 8385 has_lvds = intel_lvds_init(dev); 8386 if (!has_lvds && !HAS_PCH_SPLIT(dev)) { 8387 /* disable the panel fitter on everything but LVDS */ 8388 I915_WRITE(PFIT_CONTROL, 0); 8389 } 8390 8391 if (!IS_ULT(dev)) 8392 intel_crt_init(dev); 8393 8394 if (HAS_DDI(dev)) { 8395 int found; 8396 8397 /* Haswell uses DDI functions to detect digital outputs */ 8398 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; 8399 /* DDI A only supports eDP */ 8400 if (found) 8401 intel_ddi_init(dev, PORT_A); 8402 8403 /* DDI B, C and D detection is indicated by the SFUSE_STRAP 8404 * register */ 8405 found = I915_READ(SFUSE_STRAP); 8406 8407 if (found & SFUSE_STRAP_DDIB_DETECTED) 8408 intel_ddi_init(dev, PORT_B); 8409 if (found & SFUSE_STRAP_DDIC_DETECTED) 8410 intel_ddi_init(dev, PORT_C); 8411 if (found & SFUSE_STRAP_DDID_DETECTED) 8412 intel_ddi_init(dev, PORT_D); 8413 } else if (HAS_PCH_SPLIT(dev)) { 8414 int found; 8415 dpd_is_edp = intel_dpd_is_edp(dev); 8416 8417 if (has_edp_a(dev)) 8418 intel_dp_init(dev, DP_A, PORT_A); 8419 8420 if (I915_READ(HDMIB) & PORT_DETECTED) { 8421 /* PCH SDVOB multiplex with HDMIB */ 8422 found = intel_sdvo_init(dev, PCH_SDVOB, true); 8423 if (!found) 8424 intel_hdmi_init(dev, HDMIB, PORT_B); 8425 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) 8426 intel_dp_init(dev, PCH_DP_B, PORT_B); 8427 } 8428 8429 if (I915_READ(HDMIC) & PORT_DETECTED) 8430 intel_hdmi_init(dev, HDMIC, PORT_C); 8431 8432 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED) 8433 intel_hdmi_init(dev, HDMID, PORT_D); 8434 8435 if (I915_READ(PCH_DP_C) & DP_DETECTED) 8436 intel_dp_init(dev, PCH_DP_C, PORT_C); 8437 8438 if (I915_READ(PCH_DP_D) & DP_DETECTED) 8439 intel_dp_init(dev, PCH_DP_D, PORT_D); 8440 } else if (IS_VALLEYVIEW(dev)) { 8441 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */ 8442 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) 8443 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); 8444 8445 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) { 8446 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B); 8447 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) 8448 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); 8449 } 8450 8451 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED) 8452 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C); 8453 8454 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { 8455 bool found = false; 8456 8457 if (I915_READ(SDVOB) & SDVO_DETECTED) { 8458 DRM_DEBUG_KMS("probing SDVOB\n"); 8459 found = intel_sdvo_init(dev, SDVOB, true); 8460 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { 8461 DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); 8462 intel_hdmi_init(dev, SDVOB, PORT_B); 8463 } 8464 8465 if (!found && SUPPORTS_INTEGRATED_DP(dev)) { 8466 DRM_DEBUG_KMS("probing DP_B\n"); 8467 intel_dp_init(dev, DP_B, PORT_B); 8468 } 8469 } 8470 8471 /* Before G4X SDVOC doesn't have its own detect register */ 8472 8473 if (I915_READ(SDVOB) & SDVO_DETECTED) { 8474 DRM_DEBUG_KMS("probing SDVOC\n"); 8475 found = intel_sdvo_init(dev, SDVOC, false); 8476 } 8477 8478 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) { 8479 8480 if (SUPPORTS_INTEGRATED_HDMI(dev)) { 8481 DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); 8482 intel_hdmi_init(dev, SDVOC, PORT_C); 8483 } 8484 if (SUPPORTS_INTEGRATED_DP(dev)) { 8485 DRM_DEBUG_KMS("probing DP_C\n"); 8486 intel_dp_init(dev, DP_C, PORT_C); 8487 } 8488 } 8489 8490 if (SUPPORTS_INTEGRATED_DP(dev) && 8491 (I915_READ(DP_D) & DP_DETECTED)) { 8492 DRM_DEBUG_KMS("probing DP_D\n"); 8493 intel_dp_init(dev, DP_D, PORT_D); 8494 } 8495 } else if (IS_GEN2(dev)) { 8496 #if 0 8497 intel_dvo_init(dev); 8498 #endif 8499 } 8500 8501 if (SUPPORTS_TV(dev)) 8502 intel_tv_init(dev); 8503 8504 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { 8505 encoder->base.possible_crtcs = encoder->crtc_mask; 8506 encoder->base.possible_clones = 8507 intel_encoder_clones(encoder); 8508 } 8509 8510 intel_init_pch_refclk(dev); 8511 8512 drm_helper_move_panel_connectors_to_head(dev); 8513 } 8514 8515 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) 8516 { 8517 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 8518 8519 drm_framebuffer_cleanup(fb); 8520 drm_gem_object_unreference_unlocked(&intel_fb->obj->base); 8521 8522 drm_free(intel_fb, M_DRM); 8523 } 8524 8525 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, 8526 struct drm_file *file, 8527 unsigned int *handle) 8528 { 8529 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 8530 struct drm_i915_gem_object *obj = intel_fb->obj; 8531 8532 return drm_gem_handle_create(file, &obj->base, handle); 8533 } 8534 8535 static const struct drm_framebuffer_funcs intel_fb_funcs = { 8536 .destroy = intel_user_framebuffer_destroy, 8537 .create_handle = intel_user_framebuffer_create_handle, 8538 }; 8539 8540 int intel_framebuffer_init(struct drm_device *dev, 8541 struct intel_framebuffer *intel_fb, 8542 struct drm_mode_fb_cmd2 *mode_cmd, 8543 struct drm_i915_gem_object *obj) 8544 { 8545 int ret; 8546 8547 if (obj->tiling_mode == I915_TILING_Y) { 8548 DRM_DEBUG("hardware does not support tiling Y\n"); 8549 return -EINVAL; 8550 } 8551 8552 if (mode_cmd->pitches[0] & 63) { 8553 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", 8554 mode_cmd->pitches[0]); 8555 return -EINVAL; 8556 } 8557 8558 /* FIXME <= Gen4 stride limits are bit unclear */ 8559 if (mode_cmd->pitches[0] > 32768) { 8560 DRM_DEBUG("pitch (%d) must be at less than 32768\n", 8561 mode_cmd->pitches[0]); 8562 return -EINVAL; 8563 } 8564 8565 if (obj->tiling_mode != I915_TILING_NONE && 8566 mode_cmd->pitches[0] != obj->stride) { 8567 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", 8568 mode_cmd->pitches[0], obj->stride); 8569 return -EINVAL; 8570 } 8571 8572 /* Reject formats not supported by any plane early. */ 8573 switch (mode_cmd->pixel_format) { 8574 case DRM_FORMAT_C8: 8575 case DRM_FORMAT_RGB565: 8576 case DRM_FORMAT_XRGB8888: 8577 case DRM_FORMAT_ARGB8888: 8578 break; 8579 case DRM_FORMAT_XRGB1555: 8580 case DRM_FORMAT_ARGB1555: 8581 if (INTEL_INFO(dev)->gen > 3) { 8582 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 8583 return -EINVAL; 8584 } 8585 break; 8586 case DRM_FORMAT_XBGR8888: 8587 case DRM_FORMAT_ABGR8888: 8588 case DRM_FORMAT_XRGB2101010: 8589 case DRM_FORMAT_ARGB2101010: 8590 case DRM_FORMAT_XBGR2101010: 8591 case DRM_FORMAT_ABGR2101010: 8592 if (INTEL_INFO(dev)->gen < 4) { 8593 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 8594 return -EINVAL; 8595 } 8596 break; 8597 case DRM_FORMAT_YUYV: 8598 case DRM_FORMAT_UYVY: 8599 case DRM_FORMAT_YVYU: 8600 case DRM_FORMAT_VYUY: 8601 if (INTEL_INFO(dev)->gen < 5) { 8602 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format); 8603 return -EINVAL; 8604 } 8605 break; 8606 default: 8607 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format); 8608 return -EINVAL; 8609 } 8610 8611 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ 8612 if (mode_cmd->offsets[0] != 0) 8613 return -EINVAL; 8614 8615 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); 8616 intel_fb->obj = obj; 8617 8618 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); 8619 if (ret) { 8620 DRM_ERROR("framebuffer init failed %d\n", ret); 8621 return ret; 8622 } 8623 8624 return 0; 8625 } 8626 8627 static struct drm_framebuffer * 8628 intel_user_framebuffer_create(struct drm_device *dev, 8629 struct drm_file *filp, 8630 struct drm_mode_fb_cmd2 *mode_cmd) 8631 { 8632 struct drm_i915_gem_object *obj; 8633 8634 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, 8635 mode_cmd->handles[0])); 8636 if (&obj->base == NULL) 8637 return ERR_PTR(-ENOENT); 8638 8639 return intel_framebuffer_create(dev, mode_cmd, obj); 8640 } 8641 8642 static const struct drm_mode_config_funcs intel_mode_funcs = { 8643 .fb_create = intel_user_framebuffer_create, 8644 .output_poll_changed = intel_fb_output_poll_changed, 8645 }; 8646 8647 /* Set up chip specific display functions */ 8648 static void intel_init_display(struct drm_device *dev) 8649 { 8650 struct drm_i915_private *dev_priv = dev->dev_private; 8651 8652 /* We always want a DPMS function */ 8653 if (HAS_DDI(dev)) { 8654 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; 8655 dev_priv->display.crtc_enable = haswell_crtc_enable; 8656 dev_priv->display.crtc_disable = haswell_crtc_disable; 8657 dev_priv->display.off = haswell_crtc_off; 8658 dev_priv->display.update_plane = ironlake_update_plane; 8659 } else if (HAS_PCH_SPLIT(dev)) { 8660 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; 8661 dev_priv->display.crtc_enable = ironlake_crtc_enable; 8662 dev_priv->display.crtc_disable = ironlake_crtc_disable; 8663 dev_priv->display.off = ironlake_crtc_off; 8664 dev_priv->display.update_plane = ironlake_update_plane; 8665 } else { 8666 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; 8667 dev_priv->display.crtc_enable = i9xx_crtc_enable; 8668 dev_priv->display.crtc_disable = i9xx_crtc_disable; 8669 dev_priv->display.off = i9xx_crtc_off; 8670 dev_priv->display.update_plane = i9xx_update_plane; 8671 } 8672 8673 /* Returns the core display clock speed */ 8674 if (IS_VALLEYVIEW(dev)) 8675 dev_priv->display.get_display_clock_speed = 8676 valleyview_get_display_clock_speed; 8677 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) 8678 dev_priv->display.get_display_clock_speed = 8679 i945_get_display_clock_speed; 8680 else if (IS_I915G(dev)) 8681 dev_priv->display.get_display_clock_speed = 8682 i915_get_display_clock_speed; 8683 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) 8684 dev_priv->display.get_display_clock_speed = 8685 i9xx_misc_get_display_clock_speed; 8686 else if (IS_I915GM(dev)) 8687 dev_priv->display.get_display_clock_speed = 8688 i915gm_get_display_clock_speed; 8689 else if (IS_I865G(dev)) 8690 dev_priv->display.get_display_clock_speed = 8691 i865_get_display_clock_speed; 8692 else if (IS_I85X(dev)) 8693 dev_priv->display.get_display_clock_speed = 8694 i855_get_display_clock_speed; 8695 else /* 852, 830 */ 8696 dev_priv->display.get_display_clock_speed = 8697 i830_get_display_clock_speed; 8698 8699 if (HAS_PCH_SPLIT(dev)) { 8700 if (IS_GEN5(dev)) { 8701 dev_priv->display.fdi_link_train = ironlake_fdi_link_train; 8702 dev_priv->display.write_eld = ironlake_write_eld; 8703 } else if (IS_GEN6(dev)) { 8704 dev_priv->display.fdi_link_train = gen6_fdi_link_train; 8705 dev_priv->display.write_eld = ironlake_write_eld; 8706 } else if (IS_IVYBRIDGE(dev)) { 8707 /* FIXME: detect B0+ stepping and use auto training */ 8708 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; 8709 dev_priv->display.write_eld = ironlake_write_eld; 8710 dev_priv->display.modeset_global_resources = 8711 ivb_modeset_global_resources; 8712 } else if (IS_HASWELL(dev)) { 8713 dev_priv->display.fdi_link_train = hsw_fdi_link_train; 8714 dev_priv->display.write_eld = haswell_write_eld; 8715 dev_priv->display.modeset_global_resources = 8716 haswell_modeset_global_resources; 8717 } 8718 } else if (IS_G4X(dev)) { 8719 dev_priv->display.write_eld = g4x_write_eld; 8720 } 8721 8722 /* Default just returns -ENODEV to indicate unsupported */ 8723 dev_priv->display.queue_flip = intel_default_queue_flip; 8724 8725 switch (INTEL_INFO(dev)->gen) { 8726 case 2: 8727 dev_priv->display.queue_flip = intel_gen2_queue_flip; 8728 break; 8729 8730 case 3: 8731 dev_priv->display.queue_flip = intel_gen3_queue_flip; 8732 break; 8733 8734 case 4: 8735 case 5: 8736 dev_priv->display.queue_flip = intel_gen4_queue_flip; 8737 break; 8738 8739 case 6: 8740 dev_priv->display.queue_flip = intel_gen6_queue_flip; 8741 break; 8742 case 7: 8743 dev_priv->display.queue_flip = intel_gen7_queue_flip; 8744 break; 8745 } 8746 } 8747 8748 /* 8749 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, 8750 * resume, or other times. This quirk makes sure that's the case for 8751 * affected systems. 8752 */ 8753 static void quirk_pipea_force(struct drm_device *dev) 8754 { 8755 struct drm_i915_private *dev_priv = dev->dev_private; 8756 8757 dev_priv->quirks |= QUIRK_PIPEA_FORCE; 8758 DRM_INFO("applying pipe a force quirk\n"); 8759 } 8760 8761 /* 8762 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason 8763 */ 8764 static void quirk_ssc_force_disable(struct drm_device *dev) 8765 { 8766 struct drm_i915_private *dev_priv = dev->dev_private; 8767 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; 8768 DRM_INFO("applying lvds SSC disable quirk\n"); 8769 } 8770 8771 /* 8772 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight 8773 * brightness value 8774 */ 8775 static void quirk_invert_brightness(struct drm_device *dev) 8776 { 8777 struct drm_i915_private *dev_priv = dev->dev_private; 8778 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; 8779 DRM_INFO("applying inverted panel brightness quirk\n"); 8780 } 8781 8782 struct intel_quirk { 8783 int device; 8784 int subsystem_vendor; 8785 int subsystem_device; 8786 void (*hook)(struct drm_device *dev); 8787 }; 8788 8789 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ 8790 struct intel_dmi_quirk { 8791 void (*hook)(struct drm_device *dev); 8792 const struct dmi_system_id (*dmi_id_list)[]; 8793 }; 8794 8795 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) 8796 { 8797 DRM_INFO("Backlight polarity reversed on %s\n", id->ident); 8798 return 1; 8799 } 8800 8801 static const struct intel_dmi_quirk intel_dmi_quirks[] = { 8802 { 8803 .dmi_id_list = &(const struct dmi_system_id[]) { 8804 { 8805 .callback = intel_dmi_reverse_brightness, 8806 .ident = "NCR Corporation", 8807 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), 8808 DMI_MATCH(DMI_PRODUCT_NAME, ""), 8809 }, 8810 }, 8811 { } /* terminating entry */ 8812 }, 8813 .hook = quirk_invert_brightness, 8814 }, 8815 }; 8816 8817 static struct intel_quirk intel_quirks[] = { 8818 /* HP Mini needs pipe A force quirk (LP: #322104) */ 8819 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, 8820 8821 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ 8822 { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, 8823 8824 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ 8825 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, 8826 8827 /* 830/845 need to leave pipe A & dpll A up */ 8828 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 8829 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, 8830 8831 /* Lenovo U160 cannot use SSC on LVDS */ 8832 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, 8833 8834 /* Sony Vaio Y cannot use SSC on LVDS */ 8835 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, 8836 8837 /* Acer Aspire 5734Z must invert backlight brightness */ 8838 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, 8839 8840 /* Acer/eMachines G725 */ 8841 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, 8842 8843 /* Acer/eMachines e725 */ 8844 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, 8845 8846 /* Acer/Packard Bell NCL20 */ 8847 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, 8848 8849 /* Acer Aspire 4736Z */ 8850 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, 8851 }; 8852 8853 static void intel_init_quirks(struct drm_device *dev) 8854 { 8855 device_t d; 8856 int i; 8857 8858 d = dev->dev; 8859 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { 8860 struct intel_quirk *q = &intel_quirks[i]; 8861 if (pci_get_device(d) == q->device && 8862 (pci_get_subvendor(d) == q->subsystem_vendor || 8863 q->subsystem_vendor == PCI_ANY_ID) && 8864 (pci_get_subdevice(d) == q->subsystem_device || 8865 q->subsystem_device == PCI_ANY_ID)) 8866 q->hook(dev); 8867 } 8868 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { 8869 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) 8870 intel_dmi_quirks[i].hook(dev); 8871 } 8872 } 8873 8874 /* Disable the VGA plane that we never use */ 8875 static void i915_disable_vga(struct drm_device *dev) 8876 { 8877 struct drm_i915_private *dev_priv = dev->dev_private; 8878 u8 sr1; 8879 u32 vga_reg = i915_vgacntrl_reg(dev); 8880 8881 #if 0 8882 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); 8883 #endif 8884 outb(VGA_SR_INDEX, 1); 8885 sr1 = inb(VGA_SR_DATA); 8886 outb(VGA_SR_DATA, sr1 | 1 << 5); 8887 #if 0 8888 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); 8889 #endif 8890 udelay(300); 8891 8892 I915_WRITE(vga_reg, VGA_DISP_DISABLE); 8893 POSTING_READ(vga_reg); 8894 } 8895 8896 void intel_modeset_init_hw(struct drm_device *dev) 8897 { 8898 intel_init_power_well(dev); 8899 8900 intel_prepare_ddi(dev); 8901 8902 intel_init_clock_gating(dev); 8903 8904 mutex_lock(&dev->struct_mutex); 8905 intel_enable_gt_powersave(dev); 8906 mutex_unlock(&dev->struct_mutex); 8907 } 8908 8909 void intel_modeset_init(struct drm_device *dev) 8910 { 8911 struct drm_i915_private *dev_priv = dev->dev_private; 8912 int i, ret; 8913 8914 drm_mode_config_init(dev); 8915 8916 dev->mode_config.min_width = 0; 8917 dev->mode_config.min_height = 0; 8918 8919 dev->mode_config.preferred_depth = 24; 8920 dev->mode_config.prefer_shadow = 1; 8921 8922 dev->mode_config.funcs = &intel_mode_funcs; 8923 8924 intel_init_quirks(dev); 8925 8926 intel_init_pm(dev); 8927 8928 intel_init_display(dev); 8929 8930 if (IS_GEN2(dev)) { 8931 dev->mode_config.max_width = 2048; 8932 dev->mode_config.max_height = 2048; 8933 } else if (IS_GEN3(dev)) { 8934 dev->mode_config.max_width = 4096; 8935 dev->mode_config.max_height = 4096; 8936 } else { 8937 dev->mode_config.max_width = 8192; 8938 dev->mode_config.max_height = 8192; 8939 } 8940 dev->mode_config.fb_base = dev->agp->base; 8941 8942 DRM_DEBUG_KMS("%d display pipe%s available.\n", 8943 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : ""); 8944 8945 for (i = 0; i < dev_priv->num_pipe; i++) { 8946 intel_crtc_init(dev, i); 8947 ret = intel_plane_init(dev, i); 8948 if (ret) 8949 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret); 8950 } 8951 8952 intel_cpu_pll_init(dev); 8953 intel_pch_pll_init(dev); 8954 8955 /* Just disable it once at startup */ 8956 i915_disable_vga(dev); 8957 intel_setup_outputs(dev); 8958 8959 /* Just in case the BIOS is doing something questionable. */ 8960 intel_disable_fbc(dev); 8961 } 8962 8963 static void 8964 intel_connector_break_all_links(struct intel_connector *connector) 8965 { 8966 connector->base.dpms = DRM_MODE_DPMS_OFF; 8967 connector->base.encoder = NULL; 8968 connector->encoder->connectors_active = false; 8969 connector->encoder->base.crtc = NULL; 8970 } 8971 8972 static void intel_enable_pipe_a(struct drm_device *dev) 8973 { 8974 struct intel_connector *connector; 8975 struct drm_connector *crt = NULL; 8976 struct intel_load_detect_pipe load_detect_temp; 8977 8978 /* We can't just switch on the pipe A, we need to set things up with a 8979 * proper mode and output configuration. As a gross hack, enable pipe A 8980 * by enabling the load detect pipe once. */ 8981 list_for_each_entry(connector, 8982 &dev->mode_config.connector_list, 8983 base.head) { 8984 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { 8985 crt = &connector->base; 8986 break; 8987 } 8988 } 8989 8990 if (!crt) 8991 return; 8992 8993 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp)) 8994 intel_release_load_detect_pipe(crt, &load_detect_temp); 8995 8996 8997 } 8998 8999 static bool 9000 intel_check_plane_mapping(struct intel_crtc *crtc) 9001 { 9002 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; 9003 u32 reg, val; 9004 9005 if (dev_priv->num_pipe == 1) 9006 return true; 9007 9008 reg = DSPCNTR(!crtc->plane); 9009 val = I915_READ(reg); 9010 9011 if ((val & DISPLAY_PLANE_ENABLE) && 9012 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) 9013 return false; 9014 9015 return true; 9016 } 9017 9018 static void intel_sanitize_crtc(struct intel_crtc *crtc) 9019 { 9020 struct drm_device *dev = crtc->base.dev; 9021 struct drm_i915_private *dev_priv = dev->dev_private; 9022 u32 reg; 9023 9024 /* Clear any frame start delays used for debugging left by the BIOS */ 9025 reg = PIPECONF(crtc->cpu_transcoder); 9026 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); 9027 9028 /* We need to sanitize the plane -> pipe mapping first because this will 9029 * disable the crtc (and hence change the state) if it is wrong. Note 9030 * that gen4+ has a fixed plane -> pipe mapping. */ 9031 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { 9032 struct intel_connector *connector; 9033 bool plane; 9034 9035 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", 9036 crtc->base.base.id); 9037 9038 /* Pipe has the wrong plane attached and the plane is active. 9039 * Temporarily change the plane mapping and disable everything 9040 * ... */ 9041 plane = crtc->plane; 9042 crtc->plane = !plane; 9043 dev_priv->display.crtc_disable(&crtc->base); 9044 crtc->plane = plane; 9045 9046 /* ... and break all links. */ 9047 list_for_each_entry(connector, &dev->mode_config.connector_list, 9048 base.head) { 9049 if (connector->encoder->base.crtc != &crtc->base) 9050 continue; 9051 9052 intel_connector_break_all_links(connector); 9053 } 9054 9055 WARN_ON(crtc->active); 9056 crtc->base.enabled = false; 9057 } 9058 9059 if (dev_priv->quirks & QUIRK_PIPEA_FORCE && 9060 crtc->pipe == PIPE_A && !crtc->active) { 9061 /* BIOS forgot to enable pipe A, this mostly happens after 9062 * resume. Force-enable the pipe to fix this, the update_dpms 9063 * call below we restore the pipe to the right state, but leave 9064 * the required bits on. */ 9065 intel_enable_pipe_a(dev); 9066 } 9067 9068 /* Adjust the state of the output pipe according to whether we 9069 * have active connectors/encoders. */ 9070 intel_crtc_update_dpms(&crtc->base); 9071 9072 if (crtc->active != crtc->base.enabled) { 9073 struct intel_encoder *encoder; 9074 9075 /* This can happen either due to bugs in the get_hw_state 9076 * functions or because the pipe is force-enabled due to the 9077 * pipe A quirk. */ 9078 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", 9079 crtc->base.base.id, 9080 crtc->base.enabled ? "enabled" : "disabled", 9081 crtc->active ? "enabled" : "disabled"); 9082 9083 crtc->base.enabled = crtc->active; 9084 9085 /* Because we only establish the connector -> encoder -> 9086 * crtc links if something is active, this means the 9087 * crtc is now deactivated. Break the links. connector 9088 * -> encoder links are only establish when things are 9089 * actually up, hence no need to break them. */ 9090 WARN_ON(crtc->active); 9091 9092 for_each_encoder_on_crtc(dev, &crtc->base, encoder) { 9093 WARN_ON(encoder->connectors_active); 9094 encoder->base.crtc = NULL; 9095 } 9096 } 9097 } 9098 9099 static void intel_sanitize_encoder(struct intel_encoder *encoder) 9100 { 9101 struct intel_connector *connector; 9102 struct drm_device *dev = encoder->base.dev; 9103 9104 /* We need to check both for a crtc link (meaning that the 9105 * encoder is active and trying to read from a pipe) and the 9106 * pipe itself being active. */ 9107 bool has_active_crtc = encoder->base.crtc && 9108 to_intel_crtc(encoder->base.crtc)->active; 9109 9110 if (encoder->connectors_active && !has_active_crtc) { 9111 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", 9112 encoder->base.base.id, 9113 drm_get_encoder_name(&encoder->base)); 9114 9115 /* Connector is active, but has no active pipe. This is 9116 * fallout from our resume register restoring. Disable 9117 * the encoder manually again. */ 9118 if (encoder->base.crtc) { 9119 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", 9120 encoder->base.base.id, 9121 drm_get_encoder_name(&encoder->base)); 9122 encoder->disable(encoder); 9123 } 9124 9125 /* Inconsistent output/port/pipe state happens presumably due to 9126 * a bug in one of the get_hw_state functions. Or someplace else 9127 * in our code, like the register restore mess on resume. Clamp 9128 * things to off as a safer default. */ 9129 list_for_each_entry(connector, 9130 &dev->mode_config.connector_list, 9131 base.head) { 9132 if (connector->encoder != encoder) 9133 continue; 9134 9135 intel_connector_break_all_links(connector); 9136 } 9137 } 9138 /* Enabled encoders without active connectors will be fixed in 9139 * the crtc fixup. */ 9140 } 9141 9142 void i915_redisable_vga(struct drm_device *dev) 9143 { 9144 struct drm_i915_private *dev_priv = dev->dev_private; 9145 u32 vga_reg = i915_vgacntrl_reg(dev); 9146 9147 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) { 9148 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); 9149 i915_disable_vga(dev); 9150 } 9151 } 9152 9153 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm 9154 * and i915 state tracking structures. */ 9155 void intel_modeset_setup_hw_state(struct drm_device *dev, 9156 bool force_restore) 9157 { 9158 struct drm_i915_private *dev_priv = dev->dev_private; 9159 enum i915_pipe pipe; 9160 u32 tmp; 9161 struct intel_crtc *crtc; 9162 struct intel_encoder *encoder; 9163 struct intel_connector *connector; 9164 9165 if (HAS_DDI(dev)) { 9166 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 9167 9168 if (tmp & TRANS_DDI_FUNC_ENABLE) { 9169 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 9170 case TRANS_DDI_EDP_INPUT_A_ON: 9171 case TRANS_DDI_EDP_INPUT_A_ONOFF: 9172 pipe = PIPE_A; 9173 break; 9174 case TRANS_DDI_EDP_INPUT_B_ONOFF: 9175 pipe = PIPE_B; 9176 break; 9177 case TRANS_DDI_EDP_INPUT_C_ONOFF: 9178 pipe = PIPE_C; 9179 break; 9180 } 9181 9182 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 9183 crtc->cpu_transcoder = TRANSCODER_EDP; 9184 9185 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n", 9186 pipe_name(pipe)); 9187 } 9188 } 9189 9190 for_each_pipe(pipe) { 9191 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 9192 9193 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder)); 9194 if (tmp & PIPECONF_ENABLE) 9195 crtc->active = true; 9196 else 9197 crtc->active = false; 9198 9199 crtc->base.enabled = crtc->active; 9200 9201 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", 9202 crtc->base.base.id, 9203 crtc->active ? "enabled" : "disabled"); 9204 } 9205 9206 if (HAS_DDI(dev)) 9207 intel_ddi_setup_hw_pll_state(dev); 9208 9209 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9210 base.head) { 9211 pipe = 0; 9212 9213 if (encoder->get_hw_state(encoder, &pipe)) { 9214 encoder->base.crtc = 9215 dev_priv->pipe_to_crtc_mapping[pipe]; 9216 } else { 9217 encoder->base.crtc = NULL; 9218 } 9219 9220 encoder->connectors_active = false; 9221 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n", 9222 encoder->base.base.id, 9223 drm_get_encoder_name(&encoder->base), 9224 encoder->base.crtc ? "enabled" : "disabled", 9225 pipe); 9226 } 9227 9228 list_for_each_entry(connector, &dev->mode_config.connector_list, 9229 base.head) { 9230 if (connector->get_hw_state(connector)) { 9231 connector->base.dpms = DRM_MODE_DPMS_ON; 9232 connector->encoder->connectors_active = true; 9233 connector->base.encoder = &connector->encoder->base; 9234 } else { 9235 connector->base.dpms = DRM_MODE_DPMS_OFF; 9236 connector->base.encoder = NULL; 9237 } 9238 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", 9239 connector->base.base.id, 9240 drm_get_connector_name(&connector->base), 9241 connector->base.encoder ? "enabled" : "disabled"); 9242 } 9243 9244 /* HW state is read out, now we need to sanitize this mess. */ 9245 list_for_each_entry(encoder, &dev->mode_config.encoder_list, 9246 base.head) { 9247 intel_sanitize_encoder(encoder); 9248 } 9249 9250 for_each_pipe(pipe) { 9251 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 9252 intel_sanitize_crtc(crtc); 9253 } 9254 9255 if (force_restore) { 9256 /* 9257 * We need to use raw interfaces for restoring state to avoid 9258 * checking (bogus) intermediate states. 9259 */ 9260 for_each_pipe(pipe) { 9261 struct drm_crtc *crtc = 9262 dev_priv->pipe_to_crtc_mapping[pipe]; 9263 9264 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, 9265 crtc->fb); 9266 } 9267 9268 i915_redisable_vga(dev); 9269 } else { 9270 intel_modeset_update_staged_output_state(dev); 9271 } 9272 9273 intel_modeset_check_state(dev); 9274 9275 drm_mode_config_reset(dev); 9276 } 9277 9278 void intel_modeset_gem_init(struct drm_device *dev) 9279 { 9280 intel_modeset_init_hw(dev); 9281 9282 intel_setup_overlay(dev); 9283 9284 intel_modeset_setup_hw_state(dev, false); 9285 } 9286 9287 void intel_modeset_cleanup(struct drm_device *dev) 9288 { 9289 struct drm_i915_private *dev_priv = dev->dev_private; 9290 struct drm_crtc *crtc; 9291 struct intel_crtc *intel_crtc; 9292 9293 drm_kms_helper_poll_fini(dev); 9294 mutex_lock(&dev->struct_mutex); 9295 9296 #if 0 9297 intel_unregister_dsm_handler(); 9298 #endif 9299 9300 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 9301 /* Skip inactive CRTCs */ 9302 if (!crtc->fb) 9303 continue; 9304 9305 intel_crtc = to_intel_crtc(crtc); 9306 intel_increase_pllclock(crtc); 9307 } 9308 9309 intel_disable_fbc(dev); 9310 9311 intel_disable_gt_powersave(dev); 9312 9313 ironlake_teardown_rc6(dev); 9314 9315 if (IS_VALLEYVIEW(dev)) 9316 vlv_init_dpio(dev); 9317 9318 mutex_unlock(&dev->struct_mutex); 9319 9320 /* Disable the irq before mode object teardown, for the irq might 9321 * enqueue unpin/hotplug work. */ 9322 drm_irq_uninstall(dev); 9323 cancel_work_sync(&dev_priv->hotplug_work); 9324 cancel_work_sync(&dev_priv->rps.work); 9325 9326 /* flush any delayed tasks or pending work */ 9327 flush_scheduled_work(); 9328 9329 /* destroy backlight, if any, before the connectors */ 9330 intel_panel_destroy_backlight(dev); 9331 9332 drm_mode_config_cleanup(dev); 9333 9334 intel_cleanup_overlay(dev); 9335 } 9336 9337 /* 9338 * Return which encoder is currently attached for connector. 9339 */ 9340 struct drm_encoder *intel_best_encoder(struct drm_connector *connector) 9341 { 9342 return &intel_attached_encoder(connector)->base; 9343 } 9344 9345 void intel_connector_attach_encoder(struct intel_connector *connector, 9346 struct intel_encoder *encoder) 9347 { 9348 connector->encoder = encoder; 9349 drm_mode_connector_attach_encoder(&connector->base, 9350 &encoder->base); 9351 } 9352 9353 /* 9354 * set vga decode state - true == enable VGA decode 9355 */ 9356 int intel_modeset_vga_set_state(struct drm_device *dev, bool state) 9357 { 9358 struct drm_i915_private *dev_priv = dev->dev_private; 9359 u16 gmch_ctrl; 9360 9361 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl); 9362 if (state) 9363 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; 9364 else 9365 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; 9366 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl); 9367 return 0; 9368 } 9369 9370 #ifdef CONFIG_DEBUG_FS 9371 #include <linux/seq_file.h> 9372 9373 struct intel_display_error_state { 9374 struct intel_cursor_error_state { 9375 u32 control; 9376 u32 position; 9377 u32 base; 9378 u32 size; 9379 } cursor[I915_MAX_PIPES]; 9380 9381 struct intel_pipe_error_state { 9382 u32 conf; 9383 u32 source; 9384 9385 u32 htotal; 9386 u32 hblank; 9387 u32 hsync; 9388 u32 vtotal; 9389 u32 vblank; 9390 u32 vsync; 9391 } pipe[I915_MAX_PIPES]; 9392 9393 struct intel_plane_error_state { 9394 u32 control; 9395 u32 stride; 9396 u32 size; 9397 u32 pos; 9398 u32 addr; 9399 u32 surface; 9400 u32 tile_offset; 9401 } plane[I915_MAX_PIPES]; 9402 }; 9403 9404 struct intel_display_error_state * 9405 intel_display_capture_error_state(struct drm_device *dev) 9406 { 9407 drm_i915_private_t *dev_priv = dev->dev_private; 9408 struct intel_display_error_state *error; 9409 enum transcoder cpu_transcoder; 9410 int i; 9411 9412 error = kmalloc(sizeof(*error), M_DRM, M_WAITOK | M_NULLOK); 9413 if (error == NULL) 9414 return NULL; 9415 9416 for_each_pipe(i) { 9417 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i); 9418 9419 error->cursor[i].control = I915_READ(CURCNTR(i)); 9420 error->cursor[i].position = I915_READ(CURPOS(i)); 9421 error->cursor[i].base = I915_READ(CURBASE(i)); 9422 9423 error->plane[i].control = I915_READ(DSPCNTR(i)); 9424 error->plane[i].stride = I915_READ(DSPSTRIDE(i)); 9425 error->plane[i].size = I915_READ(DSPSIZE(i)); 9426 error->plane[i].pos = I915_READ(DSPPOS(i)); 9427 error->plane[i].addr = I915_READ(DSPADDR(i)); 9428 if (INTEL_INFO(dev)->gen >= 4) { 9429 error->plane[i].surface = I915_READ(DSPSURF(i)); 9430 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); 9431 } 9432 9433 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder)); 9434 error->pipe[i].source = I915_READ(PIPESRC(i)); 9435 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); 9436 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder)); 9437 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder)); 9438 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); 9439 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder)); 9440 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder)); 9441 } 9442 9443 return error; 9444 } 9445 9446 void 9447 intel_display_print_error_state(struct seq_file *m, 9448 struct drm_device *dev, 9449 struct intel_display_error_state *error) 9450 { 9451 drm_i915_private_t *dev_priv = dev->dev_private; 9452 int i; 9453 9454 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe); 9455 for_each_pipe(i) { 9456 seq_printf(m, "Pipe [%d]:\n", i); 9457 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf); 9458 seq_printf(m, " SRC: %08x\n", error->pipe[i].source); 9459 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal); 9460 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank); 9461 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync); 9462 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal); 9463 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank); 9464 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync); 9465 9466 seq_printf(m, "Plane [%d]:\n", i); 9467 seq_printf(m, " CNTR: %08x\n", error->plane[i].control); 9468 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride); 9469 seq_printf(m, " SIZE: %08x\n", error->plane[i].size); 9470 seq_printf(m, " POS: %08x\n", error->plane[i].pos); 9471 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); 9472 if (INTEL_INFO(dev)->gen >= 4) { 9473 seq_printf(m, " SURF: %08x\n", error->plane[i].surface); 9474 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); 9475 } 9476 9477 seq_printf(m, "Cursor [%d]:\n", i); 9478 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control); 9479 seq_printf(m, " POS: %08x\n", error->cursor[i].position); 9480 seq_printf(m, " BASE: %08x\n", error->cursor[i].base); 9481 } 9482 } 9483 #endif 9484