1 /* 2 * Copyright © 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eugeni Dodonov <eugeni.dodonov@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_drv.h" 30 #include <asm/int-ll64.h> 31 32 struct ddi_buf_trans { 33 u32 trans1; /* balance leg enable, de-emph level */ 34 u32 trans2; /* vref sel, vswing */ 35 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */ 36 }; 37 38 /* HDMI/DVI modes ignore everything but the last 2 items. So we share 39 * them for both DP and FDI transports, allowing those ports to 40 * automatically adapt to HDMI connections as well 41 */ 42 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { 43 { 0x00FFFFFF, 0x0006000E, 0x0 }, 44 { 0x00D75FFF, 0x0005000A, 0x0 }, 45 { 0x00C30FFF, 0x00040006, 0x0 }, 46 { 0x80AAAFFF, 0x000B0000, 0x0 }, 47 { 0x00FFFFFF, 0x0005000A, 0x0 }, 48 { 0x00D75FFF, 0x000C0004, 0x0 }, 49 { 0x80C30FFF, 0x000B0000, 0x0 }, 50 { 0x00FFFFFF, 0x00040006, 0x0 }, 51 { 0x80D75FFF, 0x000B0000, 0x0 }, 52 }; 53 54 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { 55 { 0x00FFFFFF, 0x0007000E, 0x0 }, 56 { 0x00D75FFF, 0x000F000A, 0x0 }, 57 { 0x00C30FFF, 0x00060006, 0x0 }, 58 { 0x00AAAFFF, 0x001E0000, 0x0 }, 59 { 0x00FFFFFF, 0x000F000A, 0x0 }, 60 { 0x00D75FFF, 0x00160004, 0x0 }, 61 { 0x00C30FFF, 0x001E0000, 0x0 }, 62 { 0x00FFFFFF, 0x00060006, 0x0 }, 63 { 0x00D75FFF, 0x001E0000, 0x0 }, 64 }; 65 66 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { 67 /* Idx NT mV d T mV d db */ 68 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */ 69 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */ 70 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */ 71 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */ 72 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */ 73 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */ 74 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */ 75 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */ 76 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */ 77 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */ 78 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */ 79 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */ 80 }; 81 82 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { 83 { 0x00FFFFFF, 0x00000012, 0x0 }, 84 { 0x00EBAFFF, 0x00020011, 0x0 }, 85 { 0x00C71FFF, 0x0006000F, 0x0 }, 86 { 0x00AAAFFF, 0x000E000A, 0x0 }, 87 { 0x00FFFFFF, 0x00020011, 0x0 }, 88 { 0x00DB6FFF, 0x0005000F, 0x0 }, 89 { 0x00BEEFFF, 0x000A000C, 0x0 }, 90 { 0x00FFFFFF, 0x0005000F, 0x0 }, 91 { 0x00DB6FFF, 0x000A000C, 0x0 }, 92 }; 93 94 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { 95 { 0x00FFFFFF, 0x0007000E, 0x0 }, 96 { 0x00D75FFF, 0x000E000A, 0x0 }, 97 { 0x00BEFFFF, 0x00140006, 0x0 }, 98 { 0x80B2CFFF, 0x001B0002, 0x0 }, 99 { 0x00FFFFFF, 0x000E000A, 0x0 }, 100 { 0x00DB6FFF, 0x00160005, 0x0 }, 101 { 0x80C71FFF, 0x001A0002, 0x0 }, 102 { 0x00F7DFFF, 0x00180004, 0x0 }, 103 { 0x80D75FFF, 0x001B0002, 0x0 }, 104 }; 105 106 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { 107 { 0x00FFFFFF, 0x0001000E, 0x0 }, 108 { 0x00D75FFF, 0x0004000A, 0x0 }, 109 { 0x00C30FFF, 0x00070006, 0x0 }, 110 { 0x00AAAFFF, 0x000C0000, 0x0 }, 111 { 0x00FFFFFF, 0x0004000A, 0x0 }, 112 { 0x00D75FFF, 0x00090004, 0x0 }, 113 { 0x00C30FFF, 0x000C0000, 0x0 }, 114 { 0x00FFFFFF, 0x00070006, 0x0 }, 115 { 0x00D75FFF, 0x000C0000, 0x0 }, 116 }; 117 118 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { 119 /* Idx NT mV d T mV df db */ 120 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */ 121 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */ 122 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */ 123 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */ 124 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */ 125 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */ 126 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */ 127 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */ 128 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */ 129 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */ 130 }; 131 132 /* Skylake H and S */ 133 static const struct ddi_buf_trans skl_ddi_translations_dp[] = { 134 { 0x00002016, 0x000000A0, 0x0 }, 135 { 0x00005012, 0x0000009B, 0x0 }, 136 { 0x00007011, 0x00000088, 0x0 }, 137 { 0x00009010, 0x000000C7, 0x0 }, 138 { 0x00002016, 0x0000009B, 0x0 }, 139 { 0x00005012, 0x00000088, 0x0 }, 140 { 0x00007011, 0x000000C7, 0x0 }, 141 { 0x00002016, 0x000000DF, 0x0 }, 142 { 0x00005012, 0x000000C7, 0x0 }, 143 }; 144 145 /* Skylake U */ 146 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = { 147 { 0x0000201B, 0x000000A2, 0x0 }, 148 { 0x00005012, 0x00000088, 0x0 }, 149 { 0x00007011, 0x00000087, 0x0 }, 150 { 0x80009010, 0x000000C7, 0x1 }, /* Uses I_boost level 0x1 */ 151 { 0x0000201B, 0x0000009D, 0x0 }, 152 { 0x00005012, 0x000000C7, 0x0 }, 153 { 0x00007011, 0x000000C7, 0x0 }, 154 { 0x00002016, 0x00000088, 0x0 }, 155 { 0x00005012, 0x000000C7, 0x0 }, 156 }; 157 158 /* Skylake Y */ 159 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = { 160 { 0x00000018, 0x000000A2, 0x0 }, 161 { 0x00005012, 0x00000088, 0x0 }, 162 { 0x00007011, 0x00000087, 0x0 }, 163 { 0x80009010, 0x000000C7, 0x3 }, /* Uses I_boost level 0x3 */ 164 { 0x00000018, 0x0000009D, 0x0 }, 165 { 0x00005012, 0x000000C7, 0x0 }, 166 { 0x00007011, 0x000000C7, 0x0 }, 167 { 0x00000018, 0x00000088, 0x0 }, 168 { 0x00005012, 0x000000C7, 0x0 }, 169 }; 170 171 /* 172 * Skylake H and S 173 * eDP 1.4 low vswing translation parameters 174 */ 175 static const struct ddi_buf_trans skl_ddi_translations_edp[] = { 176 { 0x00000018, 0x000000A8, 0x0 }, 177 { 0x00004013, 0x000000A9, 0x0 }, 178 { 0x00007011, 0x000000A2, 0x0 }, 179 { 0x00009010, 0x0000009C, 0x0 }, 180 { 0x00000018, 0x000000A9, 0x0 }, 181 { 0x00006013, 0x000000A2, 0x0 }, 182 { 0x00007011, 0x000000A6, 0x0 }, 183 { 0x00000018, 0x000000AB, 0x0 }, 184 { 0x00007013, 0x0000009F, 0x0 }, 185 { 0x00000018, 0x000000DF, 0x0 }, 186 }; 187 188 /* 189 * Skylake U 190 * eDP 1.4 low vswing translation parameters 191 */ 192 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = { 193 { 0x00000018, 0x000000A8, 0x0 }, 194 { 0x00004013, 0x000000A9, 0x0 }, 195 { 0x00007011, 0x000000A2, 0x0 }, 196 { 0x00009010, 0x0000009C, 0x0 }, 197 { 0x00000018, 0x000000A9, 0x0 }, 198 { 0x00006013, 0x000000A2, 0x0 }, 199 { 0x00007011, 0x000000A6, 0x0 }, 200 { 0x00002016, 0x000000AB, 0x0 }, 201 { 0x00005013, 0x0000009F, 0x0 }, 202 { 0x00000018, 0x000000DF, 0x0 }, 203 }; 204 205 /* 206 * Skylake Y 207 * eDP 1.4 low vswing translation parameters 208 */ 209 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = { 210 { 0x00000018, 0x000000A8, 0x0 }, 211 { 0x00004013, 0x000000AB, 0x0 }, 212 { 0x00007011, 0x000000A4, 0x0 }, 213 { 0x00009010, 0x000000DF, 0x0 }, 214 { 0x00000018, 0x000000AA, 0x0 }, 215 { 0x00006013, 0x000000A4, 0x0 }, 216 { 0x00007011, 0x0000009D, 0x0 }, 217 { 0x00000018, 0x000000A0, 0x0 }, 218 { 0x00006012, 0x000000DF, 0x0 }, 219 { 0x00000018, 0x0000008A, 0x0 }, 220 }; 221 222 /* Skylake U, H and S */ 223 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { 224 { 0x00000018, 0x000000AC, 0x0 }, 225 { 0x00005012, 0x0000009D, 0x0 }, 226 { 0x00007011, 0x00000088, 0x0 }, 227 { 0x00000018, 0x000000A1, 0x0 }, 228 { 0x00000018, 0x00000098, 0x0 }, 229 { 0x00004013, 0x00000088, 0x0 }, 230 { 0x00006012, 0x00000087, 0x0 }, 231 { 0x00000018, 0x000000DF, 0x0 }, 232 { 0x00003015, 0x00000087, 0x0 }, /* Default */ 233 { 0x00003015, 0x000000C7, 0x0 }, 234 { 0x00000018, 0x000000C7, 0x0 }, 235 }; 236 237 /* Skylake Y */ 238 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = { 239 { 0x00000018, 0x000000A1, 0x0 }, 240 { 0x00005012, 0x000000DF, 0x0 }, 241 { 0x00007011, 0x00000084, 0x0 }, 242 { 0x00000018, 0x000000A4, 0x0 }, 243 { 0x00000018, 0x0000009D, 0x0 }, 244 { 0x00004013, 0x00000080, 0x0 }, 245 { 0x00006013, 0x000000C7, 0x0 }, 246 { 0x00000018, 0x0000008A, 0x0 }, 247 { 0x00003015, 0x000000C7, 0x0 }, /* Default */ 248 { 0x80003015, 0x000000C7, 0x7 }, /* Uses I_boost level 0x7 */ 249 { 0x00000018, 0x000000C7, 0x0 }, 250 }; 251 252 struct bxt_ddi_buf_trans { 253 u32 margin; /* swing value */ 254 u32 scale; /* scale value */ 255 u32 enable; /* scale enable */ 256 u32 deemphasis; 257 bool default_index; /* true if the entry represents default value */ 258 }; 259 260 /* BSpec does not define separate vswing/pre-emphasis values for eDP. 261 * Using DP values for eDP as well. 262 */ 263 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { 264 /* Idx NT mV diff db */ 265 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */ 266 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 267 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */ 268 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 269 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 270 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 271 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */ 272 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 273 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 274 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ 275 }; 276 277 /* BSpec has 2 recommended values - entries 0 and 8. 278 * Using the entry with higher vswing. 279 */ 280 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { 281 /* Idx NT mV diff db */ 282 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */ 283 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */ 284 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */ 285 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */ 286 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */ 287 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */ 288 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */ 289 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */ 290 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */ 291 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ 292 }; 293 294 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 295 enum port port, int type); 296 297 static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, 298 struct intel_digital_port **dig_port, 299 enum port *port) 300 { 301 struct drm_encoder *encoder = &intel_encoder->base; 302 int type = intel_encoder->type; 303 304 if (type == INTEL_OUTPUT_DP_MST) { 305 *dig_port = enc_to_mst(encoder)->primary; 306 *port = (*dig_port)->port; 307 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || 308 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { 309 *dig_port = enc_to_dig_port(encoder); 310 *port = (*dig_port)->port; 311 } else if (type == INTEL_OUTPUT_ANALOG) { 312 *dig_port = NULL; 313 *port = PORT_E; 314 } else { 315 DRM_ERROR("Invalid DDI encoder type %d\n", type); 316 BUG(); 317 } 318 } 319 320 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) 321 { 322 struct intel_digital_port *dig_port; 323 enum port port; 324 325 ddi_get_encoder_port(intel_encoder, &dig_port, &port); 326 327 return port; 328 } 329 330 static bool 331 intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) 332 { 333 return intel_dig_port->hdmi.hdmi_reg; 334 } 335 336 static const struct ddi_buf_trans *skl_get_buf_trans_dp(struct drm_device *dev, 337 int *n_entries) 338 { 339 const struct ddi_buf_trans *ddi_translations; 340 341 if (IS_SKL_ULX(dev)) { 342 ddi_translations = skl_y_ddi_translations_dp; 343 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 344 } else if (IS_SKL_ULT(dev)) { 345 ddi_translations = skl_u_ddi_translations_dp; 346 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 347 } else { 348 ddi_translations = skl_ddi_translations_dp; 349 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 350 } 351 352 return ddi_translations; 353 } 354 355 static const struct ddi_buf_trans *skl_get_buf_trans_edp(struct drm_device *dev, 356 int *n_entries) 357 { 358 struct drm_i915_private *dev_priv = dev->dev_private; 359 const struct ddi_buf_trans *ddi_translations; 360 361 if (IS_SKL_ULX(dev)) { 362 if (dev_priv->edp_low_vswing) { 363 ddi_translations = skl_y_ddi_translations_edp; 364 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp); 365 } else { 366 ddi_translations = skl_y_ddi_translations_dp; 367 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp); 368 } 369 } else if (IS_SKL_ULT(dev)) { 370 if (dev_priv->edp_low_vswing) { 371 ddi_translations = skl_u_ddi_translations_edp; 372 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp); 373 } else { 374 ddi_translations = skl_u_ddi_translations_dp; 375 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp); 376 } 377 } else { 378 if (dev_priv->edp_low_vswing) { 379 ddi_translations = skl_ddi_translations_edp; 380 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp); 381 } else { 382 ddi_translations = skl_ddi_translations_dp; 383 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp); 384 } 385 } 386 387 return ddi_translations; 388 } 389 390 static const struct ddi_buf_trans * 391 skl_get_buf_trans_hdmi(struct drm_device *dev, 392 int *n_entries) 393 { 394 const struct ddi_buf_trans *ddi_translations; 395 396 if (IS_SKL_ULX(dev)) { 397 ddi_translations = skl_y_ddi_translations_hdmi; 398 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi); 399 } else { 400 ddi_translations = skl_ddi_translations_hdmi; 401 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); 402 } 403 404 return ddi_translations; 405 } 406 407 /* 408 * Starting with Haswell, DDI port buffers must be programmed with correct 409 * values in advance. The buffer values are different for FDI and DP modes, 410 * but the HDMI/DVI fields are shared among those. So we program the DDI 411 * in either FDI or DP modes only, as HDMI connections will work with both 412 * of those 413 */ 414 static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, 415 bool supports_hdmi) 416 { 417 struct drm_i915_private *dev_priv = dev->dev_private; 418 u32 reg; 419 u32 iboost_bit = 0; 420 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, 421 size; 422 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; 423 const struct ddi_buf_trans *ddi_translations_fdi = NULL; 424 const struct ddi_buf_trans *ddi_translations_dp; 425 const struct ddi_buf_trans *ddi_translations_edp; 426 const struct ddi_buf_trans *ddi_translations_hdmi; 427 const struct ddi_buf_trans *ddi_translations; 428 429 if (IS_BROXTON(dev)) { 430 if (!supports_hdmi) 431 return; 432 433 /* Vswing programming for HDMI */ 434 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 435 INTEL_OUTPUT_HDMI); 436 return; 437 } else if (IS_SKYLAKE(dev)) { 438 ddi_translations_fdi = NULL; 439 ddi_translations_dp = 440 skl_get_buf_trans_dp(dev, &n_dp_entries); 441 ddi_translations_edp = 442 skl_get_buf_trans_edp(dev, &n_edp_entries); 443 ddi_translations_hdmi = 444 skl_get_buf_trans_hdmi(dev, &n_hdmi_entries); 445 hdmi_default_entry = 8; 446 /* If we're boosting the current, set bit 31 of trans1 */ 447 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level || 448 dev_priv->vbt.ddi_port_info[port].dp_boost_level) 449 iboost_bit = 1<<31; 450 } else if (IS_BROADWELL(dev)) { 451 ddi_translations_fdi = bdw_ddi_translations_fdi; 452 ddi_translations_dp = bdw_ddi_translations_dp; 453 ddi_translations_edp = bdw_ddi_translations_edp; 454 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 455 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 456 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 457 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 458 hdmi_default_entry = 7; 459 } else if (IS_HASWELL(dev)) { 460 ddi_translations_fdi = hsw_ddi_translations_fdi; 461 ddi_translations_dp = hsw_ddi_translations_dp; 462 ddi_translations_edp = hsw_ddi_translations_dp; 463 ddi_translations_hdmi = hsw_ddi_translations_hdmi; 464 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); 465 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); 466 hdmi_default_entry = 6; 467 } else { 468 WARN(1, "ddi translation table missing\n"); 469 ddi_translations_edp = bdw_ddi_translations_dp; 470 ddi_translations_fdi = bdw_ddi_translations_fdi; 471 ddi_translations_dp = bdw_ddi_translations_dp; 472 ddi_translations_hdmi = bdw_ddi_translations_hdmi; 473 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); 474 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); 475 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); 476 hdmi_default_entry = 7; 477 } 478 479 switch (port) { 480 case PORT_A: 481 ddi_translations = ddi_translations_edp; 482 size = n_edp_entries; 483 break; 484 case PORT_B: 485 case PORT_C: 486 ddi_translations = ddi_translations_dp; 487 size = n_dp_entries; 488 break; 489 case PORT_D: 490 if (intel_dp_is_edp(dev, PORT_D)) { 491 ddi_translations = ddi_translations_edp; 492 size = n_edp_entries; 493 } else { 494 ddi_translations = ddi_translations_dp; 495 size = n_dp_entries; 496 } 497 break; 498 case PORT_E: 499 if (ddi_translations_fdi) 500 ddi_translations = ddi_translations_fdi; 501 else 502 ddi_translations = ddi_translations_dp; 503 size = n_dp_entries; 504 break; 505 default: 506 BUG(); 507 } 508 509 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) { 510 I915_WRITE(reg, ddi_translations[i].trans1 | iboost_bit); 511 reg += 4; 512 I915_WRITE(reg, ddi_translations[i].trans2); 513 reg += 4; 514 } 515 516 if (!supports_hdmi) 517 return; 518 519 /* Choose a good default if VBT is badly populated */ 520 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || 521 hdmi_level >= n_hdmi_entries) 522 hdmi_level = hdmi_default_entry; 523 524 /* Entry 9 is for HDMI: */ 525 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit); 526 reg += 4; 527 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); 528 reg += 4; 529 } 530 531 /* Program DDI buffers translations for DP. By default, program ports A-D in DP 532 * mode and port E for FDI. 533 */ 534 void intel_prepare_ddi(struct drm_device *dev) 535 { 536 struct intel_encoder *intel_encoder; 537 bool visited[I915_MAX_PORTS] = { 0, }; 538 539 if (!HAS_DDI(dev)) 540 return; 541 542 for_each_intel_encoder(dev, intel_encoder) { 543 struct intel_digital_port *intel_dig_port; 544 enum port port; 545 bool supports_hdmi; 546 547 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); 548 549 if (visited[port]) 550 continue; 551 552 supports_hdmi = intel_dig_port && 553 intel_dig_port_supports_hdmi(intel_dig_port); 554 555 intel_prepare_ddi_buffers(dev, port, supports_hdmi); 556 visited[port] = true; 557 } 558 } 559 560 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, 561 enum port port) 562 { 563 uint32_t reg = DDI_BUF_CTL(port); 564 int i; 565 566 for (i = 0; i < 16; i++) { 567 udelay(1); 568 if (I915_READ(reg) & DDI_BUF_IS_IDLE) 569 return; 570 } 571 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); 572 } 573 574 /* Starting with Haswell, different DDI ports can work in FDI mode for 575 * connection to the PCH-located connectors. For this, it is necessary to train 576 * both the DDI port and PCH receiver for the desired DDI buffer settings. 577 * 578 * The recommended port to work in FDI mode is DDI E, which we use here. Also, 579 * please note that when FDI mode is active on DDI E, it shares 2 lines with 580 * DDI A (which is used for eDP) 581 */ 582 583 void hsw_fdi_link_train(struct drm_crtc *crtc) 584 { 585 struct drm_device *dev = crtc->dev; 586 struct drm_i915_private *dev_priv = dev->dev_private; 587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 588 u32 temp, i, rx_ctl_val; 589 590 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the 591 * mode set "sequence for CRT port" document: 592 * - TP1 to TP2 time with the default value 593 * - FDI delay to 90h 594 * 595 * WaFDIAutoLinkSetTimingOverrride:hsw 596 */ 597 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | 598 FDI_RX_PWRDN_LANE0_VAL(2) | 599 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); 600 601 /* Enable the PCH Receiver FDI PLL */ 602 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 603 FDI_RX_PLL_ENABLE | 604 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); 605 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 606 POSTING_READ(_FDI_RXA_CTL); 607 udelay(220); 608 609 /* Switch from Rawclk to PCDclk */ 610 rx_ctl_val |= FDI_PCDCLK; 611 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 612 613 /* Configure Port Clock Select */ 614 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); 615 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); 616 617 /* Start the training iterating through available voltages and emphasis, 618 * testing each value twice. */ 619 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { 620 /* Configure DP_TP_CTL with auto-training */ 621 I915_WRITE(DP_TP_CTL(PORT_E), 622 DP_TP_CTL_FDI_AUTOTRAIN | 623 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 624 DP_TP_CTL_LINK_TRAIN_PAT1 | 625 DP_TP_CTL_ENABLE); 626 627 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. 628 * DDI E does not support port reversal, the functionality is 629 * achieved on the PCH side in FDI_RX_CTL, so no need to set the 630 * port reversal bit */ 631 I915_WRITE(DDI_BUF_CTL(PORT_E), 632 DDI_BUF_CTL_ENABLE | 633 ((intel_crtc->config->fdi_lanes - 1) << 1) | 634 DDI_BUF_TRANS_SELECT(i / 2)); 635 POSTING_READ(DDI_BUF_CTL(PORT_E)); 636 637 udelay(600); 638 639 /* Program PCH FDI Receiver TU */ 640 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); 641 642 /* Enable PCH FDI Receiver with auto-training */ 643 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; 644 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 645 POSTING_READ(_FDI_RXA_CTL); 646 647 /* Wait for FDI receiver lane calibration */ 648 udelay(30); 649 650 /* Unset FDI_RX_MISC pwrdn lanes */ 651 temp = I915_READ(_FDI_RXA_MISC); 652 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 653 I915_WRITE(_FDI_RXA_MISC, temp); 654 POSTING_READ(_FDI_RXA_MISC); 655 656 /* Wait for FDI auto training time */ 657 udelay(5); 658 659 temp = I915_READ(DP_TP_STATUS(PORT_E)); 660 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { 661 DRM_DEBUG_KMS("FDI link training done on step %d\n", i); 662 663 /* Enable normal pixel sending for FDI */ 664 I915_WRITE(DP_TP_CTL(PORT_E), 665 DP_TP_CTL_FDI_AUTOTRAIN | 666 DP_TP_CTL_LINK_TRAIN_NORMAL | 667 DP_TP_CTL_ENHANCED_FRAME_ENABLE | 668 DP_TP_CTL_ENABLE); 669 670 return; 671 } 672 673 temp = I915_READ(DDI_BUF_CTL(PORT_E)); 674 temp &= ~DDI_BUF_CTL_ENABLE; 675 I915_WRITE(DDI_BUF_CTL(PORT_E), temp); 676 POSTING_READ(DDI_BUF_CTL(PORT_E)); 677 678 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ 679 temp = I915_READ(DP_TP_CTL(PORT_E)); 680 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 681 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 682 I915_WRITE(DP_TP_CTL(PORT_E), temp); 683 POSTING_READ(DP_TP_CTL(PORT_E)); 684 685 intel_wait_ddi_buf_idle(dev_priv, PORT_E); 686 687 rx_ctl_val &= ~FDI_RX_ENABLE; 688 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); 689 POSTING_READ(_FDI_RXA_CTL); 690 691 /* Reset FDI_RX_MISC pwrdn lanes */ 692 temp = I915_READ(_FDI_RXA_MISC); 693 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 694 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 695 I915_WRITE(_FDI_RXA_MISC, temp); 696 POSTING_READ(_FDI_RXA_MISC); 697 } 698 699 DRM_ERROR("FDI link training failed!\n"); 700 } 701 702 void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) 703 { 704 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 705 struct intel_digital_port *intel_dig_port = 706 enc_to_dig_port(&encoder->base); 707 708 intel_dp->DP = intel_dig_port->saved_port_bits | 709 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); 710 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); 711 712 } 713 714 static struct intel_encoder * 715 intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) 716 { 717 struct drm_device *dev = crtc->dev; 718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 719 struct intel_encoder *intel_encoder, *ret = NULL; 720 int num_encoders = 0; 721 722 for_each_encoder_on_crtc(dev, crtc, intel_encoder) { 723 ret = intel_encoder; 724 num_encoders++; 725 } 726 727 if (num_encoders != 1) 728 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, 729 pipe_name(intel_crtc->pipe)); 730 731 BUG_ON(ret == NULL); 732 return ret; 733 } 734 735 struct intel_encoder * 736 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) 737 { 738 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 739 struct intel_encoder *ret = NULL; 740 struct drm_atomic_state *state; 741 struct drm_connector *connector; 742 struct drm_connector_state *connector_state; 743 int num_encoders = 0; 744 int i; 745 746 state = crtc_state->base.state; 747 748 for_each_connector_in_state(state, connector, connector_state, i) { 749 if (connector_state->crtc != crtc_state->base.crtc) 750 continue; 751 752 ret = to_intel_encoder(connector_state->best_encoder); 753 num_encoders++; 754 } 755 756 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, 757 pipe_name(crtc->pipe)); 758 759 BUG_ON(ret == NULL); 760 return ret; 761 } 762 763 #define LC_FREQ 2700 764 #define LC_FREQ_2K U64_C(LC_FREQ * 2000) 765 766 #define P_MIN 2 767 #define P_MAX 64 768 #define P_INC 2 769 770 /* Constraints for PLL good behavior */ 771 #define REF_MIN 48 772 #define REF_MAX 400 773 #define VCO_MIN 2400 774 #define VCO_MAX 4800 775 776 #define abs_diff(a, b) ({ \ 777 typeof(a) __a = (a); \ 778 typeof(b) __b = (b); \ 779 (void) (&__a == &__b); \ 780 __a > __b ? (__a - __b) : (__b - __a); }) 781 782 struct hsw_wrpll_rnp { 783 unsigned p, n2, r2; 784 }; 785 786 static unsigned hsw_wrpll_get_budget_for_freq(int clock) 787 { 788 unsigned budget; 789 790 switch (clock) { 791 case 25175000: 792 case 25200000: 793 case 27000000: 794 case 27027000: 795 case 37762500: 796 case 37800000: 797 case 40500000: 798 case 40541000: 799 case 54000000: 800 case 54054000: 801 case 59341000: 802 case 59400000: 803 case 72000000: 804 case 74176000: 805 case 74250000: 806 case 81000000: 807 case 81081000: 808 case 89012000: 809 case 89100000: 810 case 108000000: 811 case 108108000: 812 case 111264000: 813 case 111375000: 814 case 148352000: 815 case 148500000: 816 case 162000000: 817 case 162162000: 818 case 222525000: 819 case 222750000: 820 case 296703000: 821 case 297000000: 822 budget = 0; 823 break; 824 case 233500000: 825 case 245250000: 826 case 247750000: 827 case 253250000: 828 case 298000000: 829 budget = 1500; 830 break; 831 case 169128000: 832 case 169500000: 833 case 179500000: 834 case 202000000: 835 budget = 2000; 836 break; 837 case 256250000: 838 case 262500000: 839 case 270000000: 840 case 272500000: 841 case 273750000: 842 case 280750000: 843 case 281250000: 844 case 286000000: 845 case 291750000: 846 budget = 4000; 847 break; 848 case 267250000: 849 case 268500000: 850 budget = 5000; 851 break; 852 default: 853 budget = 1000; 854 break; 855 } 856 857 return budget; 858 } 859 860 static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget, 861 unsigned r2, unsigned n2, unsigned p, 862 struct hsw_wrpll_rnp *best) 863 { 864 uint64_t a, b, c, d, diff, diff_best; 865 866 /* No best (r,n,p) yet */ 867 if (best->p == 0) { 868 best->p = p; 869 best->n2 = n2; 870 best->r2 = r2; 871 return; 872 } 873 874 /* 875 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to 876 * freq2k. 877 * 878 * delta = 1e6 * 879 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / 880 * freq2k; 881 * 882 * and we would like delta <= budget. 883 * 884 * If the discrepancy is above the PPM-based budget, always prefer to 885 * improve upon the previous solution. However, if you're within the 886 * budget, try to maximize Ref * VCO, that is N / (P * R^2). 887 */ 888 a = freq2k * budget * p * r2; 889 b = freq2k * budget * best->p * best->r2; 890 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); 891 diff_best = abs_diff(freq2k * best->p * best->r2, 892 LC_FREQ_2K * best->n2); 893 c = 1000000 * diff; 894 d = 1000000 * diff_best; 895 896 if (a < c && b < d) { 897 /* If both are above the budget, pick the closer */ 898 if (best->p * best->r2 * diff < p * r2 * diff_best) { 899 best->p = p; 900 best->n2 = n2; 901 best->r2 = r2; 902 } 903 } else if (a >= c && b < d) { 904 /* If A is below the threshold but B is above it? Update. */ 905 best->p = p; 906 best->n2 = n2; 907 best->r2 = r2; 908 } else if (a >= c && b >= d) { 909 /* Both are below the limit, so pick the higher n2/(r2*r2) */ 910 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { 911 best->p = p; 912 best->n2 = n2; 913 best->r2 = r2; 914 } 915 } 916 /* Otherwise a < c && b >= d, do nothing */ 917 } 918 919 static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg) 920 { 921 int refclk = LC_FREQ; 922 int n, p, r; 923 u32 wrpll; 924 925 wrpll = I915_READ(reg); 926 switch (wrpll & WRPLL_PLL_REF_MASK) { 927 case WRPLL_PLL_SSC: 928 case WRPLL_PLL_NON_SSC: 929 /* 930 * We could calculate spread here, but our checking 931 * code only cares about 5% accuracy, and spread is a max of 932 * 0.5% downspread. 933 */ 934 refclk = 135; 935 break; 936 case WRPLL_PLL_LCPLL: 937 refclk = LC_FREQ; 938 break; 939 default: 940 WARN(1, "bad wrpll refclk\n"); 941 return 0; 942 } 943 944 r = wrpll & WRPLL_DIVIDER_REF_MASK; 945 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; 946 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; 947 948 /* Convert to KHz, p & r have a fixed point portion */ 949 return (refclk * n * 100) / (p * r); 950 } 951 952 static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, 953 uint32_t dpll) 954 { 955 uint32_t cfgcr1_reg, cfgcr2_reg; 956 uint32_t cfgcr1_val, cfgcr2_val; 957 uint32_t p0, p1, p2, dco_freq; 958 959 cfgcr1_reg = GET_CFG_CR1_REG(dpll); 960 cfgcr2_reg = GET_CFG_CR2_REG(dpll); 961 962 cfgcr1_val = I915_READ(cfgcr1_reg); 963 cfgcr2_val = I915_READ(cfgcr2_reg); 964 965 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; 966 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; 967 968 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) 969 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; 970 else 971 p1 = 1; 972 973 974 switch (p0) { 975 case DPLL_CFGCR2_PDIV_1: 976 p0 = 1; 977 break; 978 case DPLL_CFGCR2_PDIV_2: 979 p0 = 2; 980 break; 981 case DPLL_CFGCR2_PDIV_3: 982 p0 = 3; 983 break; 984 case DPLL_CFGCR2_PDIV_7: 985 p0 = 7; 986 break; 987 } 988 989 switch (p2) { 990 case DPLL_CFGCR2_KDIV_5: 991 p2 = 5; 992 break; 993 case DPLL_CFGCR2_KDIV_2: 994 p2 = 2; 995 break; 996 case DPLL_CFGCR2_KDIV_3: 997 p2 = 3; 998 break; 999 case DPLL_CFGCR2_KDIV_1: 1000 p2 = 1; 1001 break; 1002 } 1003 1004 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; 1005 1006 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * 1007 1000) / 0x8000; 1008 1009 return dco_freq / (p0 * p1 * p2 * 5); 1010 } 1011 1012 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) 1013 { 1014 int dotclock; 1015 1016 if (pipe_config->has_pch_encoder) 1017 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1018 &pipe_config->fdi_m_n); 1019 else if (pipe_config->has_dp_encoder) 1020 dotclock = intel_dotclock_calculate(pipe_config->port_clock, 1021 &pipe_config->dp_m_n); 1022 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36) 1023 dotclock = pipe_config->port_clock * 2 / 3; 1024 else 1025 dotclock = pipe_config->port_clock; 1026 1027 if (pipe_config->pixel_multiplier) 1028 dotclock /= pipe_config->pixel_multiplier; 1029 1030 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 1031 } 1032 1033 static void skl_ddi_clock_get(struct intel_encoder *encoder, 1034 struct intel_crtc_state *pipe_config) 1035 { 1036 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1037 int link_clock = 0; 1038 uint32_t dpll_ctl1, dpll; 1039 1040 dpll = pipe_config->ddi_pll_sel; 1041 1042 dpll_ctl1 = I915_READ(DPLL_CTRL1); 1043 1044 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { 1045 link_clock = skl_calc_wrpll_link(dev_priv, dpll); 1046 } else { 1047 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); 1048 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); 1049 1050 switch (link_clock) { 1051 case DPLL_CTRL1_LINK_RATE_810: 1052 link_clock = 81000; 1053 break; 1054 case DPLL_CTRL1_LINK_RATE_1080: 1055 link_clock = 108000; 1056 break; 1057 case DPLL_CTRL1_LINK_RATE_1350: 1058 link_clock = 135000; 1059 break; 1060 case DPLL_CTRL1_LINK_RATE_1620: 1061 link_clock = 162000; 1062 break; 1063 case DPLL_CTRL1_LINK_RATE_2160: 1064 link_clock = 216000; 1065 break; 1066 case DPLL_CTRL1_LINK_RATE_2700: 1067 link_clock = 270000; 1068 break; 1069 default: 1070 WARN(1, "Unsupported link rate\n"); 1071 break; 1072 } 1073 link_clock *= 2; 1074 } 1075 1076 pipe_config->port_clock = link_clock; 1077 1078 ddi_dotclock_get(pipe_config); 1079 } 1080 1081 static void hsw_ddi_clock_get(struct intel_encoder *encoder, 1082 struct intel_crtc_state *pipe_config) 1083 { 1084 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1085 int link_clock = 0; 1086 u32 val, pll; 1087 1088 val = pipe_config->ddi_pll_sel; 1089 switch (val & PORT_CLK_SEL_MASK) { 1090 case PORT_CLK_SEL_LCPLL_810: 1091 link_clock = 81000; 1092 break; 1093 case PORT_CLK_SEL_LCPLL_1350: 1094 link_clock = 135000; 1095 break; 1096 case PORT_CLK_SEL_LCPLL_2700: 1097 link_clock = 270000; 1098 break; 1099 case PORT_CLK_SEL_WRPLL1: 1100 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); 1101 break; 1102 case PORT_CLK_SEL_WRPLL2: 1103 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); 1104 break; 1105 case PORT_CLK_SEL_SPLL: 1106 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; 1107 if (pll == SPLL_PLL_FREQ_810MHz) 1108 link_clock = 81000; 1109 else if (pll == SPLL_PLL_FREQ_1350MHz) 1110 link_clock = 135000; 1111 else if (pll == SPLL_PLL_FREQ_2700MHz) 1112 link_clock = 270000; 1113 else { 1114 WARN(1, "bad spll freq\n"); 1115 return; 1116 } 1117 break; 1118 default: 1119 WARN(1, "bad port clock sel\n"); 1120 return; 1121 } 1122 1123 pipe_config->port_clock = link_clock * 2; 1124 1125 ddi_dotclock_get(pipe_config); 1126 } 1127 1128 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, 1129 enum intel_dpll_id dpll) 1130 { 1131 struct intel_shared_dpll *pll; 1132 struct intel_dpll_hw_state *state; 1133 intel_clock_t clock; 1134 1135 /* For DDI ports we always use a shared PLL. */ 1136 if (WARN_ON(dpll == DPLL_ID_PRIVATE)) 1137 return 0; 1138 1139 pll = &dev_priv->shared_dplls[dpll]; 1140 state = &pll->config.hw_state; 1141 1142 clock.m1 = 2; 1143 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22; 1144 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE) 1145 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK; 1146 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT; 1147 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT; 1148 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT; 1149 1150 return chv_calc_dpll_params(100000, &clock); 1151 } 1152 1153 static void bxt_ddi_clock_get(struct intel_encoder *encoder, 1154 struct intel_crtc_state *pipe_config) 1155 { 1156 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1157 enum port port = intel_ddi_get_encoder_port(encoder); 1158 uint32_t dpll = port; 1159 1160 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll); 1161 1162 ddi_dotclock_get(pipe_config); 1163 } 1164 1165 void intel_ddi_clock_get(struct intel_encoder *encoder, 1166 struct intel_crtc_state *pipe_config) 1167 { 1168 struct drm_device *dev = encoder->base.dev; 1169 1170 if (INTEL_INFO(dev)->gen <= 8) 1171 hsw_ddi_clock_get(encoder, pipe_config); 1172 else if (IS_SKYLAKE(dev)) 1173 skl_ddi_clock_get(encoder, pipe_config); 1174 else if (IS_BROXTON(dev)) 1175 bxt_ddi_clock_get(encoder, pipe_config); 1176 } 1177 1178 static void 1179 hsw_ddi_calculate_wrpll(int clock /* in Hz */, 1180 unsigned *r2_out, unsigned *n2_out, unsigned *p_out) 1181 { 1182 uint64_t freq2k; 1183 unsigned p, n2, r2; 1184 struct hsw_wrpll_rnp best = { 0, 0, 0 }; 1185 unsigned budget; 1186 1187 freq2k = clock / 100; 1188 1189 budget = hsw_wrpll_get_budget_for_freq(clock); 1190 1191 /* Special case handling for 540 pixel clock: bypass WR PLL entirely 1192 * and directly pass the LC PLL to it. */ 1193 if (freq2k == 5400000) { 1194 *n2_out = 2; 1195 *p_out = 1; 1196 *r2_out = 2; 1197 return; 1198 } 1199 1200 /* 1201 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by 1202 * the WR PLL. 1203 * 1204 * We want R so that REF_MIN <= Ref <= REF_MAX. 1205 * Injecting R2 = 2 * R gives: 1206 * REF_MAX * r2 > LC_FREQ * 2 and 1207 * REF_MIN * r2 < LC_FREQ * 2 1208 * 1209 * Which means the desired boundaries for r2 are: 1210 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN 1211 * 1212 */ 1213 for (r2 = LC_FREQ * 2 / REF_MAX + 1; 1214 r2 <= LC_FREQ * 2 / REF_MIN; 1215 r2++) { 1216 1217 /* 1218 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R 1219 * 1220 * Once again we want VCO_MIN <= VCO <= VCO_MAX. 1221 * Injecting R2 = 2 * R and N2 = 2 * N, we get: 1222 * VCO_MAX * r2 > n2 * LC_FREQ and 1223 * VCO_MIN * r2 < n2 * LC_FREQ) 1224 * 1225 * Which means the desired boundaries for n2 are: 1226 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ 1227 */ 1228 for (n2 = VCO_MIN * r2 / LC_FREQ + 1; 1229 n2 <= VCO_MAX * r2 / LC_FREQ; 1230 n2++) { 1231 1232 for (p = P_MIN; p <= P_MAX; p += P_INC) 1233 hsw_wrpll_update_rnp(freq2k, budget, 1234 r2, n2, p, &best); 1235 } 1236 } 1237 1238 *n2_out = best.n2; 1239 *p_out = best.p; 1240 *r2_out = best.r2; 1241 } 1242 1243 static bool 1244 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, 1245 struct intel_crtc_state *crtc_state, 1246 struct intel_encoder *intel_encoder, 1247 int clock) 1248 { 1249 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1250 struct intel_shared_dpll *pll; 1251 uint32_t val; 1252 unsigned p, n2, r2; 1253 1254 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 1255 1256 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | 1257 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 1258 WRPLL_DIVIDER_POST(p); 1259 1260 memset(&crtc_state->dpll_hw_state, 0, 1261 sizeof(crtc_state->dpll_hw_state)); 1262 1263 crtc_state->dpll_hw_state.wrpll = val; 1264 1265 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1266 if (pll == NULL) { 1267 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1268 pipe_name(intel_crtc->pipe)); 1269 return false; 1270 } 1271 1272 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); 1273 } 1274 1275 return true; 1276 } 1277 1278 struct skl_wrpll_context { 1279 uint64_t min_deviation; /* current minimal deviation */ 1280 uint64_t central_freq; /* chosen central freq */ 1281 uint64_t dco_freq; /* chosen dco freq */ 1282 unsigned int p; /* chosen divider */ 1283 }; 1284 1285 static void skl_wrpll_context_init(struct skl_wrpll_context *ctx) 1286 { 1287 memset(ctx, 0, sizeof(*ctx)); 1288 1289 ctx->min_deviation = U64_MAX; 1290 } 1291 1292 /* DCO freq must be within +1%/-6% of the DCO central freq */ 1293 #define SKL_DCO_MAX_PDEVIATION 100 1294 #define SKL_DCO_MAX_NDEVIATION 600 1295 1296 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx, 1297 uint64_t central_freq, 1298 uint64_t dco_freq, 1299 unsigned int divider) 1300 { 1301 uint64_t deviation; 1302 1303 deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq), 1304 central_freq); 1305 1306 /* positive deviation */ 1307 if (dco_freq >= central_freq) { 1308 if (deviation < SKL_DCO_MAX_PDEVIATION && 1309 deviation < ctx->min_deviation) { 1310 ctx->min_deviation = deviation; 1311 ctx->central_freq = central_freq; 1312 ctx->dco_freq = dco_freq; 1313 ctx->p = divider; 1314 } 1315 /* negative deviation */ 1316 } else if (deviation < SKL_DCO_MAX_NDEVIATION && 1317 deviation < ctx->min_deviation) { 1318 ctx->min_deviation = deviation; 1319 ctx->central_freq = central_freq; 1320 ctx->dco_freq = dco_freq; 1321 ctx->p = divider; 1322 } 1323 } 1324 1325 static void skl_wrpll_get_multipliers(unsigned int p, 1326 unsigned int *p0 /* out */, 1327 unsigned int *p1 /* out */, 1328 unsigned int *p2 /* out */) 1329 { 1330 /* even dividers */ 1331 if (p % 2 == 0) { 1332 unsigned int half = p / 2; 1333 1334 if (half == 1 || half == 2 || half == 3 || half == 5) { 1335 *p0 = 2; 1336 *p1 = 1; 1337 *p2 = half; 1338 } else if (half % 2 == 0) { 1339 *p0 = 2; 1340 *p1 = half / 2; 1341 *p2 = 2; 1342 } else if (half % 3 == 0) { 1343 *p0 = 3; 1344 *p1 = half / 3; 1345 *p2 = 2; 1346 } else if (half % 7 == 0) { 1347 *p0 = 7; 1348 *p1 = half / 7; 1349 *p2 = 2; 1350 } 1351 } else if (p == 3 || p == 9) { /* 3, 5, 7, 9, 15, 21, 35 */ 1352 *p0 = 3; 1353 *p1 = 1; 1354 *p2 = p / 3; 1355 } else if (p == 5 || p == 7) { 1356 *p0 = p; 1357 *p1 = 1; 1358 *p2 = 1; 1359 } else if (p == 15) { 1360 *p0 = 3; 1361 *p1 = 1; 1362 *p2 = 5; 1363 } else if (p == 21) { 1364 *p0 = 7; 1365 *p1 = 1; 1366 *p2 = 3; 1367 } else if (p == 35) { 1368 *p0 = 7; 1369 *p1 = 1; 1370 *p2 = 5; 1371 } 1372 } 1373 1374 struct skl_wrpll_params { 1375 uint32_t dco_fraction; 1376 uint32_t dco_integer; 1377 uint32_t qdiv_ratio; 1378 uint32_t qdiv_mode; 1379 uint32_t kdiv; 1380 uint32_t pdiv; 1381 uint32_t central_freq; 1382 }; 1383 1384 static void skl_wrpll_params_populate(struct skl_wrpll_params *params, 1385 uint64_t afe_clock, 1386 uint64_t central_freq, 1387 uint32_t p0, uint32_t p1, uint32_t p2) 1388 { 1389 uint64_t dco_freq; 1390 1391 switch (central_freq) { 1392 case 9600000000ULL: 1393 params->central_freq = 0; 1394 break; 1395 case 9000000000ULL: 1396 params->central_freq = 1; 1397 break; 1398 case 8400000000ULL: 1399 params->central_freq = 3; 1400 } 1401 1402 switch (p0) { 1403 case 1: 1404 params->pdiv = 0; 1405 break; 1406 case 2: 1407 params->pdiv = 1; 1408 break; 1409 case 3: 1410 params->pdiv = 2; 1411 break; 1412 case 7: 1413 params->pdiv = 4; 1414 break; 1415 default: 1416 WARN(1, "Incorrect PDiv\n"); 1417 } 1418 1419 switch (p2) { 1420 case 5: 1421 params->kdiv = 0; 1422 break; 1423 case 2: 1424 params->kdiv = 1; 1425 break; 1426 case 3: 1427 params->kdiv = 2; 1428 break; 1429 case 1: 1430 params->kdiv = 3; 1431 break; 1432 default: 1433 WARN(1, "Incorrect KDiv\n"); 1434 } 1435 1436 params->qdiv_ratio = p1; 1437 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1; 1438 1439 dco_freq = p0 * p1 * p2 * afe_clock; 1440 1441 /* 1442 * Intermediate values are in Hz. 1443 * Divide by MHz to match bsepc 1444 */ 1445 params->dco_integer = div_u64(dco_freq, 24 * MHz(1)); 1446 params->dco_fraction = 1447 div_u64((div_u64(dco_freq, 24) - 1448 params->dco_integer * MHz(1)) * 0x8000, MHz(1)); 1449 } 1450 1451 static bool 1452 skl_ddi_calculate_wrpll(int clock /* in Hz */, 1453 struct skl_wrpll_params *wrpll_params) 1454 { 1455 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ 1456 uint64_t dco_central_freq[3] = {8400000000ULL, 1457 9000000000ULL, 1458 9600000000ULL}; 1459 static const int even_dividers[] = { 4, 6, 8, 10, 12, 14, 16, 18, 20, 1460 24, 28, 30, 32, 36, 40, 42, 44, 1461 48, 52, 54, 56, 60, 64, 66, 68, 1462 70, 72, 76, 78, 80, 84, 88, 90, 1463 92, 96, 98 }; 1464 static const int odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 }; 1465 static const struct { 1466 const int *list; 1467 int n_dividers; 1468 } dividers[] = { 1469 { even_dividers, ARRAY_SIZE(even_dividers) }, 1470 { odd_dividers, ARRAY_SIZE(odd_dividers) }, 1471 }; 1472 struct skl_wrpll_context ctx; 1473 unsigned int dco, d, i; 1474 unsigned int p0, p1, p2; 1475 1476 skl_wrpll_context_init(&ctx); 1477 1478 for (d = 0; d < ARRAY_SIZE(dividers); d++) { 1479 for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) { 1480 for (i = 0; i < dividers[d].n_dividers; i++) { 1481 unsigned int p = dividers[d].list[i]; 1482 uint64_t dco_freq = p * afe_clock; 1483 1484 skl_wrpll_try_divider(&ctx, 1485 dco_central_freq[dco], 1486 dco_freq, 1487 p); 1488 /* 1489 * Skip the remaining dividers if we're sure to 1490 * have found the definitive divider, we can't 1491 * improve a 0 deviation. 1492 */ 1493 if (ctx.min_deviation == 0) 1494 goto skip_remaining_dividers; 1495 } 1496 } 1497 1498 skip_remaining_dividers: 1499 /* 1500 * If a solution is found with an even divider, prefer 1501 * this one. 1502 */ 1503 if (d == 0 && ctx.p) 1504 break; 1505 } 1506 1507 if (!ctx.p) { 1508 DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock); 1509 return false; 1510 } 1511 1512 /* 1513 * gcc incorrectly analyses that these can be used without being 1514 * initialized. To be fair, it's hard to guess. 1515 */ 1516 p0 = p1 = p2 = 0; 1517 skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2); 1518 skl_wrpll_params_populate(wrpll_params, afe_clock, ctx.central_freq, 1519 p0, p1, p2); 1520 1521 return true; 1522 } 1523 1524 static bool 1525 skl_ddi_pll_select(struct intel_crtc *intel_crtc, 1526 struct intel_crtc_state *crtc_state, 1527 struct intel_encoder *intel_encoder, 1528 int clock) 1529 { 1530 struct intel_shared_dpll *pll; 1531 uint32_t ctrl1, cfgcr1, cfgcr2; 1532 1533 /* 1534 * See comment in intel_dpll_hw_state to understand why we always use 0 1535 * as the DPLL id in this function. 1536 */ 1537 1538 ctrl1 = DPLL_CTRL1_OVERRIDE(0); 1539 1540 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1541 struct skl_wrpll_params wrpll_params = { 0, }; 1542 1543 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); 1544 1545 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params)) 1546 return false; 1547 1548 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | 1549 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | 1550 wrpll_params.dco_integer; 1551 1552 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | 1553 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | 1554 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | 1555 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | 1556 wrpll_params.central_freq; 1557 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { 1558 switch (crtc_state->port_clock / 2) { 1559 case 81000: 1560 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); 1561 break; 1562 case 135000: 1563 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); 1564 break; 1565 case 270000: 1566 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); 1567 break; 1568 } 1569 1570 cfgcr1 = cfgcr2 = 0; 1571 } else /* eDP */ 1572 return true; 1573 1574 memset(&crtc_state->dpll_hw_state, 0, 1575 sizeof(crtc_state->dpll_hw_state)); 1576 1577 crtc_state->dpll_hw_state.ctrl1 = ctrl1; 1578 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; 1579 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; 1580 1581 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1582 if (pll == NULL) { 1583 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1584 pipe_name(intel_crtc->pipe)); 1585 return false; 1586 } 1587 1588 /* shared DPLL id 0 is DPLL 1 */ 1589 crtc_state->ddi_pll_sel = pll->id + 1; 1590 1591 return true; 1592 } 1593 1594 /* bxt clock parameters */ 1595 struct bxt_clk_div { 1596 int clock; 1597 uint32_t p1; 1598 uint32_t p2; 1599 uint32_t m2_int; 1600 uint32_t m2_frac; 1601 bool m2_frac_en; 1602 uint32_t n; 1603 }; 1604 1605 /* pre-calculated values for DP linkrates */ 1606 static const struct bxt_clk_div bxt_dp_clk_val[] = { 1607 {162000, 4, 2, 32, 1677722, 1, 1}, 1608 {270000, 4, 1, 27, 0, 0, 1}, 1609 {540000, 2, 1, 27, 0, 0, 1}, 1610 {216000, 3, 2, 32, 1677722, 1, 1}, 1611 {243000, 4, 1, 24, 1258291, 1, 1}, 1612 {324000, 4, 1, 32, 1677722, 1, 1}, 1613 {432000, 3, 1, 32, 1677722, 1, 1} 1614 }; 1615 1616 static bool 1617 bxt_ddi_pll_select(struct intel_crtc *intel_crtc, 1618 struct intel_crtc_state *crtc_state, 1619 struct intel_encoder *intel_encoder, 1620 int clock) 1621 { 1622 struct intel_shared_dpll *pll; 1623 struct bxt_clk_div clk_div = {0}; 1624 int vco = 0; 1625 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; 1626 uint32_t lanestagger; 1627 1628 if (intel_encoder->type == INTEL_OUTPUT_HDMI) { 1629 intel_clock_t best_clock; 1630 1631 /* Calculate HDMI div */ 1632 /* 1633 * FIXME: tie the following calculation into 1634 * i9xx_crtc_compute_clock 1635 */ 1636 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { 1637 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", 1638 clock, pipe_name(intel_crtc->pipe)); 1639 return false; 1640 } 1641 1642 clk_div.p1 = best_clock.p1; 1643 clk_div.p2 = best_clock.p2; 1644 WARN_ON(best_clock.m1 != 2); 1645 clk_div.n = best_clock.n; 1646 clk_div.m2_int = best_clock.m2 >> 22; 1647 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); 1648 clk_div.m2_frac_en = clk_div.m2_frac != 0; 1649 1650 vco = best_clock.vco; 1651 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || 1652 intel_encoder->type == INTEL_OUTPUT_EDP) { 1653 int i; 1654 1655 clk_div = bxt_dp_clk_val[0]; 1656 for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) { 1657 if (bxt_dp_clk_val[i].clock == clock) { 1658 clk_div = bxt_dp_clk_val[i]; 1659 break; 1660 } 1661 } 1662 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2; 1663 } 1664 1665 if (vco >= 6200000 && vco <= 6700000) { 1666 prop_coef = 4; 1667 int_coef = 9; 1668 gain_ctl = 3; 1669 targ_cnt = 8; 1670 } else if ((vco > 5400000 && vco < 6200000) || 1671 (vco >= 4800000 && vco < 5400000)) { 1672 prop_coef = 5; 1673 int_coef = 11; 1674 gain_ctl = 3; 1675 targ_cnt = 9; 1676 } else if (vco == 5400000) { 1677 prop_coef = 3; 1678 int_coef = 8; 1679 gain_ctl = 1; 1680 targ_cnt = 9; 1681 } else { 1682 DRM_ERROR("Invalid VCO\n"); 1683 return false; 1684 } 1685 1686 memset(&crtc_state->dpll_hw_state, 0, 1687 sizeof(crtc_state->dpll_hw_state)); 1688 1689 if (clock > 270000) 1690 lanestagger = 0x18; 1691 else if (clock > 135000) 1692 lanestagger = 0x0d; 1693 else if (clock > 67000) 1694 lanestagger = 0x07; 1695 else if (clock > 33000) 1696 lanestagger = 0x04; 1697 else 1698 lanestagger = 0x02; 1699 1700 crtc_state->dpll_hw_state.ebb0 = 1701 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); 1702 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; 1703 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); 1704 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; 1705 1706 if (clk_div.m2_frac_en) 1707 crtc_state->dpll_hw_state.pll3 = 1708 PORT_PLL_M2_FRAC_ENABLE; 1709 1710 crtc_state->dpll_hw_state.pll6 = 1711 prop_coef | PORT_PLL_INT_COEFF(int_coef); 1712 crtc_state->dpll_hw_state.pll6 |= 1713 PORT_PLL_GAIN_CTL(gain_ctl); 1714 1715 crtc_state->dpll_hw_state.pll8 = targ_cnt; 1716 1717 crtc_state->dpll_hw_state.pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; 1718 1719 crtc_state->dpll_hw_state.pll10 = 1720 PORT_PLL_DCO_AMP(PORT_PLL_DCO_AMP_DEFAULT) 1721 | PORT_PLL_DCO_AMP_OVR_EN_H; 1722 1723 crtc_state->dpll_hw_state.ebb4 = PORT_PLL_10BIT_CLK_ENABLE; 1724 1725 crtc_state->dpll_hw_state.pcsdw12 = 1726 LANESTAGGER_STRAP_OVRD | lanestagger; 1727 1728 pll = intel_get_shared_dpll(intel_crtc, crtc_state); 1729 if (pll == NULL) { 1730 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", 1731 pipe_name(intel_crtc->pipe)); 1732 return false; 1733 } 1734 1735 /* shared DPLL id 0 is DPLL A */ 1736 crtc_state->ddi_pll_sel = pll->id; 1737 1738 return true; 1739 } 1740 1741 /* 1742 * Tries to find a *shared* PLL for the CRTC and store it in 1743 * intel_crtc->ddi_pll_sel. 1744 * 1745 * For private DPLLs, compute_config() should do the selection for us. This 1746 * function should be folded into compute_config() eventually. 1747 */ 1748 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, 1749 struct intel_crtc_state *crtc_state) 1750 { 1751 struct drm_device *dev = intel_crtc->base.dev; 1752 struct intel_encoder *intel_encoder = 1753 intel_ddi_get_crtc_new_encoder(crtc_state); 1754 int clock = crtc_state->port_clock; 1755 1756 if (IS_SKYLAKE(dev)) 1757 return skl_ddi_pll_select(intel_crtc, crtc_state, 1758 intel_encoder, clock); 1759 else if (IS_BROXTON(dev)) 1760 return bxt_ddi_pll_select(intel_crtc, crtc_state, 1761 intel_encoder, clock); 1762 else 1763 return hsw_ddi_pll_select(intel_crtc, crtc_state, 1764 intel_encoder, clock); 1765 } 1766 1767 void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) 1768 { 1769 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1771 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1772 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1773 int type = intel_encoder->type; 1774 uint32_t temp; 1775 1776 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { 1777 temp = TRANS_MSA_SYNC_CLK; 1778 switch (intel_crtc->config->pipe_bpp) { 1779 case 18: 1780 temp |= TRANS_MSA_6_BPC; 1781 break; 1782 case 24: 1783 temp |= TRANS_MSA_8_BPC; 1784 break; 1785 case 30: 1786 temp |= TRANS_MSA_10_BPC; 1787 break; 1788 case 36: 1789 temp |= TRANS_MSA_12_BPC; 1790 break; 1791 default: 1792 BUG(); 1793 } 1794 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); 1795 } 1796 } 1797 1798 void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) 1799 { 1800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1801 struct drm_device *dev = crtc->dev; 1802 struct drm_i915_private *dev_priv = dev->dev_private; 1803 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1804 uint32_t temp; 1805 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1806 if (state == true) 1807 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1808 else 1809 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 1810 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1811 } 1812 1813 void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) 1814 { 1815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 1816 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 1817 struct drm_encoder *encoder = &intel_encoder->base; 1818 struct drm_device *dev = crtc->dev; 1819 struct drm_i915_private *dev_priv = dev->dev_private; 1820 enum i915_pipe pipe = intel_crtc->pipe; 1821 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 1822 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1823 int type = intel_encoder->type; 1824 uint32_t temp; 1825 1826 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ 1827 temp = TRANS_DDI_FUNC_ENABLE; 1828 temp |= TRANS_DDI_SELECT_PORT(port); 1829 1830 switch (intel_crtc->config->pipe_bpp) { 1831 case 18: 1832 temp |= TRANS_DDI_BPC_6; 1833 break; 1834 case 24: 1835 temp |= TRANS_DDI_BPC_8; 1836 break; 1837 case 30: 1838 temp |= TRANS_DDI_BPC_10; 1839 break; 1840 case 36: 1841 temp |= TRANS_DDI_BPC_12; 1842 break; 1843 default: 1844 BUG(); 1845 } 1846 1847 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) 1848 temp |= TRANS_DDI_PVSYNC; 1849 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) 1850 temp |= TRANS_DDI_PHSYNC; 1851 1852 if (cpu_transcoder == TRANSCODER_EDP) { 1853 switch (pipe) { 1854 case PIPE_A: 1855 /* On Haswell, can only use the always-on power well for 1856 * eDP when not using the panel fitter, and when not 1857 * using motion blur mitigation (which we don't 1858 * support). */ 1859 if (IS_HASWELL(dev) && 1860 (intel_crtc->config->pch_pfit.enabled || 1861 intel_crtc->config->pch_pfit.force_thru)) 1862 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; 1863 else 1864 temp |= TRANS_DDI_EDP_INPUT_A_ON; 1865 break; 1866 case PIPE_B: 1867 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 1868 break; 1869 case PIPE_C: 1870 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 1871 break; 1872 default: 1873 BUG(); 1874 break; 1875 } 1876 } 1877 1878 if (type == INTEL_OUTPUT_HDMI) { 1879 if (intel_crtc->config->has_hdmi_sink) 1880 temp |= TRANS_DDI_MODE_SELECT_HDMI; 1881 else 1882 temp |= TRANS_DDI_MODE_SELECT_DVI; 1883 1884 } else if (type == INTEL_OUTPUT_ANALOG) { 1885 temp |= TRANS_DDI_MODE_SELECT_FDI; 1886 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; 1887 1888 } else if (type == INTEL_OUTPUT_DISPLAYPORT || 1889 type == INTEL_OUTPUT_EDP) { 1890 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1891 1892 if (intel_dp->is_mst) { 1893 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1894 } else 1895 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1896 1897 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 1898 } else if (type == INTEL_OUTPUT_DP_MST) { 1899 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; 1900 1901 if (intel_dp->is_mst) { 1902 temp |= TRANS_DDI_MODE_SELECT_DP_MST; 1903 } else 1904 temp |= TRANS_DDI_MODE_SELECT_DP_SST; 1905 1906 temp |= DDI_PORT_WIDTH(intel_dp->lane_count); 1907 } else { 1908 WARN(1, "Invalid encoder type %d for pipe %c\n", 1909 intel_encoder->type, pipe_name(pipe)); 1910 } 1911 1912 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); 1913 } 1914 1915 void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, 1916 enum transcoder cpu_transcoder) 1917 { 1918 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); 1919 uint32_t val = I915_READ(reg); 1920 1921 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 1922 val |= TRANS_DDI_PORT_NONE; 1923 I915_WRITE(reg, val); 1924 } 1925 1926 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) 1927 { 1928 struct drm_device *dev = intel_connector->base.dev; 1929 struct drm_i915_private *dev_priv = dev->dev_private; 1930 struct intel_encoder *intel_encoder = intel_connector->encoder; 1931 int type = intel_connector->base.connector_type; 1932 enum port port = intel_ddi_get_encoder_port(intel_encoder); 1933 enum i915_pipe pipe = 0; 1934 enum transcoder cpu_transcoder; 1935 enum intel_display_power_domain power_domain; 1936 uint32_t tmp; 1937 1938 power_domain = intel_display_port_power_domain(intel_encoder); 1939 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1940 return false; 1941 1942 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) 1943 return false; 1944 1945 if (port == PORT_A) 1946 cpu_transcoder = TRANSCODER_EDP; 1947 else 1948 cpu_transcoder = (enum transcoder) pipe; 1949 1950 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 1951 1952 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { 1953 case TRANS_DDI_MODE_SELECT_HDMI: 1954 case TRANS_DDI_MODE_SELECT_DVI: 1955 return (type == DRM_MODE_CONNECTOR_HDMIA); 1956 1957 case TRANS_DDI_MODE_SELECT_DP_SST: 1958 if (type == DRM_MODE_CONNECTOR_eDP) 1959 return true; 1960 return (type == DRM_MODE_CONNECTOR_DisplayPort); 1961 case TRANS_DDI_MODE_SELECT_DP_MST: 1962 /* if the transcoder is in MST state then 1963 * connector isn't connected */ 1964 return false; 1965 1966 case TRANS_DDI_MODE_SELECT_FDI: 1967 return (type == DRM_MODE_CONNECTOR_VGA); 1968 1969 default: 1970 return false; 1971 } 1972 } 1973 1974 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, 1975 enum i915_pipe *pipe) 1976 { 1977 struct drm_device *dev = encoder->base.dev; 1978 struct drm_i915_private *dev_priv = dev->dev_private; 1979 enum port port = intel_ddi_get_encoder_port(encoder); 1980 enum intel_display_power_domain power_domain; 1981 u32 tmp; 1982 int i; 1983 1984 power_domain = intel_display_port_power_domain(encoder); 1985 if (!intel_display_power_is_enabled(dev_priv, power_domain)) 1986 return false; 1987 1988 tmp = I915_READ(DDI_BUF_CTL(port)); 1989 1990 if (!(tmp & DDI_BUF_CTL_ENABLE)) 1991 return false; 1992 1993 if (port == PORT_A) { 1994 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); 1995 1996 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1997 case TRANS_DDI_EDP_INPUT_A_ON: 1998 case TRANS_DDI_EDP_INPUT_A_ONOFF: 1999 *pipe = PIPE_A; 2000 break; 2001 case TRANS_DDI_EDP_INPUT_B_ONOFF: 2002 *pipe = PIPE_B; 2003 break; 2004 case TRANS_DDI_EDP_INPUT_C_ONOFF: 2005 *pipe = PIPE_C; 2006 break; 2007 } 2008 2009 return true; 2010 } else { 2011 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { 2012 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); 2013 2014 if ((tmp & TRANS_DDI_PORT_MASK) 2015 == TRANS_DDI_SELECT_PORT(port)) { 2016 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) 2017 return false; 2018 2019 *pipe = i; 2020 return true; 2021 } 2022 } 2023 } 2024 2025 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); 2026 2027 return false; 2028 } 2029 2030 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) 2031 { 2032 struct drm_crtc *crtc = &intel_crtc->base; 2033 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 2034 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2035 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2036 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2037 2038 if (cpu_transcoder != TRANSCODER_EDP) 2039 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2040 TRANS_CLK_SEL_PORT(port)); 2041 } 2042 2043 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) 2044 { 2045 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; 2046 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; 2047 2048 if (cpu_transcoder != TRANSCODER_EDP) 2049 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), 2050 TRANS_CLK_SEL_DISABLED); 2051 } 2052 2053 static void skl_ddi_set_iboost(struct drm_device *dev, u32 level, 2054 enum port port, int type) 2055 { 2056 struct drm_i915_private *dev_priv = dev->dev_private; 2057 const struct ddi_buf_trans *ddi_translations; 2058 uint8_t iboost; 2059 uint8_t dp_iboost, hdmi_iboost; 2060 int n_entries; 2061 u32 reg; 2062 2063 /* VBT may override standard boost values */ 2064 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level; 2065 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level; 2066 2067 if (type == INTEL_OUTPUT_DISPLAYPORT) { 2068 if (dp_iboost) { 2069 iboost = dp_iboost; 2070 } else { 2071 ddi_translations = skl_get_buf_trans_dp(dev, &n_entries); 2072 iboost = ddi_translations[port].i_boost; 2073 } 2074 } else if (type == INTEL_OUTPUT_EDP) { 2075 if (dp_iboost) { 2076 iboost = dp_iboost; 2077 } else { 2078 ddi_translations = skl_get_buf_trans_edp(dev, &n_entries); 2079 iboost = ddi_translations[port].i_boost; 2080 } 2081 } else if (type == INTEL_OUTPUT_HDMI) { 2082 if (hdmi_iboost) { 2083 iboost = hdmi_iboost; 2084 } else { 2085 ddi_translations = skl_get_buf_trans_hdmi(dev, &n_entries); 2086 iboost = ddi_translations[port].i_boost; 2087 } 2088 } else { 2089 return; 2090 } 2091 2092 /* Make sure that the requested I_boost is valid */ 2093 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) { 2094 DRM_ERROR("Invalid I_boost value %u\n", iboost); 2095 return; 2096 } 2097 2098 reg = I915_READ(DISPIO_CR_TX_BMU_CR0); 2099 reg &= ~BALANCE_LEG_MASK(port); 2100 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port)); 2101 2102 if (iboost) 2103 reg |= iboost << BALANCE_LEG_SHIFT(port); 2104 else 2105 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port); 2106 2107 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg); 2108 } 2109 2110 static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, 2111 enum port port, int type) 2112 { 2113 struct drm_i915_private *dev_priv = dev->dev_private; 2114 const struct bxt_ddi_buf_trans *ddi_translations; 2115 u32 n_entries, i; 2116 uint32_t val; 2117 2118 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2119 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); 2120 ddi_translations = bxt_ddi_translations_dp; 2121 } else if (type == INTEL_OUTPUT_HDMI) { 2122 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); 2123 ddi_translations = bxt_ddi_translations_hdmi; 2124 } else { 2125 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", 2126 type); 2127 return; 2128 } 2129 2130 /* Check if default value has to be used */ 2131 if (level >= n_entries || 2132 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { 2133 for (i = 0; i < n_entries; i++) { 2134 if (ddi_translations[i].default_index) { 2135 level = i; 2136 break; 2137 } 2138 } 2139 } 2140 2141 /* 2142 * While we write to the group register to program all lanes at once we 2143 * can read only lane registers and we pick lanes 0/1 for that. 2144 */ 2145 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2146 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 2147 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2148 2149 val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); 2150 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 2151 val |= ddi_translations[level].margin << MARGIN_000_SHIFT | 2152 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; 2153 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); 2154 2155 val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); 2156 val &= ~UNIQE_TRANGE_EN_METHOD; 2157 if (ddi_translations[level].enable) 2158 val |= UNIQE_TRANGE_EN_METHOD; 2159 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); 2160 2161 val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); 2162 val &= ~DE_EMPHASIS; 2163 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; 2164 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); 2165 2166 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); 2167 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 2168 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); 2169 } 2170 2171 static uint32_t translate_signal_level(int signal_levels) 2172 { 2173 uint32_t level; 2174 2175 switch (signal_levels) { 2176 default: 2177 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n", 2178 signal_levels); 2179 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2180 level = 0; 2181 break; 2182 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2183 level = 1; 2184 break; 2185 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2186 level = 2; 2187 break; 2188 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3: 2189 level = 3; 2190 break; 2191 2192 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2193 level = 4; 2194 break; 2195 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2196 level = 5; 2197 break; 2198 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 2199 level = 6; 2200 break; 2201 2202 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2203 level = 7; 2204 break; 2205 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 2206 level = 8; 2207 break; 2208 2209 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 2210 level = 9; 2211 break; 2212 } 2213 2214 return level; 2215 } 2216 2217 uint32_t ddi_signal_levels(struct intel_dp *intel_dp) 2218 { 2219 struct intel_digital_port *dport = dp_to_dig_port(intel_dp); 2220 struct drm_device *dev = dport->base.base.dev; 2221 struct intel_encoder *encoder = &dport->base; 2222 uint8_t train_set = intel_dp->train_set[0]; 2223 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 2224 DP_TRAIN_PRE_EMPHASIS_MASK); 2225 enum port port = dport->port; 2226 uint32_t level; 2227 2228 level = translate_signal_level(signal_levels); 2229 2230 if (IS_SKYLAKE(dev)) 2231 skl_ddi_set_iboost(dev, level, port, encoder->type); 2232 else if (IS_BROXTON(dev)) 2233 bxt_ddi_vswing_sequence(dev, level, port, encoder->type); 2234 2235 return DDI_BUF_TRANS_SELECT(level); 2236 } 2237 2238 static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) 2239 { 2240 struct drm_encoder *encoder = &intel_encoder->base; 2241 struct drm_device *dev = encoder->dev; 2242 struct drm_i915_private *dev_priv = dev->dev_private; 2243 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 2244 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2245 int type = intel_encoder->type; 2246 int hdmi_level; 2247 2248 if (type == INTEL_OUTPUT_EDP) { 2249 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2250 intel_edp_panel_on(intel_dp); 2251 } 2252 2253 if (IS_SKYLAKE(dev)) { 2254 uint32_t dpll = crtc->config->ddi_pll_sel; 2255 uint32_t val; 2256 2257 /* 2258 * DPLL0 is used for eDP and is the only "private" DPLL (as 2259 * opposed to shared) on SKL 2260 */ 2261 if (type == INTEL_OUTPUT_EDP) { 2262 WARN_ON(dpll != SKL_DPLL0); 2263 2264 val = I915_READ(DPLL_CTRL1); 2265 2266 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | 2267 DPLL_CTRL1_SSC(dpll) | 2268 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2269 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); 2270 2271 I915_WRITE(DPLL_CTRL1, val); 2272 POSTING_READ(DPLL_CTRL1); 2273 } 2274 2275 /* DDI -> PLL mapping */ 2276 val = I915_READ(DPLL_CTRL2); 2277 2278 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | 2279 DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); 2280 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | 2281 DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); 2282 2283 I915_WRITE(DPLL_CTRL2, val); 2284 2285 } else if (INTEL_INFO(dev)->gen < 9) { 2286 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); 2287 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); 2288 } 2289 2290 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2291 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2292 2293 intel_ddi_init_dp_buf_reg(intel_encoder); 2294 2295 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 2296 intel_dp_start_link_train(intel_dp); 2297 intel_dp_complete_link_train(intel_dp); 2298 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) 2299 intel_dp_stop_link_train(intel_dp); 2300 } else if (type == INTEL_OUTPUT_HDMI) { 2301 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); 2302 2303 if (IS_BROXTON(dev)) { 2304 hdmi_level = dev_priv->vbt. 2305 ddi_port_info[port].hdmi_level_shift; 2306 bxt_ddi_vswing_sequence(dev, hdmi_level, port, 2307 INTEL_OUTPUT_HDMI); 2308 } 2309 intel_hdmi->set_infoframes(encoder, 2310 crtc->config->has_hdmi_sink, 2311 &crtc->config->base.adjusted_mode); 2312 } 2313 } 2314 2315 static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) 2316 { 2317 struct drm_encoder *encoder = &intel_encoder->base; 2318 struct drm_device *dev = encoder->dev; 2319 struct drm_i915_private *dev_priv = dev->dev_private; 2320 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2321 int type = intel_encoder->type; 2322 uint32_t val; 2323 bool wait = false; 2324 2325 val = I915_READ(DDI_BUF_CTL(port)); 2326 if (val & DDI_BUF_CTL_ENABLE) { 2327 val &= ~DDI_BUF_CTL_ENABLE; 2328 I915_WRITE(DDI_BUF_CTL(port), val); 2329 wait = true; 2330 } 2331 2332 val = I915_READ(DP_TP_CTL(port)); 2333 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2334 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2335 I915_WRITE(DP_TP_CTL(port), val); 2336 2337 if (wait) 2338 intel_wait_ddi_buf_idle(dev_priv, port); 2339 2340 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 2341 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2342 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 2343 intel_edp_panel_vdd_on(intel_dp); 2344 intel_edp_panel_off(intel_dp); 2345 } 2346 2347 if (IS_SKYLAKE(dev)) 2348 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | 2349 DPLL_CTRL2_DDI_CLK_OFF(port))); 2350 else if (INTEL_INFO(dev)->gen < 9) 2351 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); 2352 } 2353 2354 static void intel_enable_ddi(struct intel_encoder *intel_encoder) 2355 { 2356 struct drm_encoder *encoder = &intel_encoder->base; 2357 struct drm_crtc *crtc = encoder->crtc; 2358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2359 struct drm_device *dev = encoder->dev; 2360 struct drm_i915_private *dev_priv = dev->dev_private; 2361 enum port port = intel_ddi_get_encoder_port(intel_encoder); 2362 int type = intel_encoder->type; 2363 2364 if (type == INTEL_OUTPUT_HDMI) { 2365 struct intel_digital_port *intel_dig_port = 2366 enc_to_dig_port(encoder); 2367 2368 /* In HDMI/DVI mode, the port width, and swing/emphasis values 2369 * are ignored so nothing special needs to be done besides 2370 * enabling the port. 2371 */ 2372 I915_WRITE(DDI_BUF_CTL(port), 2373 intel_dig_port->saved_port_bits | 2374 DDI_BUF_CTL_ENABLE); 2375 } else if (type == INTEL_OUTPUT_EDP) { 2376 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2377 2378 if (port == PORT_A && INTEL_INFO(dev)->gen < 9) 2379 intel_dp_stop_link_train(intel_dp); 2380 2381 intel_edp_backlight_on(intel_dp); 2382 intel_psr_enable(intel_dp); 2383 intel_edp_drrs_enable(intel_dp); 2384 } 2385 2386 if (intel_crtc->config->has_audio) { 2387 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 2388 intel_audio_codec_enable(intel_encoder); 2389 } 2390 } 2391 2392 static void intel_disable_ddi(struct intel_encoder *intel_encoder) 2393 { 2394 struct drm_encoder *encoder = &intel_encoder->base; 2395 struct drm_crtc *crtc = encoder->crtc; 2396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2397 int type = intel_encoder->type; 2398 struct drm_device *dev = encoder->dev; 2399 struct drm_i915_private *dev_priv = dev->dev_private; 2400 2401 if (intel_crtc->config->has_audio) { 2402 intel_audio_codec_disable(intel_encoder); 2403 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 2404 } 2405 2406 if (type == INTEL_OUTPUT_EDP) { 2407 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 2408 2409 intel_edp_drrs_disable(intel_dp); 2410 intel_psr_disable(intel_dp); 2411 intel_edp_backlight_off(intel_dp); 2412 } 2413 } 2414 2415 static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, 2416 struct intel_shared_dpll *pll) 2417 { 2418 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); 2419 POSTING_READ(WRPLL_CTL(pll->id)); 2420 udelay(20); 2421 } 2422 2423 static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, 2424 struct intel_shared_dpll *pll) 2425 { 2426 uint32_t val; 2427 2428 val = I915_READ(WRPLL_CTL(pll->id)); 2429 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); 2430 POSTING_READ(WRPLL_CTL(pll->id)); 2431 } 2432 2433 static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2434 struct intel_shared_dpll *pll, 2435 struct intel_dpll_hw_state *hw_state) 2436 { 2437 uint32_t val; 2438 2439 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2440 return false; 2441 2442 val = I915_READ(WRPLL_CTL(pll->id)); 2443 hw_state->wrpll = val; 2444 2445 return val & WRPLL_PLL_ENABLE; 2446 } 2447 2448 static const char * const hsw_ddi_pll_names[] = { 2449 "WRPLL 1", 2450 "WRPLL 2", 2451 }; 2452 2453 static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) 2454 { 2455 int i; 2456 2457 dev_priv->num_shared_dpll = 2; 2458 2459 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2460 dev_priv->shared_dplls[i].id = i; 2461 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; 2462 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; 2463 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; 2464 dev_priv->shared_dplls[i].get_hw_state = 2465 hsw_ddi_pll_get_hw_state; 2466 } 2467 } 2468 2469 static const char * const skl_ddi_pll_names[] = { 2470 "DPLL 1", 2471 "DPLL 2", 2472 "DPLL 3", 2473 }; 2474 2475 struct skl_dpll_regs { 2476 u32 ctl, cfgcr1, cfgcr2; 2477 }; 2478 2479 /* this array is indexed by the *shared* pll id */ 2480 static const struct skl_dpll_regs skl_dpll_regs[3] = { 2481 { 2482 /* DPLL 1 */ 2483 .ctl = LCPLL2_CTL, 2484 .cfgcr1 = DPLL1_CFGCR1, 2485 .cfgcr2 = DPLL1_CFGCR2, 2486 }, 2487 { 2488 /* DPLL 2 */ 2489 .ctl = WRPLL_CTL1, 2490 .cfgcr1 = DPLL2_CFGCR1, 2491 .cfgcr2 = DPLL2_CFGCR2, 2492 }, 2493 { 2494 /* DPLL 3 */ 2495 .ctl = WRPLL_CTL2, 2496 .cfgcr1 = DPLL3_CFGCR1, 2497 .cfgcr2 = DPLL3_CFGCR2, 2498 }, 2499 }; 2500 2501 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, 2502 struct intel_shared_dpll *pll) 2503 { 2504 uint32_t val; 2505 unsigned int dpll; 2506 const struct skl_dpll_regs *regs = skl_dpll_regs; 2507 2508 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2509 dpll = pll->id + 1; 2510 2511 val = I915_READ(DPLL_CTRL1); 2512 2513 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | 2514 DPLL_CTRL1_LINK_RATE_MASK(dpll)); 2515 val |= pll->config.hw_state.ctrl1 << (dpll * 6); 2516 2517 I915_WRITE(DPLL_CTRL1, val); 2518 POSTING_READ(DPLL_CTRL1); 2519 2520 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); 2521 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); 2522 POSTING_READ(regs[pll->id].cfgcr1); 2523 POSTING_READ(regs[pll->id].cfgcr2); 2524 2525 /* the enable bit is always bit 31 */ 2526 I915_WRITE(regs[pll->id].ctl, 2527 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); 2528 2529 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) 2530 DRM_ERROR("DPLL %d not locked\n", dpll); 2531 } 2532 2533 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, 2534 struct intel_shared_dpll *pll) 2535 { 2536 const struct skl_dpll_regs *regs = skl_dpll_regs; 2537 2538 /* the enable bit is always bit 31 */ 2539 I915_WRITE(regs[pll->id].ctl, 2540 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); 2541 POSTING_READ(regs[pll->id].ctl); 2542 } 2543 2544 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2545 struct intel_shared_dpll *pll, 2546 struct intel_dpll_hw_state *hw_state) 2547 { 2548 uint32_t val; 2549 unsigned int dpll; 2550 const struct skl_dpll_regs *regs = skl_dpll_regs; 2551 2552 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2553 return false; 2554 2555 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ 2556 dpll = pll->id + 1; 2557 2558 val = I915_READ(regs[pll->id].ctl); 2559 if (!(val & LCPLL_PLL_ENABLE)) 2560 return false; 2561 2562 val = I915_READ(DPLL_CTRL1); 2563 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; 2564 2565 /* avoid reading back stale values if HDMI mode is not enabled */ 2566 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { 2567 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); 2568 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); 2569 } 2570 2571 return true; 2572 } 2573 2574 static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) 2575 { 2576 int i; 2577 2578 dev_priv->num_shared_dpll = 3; 2579 2580 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2581 dev_priv->shared_dplls[i].id = i; 2582 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; 2583 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; 2584 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; 2585 dev_priv->shared_dplls[i].get_hw_state = 2586 skl_ddi_pll_get_hw_state; 2587 } 2588 } 2589 2590 static void broxton_phy_init(struct drm_i915_private *dev_priv, 2591 enum dpio_phy phy) 2592 { 2593 enum port port; 2594 uint32_t val; 2595 2596 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); 2597 val |= GT_DISPLAY_POWER_ON(phy); 2598 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); 2599 2600 /* Considering 10ms timeout until BSpec is updated */ 2601 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) 2602 DRM_ERROR("timeout during PHY%d power on\n", phy); 2603 2604 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); 2605 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { 2606 int lane; 2607 2608 for (lane = 0; lane < 4; lane++) { 2609 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); 2610 /* 2611 * Note that on CHV this flag is called UPAR, but has 2612 * the same function. 2613 */ 2614 val &= ~LATENCY_OPTIM; 2615 if (lane != 1) 2616 val |= LATENCY_OPTIM; 2617 2618 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); 2619 } 2620 } 2621 2622 /* Program PLL Rcomp code offset */ 2623 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); 2624 val &= ~IREF0RC_OFFSET_MASK; 2625 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 2626 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); 2627 2628 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); 2629 val &= ~IREF1RC_OFFSET_MASK; 2630 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 2631 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); 2632 2633 /* Program power gating */ 2634 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); 2635 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 2636 SUS_CLK_CONFIG; 2637 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); 2638 2639 if (phy == DPIO_PHY0) { 2640 val = I915_READ(BXT_PORT_CL2CM_DW6_BC); 2641 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 2642 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); 2643 } 2644 2645 val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); 2646 val &= ~OCL2_LDOFUSE_PWR_DIS; 2647 /* 2648 * On PHY1 disable power on the second channel, since no port is 2649 * connected there. On PHY0 both channels have a port, so leave it 2650 * enabled. 2651 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should 2652 * power down the second channel on PHY0 as well. 2653 */ 2654 if (phy == DPIO_PHY1) 2655 val |= OCL2_LDOFUSE_PWR_DIS; 2656 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); 2657 2658 if (phy == DPIO_PHY0) { 2659 uint32_t grc_code; 2660 /* 2661 * PHY0 isn't connected to an RCOMP resistor so copy over 2662 * the corresponding calibrated value from PHY1, and disable 2663 * the automatic calibration on PHY0. 2664 */ 2665 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, 2666 10)) 2667 DRM_ERROR("timeout waiting for PHY1 GRC\n"); 2668 2669 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); 2670 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 2671 grc_code = val << GRC_CODE_FAST_SHIFT | 2672 val << GRC_CODE_SLOW_SHIFT | 2673 val; 2674 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); 2675 2676 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); 2677 val |= GRC_DIS | GRC_RDY_OVRD; 2678 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); 2679 } 2680 2681 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2682 val |= COMMON_RESET_DIS; 2683 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2684 } 2685 2686 void broxton_ddi_phy_init(struct drm_device *dev) 2687 { 2688 /* Enable PHY1 first since it provides Rcomp for PHY0 */ 2689 broxton_phy_init(dev->dev_private, DPIO_PHY1); 2690 broxton_phy_init(dev->dev_private, DPIO_PHY0); 2691 } 2692 2693 static void broxton_phy_uninit(struct drm_i915_private *dev_priv, 2694 enum dpio_phy phy) 2695 { 2696 uint32_t val; 2697 2698 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); 2699 val &= ~COMMON_RESET_DIS; 2700 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); 2701 } 2702 2703 void broxton_ddi_phy_uninit(struct drm_device *dev) 2704 { 2705 struct drm_i915_private *dev_priv = dev->dev_private; 2706 2707 broxton_phy_uninit(dev_priv, DPIO_PHY1); 2708 broxton_phy_uninit(dev_priv, DPIO_PHY0); 2709 2710 /* FIXME: do this in broxton_phy_uninit per phy */ 2711 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); 2712 } 2713 2714 static const char * const bxt_ddi_pll_names[] = { 2715 "PORT PLL A", 2716 "PORT PLL B", 2717 "PORT PLL C", 2718 }; 2719 2720 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, 2721 struct intel_shared_dpll *pll) 2722 { 2723 uint32_t temp; 2724 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2725 2726 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2727 temp &= ~PORT_PLL_REF_SEL; 2728 /* Non-SSC reference */ 2729 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2730 2731 /* Disable 10 bit clock */ 2732 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2733 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2734 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2735 2736 /* Write P1 & P2 */ 2737 temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2738 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); 2739 temp |= pll->config.hw_state.ebb0; 2740 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); 2741 2742 /* Write M2 integer */ 2743 temp = I915_READ(BXT_PORT_PLL(port, 0)); 2744 temp &= ~PORT_PLL_M2_MASK; 2745 temp |= pll->config.hw_state.pll0; 2746 I915_WRITE(BXT_PORT_PLL(port, 0), temp); 2747 2748 /* Write N */ 2749 temp = I915_READ(BXT_PORT_PLL(port, 1)); 2750 temp &= ~PORT_PLL_N_MASK; 2751 temp |= pll->config.hw_state.pll1; 2752 I915_WRITE(BXT_PORT_PLL(port, 1), temp); 2753 2754 /* Write M2 fraction */ 2755 temp = I915_READ(BXT_PORT_PLL(port, 2)); 2756 temp &= ~PORT_PLL_M2_FRAC_MASK; 2757 temp |= pll->config.hw_state.pll2; 2758 I915_WRITE(BXT_PORT_PLL(port, 2), temp); 2759 2760 /* Write M2 fraction enable */ 2761 temp = I915_READ(BXT_PORT_PLL(port, 3)); 2762 temp &= ~PORT_PLL_M2_FRAC_ENABLE; 2763 temp |= pll->config.hw_state.pll3; 2764 I915_WRITE(BXT_PORT_PLL(port, 3), temp); 2765 2766 /* Write coeff */ 2767 temp = I915_READ(BXT_PORT_PLL(port, 6)); 2768 temp &= ~PORT_PLL_PROP_COEFF_MASK; 2769 temp &= ~PORT_PLL_INT_COEFF_MASK; 2770 temp &= ~PORT_PLL_GAIN_CTL_MASK; 2771 temp |= pll->config.hw_state.pll6; 2772 I915_WRITE(BXT_PORT_PLL(port, 6), temp); 2773 2774 /* Write calibration val */ 2775 temp = I915_READ(BXT_PORT_PLL(port, 8)); 2776 temp &= ~PORT_PLL_TARGET_CNT_MASK; 2777 temp |= pll->config.hw_state.pll8; 2778 I915_WRITE(BXT_PORT_PLL(port, 8), temp); 2779 2780 temp = I915_READ(BXT_PORT_PLL(port, 9)); 2781 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK; 2782 temp |= pll->config.hw_state.pll9; 2783 I915_WRITE(BXT_PORT_PLL(port, 9), temp); 2784 2785 temp = I915_READ(BXT_PORT_PLL(port, 10)); 2786 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H; 2787 temp &= ~PORT_PLL_DCO_AMP_MASK; 2788 temp |= pll->config.hw_state.pll10; 2789 I915_WRITE(BXT_PORT_PLL(port, 10), temp); 2790 2791 /* Recalibrate with new settings */ 2792 temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2793 temp |= PORT_PLL_RECALIBRATE; 2794 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2795 temp &= ~PORT_PLL_10BIT_CLK_ENABLE; 2796 temp |= pll->config.hw_state.ebb4; 2797 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); 2798 2799 /* Enable PLL */ 2800 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2801 temp |= PORT_PLL_ENABLE; 2802 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2803 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2804 2805 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & 2806 PORT_PLL_LOCK), 200)) 2807 DRM_ERROR("PLL %d not locked\n", port); 2808 2809 /* 2810 * While we write to the group register to program all lanes at once we 2811 * can read only lane registers and we pick lanes 0/1 for that. 2812 */ 2813 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2814 temp &= ~LANE_STAGGER_MASK; 2815 temp &= ~LANESTAGGER_STRAP_OVRD; 2816 temp |= pll->config.hw_state.pcsdw12; 2817 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); 2818 } 2819 2820 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, 2821 struct intel_shared_dpll *pll) 2822 { 2823 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2824 uint32_t temp; 2825 2826 temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2827 temp &= ~PORT_PLL_ENABLE; 2828 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); 2829 POSTING_READ(BXT_PORT_PLL_ENABLE(port)); 2830 } 2831 2832 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, 2833 struct intel_shared_dpll *pll, 2834 struct intel_dpll_hw_state *hw_state) 2835 { 2836 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ 2837 uint32_t val; 2838 2839 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) 2840 return false; 2841 2842 val = I915_READ(BXT_PORT_PLL_ENABLE(port)); 2843 if (!(val & PORT_PLL_ENABLE)) 2844 return false; 2845 2846 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); 2847 hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK; 2848 2849 hw_state->ebb4 = I915_READ(BXT_PORT_PLL_EBB_4(port)); 2850 hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE; 2851 2852 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); 2853 hw_state->pll0 &= PORT_PLL_M2_MASK; 2854 2855 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); 2856 hw_state->pll1 &= PORT_PLL_N_MASK; 2857 2858 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); 2859 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; 2860 2861 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); 2862 hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE; 2863 2864 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); 2865 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | 2866 PORT_PLL_INT_COEFF_MASK | 2867 PORT_PLL_GAIN_CTL_MASK; 2868 2869 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); 2870 hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK; 2871 2872 hw_state->pll9 = I915_READ(BXT_PORT_PLL(port, 9)); 2873 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; 2874 2875 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); 2876 hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H | 2877 PORT_PLL_DCO_AMP_MASK; 2878 2879 /* 2880 * While we write to the group register to program all lanes at once we 2881 * can read only lane registers. We configure all lanes the same way, so 2882 * here just read out lanes 0/1 and output a note if lanes 2/3 differ. 2883 */ 2884 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); 2885 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12)) 2886 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", 2887 hw_state->pcsdw12, 2888 I915_READ(BXT_PORT_PCS_DW12_LN23(port))); 2889 hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD; 2890 2891 return true; 2892 } 2893 2894 static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) 2895 { 2896 int i; 2897 2898 dev_priv->num_shared_dpll = 3; 2899 2900 for (i = 0; i < dev_priv->num_shared_dpll; i++) { 2901 dev_priv->shared_dplls[i].id = i; 2902 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; 2903 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; 2904 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; 2905 dev_priv->shared_dplls[i].get_hw_state = 2906 bxt_ddi_pll_get_hw_state; 2907 } 2908 } 2909 2910 void intel_ddi_pll_init(struct drm_device *dev) 2911 { 2912 struct drm_i915_private *dev_priv = dev->dev_private; 2913 uint32_t val = I915_READ(LCPLL_CTL); 2914 2915 if (IS_SKYLAKE(dev)) 2916 skl_shared_dplls_init(dev_priv); 2917 else if (IS_BROXTON(dev)) 2918 bxt_shared_dplls_init(dev_priv); 2919 else 2920 hsw_shared_dplls_init(dev_priv); 2921 2922 if (IS_SKYLAKE(dev)) { 2923 int cdclk_freq; 2924 2925 cdclk_freq = dev_priv->display.get_display_clock_speed(dev); 2926 dev_priv->skl_boot_cdclk = cdclk_freq; 2927 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) 2928 DRM_ERROR("LCPLL1 is disabled\n"); 2929 else 2930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); 2931 } else if (IS_BROXTON(dev)) { 2932 broxton_init_cdclk(dev); 2933 broxton_ddi_phy_init(dev); 2934 } else { 2935 /* 2936 * The LCPLL register should be turned on by the BIOS. For now 2937 * let's just check its state and print errors in case 2938 * something is wrong. Don't even try to turn it on. 2939 */ 2940 2941 if (val & LCPLL_CD_SOURCE_FCLK) 2942 DRM_ERROR("CDCLK source is not LCPLL\n"); 2943 2944 if (val & LCPLL_PLL_DISABLE) 2945 DRM_ERROR("LCPLL is disabled\n"); 2946 } 2947 } 2948 2949 void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) 2950 { 2951 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 2952 struct intel_dp *intel_dp = &intel_dig_port->dp; 2953 struct drm_i915_private *dev_priv = encoder->dev->dev_private; 2954 enum port port = intel_dig_port->port; 2955 uint32_t val; 2956 bool wait = false; 2957 2958 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { 2959 val = I915_READ(DDI_BUF_CTL(port)); 2960 if (val & DDI_BUF_CTL_ENABLE) { 2961 val &= ~DDI_BUF_CTL_ENABLE; 2962 I915_WRITE(DDI_BUF_CTL(port), val); 2963 wait = true; 2964 } 2965 2966 val = I915_READ(DP_TP_CTL(port)); 2967 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); 2968 val |= DP_TP_CTL_LINK_TRAIN_PAT1; 2969 I915_WRITE(DP_TP_CTL(port), val); 2970 POSTING_READ(DP_TP_CTL(port)); 2971 2972 if (wait) 2973 intel_wait_ddi_buf_idle(dev_priv, port); 2974 } 2975 2976 val = DP_TP_CTL_ENABLE | 2977 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; 2978 if (intel_dp->is_mst) 2979 val |= DP_TP_CTL_MODE_MST; 2980 else { 2981 val |= DP_TP_CTL_MODE_SST; 2982 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2983 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; 2984 } 2985 I915_WRITE(DP_TP_CTL(port), val); 2986 POSTING_READ(DP_TP_CTL(port)); 2987 2988 intel_dp->DP |= DDI_BUF_CTL_ENABLE; 2989 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); 2990 POSTING_READ(DDI_BUF_CTL(port)); 2991 2992 udelay(600); 2993 } 2994 2995 void intel_ddi_fdi_disable(struct drm_crtc *crtc) 2996 { 2997 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 2998 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); 2999 uint32_t val; 3000 3001 intel_ddi_post_disable(intel_encoder); 3002 3003 val = I915_READ(_FDI_RXA_CTL); 3004 val &= ~FDI_RX_ENABLE; 3005 I915_WRITE(_FDI_RXA_CTL, val); 3006 3007 val = I915_READ(_FDI_RXA_MISC); 3008 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); 3009 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); 3010 I915_WRITE(_FDI_RXA_MISC, val); 3011 3012 val = I915_READ(_FDI_RXA_CTL); 3013 val &= ~FDI_PCDCLK; 3014 I915_WRITE(_FDI_RXA_CTL, val); 3015 3016 val = I915_READ(_FDI_RXA_CTL); 3017 val &= ~FDI_RX_PLL_ENABLE; 3018 I915_WRITE(_FDI_RXA_CTL, val); 3019 } 3020 3021 void intel_ddi_get_config(struct intel_encoder *encoder, 3022 struct intel_crtc_state *pipe_config) 3023 { 3024 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 3025 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 3026 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; 3027 struct intel_hdmi *intel_hdmi; 3028 u32 temp, flags = 0; 3029 3030 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); 3031 if (temp & TRANS_DDI_PHSYNC) 3032 flags |= DRM_MODE_FLAG_PHSYNC; 3033 else 3034 flags |= DRM_MODE_FLAG_NHSYNC; 3035 if (temp & TRANS_DDI_PVSYNC) 3036 flags |= DRM_MODE_FLAG_PVSYNC; 3037 else 3038 flags |= DRM_MODE_FLAG_NVSYNC; 3039 3040 pipe_config->base.adjusted_mode.flags |= flags; 3041 3042 switch (temp & TRANS_DDI_BPC_MASK) { 3043 case TRANS_DDI_BPC_6: 3044 pipe_config->pipe_bpp = 18; 3045 break; 3046 case TRANS_DDI_BPC_8: 3047 pipe_config->pipe_bpp = 24; 3048 break; 3049 case TRANS_DDI_BPC_10: 3050 pipe_config->pipe_bpp = 30; 3051 break; 3052 case TRANS_DDI_BPC_12: 3053 pipe_config->pipe_bpp = 36; 3054 break; 3055 default: 3056 break; 3057 } 3058 3059 switch (temp & TRANS_DDI_MODE_SELECT_MASK) { 3060 case TRANS_DDI_MODE_SELECT_HDMI: 3061 pipe_config->has_hdmi_sink = true; 3062 intel_hdmi = enc_to_intel_hdmi(&encoder->base); 3063 3064 if (intel_hdmi->infoframe_enabled(&encoder->base)) 3065 pipe_config->has_infoframe = true; 3066 break; 3067 case TRANS_DDI_MODE_SELECT_DVI: 3068 case TRANS_DDI_MODE_SELECT_FDI: 3069 break; 3070 case TRANS_DDI_MODE_SELECT_DP_SST: 3071 case TRANS_DDI_MODE_SELECT_DP_MST: 3072 pipe_config->has_dp_encoder = true; 3073 intel_dp_get_m_n(intel_crtc, pipe_config); 3074 break; 3075 default: 3076 break; 3077 } 3078 3079 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { 3080 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 3081 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) 3082 pipe_config->has_audio = true; 3083 } 3084 3085 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && 3086 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { 3087 /* 3088 * This is a big fat ugly hack. 3089 * 3090 * Some machines in UEFI boot mode provide us a VBT that has 18 3091 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3092 * unknown we fail to light up. Yet the same BIOS boots up with 3093 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3094 * max, not what it tells us to use. 3095 * 3096 * Note: This will still be broken if the eDP panel is not lit 3097 * up by the BIOS, and thus we can't get the mode at module 3098 * load. 3099 */ 3100 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3101 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); 3102 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; 3103 } 3104 3105 intel_ddi_clock_get(encoder, pipe_config); 3106 } 3107 3108 static void intel_ddi_destroy(struct drm_encoder *encoder) 3109 { 3110 /* HDMI has nothing special to destroy, so we can go with this. */ 3111 intel_dp_encoder_destroy(encoder); 3112 } 3113 3114 static bool intel_ddi_compute_config(struct intel_encoder *encoder, 3115 struct intel_crtc_state *pipe_config) 3116 { 3117 int type = encoder->type; 3118 int port = intel_ddi_get_encoder_port(encoder); 3119 3120 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); 3121 3122 if (port == PORT_A) 3123 pipe_config->cpu_transcoder = TRANSCODER_EDP; 3124 3125 if (type == INTEL_OUTPUT_HDMI) 3126 return intel_hdmi_compute_config(encoder, pipe_config); 3127 else 3128 return intel_dp_compute_config(encoder, pipe_config); 3129 } 3130 3131 static const struct drm_encoder_funcs intel_ddi_funcs = { 3132 .destroy = intel_ddi_destroy, 3133 }; 3134 3135 static struct intel_connector * 3136 intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) 3137 { 3138 struct intel_connector *connector; 3139 enum port port = intel_dig_port->port; 3140 3141 connector = intel_connector_alloc(); 3142 if (!connector) 3143 return NULL; 3144 3145 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); 3146 if (!intel_dp_init_connector(intel_dig_port, connector)) { 3147 kfree(connector); 3148 return NULL; 3149 } 3150 3151 return connector; 3152 } 3153 3154 static struct intel_connector * 3155 intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) 3156 { 3157 struct intel_connector *connector; 3158 enum port port = intel_dig_port->port; 3159 3160 connector = intel_connector_alloc(); 3161 if (!connector) 3162 return NULL; 3163 3164 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); 3165 intel_hdmi_init_connector(intel_dig_port, connector); 3166 3167 return connector; 3168 } 3169 3170 void intel_ddi_init(struct drm_device *dev, enum port port) 3171 { 3172 struct drm_i915_private *dev_priv = dev->dev_private; 3173 struct intel_digital_port *intel_dig_port; 3174 struct intel_encoder *intel_encoder; 3175 struct drm_encoder *encoder; 3176 bool init_hdmi, init_dp; 3177 3178 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || 3179 dev_priv->vbt.ddi_port_info[port].supports_hdmi); 3180 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; 3181 if (!init_dp && !init_hdmi) { 3182 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n", 3183 port_name(port)); 3184 return; 3185 } 3186 3187 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 3188 if (!intel_dig_port) 3189 return; 3190 3191 intel_encoder = &intel_dig_port->base; 3192 encoder = &intel_encoder->base; 3193 3194 drm_encoder_init(dev, encoder, &intel_ddi_funcs, 3195 DRM_MODE_ENCODER_TMDS); 3196 3197 intel_encoder->compute_config = intel_ddi_compute_config; 3198 intel_encoder->enable = intel_enable_ddi; 3199 intel_encoder->pre_enable = intel_ddi_pre_enable; 3200 intel_encoder->disable = intel_disable_ddi; 3201 intel_encoder->post_disable = intel_ddi_post_disable; 3202 intel_encoder->get_hw_state = intel_ddi_get_hw_state; 3203 intel_encoder->get_config = intel_ddi_get_config; 3204 3205 intel_dig_port->port = port; 3206 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & 3207 (DDI_BUF_PORT_REVERSAL | 3208 DDI_A_4_LANES); 3209 3210 intel_encoder->type = INTEL_OUTPUT_UNKNOWN; 3211 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 3212 intel_encoder->cloneable = 0; 3213 3214 if (init_dp) { 3215 if (!intel_ddi_init_dp_connector(intel_dig_port)) 3216 goto err; 3217 3218 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 3219 dev_priv->hotplug.irq_port[port] = intel_dig_port; 3220 } 3221 3222 /* In theory we don't need the encoder->type check, but leave it just in 3223 * case we have some really bad VBTs... */ 3224 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { 3225 if (!intel_ddi_init_hdmi_connector(intel_dig_port)) 3226 goto err; 3227 } 3228 3229 return; 3230 3231 err: 3232 drm_encoder_cleanup(encoder); 3233 kfree(intel_dig_port); 3234 } 3235