1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #include <linux/firmware.h> 25 #include "i915_drv.h" 26 #include "i915_reg.h" 27 28 /** 29 * DOC: csr support for dmc 30 * 31 * Display Context Save and Restore (CSR) firmware support added from gen9 32 * onwards to drive newly added DMC (Display microcontroller) in display 33 * engine to save and restore the state of display engine when it enter into 34 * low-power state and comes back to normal. 35 */ 36 37 #define I915_CSR_GLK "i915/glk_dmc_ver1_04.bin" 38 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4) 39 40 #define I915_CSR_KBL "i915/kbl_dmc_ver1_01.bin" 41 MODULE_FIRMWARE(I915_CSR_KBL); 42 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 1) 43 44 #define I915_CSR_SKL "i915/skl_dmc_ver1_26.bin" 45 MODULE_FIRMWARE(I915_CSR_SKL); 46 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 26) 47 48 #define I915_CSR_BXT "i915/bxt_dmc_ver1_07.bin" 49 MODULE_FIRMWARE(I915_CSR_BXT); 50 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7) 51 52 #define FIRMWARE_URL "https://01.org/linuxgraphics/downloads/firmware" 53 54 55 56 57 #define CSR_MAX_FW_SIZE 0x2FFF 58 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF 59 60 struct intel_css_header { 61 /* 0x09 for DMC */ 62 uint32_t module_type; 63 64 /* Includes the DMC specific header in dwords */ 65 uint32_t header_len; 66 67 /* always value would be 0x10000 */ 68 uint32_t header_ver; 69 70 /* Not used */ 71 uint32_t module_id; 72 73 /* Not used */ 74 uint32_t module_vendor; 75 76 /* in YYYYMMDD format */ 77 uint32_t date; 78 79 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 80 uint32_t size; 81 82 /* Not used */ 83 uint32_t key_size; 84 85 /* Not used */ 86 uint32_t modulus_size; 87 88 /* Not used */ 89 uint32_t exponent_size; 90 91 /* Not used */ 92 uint32_t reserved1[12]; 93 94 /* Major Minor */ 95 uint32_t version; 96 97 /* Not used */ 98 uint32_t reserved2[8]; 99 100 /* Not used */ 101 uint32_t kernel_header_info; 102 } __packed; 103 104 struct intel_fw_info { 105 uint16_t reserved1; 106 107 /* Stepping (A, B, C, ..., *). * is a wildcard */ 108 char stepping; 109 110 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 111 char substepping; 112 113 uint32_t offset; 114 uint32_t reserved2; 115 } __packed; 116 117 struct intel_package_header { 118 /* DMC container header length in dwords */ 119 unsigned char header_len; 120 121 /* always value would be 0x01 */ 122 unsigned char header_ver; 123 124 unsigned char reserved[10]; 125 126 /* Number of valid entries in the FWInfo array below */ 127 uint32_t num_entries; 128 129 struct intel_fw_info fw_info[20]; 130 } __packed; 131 132 struct intel_dmc_header { 133 /* always value would be 0x40403E3E */ 134 uint32_t signature; 135 136 /* DMC binary header length */ 137 unsigned char header_len; 138 139 /* 0x01 */ 140 unsigned char header_ver; 141 142 /* Reserved */ 143 uint16_t dmcc_ver; 144 145 /* Major, Minor */ 146 uint32_t project; 147 148 /* Firmware program size (excluding header) in dwords */ 149 uint32_t fw_size; 150 151 /* Major Minor version */ 152 uint32_t fw_version; 153 154 /* Number of valid MMIO cycles present. */ 155 uint32_t mmio_count; 156 157 /* MMIO address */ 158 uint32_t mmioaddr[8]; 159 160 /* MMIO data */ 161 uint32_t mmiodata[8]; 162 163 /* FW filename */ 164 unsigned char dfile[32]; 165 166 uint32_t reserved1[2]; 167 } __packed; 168 169 struct stepping_info { 170 char stepping; 171 char substepping; 172 }; 173 174 static const struct stepping_info skl_stepping_info[] = { 175 {'A', '0'}, {'B', '0'}, {'C', '0'}, 176 {'D', '0'}, {'E', '0'}, {'F', '0'}, 177 {'G', '0'}, {'H', '0'}, {'I', '0'}, 178 {'J', '0'}, {'K', '0'} 179 }; 180 181 static const struct stepping_info bxt_stepping_info[] = { 182 {'A', '0'}, {'A', '1'}, {'A', '2'}, 183 {'B', '0'}, {'B', '1'}, {'B', '2'} 184 }; 185 186 static const struct stepping_info no_stepping_info = { '*', '*' }; 187 188 static const struct stepping_info * 189 intel_get_stepping_info(struct drm_i915_private *dev_priv) 190 { 191 const struct stepping_info *si; 192 unsigned int size; 193 194 if (IS_SKYLAKE(dev_priv)) { 195 size = ARRAY_SIZE(skl_stepping_info); 196 si = skl_stepping_info; 197 } else if (IS_BROXTON(dev_priv)) { 198 size = ARRAY_SIZE(bxt_stepping_info); 199 si = bxt_stepping_info; 200 } else { 201 size = 0; 202 } 203 204 if (INTEL_REVID(dev_priv) < size) 205 return si + INTEL_REVID(dev_priv); 206 207 return &no_stepping_info; 208 } 209 210 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 211 { 212 uint32_t val, mask; 213 214 mask = DC_STATE_DEBUG_MASK_MEMORY_UP; 215 216 if (IS_BROXTON(dev_priv)) 217 mask |= DC_STATE_DEBUG_MASK_CORES; 218 219 /* The below bit doesn't need to be cleared ever afterwards */ 220 val = I915_READ(DC_STATE_DEBUG); 221 if ((val & mask) != mask) { 222 val |= mask; 223 I915_WRITE(DC_STATE_DEBUG, val); 224 POSTING_READ(DC_STATE_DEBUG); 225 } 226 } 227 228 /** 229 * intel_csr_load_program() - write the firmware from memory to register. 230 * @dev_priv: i915 drm device. 231 * 232 * CSR firmware is read from a .bin file and kept in internal memory one time. 233 * Everytime display comes back from low power state this function is called to 234 * copy the firmware from internal memory to registers. 235 */ 236 void intel_csr_load_program(struct drm_i915_private *dev_priv) 237 { 238 u32 *payload = dev_priv->csr.dmc_payload; 239 uint32_t i, fw_size; 240 241 if (!IS_GEN9(dev_priv)) { 242 DRM_ERROR("No CSR support available for this platform\n"); 243 return; 244 } 245 246 if (!dev_priv->csr.dmc_payload) { 247 DRM_ERROR("Tried to program CSR with empty payload\n"); 248 return; 249 } 250 251 fw_size = dev_priv->csr.dmc_fw_size; 252 for (i = 0; i < fw_size; i++) 253 I915_WRITE(CSR_PROGRAM(i), payload[i]); 254 255 for (i = 0; i < dev_priv->csr.mmio_count; i++) { 256 I915_WRITE(dev_priv->csr.mmioaddr[i], 257 dev_priv->csr.mmiodata[i]); 258 } 259 260 dev_priv->csr.dc_state = 0; 261 262 gen9_set_dc_state_debugmask(dev_priv); 263 } 264 265 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv, 266 const struct firmware *fw) 267 { 268 struct intel_css_header *css_header; 269 struct intel_package_header *package_header; 270 struct intel_dmc_header *dmc_header; 271 struct intel_csr *csr = &dev_priv->csr; 272 const struct stepping_info *si = intel_get_stepping_info(dev_priv); 273 uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes; 274 uint32_t i; 275 uint32_t *dmc_payload; 276 uint32_t required_version; 277 278 if (!fw) 279 return NULL; 280 281 /* Extract CSS Header information*/ 282 css_header = (struct intel_css_header *)fw->data; 283 if (sizeof(struct intel_css_header) != 284 (css_header->header_len * 4)) { 285 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n", 286 (css_header->header_len * 4)); 287 return NULL; 288 } 289 290 csr->version = css_header->version; 291 292 if (IS_GEMINILAKE(dev_priv)) { 293 required_version = GLK_CSR_VERSION_REQUIRED; 294 } else if (IS_KABYLAKE(dev_priv)) { 295 required_version = KBL_CSR_VERSION_REQUIRED; 296 } else if (IS_SKYLAKE(dev_priv)) { 297 required_version = SKL_CSR_VERSION_REQUIRED; 298 } else if (IS_BROXTON(dev_priv)) { 299 required_version = BXT_CSR_VERSION_REQUIRED; 300 } else { 301 MISSING_CASE(INTEL_REVID(dev_priv)); 302 required_version = 0; 303 } 304 305 if (csr->version != required_version) { 306 DRM_INFO("Refusing to load DMC firmware v%u.%u," 307 " please use v%u.%u [" FIRMWARE_URL "].\n", 308 CSR_VERSION_MAJOR(csr->version), 309 CSR_VERSION_MINOR(csr->version), 310 CSR_VERSION_MAJOR(required_version), 311 CSR_VERSION_MINOR(required_version)); 312 return NULL; 313 } 314 315 readcount += sizeof(struct intel_css_header); 316 317 /* Extract Package Header information*/ 318 package_header = (struct intel_package_header *) 319 &fw->data[readcount]; 320 if (sizeof(struct intel_package_header) != 321 (package_header->header_len * 4)) { 322 DRM_ERROR("Firmware has wrong package header length %u bytes\n", 323 (package_header->header_len * 4)); 324 return NULL; 325 } 326 readcount += sizeof(struct intel_package_header); 327 328 /* Search for dmc_offset to find firware binary. */ 329 for (i = 0; i < package_header->num_entries; i++) { 330 if (package_header->fw_info[i].substepping == '*' && 331 si->stepping == package_header->fw_info[i].stepping) { 332 dmc_offset = package_header->fw_info[i].offset; 333 break; 334 } else if (si->stepping == package_header->fw_info[i].stepping && 335 si->substepping == package_header->fw_info[i].substepping) { 336 dmc_offset = package_header->fw_info[i].offset; 337 break; 338 } else if (package_header->fw_info[i].stepping == '*' && 339 package_header->fw_info[i].substepping == '*') 340 dmc_offset = package_header->fw_info[i].offset; 341 } 342 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) { 343 DRM_ERROR("Firmware not supported for %c stepping\n", 344 si->stepping); 345 return NULL; 346 } 347 readcount += dmc_offset; 348 349 /* Extract dmc_header information. */ 350 dmc_header = (struct intel_dmc_header *)&fw->data[readcount]; 351 if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) { 352 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n", 353 (dmc_header->header_len)); 354 return NULL; 355 } 356 readcount += sizeof(struct intel_dmc_header); 357 358 /* Cache the dmc header info. */ 359 if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) { 360 DRM_ERROR("Firmware has wrong mmio count %u\n", 361 dmc_header->mmio_count); 362 return NULL; 363 } 364 csr->mmio_count = dmc_header->mmio_count; 365 for (i = 0; i < dmc_header->mmio_count; i++) { 366 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE || 367 dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) { 368 DRM_ERROR(" Firmware has wrong mmio address 0x%x\n", 369 dmc_header->mmioaddr[i]); 370 return NULL; 371 } 372 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]); 373 csr->mmiodata[i] = dmc_header->mmiodata[i]; 374 } 375 376 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 377 nbytes = dmc_header->fw_size * 4; 378 if (nbytes > CSR_MAX_FW_SIZE) { 379 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes); 380 return NULL; 381 } 382 csr->dmc_fw_size = dmc_header->fw_size; 383 384 dmc_payload = kmalloc(nbytes, M_DRM, GFP_KERNEL); 385 if (!dmc_payload) { 386 DRM_ERROR("Memory allocation failed for dmc payload\n"); 387 return NULL; 388 } 389 390 return memcpy(dmc_payload, &fw->data[readcount], nbytes); 391 } 392 393 static void csr_load_work_fn(struct work_struct *work) 394 { 395 struct drm_i915_private *dev_priv; 396 struct intel_csr *csr; 397 const struct firmware *fw = NULL; 398 399 dev_priv = container_of(work, typeof(*dev_priv), csr.work); 400 csr = &dev_priv->csr; 401 402 request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev); 403 if (fw) 404 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw); 405 406 if (dev_priv->csr.dmc_payload) { 407 intel_csr_load_program(dev_priv); 408 409 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 410 411 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n", 412 dev_priv->csr.fw_path, 413 CSR_VERSION_MAJOR(csr->version), 414 CSR_VERSION_MINOR(csr->version)); 415 } else { 416 dev_notice(dev_priv->drm.dev, 417 "Failed to load DMC firmware" 418 " [" FIRMWARE_URL "]," 419 " disabling runtime power management.\n"); 420 } 421 422 release_firmware(fw); 423 } 424 425 /** 426 * intel_csr_ucode_init() - initialize the firmware loading. 427 * @dev_priv: i915 drm device. 428 * 429 * This function is called at the time of loading the display driver to read 430 * firmware from a .bin file and copied into a internal memory. 431 */ 432 void intel_csr_ucode_init(struct drm_i915_private *dev_priv) 433 { 434 struct intel_csr *csr = &dev_priv->csr; 435 436 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn); 437 438 if (!HAS_CSR(dev_priv)) 439 return; 440 441 if (IS_GEMINILAKE(dev_priv)) 442 csr->fw_path = I915_CSR_GLK; 443 else if (IS_KABYLAKE(dev_priv)) 444 csr->fw_path = I915_CSR_KBL; 445 else if (IS_SKYLAKE(dev_priv)) 446 csr->fw_path = I915_CSR_SKL; 447 else if (IS_BROXTON(dev_priv)) 448 csr->fw_path = I915_CSR_BXT; 449 else { 450 DRM_ERROR("Unexpected: no known CSR firmware for platform\n"); 451 return; 452 } 453 454 DRM_DEBUG_KMS("Loading %s\n", csr->fw_path); 455 456 /* 457 * Obtain a runtime pm reference, until CSR is loaded, 458 * to avoid entering runtime-suspend. 459 */ 460 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 461 462 schedule_work(&dev_priv->csr.work); 463 } 464 465 /** 466 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend 467 * @dev_priv: i915 drm device 468 * 469 * Prepare the DMC firmware before entering system suspend. This includes 470 * flushing pending work items and releasing any resources acquired during 471 * init. 472 */ 473 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv) 474 { 475 if (!HAS_CSR(dev_priv)) 476 return; 477 478 flush_work(&dev_priv->csr.work); 479 480 /* Drop the reference held in case DMC isn't loaded. */ 481 if (!dev_priv->csr.dmc_payload) 482 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); 483 } 484 485 /** 486 * intel_csr_ucode_resume() - init CSR firmware during system resume 487 * @dev_priv: i915 drm device 488 * 489 * Reinitialize the DMC firmware during system resume, reacquiring any 490 * resources released in intel_csr_ucode_suspend(). 491 */ 492 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv) 493 { 494 if (!HAS_CSR(dev_priv)) 495 return; 496 497 /* 498 * Reacquire the reference to keep RPM disabled in case DMC isn't 499 * loaded. 500 */ 501 if (!dev_priv->csr.dmc_payload) 502 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 503 } 504 505 /** 506 * intel_csr_ucode_fini() - unload the CSR firmware. 507 * @dev_priv: i915 drm device. 508 * 509 * Firmmware unloading includes freeing the internal memory and reset the 510 * firmware loading status. 511 */ 512 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv) 513 { 514 if (!HAS_CSR(dev_priv)) 515 return; 516 517 intel_csr_ucode_suspend(dev_priv); 518 519 kfree(dev_priv->csr.dmc_payload); 520 } 521