1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <drm/drmP.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_edid.h> 34 #include "intel_drv.h" 35 #include <drm/i915_drm.h> 36 #include "i915_drv.h" 37 38 /* Here's the desired hotplug mode */ 39 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 44 ADPA_CRT_HOTPLUG_ENABLE) 45 46 struct intel_crt { 47 struct intel_encoder base; 48 /* DPMS state is stored in the connector, which we need in the 49 * encoder's enable/disable callbacks */ 50 struct intel_connector *connector; 51 bool force_hotplug_required; 52 i915_reg_t adpa_reg; 53 }; 54 55 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 56 { 57 return container_of(encoder, struct intel_crt, base); 58 } 59 60 static struct intel_crt *intel_attached_crt(struct drm_connector *connector) 61 { 62 return intel_encoder_to_crt(intel_attached_encoder(connector)); 63 } 64 65 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 66 enum i915_pipe *pipe) 67 { 68 struct drm_device *dev = encoder->base.dev; 69 struct drm_i915_private *dev_priv = dev->dev_private; 70 struct intel_crt *crt = intel_encoder_to_crt(encoder); 71 enum intel_display_power_domain power_domain; 72 u32 tmp; 73 bool ret; 74 75 power_domain = intel_display_port_power_domain(encoder); 76 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) 77 return false; 78 79 ret = false; 80 81 tmp = I915_READ(crt->adpa_reg); 82 83 if (!(tmp & ADPA_DAC_ENABLE)) 84 goto out; 85 86 if (HAS_PCH_CPT(dev)) 87 *pipe = PORT_TO_PIPE_CPT(tmp); 88 else 89 *pipe = PORT_TO_PIPE(tmp); 90 91 ret = true; 92 out: 93 intel_display_power_put(dev_priv, power_domain); 94 95 return ret; 96 } 97 98 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 99 { 100 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 101 struct intel_crt *crt = intel_encoder_to_crt(encoder); 102 u32 tmp, flags = 0; 103 104 tmp = I915_READ(crt->adpa_reg); 105 106 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 107 flags |= DRM_MODE_FLAG_PHSYNC; 108 else 109 flags |= DRM_MODE_FLAG_NHSYNC; 110 111 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 112 flags |= DRM_MODE_FLAG_PVSYNC; 113 else 114 flags |= DRM_MODE_FLAG_NVSYNC; 115 116 return flags; 117 } 118 119 static void intel_crt_get_config(struct intel_encoder *encoder, 120 struct intel_crtc_state *pipe_config) 121 { 122 struct drm_device *dev = encoder->base.dev; 123 int dotclock; 124 125 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 126 127 dotclock = pipe_config->port_clock; 128 129 if (HAS_PCH_SPLIT(dev)) 130 ironlake_check_encoder_dotclock(pipe_config, dotclock); 131 132 pipe_config->base.adjusted_mode.crtc_clock = dotclock; 133 } 134 135 static void hsw_crt_get_config(struct intel_encoder *encoder, 136 struct intel_crtc_state *pipe_config) 137 { 138 intel_ddi_get_config(encoder, pipe_config); 139 140 pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 141 DRM_MODE_FLAG_NHSYNC | 142 DRM_MODE_FLAG_PVSYNC | 143 DRM_MODE_FLAG_NVSYNC); 144 pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); 145 } 146 147 /* Note: The caller is required to filter out dpms modes not supported by the 148 * platform. */ 149 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) 150 { 151 struct drm_device *dev = encoder->base.dev; 152 struct drm_i915_private *dev_priv = dev->dev_private; 153 struct intel_crt *crt = intel_encoder_to_crt(encoder); 154 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); 155 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 156 u32 adpa; 157 158 if (INTEL_INFO(dev)->gen >= 5) 159 adpa = ADPA_HOTPLUG_BITS; 160 else 161 adpa = 0; 162 163 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 164 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 165 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 166 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 167 168 /* For CPT allow 3 pipe config, for others just use A or B */ 169 if (HAS_PCH_LPT(dev)) 170 ; /* Those bits don't exist here */ 171 else if (HAS_PCH_CPT(dev)) 172 adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); 173 else if (crtc->pipe == 0) 174 adpa |= ADPA_PIPE_A_SELECT; 175 else 176 adpa |= ADPA_PIPE_B_SELECT; 177 178 if (!HAS_PCH_SPLIT(dev)) 179 I915_WRITE(BCLRPAT(crtc->pipe), 0); 180 181 switch (mode) { 182 case DRM_MODE_DPMS_ON: 183 adpa |= ADPA_DAC_ENABLE; 184 break; 185 case DRM_MODE_DPMS_STANDBY: 186 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 187 break; 188 case DRM_MODE_DPMS_SUSPEND: 189 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 190 break; 191 case DRM_MODE_DPMS_OFF: 192 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 193 break; 194 } 195 196 I915_WRITE(crt->adpa_reg, adpa); 197 } 198 199 static void intel_disable_crt(struct intel_encoder *encoder) 200 { 201 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); 202 } 203 204 static void pch_disable_crt(struct intel_encoder *encoder) 205 { 206 } 207 208 static void pch_post_disable_crt(struct intel_encoder *encoder) 209 { 210 intel_disable_crt(encoder); 211 } 212 213 static void intel_enable_crt(struct intel_encoder *encoder) 214 { 215 intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON); 216 } 217 218 static enum drm_mode_status 219 intel_crt_mode_valid(struct drm_connector *connector, 220 struct drm_display_mode *mode) 221 { 222 struct drm_device *dev = connector->dev; 223 int max_dotclk = to_i915(dev)->max_dotclk_freq; 224 225 int max_clock = 0; 226 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 227 return MODE_NO_DBLESCAN; 228 229 if (mode->clock < 25000) 230 return MODE_CLOCK_LOW; 231 232 if (IS_GEN2(dev)) 233 max_clock = 350000; 234 else 235 max_clock = 400000; 236 if (mode->clock > max_clock) 237 return MODE_CLOCK_HIGH; 238 239 if (mode->clock > max_dotclk) 240 return MODE_CLOCK_HIGH; 241 242 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 243 if (HAS_PCH_LPT(dev) && 244 (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) 245 return MODE_CLOCK_HIGH; 246 247 return MODE_OK; 248 } 249 250 static bool intel_crt_compute_config(struct intel_encoder *encoder, 251 struct intel_crtc_state *pipe_config) 252 { 253 struct drm_device *dev = encoder->base.dev; 254 255 if (HAS_PCH_SPLIT(dev)) 256 pipe_config->has_pch_encoder = true; 257 258 /* LPT FDI RX only supports 8bpc. */ 259 if (HAS_PCH_LPT(dev)) { 260 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 261 DRM_DEBUG_KMS("LPT only supports 24bpp\n"); 262 return false; 263 } 264 265 pipe_config->pipe_bpp = 24; 266 } 267 268 /* FDI must always be 2.7 GHz */ 269 if (HAS_DDI(dev)) { 270 pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; 271 pipe_config->port_clock = 135000 * 2; 272 273 pipe_config->dpll_hw_state.wrpll = 0; 274 pipe_config->dpll_hw_state.spll = 275 SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC; 276 } 277 278 return true; 279 } 280 281 static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) 282 { 283 struct drm_device *dev = connector->dev; 284 struct intel_crt *crt = intel_attached_crt(connector); 285 struct drm_i915_private *dev_priv = dev->dev_private; 286 u32 adpa; 287 bool ret; 288 289 /* The first time through, trigger an explicit detection cycle */ 290 if (crt->force_hotplug_required) { 291 bool turn_off_dac = HAS_PCH_SPLIT(dev); 292 u32 save_adpa; 293 294 crt->force_hotplug_required = 0; 295 296 save_adpa = adpa = I915_READ(crt->adpa_reg); 297 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 298 299 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 300 if (turn_off_dac) 301 adpa &= ~ADPA_DAC_ENABLE; 302 303 I915_WRITE(crt->adpa_reg, adpa); 304 305 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 306 1000)) 307 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 308 309 if (turn_off_dac) { 310 I915_WRITE(crt->adpa_reg, save_adpa); 311 POSTING_READ(crt->adpa_reg); 312 } 313 } 314 315 /* Check the status to see if both blue and green are on now */ 316 adpa = I915_READ(crt->adpa_reg); 317 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 318 ret = true; 319 else 320 ret = false; 321 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 322 323 return ret; 324 } 325 326 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 327 { 328 struct drm_device *dev = connector->dev; 329 struct intel_crt *crt = intel_attached_crt(connector); 330 struct drm_i915_private *dev_priv = dev->dev_private; 331 u32 adpa; 332 bool ret; 333 u32 save_adpa; 334 335 save_adpa = adpa = I915_READ(crt->adpa_reg); 336 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 337 338 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 339 340 I915_WRITE(crt->adpa_reg, adpa); 341 342 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, 343 1000)) { 344 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 345 I915_WRITE(crt->adpa_reg, save_adpa); 346 } 347 348 /* Check the status to see if both blue and green are on now */ 349 adpa = I915_READ(crt->adpa_reg); 350 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 351 ret = true; 352 else 353 ret = false; 354 355 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 356 357 return ret; 358 } 359 360 /** 361 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. 362 * 363 * Not for i915G/i915GM 364 * 365 * \return true if CRT is connected. 366 * \return false if CRT is disconnected. 367 */ 368 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 369 { 370 struct drm_device *dev = connector->dev; 371 struct drm_i915_private *dev_priv = dev->dev_private; 372 u32 stat; 373 bool ret = false; 374 int i, tries = 0; 375 376 if (HAS_PCH_SPLIT(dev)) 377 return intel_ironlake_crt_detect_hotplug(connector); 378 379 if (IS_VALLEYVIEW(dev)) 380 return valleyview_crt_detect_hotplug(connector); 381 382 /* 383 * On 4 series desktop, CRT detect sequence need to be done twice 384 * to get a reliable result. 385 */ 386 387 if (IS_G4X(dev) && !IS_GM45(dev)) 388 tries = 2; 389 else 390 tries = 1; 391 392 for (i = 0; i < tries ; i++) { 393 /* turn on the FORCE_DETECT */ 394 i915_hotplug_interrupt_update(dev_priv, 395 CRT_HOTPLUG_FORCE_DETECT, 396 CRT_HOTPLUG_FORCE_DETECT); 397 /* wait for FORCE_DETECT to go off */ 398 if (wait_for((I915_READ(PORT_HOTPLUG_EN) & 399 CRT_HOTPLUG_FORCE_DETECT) == 0, 400 1000)) 401 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 402 } 403 404 stat = I915_READ(PORT_HOTPLUG_STAT); 405 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 406 ret = true; 407 408 /* clear the interrupt we just generated, if any */ 409 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 410 411 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 412 413 return ret; 414 } 415 416 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 417 struct i2c_adapter *i2c) 418 { 419 struct edid *edid; 420 421 edid = drm_get_edid(connector, i2c); 422 423 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 424 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 425 intel_gmbus_force_bit(i2c, true); 426 edid = drm_get_edid(connector, i2c); 427 intel_gmbus_force_bit(i2c, false); 428 } 429 430 return edid; 431 } 432 433 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 434 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 435 struct i2c_adapter *adapter) 436 { 437 struct edid *edid; 438 int ret; 439 440 edid = intel_crt_get_edid(connector, adapter); 441 if (!edid) 442 return 0; 443 444 ret = intel_connector_update_modes(connector, edid); 445 kfree(edid); 446 447 return ret; 448 } 449 450 static bool intel_crt_detect_ddc(struct drm_connector *connector) 451 { 452 struct intel_crt *crt = intel_attached_crt(connector); 453 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; 454 struct edid *edid; 455 struct i2c_adapter *i2c; 456 457 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 458 459 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 460 edid = intel_crt_get_edid(connector, i2c); 461 462 if (edid) { 463 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 464 465 /* 466 * This may be a DVI-I connector with a shared DDC 467 * link between analog and digital outputs, so we 468 * have to check the EDID input spec of the attached device. 469 */ 470 if (!is_digital) { 471 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 472 return true; 473 } 474 475 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 476 } else { 477 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 478 } 479 480 kfree(edid); 481 482 return false; 483 } 484 485 static enum drm_connector_status 486 intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) 487 { 488 struct drm_device *dev = crt->base.base.dev; 489 struct drm_i915_private *dev_priv = dev->dev_private; 490 uint32_t save_bclrpat; 491 uint32_t save_vtotal; 492 uint32_t vtotal, vactive; 493 uint32_t vsample; 494 uint32_t vblank, vblank_start, vblank_end; 495 uint32_t dsl; 496 i915_reg_t bclrpat_reg, vtotal_reg, 497 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 498 uint8_t st00; 499 enum drm_connector_status status; 500 501 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 502 503 bclrpat_reg = BCLRPAT(pipe); 504 vtotal_reg = VTOTAL(pipe); 505 vblank_reg = VBLANK(pipe); 506 vsync_reg = VSYNC(pipe); 507 pipeconf_reg = PIPECONF(pipe); 508 pipe_dsl_reg = PIPEDSL(pipe); 509 510 save_bclrpat = I915_READ(bclrpat_reg); 511 save_vtotal = I915_READ(vtotal_reg); 512 vblank = I915_READ(vblank_reg); 513 514 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 515 vactive = (save_vtotal & 0x7ff) + 1; 516 517 vblank_start = (vblank & 0xfff) + 1; 518 vblank_end = ((vblank >> 16) & 0xfff) + 1; 519 520 /* Set the border color to purple. */ 521 I915_WRITE(bclrpat_reg, 0x500050); 522 523 if (!IS_GEN2(dev)) { 524 uint32_t pipeconf = I915_READ(pipeconf_reg); 525 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); 526 POSTING_READ(pipeconf_reg); 527 /* Wait for next Vblank to substitue 528 * border color for Color info */ 529 intel_wait_for_vblank(dev, pipe); 530 st00 = I915_READ8(_VGA_MSR_WRITE); 531 status = ((st00 & (1 << 4)) != 0) ? 532 connector_status_connected : 533 connector_status_disconnected; 534 535 I915_WRITE(pipeconf_reg, pipeconf); 536 } else { 537 bool restore_vblank = false; 538 int count, detect; 539 540 /* 541 * If there isn't any border, add some. 542 * Yes, this will flicker 543 */ 544 if (vblank_start <= vactive && vblank_end >= vtotal) { 545 uint32_t vsync = I915_READ(vsync_reg); 546 uint32_t vsync_start = (vsync & 0xffff) + 1; 547 548 vblank_start = vsync_start; 549 I915_WRITE(vblank_reg, 550 (vblank_start - 1) | 551 ((vblank_end - 1) << 16)); 552 restore_vblank = true; 553 } 554 /* sample in the vertical border, selecting the larger one */ 555 if (vblank_start - vactive >= vtotal - vblank_end) 556 vsample = (vblank_start + vactive) >> 1; 557 else 558 vsample = (vtotal + vblank_end) >> 1; 559 560 /* 561 * Wait for the border to be displayed 562 */ 563 while (I915_READ(pipe_dsl_reg) >= vactive) 564 ; 565 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) 566 ; 567 /* 568 * Watch ST00 for an entire scanline 569 */ 570 detect = 0; 571 count = 0; 572 do { 573 count++; 574 /* Read the ST00 VGA status register */ 575 st00 = I915_READ8(_VGA_MSR_WRITE); 576 if (st00 & (1 << 4)) 577 detect++; 578 } while ((I915_READ(pipe_dsl_reg) == dsl)); 579 580 /* restore vblank if necessary */ 581 if (restore_vblank) 582 I915_WRITE(vblank_reg, vblank); 583 /* 584 * If more than 3/4 of the scanline detected a monitor, 585 * then it is assumed to be present. This works even on i830, 586 * where there isn't any way to force the border color across 587 * the screen 588 */ 589 status = detect * 4 > count * 3 ? 590 connector_status_connected : 591 connector_status_disconnected; 592 } 593 594 /* Restore previous settings */ 595 I915_WRITE(bclrpat_reg, save_bclrpat); 596 597 return status; 598 } 599 600 static enum drm_connector_status 601 intel_crt_detect(struct drm_connector *connector, bool force) 602 { 603 struct drm_device *dev = connector->dev; 604 struct drm_i915_private *dev_priv = dev->dev_private; 605 struct intel_crt *crt = intel_attached_crt(connector); 606 struct intel_encoder *intel_encoder = &crt->base; 607 enum intel_display_power_domain power_domain; 608 enum drm_connector_status status; 609 struct intel_load_detect_pipe tmp; 610 struct drm_modeset_acquire_ctx ctx; 611 612 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 613 connector->base.id, connector->name, 614 force); 615 616 power_domain = intel_display_port_power_domain(intel_encoder); 617 intel_display_power_get(dev_priv, power_domain); 618 619 if (I915_HAS_HOTPLUG(dev)) { 620 /* We can not rely on the HPD pin always being correctly wired 621 * up, for example many KVM do not pass it through, and so 622 * only trust an assertion that the monitor is connected. 623 */ 624 if (intel_crt_detect_hotplug(connector)) { 625 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 626 status = connector_status_connected; 627 goto out; 628 } else 629 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 630 } 631 632 if (intel_crt_detect_ddc(connector)) { 633 status = connector_status_connected; 634 goto out; 635 } 636 637 /* Load detection is broken on HPD capable machines. Whoever wants a 638 * broken monitor (without edid) to work behind a broken kvm (that fails 639 * to have the right resistors for HP detection) needs to fix this up. 640 * For now just bail out. */ 641 if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { 642 status = connector_status_disconnected; 643 goto out; 644 } 645 646 if (!force) { 647 status = connector->status; 648 goto out; 649 } 650 651 drm_modeset_acquire_init(&ctx, 0); 652 653 /* for pre-945g platforms use load detect */ 654 if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { 655 if (intel_crt_detect_ddc(connector)) 656 status = connector_status_connected; 657 else if (INTEL_INFO(dev)->gen < 4) 658 status = intel_crt_load_detect(crt, 659 to_intel_crtc(connector->state->crtc)->pipe); 660 else 661 status = connector_status_unknown; 662 intel_release_load_detect_pipe(connector, &tmp, &ctx); 663 } else 664 status = connector_status_unknown; 665 666 drm_modeset_drop_locks(&ctx); 667 drm_modeset_acquire_fini(&ctx); 668 669 out: 670 intel_display_power_put(dev_priv, power_domain); 671 return status; 672 } 673 674 static void intel_crt_destroy(struct drm_connector *connector) 675 { 676 drm_connector_cleanup(connector); 677 kfree(connector); 678 } 679 680 static int intel_crt_get_modes(struct drm_connector *connector) 681 { 682 struct drm_device *dev = connector->dev; 683 struct drm_i915_private *dev_priv = dev->dev_private; 684 struct intel_crt *crt = intel_attached_crt(connector); 685 struct intel_encoder *intel_encoder = &crt->base; 686 enum intel_display_power_domain power_domain; 687 int ret; 688 struct i2c_adapter *i2c; 689 690 power_domain = intel_display_port_power_domain(intel_encoder); 691 intel_display_power_get(dev_priv, power_domain); 692 693 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 694 ret = intel_crt_ddc_get_modes(connector, i2c); 695 if (ret || !IS_G4X(dev)) 696 goto out; 697 698 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 699 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 700 ret = intel_crt_ddc_get_modes(connector, i2c); 701 702 out: 703 intel_display_power_put(dev_priv, power_domain); 704 705 return ret; 706 } 707 708 static int intel_crt_set_property(struct drm_connector *connector, 709 struct drm_property *property, 710 uint64_t value) 711 { 712 return 0; 713 } 714 715 static void intel_crt_reset(struct drm_connector *connector) 716 { 717 struct drm_device *dev = connector->dev; 718 struct drm_i915_private *dev_priv = dev->dev_private; 719 struct intel_crt *crt = intel_attached_crt(connector); 720 721 if (INTEL_INFO(dev)->gen >= 5) { 722 u32 adpa; 723 724 adpa = I915_READ(crt->adpa_reg); 725 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 726 adpa |= ADPA_HOTPLUG_BITS; 727 I915_WRITE(crt->adpa_reg, adpa); 728 POSTING_READ(crt->adpa_reg); 729 730 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 731 crt->force_hotplug_required = 1; 732 } 733 734 } 735 736 /* 737 * Routines for controlling stuff on the analog port 738 */ 739 740 static const struct drm_connector_funcs intel_crt_connector_funcs = { 741 .reset = intel_crt_reset, 742 .dpms = drm_atomic_helper_connector_dpms, 743 .detect = intel_crt_detect, 744 .fill_modes = drm_helper_probe_single_connector_modes, 745 .destroy = intel_crt_destroy, 746 .set_property = intel_crt_set_property, 747 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 748 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 749 .atomic_get_property = intel_connector_atomic_get_property, 750 }; 751 752 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 753 .mode_valid = intel_crt_mode_valid, 754 .get_modes = intel_crt_get_modes, 755 .best_encoder = intel_best_encoder, 756 }; 757 758 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 759 .destroy = intel_encoder_destroy, 760 }; 761 762 static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) 763 { 764 DRM_INFO("Skipping CRT initialization for %s\n", id->ident); 765 return 1; 766 } 767 768 static const struct dmi_system_id intel_no_crt[] = { 769 { 770 .callback = intel_no_crt_dmi_callback, 771 .ident = "ACER ZGB", 772 .matches = { 773 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 774 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 775 }, 776 }, 777 { 778 .callback = intel_no_crt_dmi_callback, 779 .ident = "DELL XPS 8700", 780 .matches = { 781 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), 782 DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), 783 }, 784 }, 785 { } 786 }; 787 788 void intel_crt_init(struct drm_device *dev) 789 { 790 struct drm_connector *connector; 791 struct intel_crt *crt; 792 struct intel_connector *intel_connector; 793 struct drm_i915_private *dev_priv = dev->dev_private; 794 i915_reg_t adpa_reg; 795 u32 adpa; 796 797 /* Skip machines without VGA that falsely report hotplug events */ 798 if (dmi_check_system(intel_no_crt)) 799 return; 800 801 if (HAS_PCH_SPLIT(dev)) 802 adpa_reg = PCH_ADPA; 803 else if (IS_VALLEYVIEW(dev)) 804 adpa_reg = VLV_ADPA; 805 else 806 adpa_reg = ADPA; 807 808 adpa = I915_READ(adpa_reg); 809 if ((adpa & ADPA_DAC_ENABLE) == 0) { 810 /* 811 * On some machines (some IVB at least) CRT can be 812 * fused off, but there's no known fuse bit to 813 * indicate that. On these machine the ADPA register 814 * works normally, except the DAC enable bit won't 815 * take. So the only way to tell is attempt to enable 816 * it and see what happens. 817 */ 818 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | 819 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 820 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) 821 return; 822 I915_WRITE(adpa_reg, adpa); 823 } 824 825 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 826 if (!crt) 827 return; 828 829 intel_connector = intel_connector_alloc(); 830 if (!intel_connector) { 831 kfree(crt); 832 return; 833 } 834 835 connector = &intel_connector->base; 836 crt->connector = intel_connector; 837 drm_connector_init(dev, &intel_connector->base, 838 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 839 840 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, 841 DRM_MODE_ENCODER_DAC, NULL); 842 843 intel_connector_attach_encoder(intel_connector, &crt->base); 844 845 crt->base.type = INTEL_OUTPUT_ANALOG; 846 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 847 if (IS_I830(dev)) 848 crt->base.crtc_mask = (1 << 0); 849 else 850 crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 851 852 if (IS_GEN2(dev)) 853 connector->interlace_allowed = 0; 854 else 855 connector->interlace_allowed = 1; 856 connector->doublescan_allowed = 0; 857 858 crt->adpa_reg = adpa_reg; 859 860 crt->base.compute_config = intel_crt_compute_config; 861 if (HAS_PCH_SPLIT(dev)) { 862 crt->base.disable = pch_disable_crt; 863 crt->base.post_disable = pch_post_disable_crt; 864 } else { 865 crt->base.disable = intel_disable_crt; 866 } 867 crt->base.enable = intel_enable_crt; 868 if (I915_HAS_HOTPLUG(dev)) 869 crt->base.hpd_pin = HPD_CRT; 870 if (HAS_DDI(dev)) { 871 crt->base.get_config = hsw_crt_get_config; 872 crt->base.get_hw_state = intel_ddi_get_hw_state; 873 } else { 874 crt->base.get_config = intel_crt_get_config; 875 crt->base.get_hw_state = intel_crt_get_hw_state; 876 } 877 intel_connector->get_hw_state = intel_connector_get_hw_state; 878 intel_connector->unregister = intel_connector_unregister; 879 880 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 881 882 drm_connector_register(connector); 883 884 if (!I915_HAS_HOTPLUG(dev)) 885 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 886 887 /* 888 * Configure the automatic hotplug detection stuff 889 */ 890 crt->force_hotplug_required = 0; 891 892 /* 893 * TODO: find a proper way to discover whether we need to set the the 894 * polarity and link reversal bits or not, instead of relying on the 895 * BIOS. 896 */ 897 if (HAS_PCH_LPT(dev)) { 898 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 899 FDI_RX_LINK_REVERSAL_OVERRIDE; 900 901 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; 902 } 903 904 intel_crt_reset(connector); 905 } 906