1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include <linux/kernel.h> 25 #include <drm/i915_component.h> 26 #include "intel_drv.h" 27 28 #include <drm/drmP.h> 29 #include <drm/drm_edid.h> 30 #include "i915_drv.h" 31 32 /** 33 * DOC: High Definition Audio over HDMI and Display Port 34 * 35 * The graphics and audio drivers together support High Definition Audio over 36 * HDMI and Display Port. The audio programming sequences are divided into audio 37 * codec and controller enable and disable sequences. The graphics driver 38 * handles the audio codec sequences, while the audio driver handles the audio 39 * controller sequences. 40 * 41 * The disable sequences must be performed before disabling the transcoder or 42 * port. The enable sequences may only be performed after enabling the 43 * transcoder and port, and after completed link training. Therefore the audio 44 * enable/disable sequences are part of the modeset sequence. 45 * 46 * The codec and controller sequences could be done either parallel or serial, 47 * but generally the ELDV/PD change in the codec sequence indicates to the audio 48 * driver that the controller sequence should start. Indeed, most of the 49 * co-operation between the graphics and audio drivers is handled via audio 50 * related registers. (The notable exception is the power management, not 51 * covered here.) 52 * 53 * The struct i915_audio_component is used to interact between the graphics 54 * and audio drivers. The struct i915_audio_component_ops *ops in it is 55 * defined in graphics driver and called in audio driver. The 56 * struct i915_audio_component_audio_ops *audio_ops is called from i915 driver. 57 */ 58 59 static const struct { 60 int clock; 61 u32 config; 62 } hdmi_audio_clock[] = { 63 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, 64 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ 65 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, 66 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, 67 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, 68 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, 69 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, 70 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, 71 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, 72 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, 73 }; 74 75 /* HDMI N/CTS table */ 76 #define TMDS_297M 297000 77 #define TMDS_296M 296703 78 static const struct { 79 int sample_rate; 80 int clock; 81 int n; 82 int cts; 83 } aud_ncts[] = { 84 { 44100, TMDS_296M, 4459, 234375 }, 85 { 44100, TMDS_297M, 4704, 247500 }, 86 { 48000, TMDS_296M, 5824, 281250 }, 87 { 48000, TMDS_297M, 5120, 247500 }, 88 { 32000, TMDS_296M, 5824, 421875 }, 89 { 32000, TMDS_297M, 3072, 222750 }, 90 { 88200, TMDS_296M, 8918, 234375 }, 91 { 88200, TMDS_297M, 9408, 247500 }, 92 { 96000, TMDS_296M, 11648, 281250 }, 93 { 96000, TMDS_297M, 10240, 247500 }, 94 { 176400, TMDS_296M, 17836, 234375 }, 95 { 176400, TMDS_297M, 18816, 247500 }, 96 { 192000, TMDS_296M, 23296, 281250 }, 97 { 192000, TMDS_297M, 20480, 247500 }, 98 }; 99 100 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ 101 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode) 102 { 103 int i; 104 105 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { 106 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) 107 break; 108 } 109 110 if (i == ARRAY_SIZE(hdmi_audio_clock)) { 111 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", 112 adjusted_mode->crtc_clock); 113 i = 1; 114 } 115 116 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", 117 hdmi_audio_clock[i].clock, 118 hdmi_audio_clock[i].config); 119 120 return hdmi_audio_clock[i].config; 121 } 122 123 static int audio_config_get_n(const struct drm_display_mode *mode, int rate) 124 { 125 int i; 126 127 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) { 128 if ((rate == aud_ncts[i].sample_rate) && 129 (mode->clock == aud_ncts[i].clock)) { 130 return aud_ncts[i].n; 131 } 132 } 133 return 0; 134 } 135 136 static uint32_t audio_config_setup_n_reg(int n, uint32_t val) 137 { 138 int n_low, n_up; 139 uint32_t tmp = val; 140 141 n_low = n & 0xfff; 142 n_up = (n >> 12) & 0xff; 143 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK); 144 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) | 145 (n_low << AUD_CONFIG_LOWER_N_SHIFT) | 146 AUD_CONFIG_N_PROG_ENABLE); 147 return tmp; 148 } 149 150 /* check whether N/CTS/M need be set manually */ 151 static bool audio_rate_need_prog(struct intel_crtc *crtc, 152 const struct drm_display_mode *mode) 153 { 154 if (((mode->clock == TMDS_297M) || 155 (mode->clock == TMDS_296M)) && 156 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) 157 return true; 158 else 159 return false; 160 } 161 162 static bool intel_eld_uptodate(struct drm_connector *connector, 163 i915_reg_t reg_eldv, uint32_t bits_eldv, 164 i915_reg_t reg_elda, uint32_t bits_elda, 165 i915_reg_t reg_edid) 166 { 167 struct drm_i915_private *dev_priv = connector->dev->dev_private; 168 uint8_t *eld = connector->eld; 169 uint32_t tmp; 170 int i; 171 172 tmp = I915_READ(reg_eldv); 173 tmp &= bits_eldv; 174 175 if (!tmp) 176 return false; 177 178 tmp = I915_READ(reg_elda); 179 tmp &= ~bits_elda; 180 I915_WRITE(reg_elda, tmp); 181 182 for (i = 0; i < drm_eld_size(eld) / 4; i++) 183 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) 184 return false; 185 186 return true; 187 } 188 189 static void g4x_audio_codec_disable(struct intel_encoder *encoder) 190 { 191 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 192 uint32_t eldv, tmp; 193 194 DRM_DEBUG_KMS("Disable audio codec\n"); 195 196 tmp = I915_READ(G4X_AUD_VID_DID); 197 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 198 eldv = G4X_ELDV_DEVCL_DEVBLC; 199 else 200 eldv = G4X_ELDV_DEVCTG; 201 202 /* Invalidate ELD */ 203 tmp = I915_READ(G4X_AUD_CNTL_ST); 204 tmp &= ~eldv; 205 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 206 } 207 208 static void g4x_audio_codec_enable(struct drm_connector *connector, 209 struct intel_encoder *encoder, 210 const struct drm_display_mode *adjusted_mode) 211 { 212 struct drm_i915_private *dev_priv = connector->dev->dev_private; 213 uint8_t *eld = connector->eld; 214 uint32_t eldv; 215 uint32_t tmp; 216 int len, i; 217 218 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]); 219 220 tmp = I915_READ(G4X_AUD_VID_DID); 221 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) 222 eldv = G4X_ELDV_DEVCL_DEVBLC; 223 else 224 eldv = G4X_ELDV_DEVCTG; 225 226 if (intel_eld_uptodate(connector, 227 G4X_AUD_CNTL_ST, eldv, 228 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, 229 G4X_HDMIW_HDMIEDID)) 230 return; 231 232 tmp = I915_READ(G4X_AUD_CNTL_ST); 233 tmp &= ~(eldv | G4X_ELD_ADDR_MASK); 234 len = (tmp >> 9) & 0x1f; /* ELD buffer size */ 235 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 236 237 len = min(drm_eld_size(eld) / 4, len); 238 DRM_DEBUG_DRIVER("ELD size %d\n", len); 239 for (i = 0; i < len; i++) 240 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); 241 242 tmp = I915_READ(G4X_AUD_CNTL_ST); 243 tmp |= eldv; 244 I915_WRITE(G4X_AUD_CNTL_ST, tmp); 245 } 246 247 static void hsw_audio_codec_disable(struct intel_encoder *encoder) 248 { 249 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 250 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 251 enum i915_pipe pipe = intel_crtc->pipe; 252 uint32_t tmp; 253 254 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); 255 256 mutex_lock(&dev_priv->av_mutex); 257 258 /* Disable timestamps */ 259 tmp = I915_READ(HSW_AUD_CFG(pipe)); 260 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 261 tmp |= AUD_CONFIG_N_PROG_ENABLE; 262 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 263 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 264 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) || 265 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST)) 266 tmp |= AUD_CONFIG_N_VALUE_INDEX; 267 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 268 269 /* Invalidate ELD */ 270 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 271 tmp &= ~AUDIO_ELD_VALID(pipe); 272 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe); 273 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 274 275 mutex_unlock(&dev_priv->av_mutex); 276 } 277 278 static void hsw_audio_codec_enable(struct drm_connector *connector, 279 struct intel_encoder *encoder, 280 const struct drm_display_mode *adjusted_mode) 281 { 282 struct drm_i915_private *dev_priv = connector->dev->dev_private; 283 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 284 enum i915_pipe pipe = intel_crtc->pipe; 285 struct i915_audio_component *acomp = dev_priv->audio_component; 286 const uint8_t *eld = connector->eld; 287 struct intel_digital_port *intel_dig_port = 288 enc_to_dig_port(&encoder->base); 289 enum port port = intel_dig_port->port; 290 uint32_t tmp; 291 int len, i; 292 int n, rate; 293 294 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", 295 pipe_name(pipe), drm_eld_size(eld)); 296 297 mutex_lock(&dev_priv->av_mutex); 298 299 /* Enable audio presence detect, invalidate ELD */ 300 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 301 tmp |= AUDIO_OUTPUT_ENABLE(pipe); 302 tmp &= ~AUDIO_ELD_VALID(pipe); 303 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 304 305 /* 306 * FIXME: We're supposed to wait for vblank here, but we have vblanks 307 * disabled during the mode set. The proper fix would be to push the 308 * rest of the setup into a vblank work item, queued here, but the 309 * infrastructure is not there yet. 310 */ 311 312 /* Reset ELD write address */ 313 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); 314 tmp &= ~IBX_ELD_ADDRESS_MASK; 315 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); 316 317 /* Up to 84 bytes of hw ELD buffer */ 318 len = min(drm_eld_size(eld), 84); 319 for (i = 0; i < len / 4; i++) 320 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const uint32_t *)eld + i)); 321 322 /* ELD valid */ 323 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); 324 tmp |= AUDIO_ELD_VALID(pipe); 325 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); 326 327 /* Enable timestamps */ 328 tmp = I915_READ(HSW_AUD_CFG(pipe)); 329 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 330 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 331 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 332 tmp |= AUD_CONFIG_N_VALUE_INDEX; 333 else 334 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); 335 336 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 337 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) { 338 if (!acomp) 339 rate = 0; 340 else if (port >= PORT_A && port <= PORT_E) 341 rate = acomp->aud_sample_rate[port]; 342 else { 343 DRM_ERROR("invalid port: %d\n", port); 344 rate = 0; 345 } 346 n = audio_config_get_n(adjusted_mode, rate); 347 if (n != 0) 348 tmp = audio_config_setup_n_reg(n, tmp); 349 else 350 DRM_DEBUG_KMS("no suitable N value is found\n"); 351 } 352 353 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 354 355 mutex_unlock(&dev_priv->av_mutex); 356 } 357 358 static void ilk_audio_codec_disable(struct intel_encoder *encoder) 359 { 360 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 361 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 362 struct intel_digital_port *intel_dig_port = 363 enc_to_dig_port(&encoder->base); 364 enum port port = intel_dig_port->port; 365 enum i915_pipe pipe = intel_crtc->pipe; 366 uint32_t tmp, eldv; 367 i915_reg_t aud_config, aud_cntrl_st2; 368 369 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n", 370 port_name(port), pipe_name(pipe)); 371 372 if (WARN_ON(port == PORT_A)) 373 return; 374 375 if (HAS_PCH_IBX(dev_priv->dev)) { 376 aud_config = IBX_AUD_CFG(pipe); 377 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 378 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 379 aud_config = VLV_AUD_CFG(pipe); 380 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 381 } else { 382 aud_config = CPT_AUD_CFG(pipe); 383 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 384 } 385 386 /* Disable timestamps */ 387 tmp = I915_READ(aud_config); 388 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 389 tmp |= AUD_CONFIG_N_PROG_ENABLE; 390 tmp &= ~AUD_CONFIG_UPPER_N_MASK; 391 tmp &= ~AUD_CONFIG_LOWER_N_MASK; 392 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) 393 tmp |= AUD_CONFIG_N_VALUE_INDEX; 394 I915_WRITE(aud_config, tmp); 395 396 eldv = IBX_ELD_VALID(port); 397 398 /* Invalidate ELD */ 399 tmp = I915_READ(aud_cntrl_st2); 400 tmp &= ~eldv; 401 I915_WRITE(aud_cntrl_st2, tmp); 402 } 403 404 static void ilk_audio_codec_enable(struct drm_connector *connector, 405 struct intel_encoder *encoder, 406 const struct drm_display_mode *adjusted_mode) 407 { 408 struct drm_i915_private *dev_priv = connector->dev->dev_private; 409 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 410 struct intel_digital_port *intel_dig_port = 411 enc_to_dig_port(&encoder->base); 412 enum port port = intel_dig_port->port; 413 enum i915_pipe pipe = intel_crtc->pipe; 414 uint8_t *eld = connector->eld; 415 uint32_t eldv; 416 uint32_t tmp; 417 int len, i; 418 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2; 419 420 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", 421 port_name(port), pipe_name(pipe), drm_eld_size(eld)); 422 423 if (WARN_ON(port == PORT_A)) 424 return; 425 426 /* 427 * FIXME: We're supposed to wait for vblank here, but we have vblanks 428 * disabled during the mode set. The proper fix would be to push the 429 * rest of the setup into a vblank work item, queued here, but the 430 * infrastructure is not there yet. 431 */ 432 433 if (HAS_PCH_IBX(connector->dev)) { 434 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); 435 aud_config = IBX_AUD_CFG(pipe); 436 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); 437 aud_cntrl_st2 = IBX_AUD_CNTL_ST2; 438 } else if (IS_VALLEYVIEW(connector->dev) || 439 IS_CHERRYVIEW(connector->dev)) { 440 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); 441 aud_config = VLV_AUD_CFG(pipe); 442 aud_cntl_st = VLV_AUD_CNTL_ST(pipe); 443 aud_cntrl_st2 = VLV_AUD_CNTL_ST2; 444 } else { 445 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); 446 aud_config = CPT_AUD_CFG(pipe); 447 aud_cntl_st = CPT_AUD_CNTL_ST(pipe); 448 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; 449 } 450 451 eldv = IBX_ELD_VALID(port); 452 453 /* Invalidate ELD */ 454 tmp = I915_READ(aud_cntrl_st2); 455 tmp &= ~eldv; 456 I915_WRITE(aud_cntrl_st2, tmp); 457 458 /* Reset ELD write address */ 459 tmp = I915_READ(aud_cntl_st); 460 tmp &= ~IBX_ELD_ADDRESS_MASK; 461 I915_WRITE(aud_cntl_st, tmp); 462 463 /* Up to 84 bytes of hw ELD buffer */ 464 len = min(drm_eld_size(eld), 84); 465 for (i = 0; i < len / 4; i++) 466 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); 467 468 /* ELD valid */ 469 tmp = I915_READ(aud_cntrl_st2); 470 tmp |= eldv; 471 I915_WRITE(aud_cntrl_st2, tmp); 472 473 /* Enable timestamps */ 474 tmp = I915_READ(aud_config); 475 tmp &= ~AUD_CONFIG_N_VALUE_INDEX; 476 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 477 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; 478 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT) || 479 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DP_MST)) 480 tmp |= AUD_CONFIG_N_VALUE_INDEX; 481 else 482 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode); 483 I915_WRITE(aud_config, tmp); 484 } 485 486 /** 487 * intel_audio_codec_enable - Enable the audio codec for HD audio 488 * @intel_encoder: encoder on which to enable audio 489 * 490 * The enable sequences may only be performed after enabling the transcoder and 491 * port, and after completed link training. 492 */ 493 void intel_audio_codec_enable(struct intel_encoder *intel_encoder) 494 { 495 struct drm_encoder *encoder = &intel_encoder->base; 496 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); 497 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; 498 struct drm_connector *connector; 499 struct drm_device *dev = encoder->dev; 500 struct drm_i915_private *dev_priv = dev->dev_private; 501 struct i915_audio_component *acomp = dev_priv->audio_component; 502 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 503 enum port port = intel_dig_port->port; 504 505 connector = drm_select_eld(encoder); 506 if (!connector) 507 return; 508 509 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 510 connector->base.id, 511 connector->name, 512 connector->encoder->base.id, 513 connector->encoder->name); 514 515 /* ELD Conn_Type */ 516 connector->eld[5] &= ~(3 << 2); 517 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || 518 intel_pipe_has_type(crtc, INTEL_OUTPUT_DP_MST)) 519 connector->eld[5] |= (1 << 2); 520 521 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2; 522 523 if (dev_priv->display.audio_codec_enable) 524 dev_priv->display.audio_codec_enable(connector, intel_encoder, 525 adjusted_mode); 526 527 mutex_lock(&dev_priv->av_mutex); 528 intel_dig_port->audio_connector = connector; 529 /* referred in audio callbacks */ 530 dev_priv->dig_port_map[port] = intel_encoder; 531 mutex_unlock(&dev_priv->av_mutex); 532 533 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 534 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); 535 } 536 537 /** 538 * intel_audio_codec_disable - Disable the audio codec for HD audio 539 * @intel_encoder: encoder on which to disable audio 540 * 541 * The disable sequences must be performed before disabling the transcoder or 542 * port. 543 */ 544 void intel_audio_codec_disable(struct intel_encoder *intel_encoder) 545 { 546 struct drm_encoder *encoder = &intel_encoder->base; 547 struct drm_device *dev = encoder->dev; 548 struct drm_i915_private *dev_priv = dev->dev_private; 549 struct i915_audio_component *acomp = dev_priv->audio_component; 550 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 551 enum port port = intel_dig_port->port; 552 553 if (dev_priv->display.audio_codec_disable) 554 dev_priv->display.audio_codec_disable(intel_encoder); 555 556 mutex_lock(&dev_priv->av_mutex); 557 intel_dig_port->audio_connector = NULL; 558 dev_priv->dig_port_map[port] = NULL; 559 mutex_unlock(&dev_priv->av_mutex); 560 561 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) 562 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port); 563 } 564 565 /** 566 * intel_init_audio - Set up chip specific audio functions 567 * @dev: drm device 568 */ 569 void intel_init_audio(struct drm_device *dev) 570 { 571 struct drm_i915_private *dev_priv = dev->dev_private; 572 573 if (IS_G4X(dev)) { 574 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; 575 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable; 576 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { 577 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 578 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 579 } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { 580 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; 581 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; 582 } else if (HAS_PCH_SPLIT(dev)) { 583 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; 584 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; 585 } 586 } 587 588 static void i915_audio_component_get_power(struct device *dev) 589 { 590 intel_display_power_get(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 591 } 592 593 static void i915_audio_component_put_power(struct device *dev) 594 { 595 intel_display_power_put(dev_to_i915(dev), POWER_DOMAIN_AUDIO); 596 } 597 598 static void i915_audio_component_codec_wake_override(struct device *dev, 599 bool enable) 600 { 601 struct drm_i915_private *dev_priv = dev_to_i915(dev); 602 u32 tmp; 603 604 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv)) 605 return; 606 607 /* 608 * Enable/disable generating the codec wake signal, overriding the 609 * internal logic to generate the codec wake to controller. 610 */ 611 tmp = I915_READ(HSW_AUD_CHICKENBIT); 612 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL; 613 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 614 usleep_range(1000, 1500); 615 616 if (enable) { 617 tmp = I915_READ(HSW_AUD_CHICKENBIT); 618 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL; 619 I915_WRITE(HSW_AUD_CHICKENBIT, tmp); 620 usleep_range(1000, 1500); 621 } 622 } 623 624 /* Get CDCLK in kHz */ 625 static int i915_audio_component_get_cdclk_freq(struct device *dev) 626 { 627 struct drm_i915_private *dev_priv = dev_to_i915(dev); 628 int ret; 629 630 if (WARN_ON_ONCE(!HAS_DDI(dev_priv))) 631 return -ENODEV; 632 633 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); 634 ret = dev_priv->display.get_display_clock_speed(dev_priv->dev); 635 636 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); 637 638 return ret; 639 } 640 641 static int i915_audio_component_sync_audio_rate(struct device *dev, 642 int port, int rate) 643 { 644 struct drm_i915_private *dev_priv = dev_to_i915(dev); 645 struct intel_encoder *intel_encoder; 646 struct intel_crtc *crtc; 647 struct drm_display_mode *mode; 648 struct i915_audio_component *acomp = dev_priv->audio_component; 649 enum i915_pipe pipe = INVALID_PIPE; 650 u32 tmp; 651 int n; 652 int err = 0; 653 654 /* HSW, BDW, SKL, KBL need this fix */ 655 if (!IS_SKYLAKE(dev_priv) && 656 !IS_KABYLAKE(dev_priv) && 657 !IS_BROADWELL(dev_priv) && 658 !IS_HASWELL(dev_priv)) 659 return 0; 660 661 mutex_lock(&dev_priv->av_mutex); 662 /* 1. get the pipe */ 663 intel_encoder = dev_priv->dig_port_map[port]; 664 /* intel_encoder might be NULL for DP MST */ 665 if (!intel_encoder || !intel_encoder->base.crtc || 666 intel_encoder->type != INTEL_OUTPUT_HDMI) { 667 DRM_DEBUG_KMS("no valid port %c\n", port_name(port)); 668 err = -ENODEV; 669 goto unlock; 670 } 671 crtc = to_intel_crtc(intel_encoder->base.crtc); 672 pipe = crtc->pipe; 673 if (pipe == INVALID_PIPE) { 674 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port)); 675 err = -ENODEV; 676 goto unlock; 677 } 678 679 DRM_DEBUG_KMS("pipe %c connects port %c\n", 680 pipe_name(pipe), port_name(port)); 681 mode = &crtc->config->base.adjusted_mode; 682 683 /* port must be valid now, otherwise the pipe will be invalid */ 684 acomp->aud_sample_rate[port] = rate; 685 686 /* 2. check whether to set the N/CTS/M manually or not */ 687 if (!audio_rate_need_prog(crtc, mode)) { 688 tmp = I915_READ(HSW_AUD_CFG(pipe)); 689 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 690 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 691 goto unlock; 692 } 693 694 n = audio_config_get_n(mode, rate); 695 if (n == 0) { 696 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n", 697 port_name(port)); 698 tmp = I915_READ(HSW_AUD_CFG(pipe)); 699 tmp &= ~AUD_CONFIG_N_PROG_ENABLE; 700 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 701 goto unlock; 702 } 703 704 /* 3. set the N/CTS/M */ 705 tmp = I915_READ(HSW_AUD_CFG(pipe)); 706 tmp = audio_config_setup_n_reg(n, tmp); 707 I915_WRITE(HSW_AUD_CFG(pipe), tmp); 708 709 unlock: 710 mutex_unlock(&dev_priv->av_mutex); 711 return err; 712 } 713 714 static int i915_audio_component_get_eld(struct device *dev, int port, 715 bool *enabled, 716 unsigned char *buf, int max_bytes) 717 { 718 struct drm_i915_private *dev_priv = dev_to_i915(dev); 719 struct intel_encoder *intel_encoder; 720 struct intel_digital_port *intel_dig_port; 721 const u8 *eld; 722 int ret = -EINVAL; 723 724 mutex_lock(&dev_priv->av_mutex); 725 intel_encoder = dev_priv->dig_port_map[port]; 726 /* intel_encoder might be NULL for DP MST */ 727 if (intel_encoder) { 728 ret = 0; 729 intel_dig_port = enc_to_dig_port(&intel_encoder->base); 730 *enabled = intel_dig_port->audio_connector != NULL; 731 if (*enabled) { 732 eld = intel_dig_port->audio_connector->eld; 733 ret = drm_eld_size(eld); 734 memcpy(buf, eld, min(max_bytes, ret)); 735 } 736 } 737 738 mutex_unlock(&dev_priv->av_mutex); 739 return ret; 740 } 741 742 static const struct i915_audio_component_ops i915_audio_component_ops = { 743 .owner = THIS_MODULE, 744 .get_power = i915_audio_component_get_power, 745 .put_power = i915_audio_component_put_power, 746 .codec_wake_override = i915_audio_component_codec_wake_override, 747 .get_cdclk_freq = i915_audio_component_get_cdclk_freq, 748 .sync_audio_rate = i915_audio_component_sync_audio_rate, 749 .get_eld = i915_audio_component_get_eld, 750 }; 751 752 #if 0 753 static int i915_audio_component_bind(struct device *i915_dev, 754 struct device *hda_dev, void *data) 755 { 756 struct i915_audio_component *acomp = data; 757 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); 758 int i; 759 760 if (WARN_ON(acomp->ops || acomp->dev)) 761 return -EEXIST; 762 763 drm_modeset_lock_all(dev_priv->dev); 764 acomp->ops = &i915_audio_component_ops; 765 acomp->dev = i915_dev; 766 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS); 767 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++) 768 acomp->aud_sample_rate[i] = 0; 769 dev_priv->audio_component = acomp; 770 drm_modeset_unlock_all(dev_priv->dev); 771 772 return 0; 773 } 774 775 static void i915_audio_component_unbind(struct device *i915_dev, 776 struct device *hda_dev, void *data) 777 { 778 struct i915_audio_component *acomp = data; 779 struct drm_i915_private *dev_priv = dev_to_i915(i915_dev); 780 781 drm_modeset_lock_all(dev_priv->dev); 782 acomp->ops = NULL; 783 acomp->dev = NULL; 784 dev_priv->audio_component = NULL; 785 drm_modeset_unlock_all(dev_priv->dev); 786 } 787 788 static const struct component_ops i915_audio_component_bind_ops = { 789 .bind = i915_audio_component_bind, 790 .unbind = i915_audio_component_unbind, 791 }; 792 #endif 793 794 /** 795 * i915_audio_component_init - initialize and register the audio component 796 * @dev_priv: i915 device instance 797 * 798 * This will register with the component framework a child component which 799 * will bind dynamically to the snd_hda_intel driver's corresponding master 800 * component when the latter is registered. During binding the child 801 * initializes an instance of struct i915_audio_component which it receives 802 * from the master. The master can then start to use the interface defined by 803 * this struct. Each side can break the binding at any point by deregistering 804 * its own component after which each side's component unbind callback is 805 * called. 806 * 807 * We ignore any error during registration and continue with reduced 808 * functionality (i.e. without HDMI audio). 809 */ 810 void i915_audio_component_init(struct drm_i915_private *dev_priv) 811 { 812 #if 0 813 int ret; 814 815 ret = component_add(dev_priv->dev->dev, &i915_audio_component_bind_ops); 816 if (ret < 0) { 817 DRM_ERROR("failed to add audio component (%d)\n", ret); 818 /* continue with reduced functionality */ 819 return; 820 } 821 #endif 822 823 dev_priv->audio_component_registered = true; 824 } 825 826 /** 827 * i915_audio_component_cleanup - deregister the audio component 828 * @dev_priv: i915 device instance 829 * 830 * Deregisters the audio component, breaking any existing binding to the 831 * corresponding snd_hda_intel driver's master component. 832 */ 833 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv) 834 { 835 if (!dev_priv->audio_component_registered) 836 return; 837 838 #if 0 839 component_del(dev_priv->dev->dev, &i915_audio_component_bind_ops); 840 #endif 841 dev_priv->audio_component_registered = false; 842 } 843