1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /*- 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * $FreeBSD: src/sys/dev/drm2/i915/i915_irq.c,v 1.1 2012/05/22 11:07:44 kib Exp $ 28 */ 29 30 #include <sys/sfbuf.h> 31 32 #include <drm/drmP.h> 33 #include <drm/i915_drm.h> 34 #include "i915_drv.h" 35 #include "intel_drv.h" 36 37 static void i915_capture_error_state(struct drm_device *dev); 38 static u32 ring_last_seqno(struct intel_ring_buffer *ring); 39 40 /** 41 * Interrupts that are always left unmasked. 42 * 43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR, 44 * we leave them always unmasked in IMR and then control enabling them through 45 * PIPESTAT alone. 46 */ 47 #define I915_INTERRUPT_ENABLE_FIX \ 48 (I915_ASLE_INTERRUPT | \ 49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ 50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ 51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ 52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ 53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 54 55 /** Interrupts that we mask and unmask at runtime. */ 56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) 57 58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ 59 PIPE_VBLANK_INTERRUPT_STATUS) 60 61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ 62 PIPE_VBLANK_INTERRUPT_ENABLE) 63 64 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ 65 DRM_I915_VBLANK_PIPE_B) 66 67 /* For display hotplug interrupt */ 68 static void 69 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 70 { 71 if ((dev_priv->irq_mask & mask) != 0) { 72 dev_priv->irq_mask &= ~mask; 73 I915_WRITE(DEIMR, dev_priv->irq_mask); 74 POSTING_READ(DEIMR); 75 } 76 } 77 78 static inline void 79 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 80 { 81 if ((dev_priv->irq_mask & mask) != mask) { 82 dev_priv->irq_mask |= mask; 83 I915_WRITE(DEIMR, dev_priv->irq_mask); 84 POSTING_READ(DEIMR); 85 } 86 } 87 88 void 89 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 90 { 91 if ((dev_priv->pipestat[pipe] & mask) != mask) { 92 u32 reg = PIPESTAT(pipe); 93 94 dev_priv->pipestat[pipe] |= mask; 95 /* Enable the interrupt, clear any pending status */ 96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); 97 POSTING_READ(reg); 98 } 99 } 100 101 void 102 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) 103 { 104 if ((dev_priv->pipestat[pipe] & mask) != 0) { 105 u32 reg = PIPESTAT(pipe); 106 107 dev_priv->pipestat[pipe] &= ~mask; 108 I915_WRITE(reg, dev_priv->pipestat[pipe]); 109 POSTING_READ(reg); 110 } 111 } 112 113 /** 114 * intel_enable_asle - enable ASLE interrupt for OpRegion 115 */ 116 void intel_enable_asle(struct drm_device *dev) 117 { 118 drm_i915_private_t *dev_priv = dev->dev_private; 119 120 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 121 122 if (HAS_PCH_SPLIT(dev)) 123 ironlake_enable_display_irq(dev_priv, DE_GSE); 124 else { 125 i915_enable_pipestat(dev_priv, 1, 126 PIPE_LEGACY_BLC_EVENT_ENABLE); 127 if (INTEL_INFO(dev)->gen >= 4) 128 i915_enable_pipestat(dev_priv, 0, 129 PIPE_LEGACY_BLC_EVENT_ENABLE); 130 } 131 132 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 133 } 134 135 /** 136 * i915_pipe_enabled - check if a pipe is enabled 137 * @dev: DRM device 138 * @pipe: pipe to check 139 * 140 * Reading certain registers when the pipe is disabled can hang the chip. 141 * Use this routine to make sure the PLL is running and the pipe is active 142 * before reading such registers if unsure. 143 */ 144 static int 145 i915_pipe_enabled(struct drm_device *dev, int pipe) 146 { 147 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 148 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; 149 } 150 151 /* Called from drm generic code, passed a 'crtc', which 152 * we use as a pipe index 153 */ 154 static u32 155 i915_get_vblank_counter(struct drm_device *dev, int pipe) 156 { 157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 158 unsigned long high_frame; 159 unsigned long low_frame; 160 u32 high1, high2, low; 161 162 if (!i915_pipe_enabled(dev, pipe)) { 163 DRM_DEBUG("trying to get vblank count for disabled " 164 "pipe %c\n", pipe_name(pipe)); 165 return 0; 166 } 167 168 high_frame = PIPEFRAME(pipe); 169 low_frame = PIPEFRAMEPIXEL(pipe); 170 171 /* 172 * High & low register fields aren't synchronized, so make sure 173 * we get a low value that's stable across two reads of the high 174 * register. 175 */ 176 do { 177 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 178 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; 179 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 180 } while (high1 != high2); 181 182 high1 >>= PIPE_FRAME_HIGH_SHIFT; 183 low >>= PIPE_FRAME_LOW_SHIFT; 184 return (high1 << 8) | low; 185 } 186 187 static u32 188 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 189 { 190 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 191 int reg = PIPE_FRMCOUNT_GM45(pipe); 192 193 if (!i915_pipe_enabled(dev, pipe)) { 194 DRM_DEBUG("i915: trying to get vblank count for disabled " 195 "pipe %c\n", pipe_name(pipe)); 196 return 0; 197 } 198 199 return I915_READ(reg); 200 } 201 202 static int 203 i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 204 int *vpos, int *hpos) 205 { 206 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 207 u32 vbl = 0, position = 0; 208 int vbl_start, vbl_end, htotal, vtotal; 209 bool in_vbl = true; 210 int ret = 0; 211 212 if (!i915_pipe_enabled(dev, pipe)) { 213 DRM_DEBUG("i915: trying to get scanoutpos for disabled " 214 "pipe %c\n", pipe_name(pipe)); 215 return 0; 216 } 217 218 /* Get vtotal. */ 219 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); 220 221 if (INTEL_INFO(dev)->gen >= 4) { 222 /* No obvious pixelcount register. Only query vertical 223 * scanout position from Display scan line register. 224 */ 225 position = I915_READ(PIPEDSL(pipe)); 226 227 /* Decode into vertical scanout position. Don't have 228 * horizontal scanout position. 229 */ 230 *vpos = position & 0x1fff; 231 *hpos = 0; 232 } else { 233 /* Have access to pixelcount since start of frame. 234 * We can split this into vertical and horizontal 235 * scanout position. 236 */ 237 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 238 239 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); 240 *vpos = position / htotal; 241 *hpos = position - (*vpos * htotal); 242 } 243 244 /* Query vblank area. */ 245 vbl = I915_READ(VBLANK(pipe)); 246 247 /* Test position against vblank region. */ 248 vbl_start = vbl & 0x1fff; 249 vbl_end = (vbl >> 16) & 0x1fff; 250 251 if ((*vpos < vbl_start) || (*vpos > vbl_end)) 252 in_vbl = false; 253 254 /* Inside "upper part" of vblank area? Apply corrective offset: */ 255 if (in_vbl && (*vpos >= vbl_start)) 256 *vpos = *vpos - vtotal; 257 258 /* Readouts valid? */ 259 if (vbl > 0) 260 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 261 262 /* In vblank? */ 263 if (in_vbl) 264 ret |= DRM_SCANOUTPOS_INVBL; 265 266 return ret; 267 } 268 269 static int 270 i915_get_vblank_timestamp(struct drm_device *dev, int pipe, int *max_error, 271 struct timeval *vblank_time, unsigned flags) 272 { 273 struct drm_i915_private *dev_priv = dev->dev_private; 274 struct drm_crtc *crtc; 275 276 if (pipe < 0 || pipe >= dev_priv->num_pipe) { 277 DRM_ERROR("Invalid crtc %d\n", pipe); 278 return -EINVAL; 279 } 280 281 /* Get drm_crtc to timestamp: */ 282 crtc = intel_get_crtc_for_pipe(dev, pipe); 283 if (crtc == NULL) { 284 DRM_ERROR("Invalid crtc %d\n", pipe); 285 return -EINVAL; 286 } 287 288 if (!crtc->enabled) { 289 #if 0 290 DRM_DEBUG("crtc %d is disabled\n", pipe); 291 #endif 292 return -EBUSY; 293 } 294 295 /* Helper routine in DRM core does all the work: */ 296 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 297 vblank_time, flags, 298 crtc); 299 } 300 301 /* 302 * Handle hotplug events outside the interrupt handler proper. 303 */ 304 static void 305 i915_hotplug_work_func(void *context, int pending) 306 { 307 drm_i915_private_t *dev_priv = context; 308 struct drm_device *dev = dev_priv->dev; 309 struct drm_mode_config *mode_config; 310 struct intel_encoder *encoder; 311 312 DRM_DEBUG("running encoder hotplug functions\n"); 313 dev_priv = context; 314 dev = dev_priv->dev; 315 316 mode_config = &dev->mode_config; 317 318 lockmgr(&mode_config->mutex, LK_EXCLUSIVE); 319 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 320 321 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) 322 if (encoder->hot_plug) 323 encoder->hot_plug(encoder); 324 325 lockmgr(&mode_config->mutex, LK_RELEASE); 326 327 /* Just fire off a uevent and let userspace tell us what to do */ 328 #if 0 329 drm_helper_hpd_irq_event(dev); 330 #endif 331 } 332 333 static void ironlake_handle_rps_change(struct drm_device *dev) 334 { 335 drm_i915_private_t *dev_priv = dev->dev_private; 336 u32 busy_up, busy_down, max_avg, min_avg; 337 u8 new_delay; 338 339 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 340 341 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 342 343 new_delay = dev_priv->cur_delay; 344 345 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 346 busy_up = I915_READ(RCPREVBSYTUPAVG); 347 busy_down = I915_READ(RCPREVBSYTDNAVG); 348 max_avg = I915_READ(RCBMAXAVG); 349 min_avg = I915_READ(RCBMINAVG); 350 351 /* Handle RCS change request from hw */ 352 if (busy_up > max_avg) { 353 if (dev_priv->cur_delay != dev_priv->max_delay) 354 new_delay = dev_priv->cur_delay - 1; 355 if (new_delay < dev_priv->max_delay) 356 new_delay = dev_priv->max_delay; 357 } else if (busy_down < min_avg) { 358 if (dev_priv->cur_delay != dev_priv->min_delay) 359 new_delay = dev_priv->cur_delay + 1; 360 if (new_delay > dev_priv->min_delay) 361 new_delay = dev_priv->min_delay; 362 } 363 364 if (ironlake_set_drps(dev, new_delay)) 365 dev_priv->cur_delay = new_delay; 366 367 lockmgr(&mchdev_lock, LK_RELEASE); 368 369 return; 370 } 371 372 static void notify_ring(struct drm_device *dev, 373 struct intel_ring_buffer *ring) 374 { 375 struct drm_i915_private *dev_priv = dev->dev_private; 376 u32 seqno; 377 378 if (ring->obj == NULL) 379 return; 380 381 seqno = ring->get_seqno(ring); 382 383 lockmgr(&ring->irq_lock, LK_EXCLUSIVE); 384 ring->irq_seqno = seqno; 385 wakeup(ring); 386 lockmgr(&ring->irq_lock, LK_RELEASE); 387 388 if (i915_enable_hangcheck) { 389 dev_priv->hangcheck_count = 0; 390 mod_timer(&dev_priv->hangcheck_timer, 391 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 392 } 393 } 394 395 static void 396 gen6_pm_rps_work_func(void *arg, int pending) 397 { 398 struct drm_device *dev; 399 drm_i915_private_t *dev_priv; 400 u8 new_delay; 401 u32 pm_iir, pm_imr; 402 403 dev_priv = (drm_i915_private_t *)arg; 404 dev = dev_priv->dev; 405 new_delay = dev_priv->cur_delay; 406 407 lockmgr(&dev_priv->rps_lock, LK_EXCLUSIVE); 408 pm_iir = dev_priv->pm_iir; 409 dev_priv->pm_iir = 0; 410 pm_imr = I915_READ(GEN6_PMIMR); 411 I915_WRITE(GEN6_PMIMR, 0); 412 lockmgr(&dev_priv->rps_lock, LK_RELEASE); 413 414 if (!pm_iir) 415 return; 416 417 DRM_LOCK(dev); 418 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 419 if (dev_priv->cur_delay != dev_priv->max_delay) 420 new_delay = dev_priv->cur_delay + 1; 421 if (new_delay > dev_priv->max_delay) 422 new_delay = dev_priv->max_delay; 423 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { 424 gen6_gt_force_wake_get(dev_priv); 425 if (dev_priv->cur_delay != dev_priv->min_delay) 426 new_delay = dev_priv->cur_delay - 1; 427 if (new_delay < dev_priv->min_delay) { 428 new_delay = dev_priv->min_delay; 429 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 430 I915_READ(GEN6_RP_INTERRUPT_LIMITS) | 431 ((new_delay << 16) & 0x3f0000)); 432 } else { 433 /* Make sure we continue to get down interrupts 434 * until we hit the minimum frequency */ 435 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 436 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); 437 } 438 gen6_gt_force_wake_put(dev_priv); 439 } 440 441 gen6_set_rps(dev, new_delay); 442 dev_priv->cur_delay = new_delay; 443 444 /* 445 * rps_lock not held here because clearing is non-destructive. There is 446 * an *extremely* unlikely race with gen6_rps_enable() that is prevented 447 * by holding struct_mutex for the duration of the write. 448 */ 449 DRM_UNLOCK(dev); 450 } 451 452 static void snb_gt_irq_handler(struct drm_device *dev, 453 struct drm_i915_private *dev_priv, 454 u32 gt_iir) 455 { 456 457 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT | 458 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT)) 459 notify_ring(dev, &dev_priv->ring[RCS]); 460 if (gt_iir & GEN6_BSD_USER_INTERRUPT) 461 notify_ring(dev, &dev_priv->ring[VCS]); 462 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT) 463 notify_ring(dev, &dev_priv->ring[BCS]); 464 465 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT | 466 GT_GEN6_BSD_CS_ERROR_INTERRUPT | 467 GT_RENDER_CS_ERROR_INTERRUPT)) { 468 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); 469 i915_handle_error(dev, false); 470 } 471 472 #if 0 473 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT) 474 ivybridge_handle_parity_error(dev); 475 #endif 476 } 477 478 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv, 479 u32 pm_iir) 480 { 481 482 /* 483 * IIR bits should never already be set because IMR should 484 * prevent an interrupt from being shown in IIR. The warning 485 * displays a case where we've unsafely cleared 486 * dev_priv->rps.pm_iir. Although missing an interrupt of the same 487 * type is not a problem, it displays a problem in the logic. 488 * 489 * The mask bit in IMR is cleared by dev_priv->rps.work. 490 */ 491 492 lockmgr(&dev_priv->rps_lock, LK_EXCLUSIVE); 493 dev_priv->pm_iir |= pm_iir; 494 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir); 495 POSTING_READ(GEN6_PMIMR); 496 lockmgr(&dev_priv->rps_lock, LK_RELEASE); 497 498 taskqueue_enqueue(dev_priv->tq, &dev_priv->rps_task); 499 } 500 501 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 502 { 503 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 504 int pipe; 505 506 if (pch_iir & SDE_HOTPLUG_MASK) 507 taskqueue_enqueue(dev_priv->tq, &dev_priv->hotplug_task); 508 509 if (pch_iir & SDE_AUDIO_POWER_MASK) 510 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 511 (pch_iir & SDE_AUDIO_POWER_MASK) >> 512 SDE_AUDIO_POWER_SHIFT); 513 514 if (pch_iir & SDE_GMBUS) 515 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 516 517 if (pch_iir & SDE_AUDIO_HDCP_MASK) 518 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 519 520 if (pch_iir & SDE_AUDIO_TRANS_MASK) 521 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 522 523 if (pch_iir & SDE_POISON) 524 DRM_ERROR("PCH poison interrupt\n"); 525 526 if (pch_iir & SDE_FDI_MASK) 527 for_each_pipe(pipe) 528 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 529 pipe_name(pipe), 530 I915_READ(FDI_RX_IIR(pipe))); 531 532 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 533 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 534 535 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 536 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 537 538 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 539 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); 540 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 541 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); 542 } 543 544 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) 545 { 546 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 547 int pipe; 548 549 if (pch_iir & SDE_HOTPLUG_MASK_CPT) 550 taskqueue_enqueue(dev_priv->tq, &dev_priv->hotplug_task); 551 552 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) 553 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 554 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 555 SDE_AUDIO_POWER_SHIFT_CPT); 556 557 if (pch_iir & SDE_AUX_MASK_CPT) 558 DRM_DEBUG_DRIVER("AUX channel interrupt\n"); 559 560 if (pch_iir & SDE_GMBUS_CPT) 561 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); 562 563 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 564 DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); 565 566 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 567 DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); 568 569 if (pch_iir & SDE_FDI_MASK_CPT) 570 for_each_pipe(pipe) 571 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 572 pipe_name(pipe), 573 I915_READ(FDI_RX_IIR(pipe))); 574 } 575 576 static void 577 ivybridge_irq_handler(void *arg) 578 { 579 struct drm_device *dev = (struct drm_device *) arg; 580 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 581 u32 de_iir, gt_iir, de_ier, pm_iir; 582 int i; 583 584 atomic_inc(&dev_priv->irq_received); 585 586 /* disable master interrupt before clearing iir */ 587 de_ier = I915_READ(DEIER); 588 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 589 590 gt_iir = I915_READ(GTIIR); 591 if (gt_iir) { 592 snb_gt_irq_handler(dev, dev_priv, gt_iir); 593 I915_WRITE(GTIIR, gt_iir); 594 } 595 596 de_iir = I915_READ(DEIER); 597 if (de_iir) { 598 #if 0 599 if (de_iir & DE_GSE_IVB) 600 intel_opregion_gse_intr(dev); 601 #endif 602 603 for (i = 0; i < 3; i++) { 604 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i))) 605 drm_handle_vblank(dev, i); 606 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) { 607 intel_prepare_page_flip(dev, i); 608 intel_finish_page_flip_plane(dev, i); 609 } 610 } 611 612 /* check event from PCH */ 613 if (de_iir & DE_PCH_EVENT_IVB) { 614 u32 pch_iir = I915_READ(SDEIIR); 615 616 cpt_irq_handler(dev, pch_iir); 617 618 /* clear PCH hotplug event before clear CPU irq */ 619 I915_WRITE(SDEIIR, pch_iir); 620 } 621 622 I915_WRITE(DEIIR, de_iir); 623 } 624 625 pm_iir = I915_READ(GEN6_PMIIR); 626 if (pm_iir) { 627 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) 628 gen6_queue_rps_work(dev_priv, pm_iir); 629 I915_WRITE(GEN6_PMIIR, pm_iir); 630 } 631 632 I915_WRITE(DEIER, de_ier); 633 POSTING_READ(DEIER); 634 } 635 636 static void ilk_gt_irq_handler(struct drm_device *dev, 637 struct drm_i915_private *dev_priv, 638 u32 gt_iir) 639 { 640 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) 641 notify_ring(dev, &dev_priv->ring[RCS]); 642 if (gt_iir & GT_BSD_USER_INTERRUPT) 643 notify_ring(dev, &dev_priv->ring[VCS]); 644 } 645 646 static void 647 ironlake_irq_handler(void *arg) 648 { 649 struct drm_device *dev = arg; 650 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 651 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; 652 653 atomic_inc(&dev_priv->irq_received); 654 655 /* disable master interrupt before clearing iir */ 656 de_ier = I915_READ(DEIER); 657 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 658 POSTING_READ(DEIER); 659 660 de_iir = I915_READ(DEIIR); 661 gt_iir = I915_READ(GTIIR); 662 pch_iir = I915_READ(SDEIIR); 663 pm_iir = I915_READ(GEN6_PMIIR); 664 665 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && 666 (!IS_GEN6(dev) || pm_iir == 0)) 667 goto done; 668 669 if (IS_GEN5(dev)) 670 ilk_gt_irq_handler(dev, dev_priv, gt_iir); 671 else 672 snb_gt_irq_handler(dev, dev_priv, gt_iir); 673 674 if (gt_iir & GT_GEN6_BLT_USER_INTERRUPT) 675 notify_ring(dev, &dev_priv->ring[BCS]); 676 677 if (de_iir & DE_GSE) { 678 #if 1 679 KIB_NOTYET(); 680 #else 681 intel_opregion_gse_intr(dev); 682 #endif 683 } 684 685 if (de_iir & DE_PIPEA_VBLANK) 686 drm_handle_vblank(dev, 0); 687 688 if (de_iir & DE_PIPEB_VBLANK) 689 drm_handle_vblank(dev, 1); 690 691 if (de_iir & DE_PLANEA_FLIP_DONE) { 692 intel_prepare_page_flip(dev, 0); 693 intel_finish_page_flip_plane(dev, 0); 694 } 695 696 if (de_iir & DE_PLANEB_FLIP_DONE) { 697 intel_prepare_page_flip(dev, 1); 698 intel_finish_page_flip_plane(dev, 1); 699 } 700 701 /* check event from PCH */ 702 if (de_iir & DE_PCH_EVENT) { 703 if (HAS_PCH_CPT(dev)) 704 cpt_irq_handler(dev, pch_iir); 705 else 706 ibx_irq_handler(dev, pch_iir); 707 } 708 709 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) 710 ironlake_handle_rps_change(dev); 711 712 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) 713 gen6_queue_rps_work(dev_priv, pm_iir); 714 715 /* should clear PCH hotplug event before clear CPU irq */ 716 I915_WRITE(SDEIIR, pch_iir); 717 I915_WRITE(GTIIR, gt_iir); 718 I915_WRITE(DEIIR, de_iir); 719 I915_WRITE(GEN6_PMIIR, pm_iir); 720 721 done: 722 I915_WRITE(DEIER, de_ier); 723 POSTING_READ(DEIER); 724 } 725 726 /** 727 * i915_error_work_func - do process context error handling work 728 * @work: work struct 729 * 730 * Fire an error uevent so userspace can see that a hang or error 731 * was detected. 732 */ 733 static void 734 i915_error_work_func(void *context, int pending) 735 { 736 drm_i915_private_t *dev_priv = context; 737 struct drm_device *dev = dev_priv->dev; 738 739 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); */ 740 741 if (atomic_read(&dev_priv->mm.wedged)) { 742 DRM_DEBUG("i915: resetting chip\n"); 743 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); */ 744 if (!i915_reset(dev, GRDOM_RENDER)) { 745 atomic_set(&dev_priv->mm.wedged, 0); 746 /* kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); */ 747 } 748 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE); 749 dev_priv->error_completion++; 750 wakeup(&dev_priv->error_completion); 751 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE); 752 } 753 } 754 755 static void i915_report_and_clear_eir(struct drm_device *dev) 756 { 757 struct drm_i915_private *dev_priv = dev->dev_private; 758 u32 eir = I915_READ(EIR); 759 int pipe; 760 761 if (!eir) 762 return; 763 764 kprintf("i915: render error detected, EIR: 0x%08x\n", eir); 765 766 if (IS_G4X(dev)) { 767 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 768 u32 ipeir = I915_READ(IPEIR_I965); 769 770 kprintf(" IPEIR: 0x%08x\n", 771 I915_READ(IPEIR_I965)); 772 kprintf(" IPEHR: 0x%08x\n", 773 I915_READ(IPEHR_I965)); 774 kprintf(" INSTDONE: 0x%08x\n", 775 I915_READ(INSTDONE_I965)); 776 kprintf(" INSTPS: 0x%08x\n", 777 I915_READ(INSTPS)); 778 kprintf(" INSTDONE1: 0x%08x\n", 779 I915_READ(INSTDONE1)); 780 kprintf(" ACTHD: 0x%08x\n", 781 I915_READ(ACTHD_I965)); 782 I915_WRITE(IPEIR_I965, ipeir); 783 POSTING_READ(IPEIR_I965); 784 } 785 if (eir & GM45_ERROR_PAGE_TABLE) { 786 u32 pgtbl_err = I915_READ(PGTBL_ER); 787 kprintf("page table error\n"); 788 kprintf(" PGTBL_ER: 0x%08x\n", 789 pgtbl_err); 790 I915_WRITE(PGTBL_ER, pgtbl_err); 791 POSTING_READ(PGTBL_ER); 792 } 793 } 794 795 if (!IS_GEN2(dev)) { 796 if (eir & I915_ERROR_PAGE_TABLE) { 797 u32 pgtbl_err = I915_READ(PGTBL_ER); 798 kprintf("page table error\n"); 799 kprintf(" PGTBL_ER: 0x%08x\n", 800 pgtbl_err); 801 I915_WRITE(PGTBL_ER, pgtbl_err); 802 POSTING_READ(PGTBL_ER); 803 } 804 } 805 806 if (eir & I915_ERROR_MEMORY_REFRESH) { 807 kprintf("memory refresh error:\n"); 808 for_each_pipe(pipe) 809 kprintf("pipe %c stat: 0x%08x\n", 810 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 811 /* pipestat has already been acked */ 812 } 813 if (eir & I915_ERROR_INSTRUCTION) { 814 kprintf("instruction error\n"); 815 kprintf(" INSTPM: 0x%08x\n", 816 I915_READ(INSTPM)); 817 if (INTEL_INFO(dev)->gen < 4) { 818 u32 ipeir = I915_READ(IPEIR); 819 820 kprintf(" IPEIR: 0x%08x\n", 821 I915_READ(IPEIR)); 822 kprintf(" IPEHR: 0x%08x\n", 823 I915_READ(IPEHR)); 824 kprintf(" INSTDONE: 0x%08x\n", 825 I915_READ(INSTDONE)); 826 kprintf(" ACTHD: 0x%08x\n", 827 I915_READ(ACTHD)); 828 I915_WRITE(IPEIR, ipeir); 829 POSTING_READ(IPEIR); 830 } else { 831 u32 ipeir = I915_READ(IPEIR_I965); 832 833 kprintf(" IPEIR: 0x%08x\n", 834 I915_READ(IPEIR_I965)); 835 kprintf(" IPEHR: 0x%08x\n", 836 I915_READ(IPEHR_I965)); 837 kprintf(" INSTDONE: 0x%08x\n", 838 I915_READ(INSTDONE_I965)); 839 kprintf(" INSTPS: 0x%08x\n", 840 I915_READ(INSTPS)); 841 kprintf(" INSTDONE1: 0x%08x\n", 842 I915_READ(INSTDONE1)); 843 kprintf(" ACTHD: 0x%08x\n", 844 I915_READ(ACTHD_I965)); 845 I915_WRITE(IPEIR_I965, ipeir); 846 POSTING_READ(IPEIR_I965); 847 } 848 } 849 850 I915_WRITE(EIR, eir); 851 POSTING_READ(EIR); 852 eir = I915_READ(EIR); 853 if (eir) { 854 /* 855 * some errors might have become stuck, 856 * mask them. 857 */ 858 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 859 I915_WRITE(EMR, I915_READ(EMR) | eir); 860 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 861 } 862 } 863 864 /** 865 * i915_handle_error - handle an error interrupt 866 * @dev: drm device 867 * 868 * Do some basic checking of regsiter state at error interrupt time and 869 * dump it to the syslog. Also call i915_capture_error_state() to make 870 * sure we get a record and make it available in debugfs. Fire a uevent 871 * so userspace knows something bad happened (should trigger collection 872 * of a ring dump etc.). 873 */ 874 void i915_handle_error(struct drm_device *dev, bool wedged) 875 { 876 struct drm_i915_private *dev_priv = dev->dev_private; 877 878 i915_capture_error_state(dev); 879 i915_report_and_clear_eir(dev); 880 881 if (wedged) { 882 lockmgr(&dev_priv->error_completion_lock, LK_EXCLUSIVE); 883 dev_priv->error_completion = 0; 884 atomic_set(&dev_priv->mm.wedged, 1); 885 /* unlock acts as rel barrier for store to wedged */ 886 lockmgr(&dev_priv->error_completion_lock, LK_RELEASE); 887 888 /* 889 * Wakeup waiting processes so they don't hang 890 */ 891 lockmgr(&dev_priv->ring[RCS].irq_lock, LK_EXCLUSIVE); 892 wakeup(&dev_priv->ring[RCS]); 893 lockmgr(&dev_priv->ring[RCS].irq_lock, LK_RELEASE); 894 if (HAS_BSD(dev)) { 895 lockmgr(&dev_priv->ring[VCS].irq_lock, LK_EXCLUSIVE); 896 wakeup(&dev_priv->ring[VCS]); 897 lockmgr(&dev_priv->ring[VCS].irq_lock, LK_RELEASE); 898 } 899 if (HAS_BLT(dev)) { 900 lockmgr(&dev_priv->ring[BCS].irq_lock, LK_EXCLUSIVE); 901 wakeup(&dev_priv->ring[BCS]); 902 lockmgr(&dev_priv->ring[BCS].irq_lock, LK_RELEASE); 903 } 904 } 905 906 taskqueue_enqueue(dev_priv->tq, &dev_priv->error_task); 907 } 908 909 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) 910 { 911 drm_i915_private_t *dev_priv = dev->dev_private; 912 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 914 struct drm_i915_gem_object *obj; 915 struct intel_unpin_work *work; 916 bool stall_detected; 917 918 /* Ignore early vblank irqs */ 919 if (intel_crtc == NULL) 920 return; 921 922 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 923 work = intel_crtc->unpin_work; 924 925 if (work == NULL || atomic_read(&work->pending) || 926 !work->enable_stall_check) { 927 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 928 lockmgr(&dev->event_lock, LK_RELEASE); 929 return; 930 } 931 932 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 933 obj = work->pending_flip_obj; 934 if (INTEL_INFO(dev)->gen >= 4) { 935 int dspsurf = DSPSURF(intel_crtc->plane); 936 stall_detected = I915_READ(dspsurf) == obj->gtt_offset; 937 } else { 938 int dspaddr = DSPADDR(intel_crtc->plane); 939 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + 940 crtc->y * crtc->fb->pitches[0] + 941 crtc->x * crtc->fb->bits_per_pixel/8); 942 } 943 944 lockmgr(&dev->event_lock, LK_RELEASE); 945 946 if (stall_detected) { 947 DRM_DEBUG("Pageflip stall detected\n"); 948 intel_prepare_page_flip(dev, intel_crtc->plane); 949 } 950 } 951 952 static void 953 i915_driver_irq_handler(void *arg) 954 { 955 struct drm_device *dev = (struct drm_device *)arg; 956 drm_i915_private_t *dev_priv = (drm_i915_private_t *)dev->dev_private; 957 #if 0 958 struct drm_i915_master_private *master_priv; 959 #endif 960 u32 iir, new_iir; 961 u32 pipe_stats[I915_MAX_PIPES]; 962 u32 vblank_status; 963 int vblank = 0; 964 int irq_received; 965 int pipe; 966 bool blc_event = false; 967 968 atomic_inc(&dev_priv->irq_received); 969 970 iir = I915_READ(IIR); 971 972 if (INTEL_INFO(dev)->gen >= 4) 973 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; 974 else 975 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; 976 977 for (;;) { 978 irq_received = iir != 0; 979 980 /* Can't rely on pipestat interrupt bit in iir as it might 981 * have been cleared after the pipestat interrupt was received. 982 * It doesn't set the bit in iir again, but it still produces 983 * interrupts (for non-MSI). 984 */ 985 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 986 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 987 i915_handle_error(dev, false); 988 989 for_each_pipe(pipe) { 990 int reg = PIPESTAT(pipe); 991 pipe_stats[pipe] = I915_READ(reg); 992 993 /* 994 * Clear the PIPE*STAT regs before the IIR 995 */ 996 if (pipe_stats[pipe] & 0x8000ffff) { 997 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 998 DRM_DEBUG("pipe %c underrun\n", 999 pipe_name(pipe)); 1000 I915_WRITE(reg, pipe_stats[pipe]); 1001 irq_received = 1; 1002 } 1003 } 1004 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1005 1006 if (!irq_received) 1007 break; 1008 1009 /* Consume port. Then clear IIR or we'll miss events */ 1010 if ((I915_HAS_HOTPLUG(dev)) && 1011 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 1012 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 1013 1014 DRM_DEBUG("i915: hotplug event received, stat 0x%08x\n", 1015 hotplug_status); 1016 if (hotplug_status & dev_priv->hotplug_supported_mask) 1017 taskqueue_enqueue(dev_priv->tq, 1018 &dev_priv->hotplug_task); 1019 1020 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 1021 I915_READ(PORT_HOTPLUG_STAT); 1022 } 1023 1024 I915_WRITE(IIR, iir); 1025 new_iir = I915_READ(IIR); /* Flush posted writes */ 1026 1027 #if 0 1028 if (dev->primary->master) { 1029 master_priv = dev->primary->master->driver_priv; 1030 if (master_priv->sarea_priv) 1031 master_priv->sarea_priv->last_dispatch = 1032 READ_BREADCRUMB(dev_priv); 1033 } 1034 #else 1035 if (dev_priv->sarea_priv) 1036 dev_priv->sarea_priv->last_dispatch = 1037 READ_BREADCRUMB(dev_priv); 1038 #endif 1039 1040 if (iir & I915_USER_INTERRUPT) 1041 notify_ring(dev, &dev_priv->ring[RCS]); 1042 if (iir & I915_BSD_USER_INTERRUPT) 1043 notify_ring(dev, &dev_priv->ring[VCS]); 1044 1045 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { 1046 intel_prepare_page_flip(dev, 0); 1047 if (dev_priv->flip_pending_is_done) 1048 intel_finish_page_flip_plane(dev, 0); 1049 } 1050 1051 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { 1052 intel_prepare_page_flip(dev, 1); 1053 if (dev_priv->flip_pending_is_done) 1054 intel_finish_page_flip_plane(dev, 1); 1055 } 1056 1057 for_each_pipe(pipe) { 1058 if (pipe_stats[pipe] & vblank_status && 1059 drm_handle_vblank(dev, pipe)) { 1060 vblank++; 1061 if (!dev_priv->flip_pending_is_done) { 1062 i915_pageflip_stall_check(dev, pipe); 1063 intel_finish_page_flip(dev, pipe); 1064 } 1065 } 1066 1067 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 1068 blc_event = true; 1069 } 1070 1071 1072 if (blc_event || (iir & I915_ASLE_INTERRUPT)) { 1073 #if 1 1074 KIB_NOTYET(); 1075 #else 1076 intel_opregion_asle_intr(dev); 1077 #endif 1078 } 1079 1080 /* With MSI, interrupts are only generated when iir 1081 * transitions from zero to nonzero. If another bit got 1082 * set while we were handling the existing iir bits, then 1083 * we would never get another interrupt. 1084 * 1085 * This is fine on non-MSI as well, as if we hit this path 1086 * we avoid exiting the interrupt handler only to generate 1087 * another one. 1088 * 1089 * Note that for MSI this could cause a stray interrupt report 1090 * if an interrupt landed in the time between writing IIR and 1091 * the posting read. This should be rare enough to never 1092 * trigger the 99% of 100,000 interrupts test for disabling 1093 * stray interrupts. 1094 */ 1095 iir = new_iir; 1096 } 1097 } 1098 1099 static int i915_emit_irq(struct drm_device * dev) 1100 { 1101 drm_i915_private_t *dev_priv = dev->dev_private; 1102 #if 0 1103 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1104 #endif 1105 1106 i915_kernel_lost_context(dev); 1107 1108 DRM_DEBUG("i915: emit_irq\n"); 1109 1110 dev_priv->counter++; 1111 if (dev_priv->counter > 0x7FFFFFFFUL) 1112 dev_priv->counter = 1; 1113 #if 0 1114 if (master_priv->sarea_priv) 1115 master_priv->sarea_priv->last_enqueue = dev_priv->counter; 1116 #else 1117 if (dev_priv->sarea_priv) 1118 dev_priv->sarea_priv->last_enqueue = dev_priv->counter; 1119 #endif 1120 1121 if (BEGIN_LP_RING(4) == 0) { 1122 OUT_RING(MI_STORE_DWORD_INDEX); 1123 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); 1124 OUT_RING(dev_priv->counter); 1125 OUT_RING(MI_USER_INTERRUPT); 1126 ADVANCE_LP_RING(); 1127 } 1128 1129 return dev_priv->counter; 1130 } 1131 1132 static int i915_wait_irq(struct drm_device * dev, int irq_nr) 1133 { 1134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1135 #if 0 1136 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; 1137 #endif 1138 int ret; 1139 struct intel_ring_buffer *ring = LP_RING(dev_priv); 1140 1141 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, 1142 READ_BREADCRUMB(dev_priv)); 1143 1144 #if 0 1145 if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 1146 if (master_priv->sarea_priv) 1147 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 1148 return 0; 1149 } 1150 1151 if (master_priv->sarea_priv) 1152 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 1153 #else 1154 if (READ_BREADCRUMB(dev_priv) >= irq_nr) { 1155 if (dev_priv->sarea_priv) { 1156 dev_priv->sarea_priv->last_dispatch = 1157 READ_BREADCRUMB(dev_priv); 1158 } 1159 return 0; 1160 } 1161 1162 if (dev_priv->sarea_priv) 1163 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; 1164 #endif 1165 1166 ret = 0; 1167 lockmgr(&ring->irq_lock, LK_EXCLUSIVE); 1168 if (ring->irq_get(ring)) { 1169 DRM_UNLOCK(dev); 1170 while (ret == 0 && READ_BREADCRUMB(dev_priv) < irq_nr) { 1171 ret = -lksleep(ring, &ring->irq_lock, PCATCH, 1172 "915wtq", 3 * hz); 1173 } 1174 ring->irq_put(ring); 1175 lockmgr(&ring->irq_lock, LK_RELEASE); 1176 DRM_LOCK(dev); 1177 } else { 1178 lockmgr(&ring->irq_lock, LK_RELEASE); 1179 if (_intel_wait_for(dev, READ_BREADCRUMB(dev_priv) >= irq_nr, 1180 3000, 1, "915wir")) 1181 ret = -EBUSY; 1182 } 1183 1184 if (ret == -EBUSY) { 1185 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", 1186 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); 1187 } 1188 1189 return ret; 1190 } 1191 1192 /* Needs the lock as it touches the ring. 1193 */ 1194 int i915_irq_emit(struct drm_device *dev, void *data, 1195 struct drm_file *file_priv) 1196 { 1197 drm_i915_private_t *dev_priv = dev->dev_private; 1198 drm_i915_irq_emit_t *emit = data; 1199 int result; 1200 1201 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { 1202 DRM_ERROR("called with no initialization\n"); 1203 return -EINVAL; 1204 } 1205 1206 RING_LOCK_TEST_WITH_RETURN(dev, file_priv); 1207 1208 DRM_LOCK(dev); 1209 result = i915_emit_irq(dev); 1210 DRM_UNLOCK(dev); 1211 1212 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { 1213 DRM_ERROR("copy_to_user\n"); 1214 return -EFAULT; 1215 } 1216 1217 return 0; 1218 } 1219 1220 /* Doesn't need the hardware lock. 1221 */ 1222 int i915_irq_wait(struct drm_device *dev, void *data, 1223 struct drm_file *file_priv) 1224 { 1225 drm_i915_private_t *dev_priv = dev->dev_private; 1226 drm_i915_irq_wait_t *irqwait = data; 1227 1228 if (!dev_priv) { 1229 DRM_ERROR("called with no initialization\n"); 1230 return -EINVAL; 1231 } 1232 1233 return i915_wait_irq(dev, irqwait->irq_seq); 1234 } 1235 1236 /* Called from drm generic code, passed 'crtc' which 1237 * we use as a pipe index 1238 */ 1239 static int 1240 i915_enable_vblank(struct drm_device *dev, int pipe) 1241 { 1242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1243 1244 if (!i915_pipe_enabled(dev, pipe)) 1245 return -EINVAL; 1246 1247 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1248 if (INTEL_INFO(dev)->gen >= 4) 1249 i915_enable_pipestat(dev_priv, pipe, 1250 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1251 else 1252 i915_enable_pipestat(dev_priv, pipe, 1253 PIPE_VBLANK_INTERRUPT_ENABLE); 1254 1255 /* maintain vblank delivery even in deep C-states */ 1256 if (dev_priv->info->gen == 3) 1257 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16); 1258 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1259 1260 return 0; 1261 } 1262 1263 static int 1264 ironlake_enable_vblank(struct drm_device *dev, int pipe) 1265 { 1266 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1267 1268 if (!i915_pipe_enabled(dev, pipe)) 1269 return -EINVAL; 1270 1271 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1272 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1273 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1274 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1275 1276 return 0; 1277 } 1278 1279 static int 1280 ivybridge_enable_vblank(struct drm_device *dev, int pipe) 1281 { 1282 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1283 1284 if (!i915_pipe_enabled(dev, pipe)) 1285 return -EINVAL; 1286 1287 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1288 ironlake_enable_display_irq(dev_priv, (pipe == 0) ? 1289 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); 1290 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1291 1292 return 0; 1293 } 1294 1295 1296 /* Called from drm generic code, passed 'crtc' which 1297 * we use as a pipe index 1298 */ 1299 static void 1300 i915_disable_vblank(struct drm_device *dev, int pipe) 1301 { 1302 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1303 1304 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1305 if (dev_priv->info->gen == 3) 1306 I915_WRITE(INSTPM, 1307 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); 1308 1309 i915_disable_pipestat(dev_priv, pipe, 1310 PIPE_VBLANK_INTERRUPT_ENABLE | 1311 PIPE_START_VBLANK_INTERRUPT_ENABLE); 1312 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1313 } 1314 1315 static void 1316 ironlake_disable_vblank(struct drm_device *dev, int pipe) 1317 { 1318 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1319 1320 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1321 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1322 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK); 1323 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1324 } 1325 1326 static void 1327 ivybridge_disable_vblank(struct drm_device *dev, int pipe) 1328 { 1329 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1330 1331 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1332 ironlake_disable_display_irq(dev_priv, (pipe == 0) ? 1333 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); 1334 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1335 } 1336 1337 /* Set the vblank monitor pipe 1338 */ 1339 int i915_vblank_pipe_set(struct drm_device *dev, void *data, 1340 struct drm_file *file_priv) 1341 { 1342 drm_i915_private_t *dev_priv = dev->dev_private; 1343 1344 if (!dev_priv) { 1345 DRM_ERROR("called with no initialization\n"); 1346 return -EINVAL; 1347 } 1348 1349 return 0; 1350 } 1351 1352 int i915_vblank_pipe_get(struct drm_device *dev, void *data, 1353 struct drm_file *file_priv) 1354 { 1355 drm_i915_private_t *dev_priv = dev->dev_private; 1356 drm_i915_vblank_pipe_t *pipe = data; 1357 1358 if (!dev_priv) { 1359 DRM_ERROR("called with no initialization\n"); 1360 return -EINVAL; 1361 } 1362 1363 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1364 1365 return 0; 1366 } 1367 1368 /** 1369 * Schedule buffer swap at given vertical blank. 1370 */ 1371 int i915_vblank_swap(struct drm_device *dev, void *data, 1372 struct drm_file *file_priv) 1373 { 1374 /* The delayed swap mechanism was fundamentally racy, and has been 1375 * removed. The model was that the client requested a delayed flip/swap 1376 * from the kernel, then waited for vblank before continuing to perform 1377 * rendering. The problem was that the kernel might wake the client 1378 * up before it dispatched the vblank swap (since the lock has to be 1379 * held while touching the ringbuffer), in which case the client would 1380 * clear and start the next frame before the swap occurred, and 1381 * flicker would occur in addition to likely missing the vblank. 1382 * 1383 * In the absence of this ioctl, userland falls back to a correct path 1384 * of waiting for a vblank, then dispatching the swap on its own. 1385 * Context switching to userland and back is plenty fast enough for 1386 * meeting the requirements of vblank swapping. 1387 */ 1388 return -EINVAL; 1389 } 1390 1391 static u32 1392 ring_last_seqno(struct intel_ring_buffer *ring) 1393 { 1394 1395 if (list_empty(&ring->request_list)) 1396 return (0); 1397 else 1398 return (list_entry(ring->request_list.prev, 1399 struct drm_i915_gem_request, list)->seqno); 1400 } 1401 1402 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) 1403 { 1404 if (list_empty(&ring->request_list) || 1405 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { 1406 /* Issue a wake-up to catch stuck h/w. */ 1407 if (ring->waiting_seqno) { 1408 DRM_ERROR( 1409 "Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", 1410 ring->name, 1411 ring->waiting_seqno, 1412 ring->get_seqno(ring)); 1413 wakeup(ring); 1414 *err = true; 1415 } 1416 return true; 1417 } 1418 return false; 1419 } 1420 1421 static bool kick_ring(struct intel_ring_buffer *ring) 1422 { 1423 struct drm_device *dev = ring->dev; 1424 struct drm_i915_private *dev_priv = dev->dev_private; 1425 u32 tmp = I915_READ_CTL(ring); 1426 if (tmp & RING_WAIT) { 1427 DRM_ERROR("Kicking stuck wait on %s\n", 1428 ring->name); 1429 I915_WRITE_CTL(ring, tmp); 1430 return true; 1431 } 1432 return false; 1433 } 1434 1435 /** 1436 * This is called when the chip hasn't reported back with completed 1437 * batchbuffers in a long time. The first time this is called we simply record 1438 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses 1439 * again, we assume the chip is wedged and try to fix it. 1440 */ 1441 void i915_hangcheck_elapsed(unsigned long data) 1442 { 1443 struct drm_device *dev = (struct drm_device *)data; 1444 drm_i915_private_t *dev_priv = dev->dev_private; 1445 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt; 1446 bool err = false; 1447 1448 if (!i915_enable_hangcheck) 1449 return; 1450 1451 /* If all work is done then ACTHD clearly hasn't advanced. */ 1452 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && 1453 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && 1454 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { 1455 dev_priv->hangcheck_count = 0; 1456 if (err) 1457 goto repeat; 1458 return; 1459 } 1460 1461 if (INTEL_INFO(dev)->gen < 4) { 1462 instdone = I915_READ(INSTDONE); 1463 instdone1 = 0; 1464 } else { 1465 instdone = I915_READ(INSTDONE_I965); 1466 instdone1 = I915_READ(INSTDONE1); 1467 } 1468 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]); 1469 acthd_bsd = HAS_BSD(dev) ? 1470 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0; 1471 acthd_blt = HAS_BLT(dev) ? 1472 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0; 1473 1474 if (dev_priv->last_acthd == acthd && 1475 dev_priv->last_acthd_bsd == acthd_bsd && 1476 dev_priv->last_acthd_blt == acthd_blt && 1477 dev_priv->last_instdone == instdone && 1478 dev_priv->last_instdone1 == instdone1) { 1479 if (dev_priv->hangcheck_count++ > 1) { 1480 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); 1481 i915_handle_error(dev, true); 1482 1483 if (!IS_GEN2(dev)) { 1484 /* Is the chip hanging on a WAIT_FOR_EVENT? 1485 * If so we can simply poke the RB_WAIT bit 1486 * and break the hang. This should work on 1487 * all but the second generation chipsets. 1488 */ 1489 if (kick_ring(&dev_priv->ring[RCS])) 1490 goto repeat; 1491 1492 if (HAS_BSD(dev) && 1493 kick_ring(&dev_priv->ring[VCS])) 1494 goto repeat; 1495 1496 if (HAS_BLT(dev) && 1497 kick_ring(&dev_priv->ring[BCS])) 1498 goto repeat; 1499 } 1500 1501 return; 1502 } 1503 } else { 1504 dev_priv->hangcheck_count = 0; 1505 1506 dev_priv->last_acthd = acthd; 1507 dev_priv->last_acthd_bsd = acthd_bsd; 1508 dev_priv->last_acthd_blt = acthd_blt; 1509 dev_priv->last_instdone = instdone; 1510 dev_priv->last_instdone1 = instdone1; 1511 } 1512 1513 repeat: 1514 /* Reset timer case chip hangs without another request being added */ 1515 mod_timer(&dev_priv->hangcheck_timer, 1516 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 1517 } 1518 1519 /* drm_dma.h hooks 1520 */ 1521 static void 1522 ironlake_irq_preinstall(struct drm_device *dev) 1523 { 1524 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1525 1526 atomic_set(&dev_priv->irq_received, 0); 1527 1528 TASK_INIT(&dev_priv->hotplug_task, 0, i915_hotplug_work_func, 1529 dev->dev_private); 1530 TASK_INIT(&dev_priv->error_task, 0, i915_error_work_func, 1531 dev->dev_private); 1532 TASK_INIT(&dev_priv->rps_task, 0, gen6_pm_rps_work_func, 1533 dev->dev_private); 1534 1535 I915_WRITE(HWSTAM, 0xeffe); 1536 1537 /* XXX hotplug from PCH */ 1538 1539 I915_WRITE(DEIMR, 0xffffffff); 1540 I915_WRITE(DEIER, 0x0); 1541 POSTING_READ(DEIER); 1542 1543 /* and GT */ 1544 I915_WRITE(GTIMR, 0xffffffff); 1545 I915_WRITE(GTIER, 0x0); 1546 POSTING_READ(GTIER); 1547 1548 /* south display irq */ 1549 I915_WRITE(SDEIMR, 0xffffffff); 1550 I915_WRITE(SDEIER, 0x0); 1551 POSTING_READ(SDEIER); 1552 } 1553 1554 /* 1555 * Enable digital hotplug on the PCH, and configure the DP short pulse 1556 * duration to 2ms (which is the minimum in the Display Port spec) 1557 * 1558 * This register is the same on all known PCH chips. 1559 */ 1560 1561 static void ironlake_enable_pch_hotplug(struct drm_device *dev) 1562 { 1563 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1564 u32 hotplug; 1565 1566 hotplug = I915_READ(PCH_PORT_HOTPLUG); 1567 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 1568 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 1569 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 1570 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 1571 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 1572 } 1573 1574 static int ironlake_irq_postinstall(struct drm_device *dev) 1575 { 1576 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1577 /* enable kind of interrupts always enabled */ 1578 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 1579 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; 1580 u32 render_irqs; 1581 u32 hotplug_mask; 1582 1583 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1584 dev_priv->irq_mask = ~display_mask; 1585 1586 /* should always can generate irq */ 1587 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1588 I915_WRITE(DEIMR, dev_priv->irq_mask); 1589 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); 1590 POSTING_READ(DEIER); 1591 1592 dev_priv->gt_irq_mask = ~0; 1593 1594 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1595 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1596 1597 if (IS_GEN6(dev)) 1598 render_irqs = 1599 GT_USER_INTERRUPT | 1600 GT_GEN6_BSD_USER_INTERRUPT | 1601 GT_GEN6_BLT_USER_INTERRUPT; 1602 else 1603 render_irqs = 1604 GT_USER_INTERRUPT | 1605 GT_PIPE_NOTIFY | 1606 GT_BSD_USER_INTERRUPT; 1607 I915_WRITE(GTIER, render_irqs); 1608 POSTING_READ(GTIER); 1609 1610 if (HAS_PCH_CPT(dev)) { 1611 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1612 SDE_PORTB_HOTPLUG_CPT | 1613 SDE_PORTC_HOTPLUG_CPT | 1614 SDE_PORTD_HOTPLUG_CPT); 1615 } else { 1616 hotplug_mask = (SDE_CRT_HOTPLUG | 1617 SDE_PORTB_HOTPLUG | 1618 SDE_PORTC_HOTPLUG | 1619 SDE_PORTD_HOTPLUG | 1620 SDE_AUX_MASK); 1621 } 1622 1623 dev_priv->pch_irq_mask = ~hotplug_mask; 1624 1625 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1626 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1627 I915_WRITE(SDEIER, hotplug_mask); 1628 POSTING_READ(SDEIER); 1629 1630 ironlake_enable_pch_hotplug(dev); 1631 1632 if (IS_IRONLAKE_M(dev)) { 1633 /* Clear & enable PCU event interrupts */ 1634 I915_WRITE(DEIIR, DE_PCU_EVENT); 1635 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); 1636 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 1637 } 1638 1639 return 0; 1640 } 1641 1642 static int 1643 ivybridge_irq_postinstall(struct drm_device *dev) 1644 { 1645 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1646 /* enable kind of interrupts always enabled */ 1647 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 1648 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | 1649 DE_PLANEB_FLIP_DONE_IVB; 1650 u32 render_irqs; 1651 u32 hotplug_mask; 1652 1653 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1654 dev_priv->irq_mask = ~display_mask; 1655 1656 /* should always can generate irq */ 1657 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1658 I915_WRITE(DEIMR, dev_priv->irq_mask); 1659 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | 1660 DE_PIPEB_VBLANK_IVB); 1661 POSTING_READ(DEIER); 1662 1663 dev_priv->gt_irq_mask = ~0; 1664 1665 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1666 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 1667 1668 render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT | 1669 GT_GEN6_BLT_USER_INTERRUPT; 1670 I915_WRITE(GTIER, render_irqs); 1671 POSTING_READ(GTIER); 1672 1673 hotplug_mask = (SDE_CRT_HOTPLUG_CPT | 1674 SDE_PORTB_HOTPLUG_CPT | 1675 SDE_PORTC_HOTPLUG_CPT | 1676 SDE_PORTD_HOTPLUG_CPT); 1677 dev_priv->pch_irq_mask = ~hotplug_mask; 1678 1679 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1680 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); 1681 I915_WRITE(SDEIER, hotplug_mask); 1682 POSTING_READ(SDEIER); 1683 1684 ironlake_enable_pch_hotplug(dev); 1685 1686 return 0; 1687 } 1688 1689 static void 1690 i915_driver_irq_preinstall(struct drm_device * dev) 1691 { 1692 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1693 int pipe; 1694 1695 atomic_set(&dev_priv->irq_received, 0); 1696 1697 TASK_INIT(&dev_priv->hotplug_task, 0, i915_hotplug_work_func, 1698 dev->dev_private); 1699 TASK_INIT(&dev_priv->error_task, 0, i915_error_work_func, 1700 dev->dev_private); 1701 TASK_INIT(&dev_priv->rps_task, 0, gen6_pm_rps_work_func, 1702 dev->dev_private); 1703 1704 if (I915_HAS_HOTPLUG(dev)) { 1705 I915_WRITE(PORT_HOTPLUG_EN, 0); 1706 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1707 } 1708 1709 I915_WRITE(HWSTAM, 0xeffe); 1710 for_each_pipe(pipe) 1711 I915_WRITE(PIPESTAT(pipe), 0); 1712 I915_WRITE(IMR, 0xffffffff); 1713 I915_WRITE(IER, 0x0); 1714 POSTING_READ(IER); 1715 } 1716 1717 /* 1718 * Must be called after intel_modeset_init or hotplug interrupts won't be 1719 * enabled correctly. 1720 */ 1721 static int 1722 i915_driver_irq_postinstall(struct drm_device *dev) 1723 { 1724 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1725 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; 1726 u32 error_mask; 1727 1728 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; 1729 1730 /* Unmask the interrupts that we always want on. */ 1731 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; 1732 1733 dev_priv->pipestat[0] = 0; 1734 dev_priv->pipestat[1] = 0; 1735 1736 if (I915_HAS_HOTPLUG(dev)) { 1737 /* Enable in IER... */ 1738 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 1739 /* and unmask in IMR */ 1740 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 1741 } 1742 1743 /* 1744 * Enable some error detection, note the instruction error mask 1745 * bit is reserved, so we leave it masked. 1746 */ 1747 if (IS_G4X(dev)) { 1748 error_mask = ~(GM45_ERROR_PAGE_TABLE | 1749 GM45_ERROR_MEM_PRIV | 1750 GM45_ERROR_CP_PRIV | 1751 I915_ERROR_MEMORY_REFRESH); 1752 } else { 1753 error_mask = ~(I915_ERROR_PAGE_TABLE | 1754 I915_ERROR_MEMORY_REFRESH); 1755 } 1756 I915_WRITE(EMR, error_mask); 1757 1758 I915_WRITE(IMR, dev_priv->irq_mask); 1759 I915_WRITE(IER, enable_mask); 1760 POSTING_READ(IER); 1761 1762 if (I915_HAS_HOTPLUG(dev)) { 1763 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 1764 1765 /* Note HDMI and DP share bits */ 1766 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) 1767 hotplug_en |= HDMIB_HOTPLUG_INT_EN; 1768 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) 1769 hotplug_en |= HDMIC_HOTPLUG_INT_EN; 1770 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) 1771 hotplug_en |= HDMID_HOTPLUG_INT_EN; 1772 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915) 1773 hotplug_en |= SDVOC_HOTPLUG_INT_EN; 1774 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915) 1775 hotplug_en |= SDVOB_HOTPLUG_INT_EN; 1776 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { 1777 hotplug_en |= CRT_HOTPLUG_INT_EN; 1778 1779 /* Programming the CRT detection parameters tends 1780 to generate a spurious hotplug event about three 1781 seconds later. So just do it once. 1782 */ 1783 if (IS_G4X(dev)) 1784 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 1785 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 1786 } 1787 1788 /* Ignore TV since it's buggy */ 1789 1790 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 1791 } 1792 1793 #if 1 1794 KIB_NOTYET(); 1795 #else 1796 intel_opregion_enable_asle(dev); 1797 #endif 1798 1799 return 0; 1800 } 1801 1802 static void 1803 ironlake_irq_uninstall(struct drm_device *dev) 1804 { 1805 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1806 1807 if (dev_priv == NULL) 1808 return; 1809 1810 dev_priv->vblank_pipe = 0; 1811 1812 I915_WRITE(HWSTAM, 0xffffffff); 1813 1814 I915_WRITE(DEIMR, 0xffffffff); 1815 I915_WRITE(DEIER, 0x0); 1816 I915_WRITE(DEIIR, I915_READ(DEIIR)); 1817 1818 I915_WRITE(GTIMR, 0xffffffff); 1819 I915_WRITE(GTIER, 0x0); 1820 I915_WRITE(GTIIR, I915_READ(GTIIR)); 1821 1822 I915_WRITE(SDEIMR, 0xffffffff); 1823 I915_WRITE(SDEIER, 0x0); 1824 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 1825 1826 taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task); 1827 taskqueue_drain(dev_priv->tq, &dev_priv->error_task); 1828 taskqueue_drain(dev_priv->tq, &dev_priv->rps_task); 1829 } 1830 1831 static void i915_driver_irq_uninstall(struct drm_device * dev) 1832 { 1833 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1834 int pipe; 1835 1836 if (!dev_priv) 1837 return; 1838 1839 dev_priv->vblank_pipe = 0; 1840 1841 if (I915_HAS_HOTPLUG(dev)) { 1842 I915_WRITE(PORT_HOTPLUG_EN, 0); 1843 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 1844 } 1845 1846 I915_WRITE(HWSTAM, 0xffffffff); 1847 for_each_pipe(pipe) 1848 I915_WRITE(PIPESTAT(pipe), 0); 1849 I915_WRITE(IMR, 0xffffffff); 1850 I915_WRITE(IER, 0x0); 1851 1852 for_each_pipe(pipe) 1853 I915_WRITE(PIPESTAT(pipe), 1854 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 1855 I915_WRITE(IIR, I915_READ(IIR)); 1856 1857 taskqueue_drain(dev_priv->tq, &dev_priv->hotplug_task); 1858 taskqueue_drain(dev_priv->tq, &dev_priv->error_task); 1859 taskqueue_drain(dev_priv->tq, &dev_priv->rps_task); 1860 } 1861 1862 void 1863 intel_irq_init(struct drm_device *dev) 1864 { 1865 1866 dev->driver->get_vblank_counter = i915_get_vblank_counter; 1867 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 1868 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { 1869 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 1870 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 1871 } 1872 1873 if (drm_core_check_feature(dev, DRIVER_MODESET)) 1874 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 1875 else 1876 dev->driver->get_vblank_timestamp = NULL; 1877 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 1878 1879 if (IS_IVYBRIDGE(dev)) { 1880 /* Share pre & uninstall handlers with ILK/SNB */ 1881 dev->driver->irq_handler = ivybridge_irq_handler; 1882 dev->driver->irq_preinstall = ironlake_irq_preinstall; 1883 dev->driver->irq_postinstall = ivybridge_irq_postinstall; 1884 dev->driver->irq_uninstall = ironlake_irq_uninstall; 1885 dev->driver->enable_vblank = ivybridge_enable_vblank; 1886 dev->driver->disable_vblank = ivybridge_disable_vblank; 1887 } else if (HAS_PCH_SPLIT(dev)) { 1888 dev->driver->irq_handler = ironlake_irq_handler; 1889 dev->driver->irq_preinstall = ironlake_irq_preinstall; 1890 dev->driver->irq_postinstall = ironlake_irq_postinstall; 1891 dev->driver->irq_uninstall = ironlake_irq_uninstall; 1892 dev->driver->enable_vblank = ironlake_enable_vblank; 1893 dev->driver->disable_vblank = ironlake_disable_vblank; 1894 } else { 1895 dev->driver->irq_preinstall = i915_driver_irq_preinstall; 1896 dev->driver->irq_postinstall = i915_driver_irq_postinstall; 1897 dev->driver->irq_uninstall = i915_driver_irq_uninstall; 1898 dev->driver->irq_handler = i915_driver_irq_handler; 1899 dev->driver->enable_vblank = i915_enable_vblank; 1900 dev->driver->disable_vblank = i915_disable_vblank; 1901 } 1902 } 1903 1904 static struct drm_i915_error_object * 1905 i915_error_object_create(struct drm_i915_private *dev_priv, 1906 struct drm_i915_gem_object *src) 1907 { 1908 struct drm_i915_error_object *dst; 1909 struct sf_buf *sf; 1910 void *d, *s; 1911 int page, page_count; 1912 u32 reloc_offset; 1913 1914 if (src == NULL || src->pages == NULL) 1915 return NULL; 1916 1917 page_count = src->base.size / PAGE_SIZE; 1918 1919 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), DRM_I915_GEM, 1920 M_NOWAIT); 1921 if (dst == NULL) 1922 return (NULL); 1923 1924 reloc_offset = src->gtt_offset; 1925 for (page = 0; page < page_count; page++) { 1926 d = kmalloc(PAGE_SIZE, DRM_I915_GEM, M_NOWAIT); 1927 if (d == NULL) 1928 goto unwind; 1929 1930 if (reloc_offset < dev_priv->mm.gtt_mappable_end) { 1931 /* Simply ignore tiling or any overlapping fence. 1932 * It's part of the error state, and this hopefully 1933 * captures what the GPU read. 1934 */ 1935 s = pmap_mapdev_attr(src->base.dev->agp->base + 1936 reloc_offset, PAGE_SIZE, PAT_WRITE_COMBINING); 1937 memcpy(d, s, PAGE_SIZE); 1938 pmap_unmapdev((vm_offset_t)s, PAGE_SIZE); 1939 } else { 1940 drm_clflush_pages(&src->pages[page], 1); 1941 1942 sf = sf_buf_alloc(src->pages[page]); 1943 if (sf != NULL) { 1944 s = (void *)(uintptr_t)sf_buf_kva(sf); 1945 memcpy(d, s, PAGE_SIZE); 1946 sf_buf_free(sf); 1947 } else { 1948 bzero(d, PAGE_SIZE); 1949 strcpy(d, "XXXKIB"); 1950 } 1951 1952 drm_clflush_pages(&src->pages[page], 1); 1953 } 1954 1955 dst->pages[page] = d; 1956 1957 reloc_offset += PAGE_SIZE; 1958 } 1959 dst->page_count = page_count; 1960 dst->gtt_offset = src->gtt_offset; 1961 1962 return (dst); 1963 1964 unwind: 1965 while (page--) 1966 drm_free(dst->pages[page], DRM_I915_GEM); 1967 drm_free(dst, DRM_I915_GEM); 1968 return (NULL); 1969 } 1970 1971 static void 1972 i915_error_object_free(struct drm_i915_error_object *obj) 1973 { 1974 int page; 1975 1976 if (obj == NULL) 1977 return; 1978 1979 for (page = 0; page < obj->page_count; page++) 1980 drm_free(obj->pages[page], DRM_I915_GEM); 1981 1982 drm_free(obj, DRM_I915_GEM); 1983 } 1984 1985 static void 1986 i915_error_state_free(struct drm_device *dev, 1987 struct drm_i915_error_state *error) 1988 { 1989 int i; 1990 1991 for (i = 0; i < DRM_ARRAY_SIZE(error->ring); i++) { 1992 i915_error_object_free(error->ring[i].batchbuffer); 1993 i915_error_object_free(error->ring[i].ringbuffer); 1994 drm_free(error->ring[i].requests, DRM_I915_GEM); 1995 } 1996 1997 drm_free(error->active_bo, DRM_I915_GEM); 1998 drm_free(error->overlay, DRM_I915_GEM); 1999 drm_free(error, DRM_I915_GEM); 2000 } 2001 2002 static u32 2003 capture_bo_list(struct drm_i915_error_buffer *err, int count, 2004 struct list_head *head) 2005 { 2006 struct drm_i915_gem_object *obj; 2007 int i = 0; 2008 2009 list_for_each_entry(obj, head, mm_list) { 2010 err->size = obj->base.size; 2011 err->name = obj->base.name; 2012 err->seqno = obj->last_rendering_seqno; 2013 err->gtt_offset = obj->gtt_offset; 2014 err->read_domains = obj->base.read_domains; 2015 err->write_domain = obj->base.write_domain; 2016 err->fence_reg = obj->fence_reg; 2017 err->pinned = 0; 2018 if (obj->pin_count > 0) 2019 err->pinned = 1; 2020 if (obj->user_pin_count > 0) 2021 err->pinned = -1; 2022 err->tiling = obj->tiling_mode; 2023 err->dirty = obj->dirty; 2024 err->purgeable = obj->madv != I915_MADV_WILLNEED; 2025 err->ring = obj->ring ? obj->ring->id : -1; 2026 err->cache_level = obj->cache_level; 2027 2028 if (++i == count) 2029 break; 2030 2031 err++; 2032 } 2033 2034 return (i); 2035 } 2036 2037 static void 2038 i915_gem_record_fences(struct drm_device *dev, 2039 struct drm_i915_error_state *error) 2040 { 2041 struct drm_i915_private *dev_priv = dev->dev_private; 2042 int i; 2043 2044 /* Fences */ 2045 switch (INTEL_INFO(dev)->gen) { 2046 case 7: 2047 case 6: 2048 for (i = 0; i < 16; i++) 2049 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); 2050 break; 2051 case 5: 2052 case 4: 2053 for (i = 0; i < 16; i++) 2054 error->fence[i] = I915_READ64(FENCE_REG_965_0 + 2055 (i * 8)); 2056 break; 2057 case 3: 2058 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) 2059 for (i = 0; i < 8; i++) 2060 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + 2061 (i * 4)); 2062 case 2: 2063 for (i = 0; i < 8; i++) 2064 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); 2065 break; 2066 2067 } 2068 } 2069 2070 static struct drm_i915_error_object * 2071 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, 2072 struct intel_ring_buffer *ring) 2073 { 2074 struct drm_i915_gem_object *obj; 2075 u32 seqno; 2076 2077 if (!ring->get_seqno) 2078 return (NULL); 2079 2080 seqno = ring->get_seqno(ring); 2081 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { 2082 if (obj->ring != ring) 2083 continue; 2084 2085 if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) 2086 continue; 2087 2088 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) 2089 continue; 2090 2091 /* We need to copy these to an anonymous buffer as the simplest 2092 * method to avoid being overwritten by userspace. 2093 */ 2094 return (i915_error_object_create(dev_priv, obj)); 2095 } 2096 2097 return NULL; 2098 } 2099 2100 static void 2101 i915_record_ring_state(struct drm_device *dev, 2102 struct drm_i915_error_state *error, 2103 struct intel_ring_buffer *ring) 2104 { 2105 struct drm_i915_private *dev_priv = dev->dev_private; 2106 2107 if (INTEL_INFO(dev)->gen >= 6) { 2108 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base)); 2109 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring)); 2110 error->semaphore_mboxes[ring->id][0] 2111 = I915_READ(RING_SYNC_0(ring->mmio_base)); 2112 error->semaphore_mboxes[ring->id][1] 2113 = I915_READ(RING_SYNC_1(ring->mmio_base)); 2114 } 2115 2116 if (INTEL_INFO(dev)->gen >= 4) { 2117 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base)); 2118 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base)); 2119 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base)); 2120 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base)); 2121 if (ring->id == RCS) { 2122 error->instdone1 = I915_READ(INSTDONE1); 2123 error->bbaddr = I915_READ64(BB_ADDR); 2124 } 2125 } else { 2126 error->ipeir[ring->id] = I915_READ(IPEIR); 2127 error->ipehr[ring->id] = I915_READ(IPEHR); 2128 error->instdone[ring->id] = I915_READ(INSTDONE); 2129 } 2130 2131 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base)); 2132 error->seqno[ring->id] = ring->get_seqno(ring); 2133 error->acthd[ring->id] = intel_ring_get_active_head(ring); 2134 error->head[ring->id] = I915_READ_HEAD(ring); 2135 error->tail[ring->id] = I915_READ_TAIL(ring); 2136 2137 error->cpu_ring_head[ring->id] = ring->head; 2138 error->cpu_ring_tail[ring->id] = ring->tail; 2139 } 2140 2141 static void 2142 i915_gem_record_rings(struct drm_device *dev, 2143 struct drm_i915_error_state *error) 2144 { 2145 struct drm_i915_private *dev_priv = dev->dev_private; 2146 struct drm_i915_gem_request *request; 2147 int i, count; 2148 2149 for (i = 0; i < I915_NUM_RINGS; i++) { 2150 struct intel_ring_buffer *ring = &dev_priv->ring[i]; 2151 2152 if (ring->obj == NULL) 2153 continue; 2154 2155 i915_record_ring_state(dev, error, ring); 2156 2157 error->ring[i].batchbuffer = 2158 i915_error_first_batchbuffer(dev_priv, ring); 2159 2160 error->ring[i].ringbuffer = 2161 i915_error_object_create(dev_priv, ring->obj); 2162 2163 count = 0; 2164 list_for_each_entry(request, &ring->request_list, list) 2165 count++; 2166 2167 error->ring[i].num_requests = count; 2168 error->ring[i].requests = kmalloc(count * 2169 sizeof(struct drm_i915_error_request), DRM_I915_GEM, 2170 M_WAITOK); 2171 if (error->ring[i].requests == NULL) { 2172 error->ring[i].num_requests = 0; 2173 continue; 2174 } 2175 2176 count = 0; 2177 list_for_each_entry(request, &ring->request_list, list) { 2178 struct drm_i915_error_request *erq; 2179 2180 erq = &error->ring[i].requests[count++]; 2181 erq->seqno = request->seqno; 2182 erq->jiffies = request->emitted_jiffies; 2183 erq->tail = request->tail; 2184 } 2185 } 2186 } 2187 2188 static void 2189 i915_capture_error_state(struct drm_device *dev) 2190 { 2191 struct drm_i915_private *dev_priv = dev->dev_private; 2192 struct drm_i915_gem_object *obj; 2193 struct drm_i915_error_state *error; 2194 int i, pipe; 2195 2196 lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE); 2197 error = dev_priv->first_error; 2198 lockmgr(&dev_priv->error_lock, LK_RELEASE); 2199 if (error != NULL) 2200 return; 2201 2202 /* Account for pipe specific data like PIPE*STAT */ 2203 error = kmalloc(sizeof(*error), DRM_I915_GEM, M_NOWAIT | M_ZERO); 2204 if (error == NULL) { 2205 DRM_DEBUG("out of memory, not capturing error state\n"); 2206 return; 2207 } 2208 2209 DRM_INFO("capturing error event; look for more information in " 2210 "sysctl hw.dri.%d.info.i915_error_state\n", dev->sysctl_node_idx); 2211 2212 error->eir = I915_READ(EIR); 2213 error->pgtbl_er = I915_READ(PGTBL_ER); 2214 for_each_pipe(pipe) 2215 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 2216 2217 if (INTEL_INFO(dev)->gen >= 6) { 2218 error->error = I915_READ(ERROR_GEN6); 2219 error->done_reg = I915_READ(DONE_REG); 2220 } 2221 2222 i915_gem_record_fences(dev, error); 2223 i915_gem_record_rings(dev, error); 2224 2225 /* Record buffers on the active and pinned lists. */ 2226 error->active_bo = NULL; 2227 error->pinned_bo = NULL; 2228 2229 i = 0; 2230 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) 2231 i++; 2232 error->active_bo_count = i; 2233 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) 2234 i++; 2235 error->pinned_bo_count = i - error->active_bo_count; 2236 2237 error->active_bo = NULL; 2238 error->pinned_bo = NULL; 2239 if (i) { 2240 error->active_bo = kmalloc(sizeof(*error->active_bo) * i, 2241 DRM_I915_GEM, M_NOWAIT); 2242 if (error->active_bo) 2243 error->pinned_bo = error->active_bo + 2244 error->active_bo_count; 2245 } 2246 2247 if (error->active_bo) 2248 error->active_bo_count = capture_bo_list(error->active_bo, 2249 error->active_bo_count, &dev_priv->mm.active_list); 2250 2251 if (error->pinned_bo) 2252 error->pinned_bo_count = capture_bo_list(error->pinned_bo, 2253 error->pinned_bo_count, &dev_priv->mm.pinned_list); 2254 2255 microtime(&error->time); 2256 2257 error->overlay = intel_overlay_capture_error_state(dev); 2258 error->display = intel_display_capture_error_state(dev); 2259 2260 lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE); 2261 if (dev_priv->first_error == NULL) { 2262 dev_priv->first_error = error; 2263 error = NULL; 2264 } 2265 lockmgr(&dev_priv->error_lock, LK_RELEASE); 2266 2267 if (error != NULL) 2268 i915_error_state_free(dev, error); 2269 } 2270 2271 void 2272 i915_destroy_error_state(struct drm_device *dev) 2273 { 2274 struct drm_i915_private *dev_priv = dev->dev_private; 2275 struct drm_i915_error_state *error; 2276 2277 lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE); 2278 error = dev_priv->first_error; 2279 dev_priv->first_error = NULL; 2280 lockmgr(&dev_priv->error_lock, LK_RELEASE); 2281 2282 if (error != NULL) 2283 i915_error_state_free(dev, error); 2284 } 2285