1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- 2 */ 3 /* 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial portions 17 * of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 26 * 27 */ 28 29 #include <drm/drmP.h> 30 #include <drm/i915_drm.h> 31 #include "i915_drv.h" 32 #include "i915_trace.h" 33 #include "intel_drv.h" 34 35 static const u32 hpd_ibx[] = { 36 [HPD_CRT] = SDE_CRT_HOTPLUG, 37 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, 38 [HPD_PORT_B] = SDE_PORTB_HOTPLUG, 39 [HPD_PORT_C] = SDE_PORTC_HOTPLUG, 40 [HPD_PORT_D] = SDE_PORTD_HOTPLUG 41 }; 42 43 static const u32 hpd_cpt[] = { 44 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, 45 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, 46 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, 47 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, 48 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT 49 }; 50 51 static const u32 hpd_mask_i915[] = { 52 [HPD_CRT] = CRT_HOTPLUG_INT_EN, 53 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, 54 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, 55 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, 56 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, 57 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN 58 }; 59 60 static const u32 hpd_status_g4x[] = { 61 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 62 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, 63 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, 64 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 65 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 66 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS 67 }; 68 69 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */ 70 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, 71 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, 72 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, 73 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, 74 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, 75 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS 76 }; 77 78 /* For display hotplug interrupt */ 79 static void 80 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 81 { 82 assert_spin_locked(&dev_priv->irq_lock); 83 84 if (dev_priv->pc8.irqs_disabled) { 85 WARN(1, "IRQs disabled\n"); 86 dev_priv->pc8.regsave.deimr &= ~mask; 87 return; 88 } 89 90 if ((dev_priv->irq_mask & mask) != 0) { 91 dev_priv->irq_mask &= ~mask; 92 I915_WRITE(DEIMR, dev_priv->irq_mask); 93 POSTING_READ(DEIMR); 94 } 95 } 96 97 static void 98 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) 99 { 100 assert_spin_locked(&dev_priv->irq_lock); 101 102 if (dev_priv->pc8.irqs_disabled) { 103 WARN(1, "IRQs disabled\n"); 104 dev_priv->pc8.regsave.deimr |= mask; 105 return; 106 } 107 108 if ((dev_priv->irq_mask & mask) != mask) { 109 dev_priv->irq_mask |= mask; 110 I915_WRITE(DEIMR, dev_priv->irq_mask); 111 POSTING_READ(DEIMR); 112 } 113 } 114 115 /** 116 * ilk_update_gt_irq - update GTIMR 117 * @dev_priv: driver private 118 * @interrupt_mask: mask of interrupt bits to update 119 * @enabled_irq_mask: mask of interrupt bits to enable 120 */ 121 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, 122 uint32_t interrupt_mask, 123 uint32_t enabled_irq_mask) 124 { 125 assert_spin_locked(&dev_priv->irq_lock); 126 127 if (dev_priv->pc8.irqs_disabled) { 128 WARN(1, "IRQs disabled\n"); 129 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask; 130 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask & 131 interrupt_mask); 132 return; 133 } 134 135 dev_priv->gt_irq_mask &= ~interrupt_mask; 136 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); 137 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 138 POSTING_READ(GTIMR); 139 } 140 141 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 142 { 143 ilk_update_gt_irq(dev_priv, mask, mask); 144 } 145 146 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) 147 { 148 ilk_update_gt_irq(dev_priv, mask, 0); 149 } 150 151 /** 152 * snb_update_pm_irq - update GEN6_PMIMR 153 * @dev_priv: driver private 154 * @interrupt_mask: mask of interrupt bits to update 155 * @enabled_irq_mask: mask of interrupt bits to enable 156 */ 157 static void snb_update_pm_irq(struct drm_i915_private *dev_priv, 158 uint32_t interrupt_mask, 159 uint32_t enabled_irq_mask) 160 { 161 uint32_t new_val; 162 163 assert_spin_locked(&dev_priv->irq_lock); 164 165 if (dev_priv->pc8.irqs_disabled) { 166 WARN(1, "IRQs disabled\n"); 167 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask; 168 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask & 169 interrupt_mask); 170 return; 171 } 172 173 new_val = dev_priv->pm_irq_mask; 174 new_val &= ~interrupt_mask; 175 new_val |= (~enabled_irq_mask & interrupt_mask); 176 177 if (new_val != dev_priv->pm_irq_mask) { 178 dev_priv->pm_irq_mask = new_val; 179 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); 180 POSTING_READ(GEN6_PMIMR); 181 } 182 } 183 184 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 185 { 186 snb_update_pm_irq(dev_priv, mask, mask); 187 } 188 189 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) 190 { 191 snb_update_pm_irq(dev_priv, mask, 0); 192 } 193 194 static bool ivb_can_enable_err_int(struct drm_device *dev) 195 { 196 struct drm_i915_private *dev_priv = dev->dev_private; 197 struct intel_crtc *crtc; 198 enum i915_pipe pipe; 199 200 assert_spin_locked(&dev_priv->irq_lock); 201 202 for_each_pipe(pipe) { 203 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 204 205 if (crtc->cpu_fifo_underrun_disabled) 206 return false; 207 } 208 209 return true; 210 } 211 212 static bool cpt_can_enable_serr_int(struct drm_device *dev) 213 { 214 struct drm_i915_private *dev_priv = dev->dev_private; 215 enum i915_pipe pipe; 216 struct intel_crtc *crtc; 217 218 assert_spin_locked(&dev_priv->irq_lock); 219 220 for_each_pipe(pipe) { 221 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 222 223 if (crtc->pch_fifo_underrun_disabled) 224 return false; 225 } 226 227 return true; 228 } 229 230 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev, 231 enum i915_pipe pipe, bool enable) 232 { 233 struct drm_i915_private *dev_priv = dev->dev_private; 234 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : 235 DE_PIPEB_FIFO_UNDERRUN; 236 237 if (enable) 238 ironlake_enable_display_irq(dev_priv, bit); 239 else 240 ironlake_disable_display_irq(dev_priv, bit); 241 } 242 243 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev, 244 enum i915_pipe pipe, bool enable) 245 { 246 struct drm_i915_private *dev_priv = dev->dev_private; 247 if (enable) { 248 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); 249 250 if (!ivb_can_enable_err_int(dev)) 251 return; 252 253 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB); 254 } else { 255 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB); 256 257 /* Change the state _after_ we've read out the current one. */ 258 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB); 259 260 if (!was_enabled && 261 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) { 262 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n", 263 pipe_name(pipe)); 264 } 265 } 266 } 267 268 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev, 269 enum i915_pipe pipe, bool enable) 270 { 271 struct drm_i915_private *dev_priv = dev->dev_private; 272 273 assert_spin_locked(&dev_priv->irq_lock); 274 275 if (enable) 276 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN; 277 else 278 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN; 279 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 280 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 281 } 282 283 /** 284 * ibx_display_interrupt_update - update SDEIMR 285 * @dev_priv: driver private 286 * @interrupt_mask: mask of interrupt bits to update 287 * @enabled_irq_mask: mask of interrupt bits to enable 288 */ 289 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, 290 uint32_t interrupt_mask, 291 uint32_t enabled_irq_mask) 292 { 293 uint32_t sdeimr = I915_READ(SDEIMR); 294 sdeimr &= ~interrupt_mask; 295 sdeimr |= (~enabled_irq_mask & interrupt_mask); 296 297 assert_spin_locked(&dev_priv->irq_lock); 298 299 if (dev_priv->pc8.irqs_disabled && 300 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) { 301 WARN(1, "IRQs disabled\n"); 302 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask; 303 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask & 304 interrupt_mask); 305 return; 306 } 307 308 I915_WRITE(SDEIMR, sdeimr); 309 POSTING_READ(SDEIMR); 310 } 311 #define ibx_enable_display_interrupt(dev_priv, bits) \ 312 ibx_display_interrupt_update((dev_priv), (bits), (bits)) 313 #define ibx_disable_display_interrupt(dev_priv, bits) \ 314 ibx_display_interrupt_update((dev_priv), (bits), 0) 315 316 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev, 317 enum transcoder pch_transcoder, 318 bool enable) 319 { 320 struct drm_i915_private *dev_priv = dev->dev_private; 321 uint32_t bit = (pch_transcoder == TRANSCODER_A) ? 322 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER; 323 324 if (enable) 325 ibx_enable_display_interrupt(dev_priv, bit); 326 else 327 ibx_disable_display_interrupt(dev_priv, bit); 328 } 329 330 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev, 331 enum transcoder pch_transcoder, 332 bool enable) 333 { 334 struct drm_i915_private *dev_priv = dev->dev_private; 335 336 if (enable) { 337 I915_WRITE(SERR_INT, 338 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); 339 340 if (!cpt_can_enable_serr_int(dev)) 341 return; 342 343 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT); 344 } else { 345 uint32_t tmp = I915_READ(SERR_INT); 346 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT); 347 348 /* Change the state _after_ we've read out the current one. */ 349 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT); 350 351 if (!was_enabled && 352 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) { 353 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n", 354 transcoder_name(pch_transcoder)); 355 } 356 } 357 } 358 359 /** 360 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages 361 * @dev: drm device 362 * @pipe: pipe 363 * @enable: true if we want to report FIFO underrun errors, false otherwise 364 * 365 * This function makes us disable or enable CPU fifo underruns for a specific 366 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun 367 * reporting for one pipe may also disable all the other CPU error interruts for 368 * the other pipes, due to the fact that there's just one interrupt mask/enable 369 * bit for all the pipes. 370 * 371 * Returns the previous state of underrun reporting. 372 */ 373 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, 374 enum i915_pipe pipe, bool enable) 375 { 376 struct drm_i915_private *dev_priv = dev->dev_private; 377 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 379 bool ret; 380 381 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 382 383 ret = !intel_crtc->cpu_fifo_underrun_disabled; 384 385 if (enable == ret) 386 goto done; 387 388 intel_crtc->cpu_fifo_underrun_disabled = !enable; 389 390 if (IS_GEN5(dev) || IS_GEN6(dev)) 391 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); 392 else if (IS_GEN7(dev)) 393 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable); 394 else if (IS_GEN8(dev)) 395 broadwell_set_fifo_underrun_reporting(dev, pipe, enable); 396 397 done: 398 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 399 return ret; 400 } 401 402 /** 403 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages 404 * @dev: drm device 405 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older) 406 * @enable: true if we want to report FIFO underrun errors, false otherwise 407 * 408 * This function makes us disable or enable PCH fifo underruns for a specific 409 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO 410 * underrun reporting for one transcoder may also disable all the other PCH 411 * error interruts for the other transcoders, due to the fact that there's just 412 * one interrupt mask/enable bit for all the transcoders. 413 * 414 * Returns the previous state of underrun reporting. 415 */ 416 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev, 417 enum transcoder pch_transcoder, 418 bool enable) 419 { 420 struct drm_i915_private *dev_priv = dev->dev_private; 421 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder]; 422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 423 bool ret; 424 425 /* 426 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT 427 * has only one pch transcoder A that all pipes can use. To avoid racy 428 * pch transcoder -> pipe lookups from interrupt code simply store the 429 * underrun statistics in crtc A. Since we never expose this anywhere 430 * nor use it outside of the fifo underrun code here using the "wrong" 431 * crtc on LPT won't cause issues. 432 */ 433 434 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 435 436 ret = !intel_crtc->pch_fifo_underrun_disabled; 437 438 if (enable == ret) 439 goto done; 440 441 intel_crtc->pch_fifo_underrun_disabled = !enable; 442 443 if (HAS_PCH_IBX(dev)) 444 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 445 else 446 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable); 447 448 done: 449 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 450 return ret; 451 } 452 453 454 void 455 i915_enable_pipestat(drm_i915_private_t *dev_priv, enum i915_pipe pipe, u32 mask) 456 { 457 u32 reg = PIPESTAT(pipe); 458 u32 pipestat = I915_READ(reg) & 0x7fff0000; 459 460 assert_spin_locked(&dev_priv->irq_lock); 461 462 if ((pipestat & mask) == mask) 463 return; 464 465 /* Enable the interrupt, clear any pending status */ 466 pipestat |= mask | (mask >> 16); 467 I915_WRITE(reg, pipestat); 468 POSTING_READ(reg); 469 } 470 471 void 472 i915_disable_pipestat(drm_i915_private_t *dev_priv, enum i915_pipe pipe, u32 mask) 473 { 474 u32 reg = PIPESTAT(pipe); 475 u32 pipestat = I915_READ(reg) & 0x7fff0000; 476 477 assert_spin_locked(&dev_priv->irq_lock); 478 479 if ((pipestat & mask) == 0) 480 return; 481 482 pipestat &= ~mask; 483 I915_WRITE(reg, pipestat); 484 POSTING_READ(reg); 485 } 486 487 /** 488 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion 489 */ 490 static void i915_enable_asle_pipestat(struct drm_device *dev) 491 { 492 drm_i915_private_t *dev_priv = dev->dev_private; 493 494 if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) 495 return; 496 497 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 498 499 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_ENABLE); 500 if (INTEL_INFO(dev)->gen >= 4) 501 i915_enable_pipestat(dev_priv, PIPE_A, 502 PIPE_LEGACY_BLC_EVENT_ENABLE); 503 504 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 505 } 506 507 /** 508 * i915_pipe_enabled - check if a pipe is enabled 509 * @dev: DRM device 510 * @pipe: pipe to check 511 * 512 * Reading certain registers when the pipe is disabled can hang the chip. 513 * Use this routine to make sure the PLL is running and the pipe is active 514 * before reading such registers if unsure. 515 */ 516 static int 517 i915_pipe_enabled(struct drm_device *dev, int pipe) 518 { 519 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 520 521 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 522 /* Locking is horribly broken here, but whatever. */ 523 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 525 526 return intel_crtc->active; 527 } else { 528 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; 529 } 530 } 531 532 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) 533 { 534 /* Gen2 doesn't have a hardware frame counter */ 535 return 0; 536 } 537 538 /* Called from drm generic code, passed a 'crtc', which 539 * we use as a pipe index 540 */ 541 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) 542 { 543 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 544 unsigned long high_frame; 545 unsigned long low_frame; 546 u32 high1, high2, low, pixel, vbl_start; 547 548 if (!i915_pipe_enabled(dev, pipe)) { 549 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 550 "pipe %c\n", pipe_name(pipe)); 551 return 0; 552 } 553 554 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 555 struct intel_crtc *intel_crtc = 556 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); 557 const struct drm_display_mode *mode = 558 &intel_crtc->config.adjusted_mode; 559 560 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal; 561 } else { 562 enum transcoder cpu_transcoder = (enum transcoder) pipe; 563 u32 htotal; 564 565 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1; 566 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1; 567 568 vbl_start *= htotal; 569 } 570 571 high_frame = PIPEFRAME(pipe); 572 low_frame = PIPEFRAMEPIXEL(pipe); 573 574 /* 575 * High & low register fields aren't synchronized, so make sure 576 * we get a low value that's stable across two reads of the high 577 * register. 578 */ 579 do { 580 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 581 low = I915_READ(low_frame); 582 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; 583 } while (high1 != high2); 584 585 high1 >>= PIPE_FRAME_HIGH_SHIFT; 586 pixel = low & PIPE_PIXEL_MASK; 587 low >>= PIPE_FRAME_LOW_SHIFT; 588 589 /* 590 * The frame counter increments at beginning of active. 591 * Cook up a vblank counter by also checking the pixel 592 * counter against vblank start. 593 */ 594 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; 595 } 596 597 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 598 { 599 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 600 int reg = PIPE_FRMCOUNT_GM45(pipe); 601 602 if (!i915_pipe_enabled(dev, pipe)) { 603 DRM_DEBUG_DRIVER("trying to get vblank count for disabled " 604 "pipe %c\n", pipe_name(pipe)); 605 return 0; 606 } 607 608 return I915_READ(reg); 609 } 610 611 /* raw reads, only for fast reads of display block, no need for forcewake etc. */ 612 #define __raw_i915_read32(dev_priv__, reg__) DRM_READ32(dev_priv__->mmio_map, reg__) 613 614 static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum i915_pipe pipe) 615 { 616 struct drm_i915_private *dev_priv = dev->dev_private; 617 uint32_t status; 618 int reg; 619 620 if (INTEL_INFO(dev)->gen >= 8) { 621 status = GEN8_PIPE_VBLANK; 622 reg = GEN8_DE_PIPE_ISR(pipe); 623 } else if (INTEL_INFO(dev)->gen >= 7) { 624 status = DE_PIPE_VBLANK_IVB(pipe); 625 reg = DEISR; 626 } else { 627 status = DE_PIPE_VBLANK(pipe); 628 reg = DEISR; 629 } 630 631 return __raw_i915_read32(dev_priv, reg) & status; 632 } 633 634 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, 635 unsigned int flags, int *vpos, int *hpos, 636 ktime_t *stime, ktime_t *etime) 637 { 638 struct drm_i915_private *dev_priv = dev->dev_private; 639 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 641 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; 642 int position; 643 int vbl_start, vbl_end, htotal, vtotal; 644 bool in_vbl = true; 645 int ret = 0; 646 647 if (!intel_crtc->active) { 648 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " 649 "pipe %c\n", pipe_name(pipe)); 650 return 0; 651 } 652 653 htotal = mode->crtc_htotal; 654 vtotal = mode->crtc_vtotal; 655 vbl_start = mode->crtc_vblank_start; 656 vbl_end = mode->crtc_vblank_end; 657 658 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 659 vbl_start = DIV_ROUND_UP(vbl_start, 2); 660 vbl_end /= 2; 661 vtotal /= 2; 662 } 663 664 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; 665 666 /* 667 * Lock uncore.lock, as we will do multiple timing critical raw 668 * register reads, potentially with preemption disabled, so the 669 * following code must not block on uncore.lock. 670 */ 671 lockmgr(&dev_priv->uncore.lock, LK_EXCLUSIVE); 672 673 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 674 675 /* Get optional system timestamp before query. */ 676 if (stime) 677 *stime = ktime_get(); 678 679 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 680 /* No obvious pixelcount register. Only query vertical 681 * scanout position from Display scan line register. 682 */ 683 if (IS_GEN2(dev)) 684 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; 685 else 686 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; 687 688 if (HAS_DDI(dev)) { 689 /* 690 * On HSW HDMI outputs there seems to be a 2 line 691 * difference, whereas eDP has the normal 1 line 692 * difference that earlier platforms have. External 693 * DP is unknown. For now just check for the 2 line 694 * difference case on all output types on HSW+. 695 * 696 * This might misinterpret the scanline counter being 697 * one line too far along on eDP, but that's less 698 * dangerous than the alternative since that would lead 699 * the vblank timestamp code astray when it sees a 700 * scanline count before vblank_start during a vblank 701 * interrupt. 702 */ 703 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); 704 if ((in_vbl && (position == vbl_start - 2 || 705 position == vbl_start - 1)) || 706 (!in_vbl && (position == vbl_end - 2 || 707 position == vbl_end - 1))) 708 position = (position + 2) % vtotal; 709 } else if (HAS_PCH_SPLIT(dev)) { 710 /* 711 * The scanline counter increments at the leading edge 712 * of hsync, ie. it completely misses the active portion 713 * of the line. Fix up the counter at both edges of vblank 714 * to get a more accurate picture whether we're in vblank 715 * or not. 716 */ 717 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe); 718 if ((in_vbl && position == vbl_start - 1) || 719 (!in_vbl && position == vbl_end - 1)) 720 position = (position + 1) % vtotal; 721 } else { 722 /* 723 * ISR vblank status bits don't work the way we'd want 724 * them to work on non-PCH platforms (for 725 * ilk_pipe_in_vblank_locked()), and there doesn't 726 * appear any other way to determine if we're currently 727 * in vblank. 728 * 729 * Instead let's assume that we're already in vblank if 730 * we got called from the vblank interrupt and the 731 * scanline counter value indicates that we're on the 732 * line just prior to vblank start. This should result 733 * in the correct answer, unless the vblank interrupt 734 * delivery really got delayed for almost exactly one 735 * full frame/field. 736 */ 737 if (flags & DRM_CALLED_FROM_VBLIRQ && 738 position == vbl_start - 1) { 739 position = (position + 1) % vtotal; 740 741 /* Signal this correction as "applied". */ 742 ret |= 0x8; 743 } 744 } 745 } else { 746 /* Have access to pixelcount since start of frame. 747 * We can split this into vertical and horizontal 748 * scanout position. 749 */ 750 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 751 752 /* convert to pixel counts */ 753 vbl_start *= htotal; 754 vbl_end *= htotal; 755 vtotal *= htotal; 756 } 757 758 /* Get optional system timestamp after query. */ 759 if (etime) 760 *etime = ktime_get(); 761 762 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 763 764 lockmgr(&dev_priv->uncore.lock, LK_RELEASE); 765 766 in_vbl = position >= vbl_start && position < vbl_end; 767 768 /* 769 * While in vblank, position will be negative 770 * counting up towards 0 at vbl_end. And outside 771 * vblank, position will be positive counting 772 * up since vbl_end. 773 */ 774 if (position >= vbl_start) 775 position -= vbl_end; 776 else 777 position += vtotal - vbl_end; 778 779 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 780 *vpos = position; 781 *hpos = 0; 782 } else { 783 *vpos = position / htotal; 784 *hpos = position - (*vpos * htotal); 785 } 786 787 /* In vblank? */ 788 if (in_vbl) 789 ret |= DRM_SCANOUTPOS_INVBL; 790 791 return ret; 792 } 793 794 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, 795 int *max_error, 796 struct timeval *vblank_time, 797 unsigned flags) 798 { 799 struct drm_crtc *crtc; 800 801 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { 802 DRM_ERROR("Invalid crtc %d\n", pipe); 803 return -EINVAL; 804 } 805 806 /* Get drm_crtc to timestamp: */ 807 crtc = intel_get_crtc_for_pipe(dev, pipe); 808 if (crtc == NULL) { 809 DRM_ERROR("Invalid crtc %d\n", pipe); 810 return -EINVAL; 811 } 812 813 if (!crtc->enabled) { 814 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); 815 return -EBUSY; 816 } 817 818 /* Helper routine in DRM core does all the work: */ 819 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 820 vblank_time, flags, 821 crtc, 822 &to_intel_crtc(crtc)->config.adjusted_mode); 823 } 824 825 static bool intel_hpd_irq_event(struct drm_device *dev, 826 struct drm_connector *connector) 827 { 828 enum drm_connector_status old_status; 829 830 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 831 old_status = connector->status; 832 833 connector->status = connector->funcs->detect(connector, false); 834 if (old_status == connector->status) 835 return false; 836 837 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", 838 connector->base.id, 839 drm_get_connector_name(connector), 840 drm_get_connector_status_name(old_status), 841 drm_get_connector_status_name(connector->status)); 842 843 return true; 844 } 845 846 /* 847 * Handle hotplug events outside the interrupt handler proper. 848 */ 849 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000) 850 851 static void i915_hotplug_work_func(struct work_struct *work) 852 { 853 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 854 hotplug_work); 855 struct drm_device *dev = dev_priv->dev; 856 struct drm_mode_config *mode_config = &dev->mode_config; 857 struct intel_connector *intel_connector; 858 struct intel_encoder *intel_encoder; 859 struct drm_connector *connector; 860 bool hpd_disabled = false; 861 bool changed = false; 862 u32 hpd_event_bits; 863 864 /* HPD irq before everything is fully set up. */ 865 if (!dev_priv->enable_hotplug_processing) 866 return; 867 868 mutex_lock(&mode_config->mutex); 869 DRM_DEBUG_KMS("running encoder hotplug functions\n"); 870 871 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 872 873 hpd_event_bits = dev_priv->hpd_event_bits; 874 dev_priv->hpd_event_bits = 0; 875 list_for_each_entry(connector, &mode_config->connector_list, head) { 876 intel_connector = to_intel_connector(connector); 877 intel_encoder = intel_connector->encoder; 878 if (intel_encoder->hpd_pin > HPD_NONE && 879 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED && 880 connector->polled == DRM_CONNECTOR_POLL_HPD) { 881 DRM_INFO("HPD interrupt storm detected on connector %s: " 882 "switching from hotplug detection to polling\n", 883 drm_get_connector_name(connector)); 884 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED; 885 connector->polled = DRM_CONNECTOR_POLL_CONNECT 886 | DRM_CONNECTOR_POLL_DISCONNECT; 887 hpd_disabled = true; 888 } 889 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { 890 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n", 891 drm_get_connector_name(connector), intel_encoder->hpd_pin); 892 } 893 } 894 /* if there were no outputs to poll, poll was disabled, 895 * therefore make sure it's enabled when disabling HPD on 896 * some connectors */ 897 if (hpd_disabled) { 898 drm_kms_helper_poll_enable(dev); 899 mod_timer(&dev_priv->hotplug_reenable_timer, 900 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY)); 901 } 902 903 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 904 905 list_for_each_entry(connector, &mode_config->connector_list, head) { 906 intel_connector = to_intel_connector(connector); 907 intel_encoder = intel_connector->encoder; 908 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) { 909 if (intel_encoder->hot_plug) 910 intel_encoder->hot_plug(intel_encoder); 911 if (intel_hpd_irq_event(dev, connector)) 912 changed = true; 913 } 914 } 915 mutex_unlock(&mode_config->mutex); 916 917 if (changed) 918 drm_kms_helper_hotplug_event(dev); 919 } 920 921 static void ironlake_rps_change_irq_handler(struct drm_device *dev) 922 { 923 drm_i915_private_t *dev_priv = dev->dev_private; 924 u32 busy_up, busy_down, max_avg, min_avg; 925 u8 new_delay; 926 927 lockmgr(&mchdev_lock, LK_EXCLUSIVE); 928 929 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); 930 931 new_delay = dev_priv->ips.cur_delay; 932 933 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); 934 busy_up = I915_READ(RCPREVBSYTUPAVG); 935 busy_down = I915_READ(RCPREVBSYTDNAVG); 936 max_avg = I915_READ(RCBMAXAVG); 937 min_avg = I915_READ(RCBMINAVG); 938 939 /* Handle RCS change request from hw */ 940 if (busy_up > max_avg) { 941 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) 942 new_delay = dev_priv->ips.cur_delay - 1; 943 if (new_delay < dev_priv->ips.max_delay) 944 new_delay = dev_priv->ips.max_delay; 945 } else if (busy_down < min_avg) { 946 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) 947 new_delay = dev_priv->ips.cur_delay + 1; 948 if (new_delay > dev_priv->ips.min_delay) 949 new_delay = dev_priv->ips.min_delay; 950 } 951 952 if (ironlake_set_drps(dev, new_delay)) 953 dev_priv->ips.cur_delay = new_delay; 954 955 lockmgr(&mchdev_lock, LK_RELEASE); 956 957 return; 958 } 959 960 static void notify_ring(struct drm_device *dev, 961 struct intel_ring_buffer *ring) 962 { 963 if (ring->obj == NULL) 964 return; 965 966 trace_i915_gem_request_complete(ring); 967 968 wake_up_all(&ring->irq_queue); 969 i915_queue_hangcheck(dev); 970 } 971 972 static void gen6_pm_rps_work(struct work_struct *work) 973 { 974 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 975 rps.work); 976 u32 pm_iir; 977 int new_delay, adj; 978 979 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 980 pm_iir = dev_priv->rps.pm_iir; 981 dev_priv->rps.pm_iir = 0; 982 /* Make sure not to corrupt PMIMR state used by ringbuffer code */ 983 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS); 984 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 985 986 /* Make sure we didn't queue anything we're not going to process. */ 987 WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS); 988 989 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0) 990 return; 991 992 mutex_lock(&dev_priv->rps.hw_lock); 993 994 adj = dev_priv->rps.last_adj; 995 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { 996 if (adj > 0) 997 adj *= 2; 998 else 999 adj = 1; 1000 new_delay = dev_priv->rps.cur_delay + adj; 1001 1002 /* 1003 * For better performance, jump directly 1004 * to RPe if we're below it. 1005 */ 1006 if (new_delay < dev_priv->rps.rpe_delay) 1007 new_delay = dev_priv->rps.rpe_delay; 1008 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { 1009 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay) 1010 new_delay = dev_priv->rps.rpe_delay; 1011 else 1012 new_delay = dev_priv->rps.min_delay; 1013 adj = 0; 1014 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { 1015 if (adj < 0) 1016 adj *= 2; 1017 else 1018 adj = -1; 1019 new_delay = dev_priv->rps.cur_delay + adj; 1020 } else { /* unknown event */ 1021 new_delay = dev_priv->rps.cur_delay; 1022 } 1023 1024 /* sysfs frequency interfaces may have snuck in while servicing the 1025 * interrupt 1026 */ 1027 new_delay = clamp_t(int, new_delay, 1028 dev_priv->rps.min_delay, dev_priv->rps.max_delay); 1029 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; 1030 1031 if (IS_VALLEYVIEW(dev_priv->dev)) 1032 valleyview_set_rps(dev_priv->dev, new_delay); 1033 else 1034 gen6_set_rps(dev_priv->dev, new_delay); 1035 1036 mutex_unlock(&dev_priv->rps.hw_lock); 1037 } 1038 1039 1040 /** 1041 * ivybridge_parity_work - Workqueue called when a parity error interrupt 1042 * occurred. 1043 * @work: workqueue struct 1044 * 1045 * Doesn't actually do anything except notify userspace. As a consequence of 1046 * this event, userspace should try to remap the bad rows since statistically 1047 * it is likely the same row is more likely to go bad again. 1048 */ 1049 static void ivybridge_parity_work(struct work_struct *work) 1050 { 1051 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, 1052 l3_parity.error_work); 1053 u32 error_status, row, bank, subbank; 1054 char *parity_event[6]; 1055 uint32_t misccpctl; 1056 uint8_t slice = 0; 1057 1058 /* We must turn off DOP level clock gating to access the L3 registers. 1059 * In order to prevent a get/put style interface, acquire struct mutex 1060 * any time we access those registers. 1061 */ 1062 mutex_lock(&dev_priv->dev->struct_mutex); 1063 1064 /* If we've screwed up tracking, just let the interrupt fire again */ 1065 if (WARN_ON(!dev_priv->l3_parity.which_slice)) 1066 goto out; 1067 1068 misccpctl = I915_READ(GEN7_MISCCPCTL); 1069 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); 1070 POSTING_READ(GEN7_MISCCPCTL); 1071 1072 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { 1073 u32 reg; 1074 1075 slice--; 1076 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) 1077 break; 1078 1079 dev_priv->l3_parity.which_slice &= ~(1<<slice); 1080 1081 reg = GEN7_L3CDERRST1 + (slice * 0x200); 1082 1083 error_status = I915_READ(reg); 1084 row = GEN7_PARITY_ERROR_ROW(error_status); 1085 bank = GEN7_PARITY_ERROR_BANK(error_status); 1086 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); 1087 1088 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); 1089 POSTING_READ(reg); 1090 1091 parity_event[0] = I915_L3_PARITY_UEVENT "=1"; 1092 parity_event[5] = NULL; 1093 1094 #if 0 1095 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, 1096 KOBJ_CHANGE, parity_event); 1097 #endif 1098 1099 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", 1100 slice, row, bank, subbank); 1101 1102 #if 0 1103 kfree(parity_event[4]); 1104 kfree(parity_event[3]); 1105 kfree(parity_event[2]); 1106 kfree(parity_event[1]); 1107 #endif 1108 } 1109 1110 I915_WRITE(GEN7_MISCCPCTL, misccpctl); 1111 1112 out: 1113 WARN_ON(dev_priv->l3_parity.which_slice); 1114 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1115 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); 1116 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1117 1118 mutex_unlock(&dev_priv->dev->struct_mutex); 1119 } 1120 1121 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) 1122 { 1123 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1124 1125 if (!HAS_L3_DPF(dev)) 1126 return; 1127 1128 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1129 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); 1130 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1131 1132 iir &= GT_PARITY_ERROR(dev); 1133 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) 1134 dev_priv->l3_parity.which_slice |= 1 << 1; 1135 1136 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) 1137 dev_priv->l3_parity.which_slice |= 1 << 0; 1138 1139 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); 1140 } 1141 1142 static void ilk_gt_irq_handler(struct drm_device *dev, 1143 struct drm_i915_private *dev_priv, 1144 u32 gt_iir) 1145 { 1146 if (gt_iir & 1147 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) 1148 notify_ring(dev, &dev_priv->ring[RCS]); 1149 if (gt_iir & ILK_BSD_USER_INTERRUPT) 1150 notify_ring(dev, &dev_priv->ring[VCS]); 1151 } 1152 1153 static void snb_gt_irq_handler(struct drm_device *dev, 1154 struct drm_i915_private *dev_priv, 1155 u32 gt_iir) 1156 { 1157 1158 if (gt_iir & 1159 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) 1160 notify_ring(dev, &dev_priv->ring[RCS]); 1161 if (gt_iir & GT_BSD_USER_INTERRUPT) 1162 notify_ring(dev, &dev_priv->ring[VCS]); 1163 if (gt_iir & GT_BLT_USER_INTERRUPT) 1164 notify_ring(dev, &dev_priv->ring[BCS]); 1165 1166 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | 1167 GT_BSD_CS_ERROR_INTERRUPT | 1168 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) { 1169 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir); 1170 i915_handle_error(dev, false); 1171 } 1172 1173 if (gt_iir & GT_PARITY_ERROR(dev)) 1174 ivybridge_parity_error_irq_handler(dev, gt_iir); 1175 } 1176 1177 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev, 1178 struct drm_i915_private *dev_priv, 1179 u32 master_ctl) 1180 { 1181 u32 rcs, bcs, vcs; 1182 uint32_t tmp = 0; 1183 1184 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { 1185 tmp = I915_READ(GEN8_GT_IIR(0)); 1186 if (tmp) { 1187 rcs = tmp >> GEN8_RCS_IRQ_SHIFT; 1188 bcs = tmp >> GEN8_BCS_IRQ_SHIFT; 1189 if (rcs & GT_RENDER_USER_INTERRUPT) 1190 notify_ring(dev, &dev_priv->ring[RCS]); 1191 if (bcs & GT_RENDER_USER_INTERRUPT) 1192 notify_ring(dev, &dev_priv->ring[BCS]); 1193 I915_WRITE(GEN8_GT_IIR(0), tmp); 1194 } else 1195 DRM_ERROR("The master control interrupt lied (GT0)!\n"); 1196 } 1197 1198 if (master_ctl & GEN8_GT_VCS1_IRQ) { 1199 tmp = I915_READ(GEN8_GT_IIR(1)); 1200 if (tmp) { 1201 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT; 1202 if (vcs & GT_RENDER_USER_INTERRUPT) 1203 notify_ring(dev, &dev_priv->ring[VCS]); 1204 I915_WRITE(GEN8_GT_IIR(1), tmp); 1205 } else 1206 DRM_ERROR("The master control interrupt lied (GT1)!\n"); 1207 } 1208 1209 if (master_ctl & GEN8_GT_VECS_IRQ) { 1210 tmp = I915_READ(GEN8_GT_IIR(3)); 1211 if (tmp) { 1212 vcs = tmp >> GEN8_VECS_IRQ_SHIFT; 1213 if (vcs & GT_RENDER_USER_INTERRUPT) 1214 notify_ring(dev, &dev_priv->ring[VECS]); 1215 I915_WRITE(GEN8_GT_IIR(3), tmp); 1216 } else 1217 DRM_ERROR("The master control interrupt lied (GT3)!\n"); 1218 } 1219 1220 } 1221 1222 #define HPD_STORM_DETECT_PERIOD 1000 1223 #define HPD_STORM_THRESHOLD 5 1224 1225 static inline void intel_hpd_irq_handler(struct drm_device *dev, 1226 u32 hotplug_trigger, 1227 const u32 *hpd) 1228 { 1229 drm_i915_private_t *dev_priv = dev->dev_private; 1230 int i; 1231 bool storm_detected = false; 1232 1233 if (!hotplug_trigger) 1234 return; 1235 1236 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1237 for (i = 1; i < HPD_NUM_PINS; i++) { 1238 1239 WARN_ONCE(hpd[i] & hotplug_trigger && 1240 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED, 1241 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", 1242 hotplug_trigger, i, hpd[i]); 1243 1244 if (!(hpd[i] & hotplug_trigger) || 1245 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) 1246 continue; 1247 1248 dev_priv->hpd_event_bits |= (1 << i); 1249 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies, 1250 dev_priv->hpd_stats[i].hpd_last_jiffies 1251 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) { 1252 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies; 1253 dev_priv->hpd_stats[i].hpd_cnt = 0; 1254 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i); 1255 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) { 1256 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED; 1257 dev_priv->hpd_event_bits &= ~(1 << i); 1258 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i); 1259 storm_detected = true; 1260 } else { 1261 dev_priv->hpd_stats[i].hpd_cnt++; 1262 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i, 1263 dev_priv->hpd_stats[i].hpd_cnt); 1264 } 1265 } 1266 1267 if (storm_detected) 1268 dev_priv->display.hpd_irq_setup(dev); 1269 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1270 1271 /* 1272 * Our hotplug handler can grab modeset locks (by calling down into the 1273 * fb helpers). Hence it must not be run on our own dev-priv->wq work 1274 * queue for otherwise the flush_work in the pageflip code will 1275 * deadlock. 1276 */ 1277 schedule_work(&dev_priv->hotplug_work); 1278 } 1279 1280 static void gmbus_irq_handler(struct drm_device *dev) 1281 { 1282 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; 1283 1284 wake_up_all(&dev_priv->gmbus_wait_queue); 1285 } 1286 1287 static void dp_aux_irq_handler(struct drm_device *dev) 1288 { 1289 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private; 1290 1291 wake_up_all(&dev_priv->gmbus_wait_queue); 1292 } 1293 1294 #if defined(CONFIG_DEBUG_FS) 1295 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum i915_pipe pipe, 1296 uint32_t crc0, uint32_t crc1, 1297 uint32_t crc2, uint32_t crc3, 1298 uint32_t crc4) 1299 { 1300 struct drm_i915_private *dev_priv = dev->dev_private; 1301 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 1302 struct intel_pipe_crc_entry *entry; 1303 int head, tail; 1304 1305 spin_lock(&pipe_crc->lock); 1306 1307 if (!pipe_crc->entries) { 1308 spin_unlock(&pipe_crc->lock); 1309 DRM_ERROR("spurious interrupt\n"); 1310 return; 1311 } 1312 1313 head = pipe_crc->head; 1314 tail = pipe_crc->tail; 1315 1316 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { 1317 spin_unlock(&pipe_crc->lock); 1318 DRM_ERROR("CRC buffer overflowing\n"); 1319 return; 1320 } 1321 1322 entry = &pipe_crc->entries[head]; 1323 1324 entry->frame = dev->driver->get_vblank_counter(dev, pipe); 1325 entry->crc[0] = crc0; 1326 entry->crc[1] = crc1; 1327 entry->crc[2] = crc2; 1328 entry->crc[3] = crc3; 1329 entry->crc[4] = crc4; 1330 1331 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); 1332 pipe_crc->head = head; 1333 1334 spin_unlock(&pipe_crc->lock); 1335 1336 wake_up_interruptible(&pipe_crc->wq); 1337 } 1338 #else 1339 static inline void 1340 display_pipe_crc_irq_handler(struct drm_device *dev, enum i915_pipe pipe, 1341 uint32_t crc0, uint32_t crc1, 1342 uint32_t crc2, uint32_t crc3, 1343 uint32_t crc4) {} 1344 #endif 1345 1346 1347 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum i915_pipe pipe) 1348 { 1349 struct drm_i915_private *dev_priv = dev->dev_private; 1350 1351 display_pipe_crc_irq_handler(dev, pipe, 1352 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1353 0, 0, 0, 0); 1354 } 1355 1356 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum i915_pipe pipe) 1357 { 1358 struct drm_i915_private *dev_priv = dev->dev_private; 1359 1360 display_pipe_crc_irq_handler(dev, pipe, 1361 I915_READ(PIPE_CRC_RES_1_IVB(pipe)), 1362 I915_READ(PIPE_CRC_RES_2_IVB(pipe)), 1363 I915_READ(PIPE_CRC_RES_3_IVB(pipe)), 1364 I915_READ(PIPE_CRC_RES_4_IVB(pipe)), 1365 I915_READ(PIPE_CRC_RES_5_IVB(pipe))); 1366 } 1367 1368 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum i915_pipe pipe) 1369 { 1370 struct drm_i915_private *dev_priv = dev->dev_private; 1371 uint32_t res1, res2; 1372 1373 if (INTEL_INFO(dev)->gen >= 3) 1374 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); 1375 else 1376 res1 = 0; 1377 1378 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) 1379 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); 1380 else 1381 res2 = 0; 1382 1383 display_pipe_crc_irq_handler(dev, pipe, 1384 I915_READ(PIPE_CRC_RES_RED(pipe)), 1385 I915_READ(PIPE_CRC_RES_GREEN(pipe)), 1386 I915_READ(PIPE_CRC_RES_BLUE(pipe)), 1387 res1, res2); 1388 } 1389 1390 /* The RPS events need forcewake, so we add them to a work queue and mask their 1391 * IMR bits until the work is done. Other interrupts can be processed without 1392 * the work queue. */ 1393 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) 1394 { 1395 if (pm_iir & GEN6_PM_RPS_EVENTS) { 1396 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1397 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS; 1398 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS); 1399 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1400 1401 queue_work(dev_priv->wq, &dev_priv->rps.work); 1402 } 1403 1404 if (HAS_VEBOX(dev_priv->dev)) { 1405 if (pm_iir & PM_VEBOX_USER_INTERRUPT) 1406 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]); 1407 1408 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) { 1409 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir); 1410 i915_handle_error(dev_priv->dev, false); 1411 } 1412 } 1413 } 1414 1415 static irqreturn_t valleyview_irq_handler(void *arg) 1416 { 1417 struct drm_device *dev = (struct drm_device *) arg; 1418 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1419 u32 iir, gt_iir, pm_iir; 1420 int pipe; 1421 u32 pipe_stats[I915_MAX_PIPES]; 1422 1423 atomic_inc(&dev_priv->irq_received); 1424 1425 while (true) { 1426 iir = I915_READ(VLV_IIR); 1427 gt_iir = I915_READ(GTIIR); 1428 pm_iir = I915_READ(GEN6_PMIIR); 1429 1430 if (gt_iir == 0 && pm_iir == 0 && iir == 0) 1431 goto out; 1432 1433 1434 snb_gt_irq_handler(dev, dev_priv, gt_iir); 1435 1436 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 1437 for_each_pipe(pipe) { 1438 int reg = PIPESTAT(pipe); 1439 pipe_stats[pipe] = I915_READ(reg); 1440 1441 /* 1442 * Clear the PIPE*STAT regs before the IIR 1443 */ 1444 if (pipe_stats[pipe] & 0x8000ffff) { 1445 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 1446 DRM_DEBUG_DRIVER("pipe %c underrun\n", 1447 pipe_name(pipe)); 1448 I915_WRITE(reg, pipe_stats[pipe]); 1449 } 1450 } 1451 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 1452 1453 for_each_pipe(pipe) { 1454 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) 1455 drm_handle_vblank(dev, pipe); 1456 1457 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) { 1458 intel_prepare_page_flip(dev, pipe); 1459 intel_finish_page_flip(dev, pipe); 1460 } 1461 1462 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 1463 i9xx_pipe_crc_irq_handler(dev, pipe); 1464 } 1465 1466 /* Consume port. Then clear IIR or we'll miss events */ 1467 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 1468 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 1469 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 1470 1471 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 1472 hotplug_status); 1473 1474 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); 1475 1476 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) 1477 dp_aux_irq_handler(dev); 1478 1479 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 1480 I915_READ(PORT_HOTPLUG_STAT); 1481 } 1482 1483 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 1484 gmbus_irq_handler(dev); 1485 1486 if (pm_iir) 1487 gen6_rps_irq_handler(dev_priv, pm_iir); 1488 1489 I915_WRITE(GTIIR, gt_iir); 1490 I915_WRITE(GEN6_PMIIR, pm_iir); 1491 I915_WRITE(VLV_IIR, iir); 1492 } 1493 1494 out: 1495 return; 1496 } 1497 1498 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) 1499 { 1500 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1501 int pipe; 1502 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; 1503 1504 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); 1505 1506 if (pch_iir & SDE_AUDIO_POWER_MASK) { 1507 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> 1508 SDE_AUDIO_POWER_SHIFT); 1509 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", 1510 port_name(port)); 1511 } 1512 1513 if (pch_iir & SDE_AUX_MASK) 1514 dp_aux_irq_handler(dev); 1515 1516 if (pch_iir & SDE_GMBUS) 1517 gmbus_irq_handler(dev); 1518 1519 if (pch_iir & SDE_AUDIO_HDCP_MASK) 1520 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); 1521 1522 if (pch_iir & SDE_AUDIO_TRANS_MASK) 1523 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); 1524 1525 if (pch_iir & SDE_POISON) 1526 DRM_ERROR("PCH poison interrupt\n"); 1527 1528 if (pch_iir & SDE_FDI_MASK) 1529 for_each_pipe(pipe) 1530 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 1531 pipe_name(pipe), 1532 I915_READ(FDI_RX_IIR(pipe))); 1533 1534 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) 1535 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); 1536 1537 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) 1538 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); 1539 1540 if (pch_iir & SDE_TRANSA_FIFO_UNDER) 1541 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 1542 false)) 1543 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); 1544 1545 if (pch_iir & SDE_TRANSB_FIFO_UNDER) 1546 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 1547 false)) 1548 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); 1549 } 1550 1551 static void ivb_err_int_handler(struct drm_device *dev) 1552 { 1553 struct drm_i915_private *dev_priv = dev->dev_private; 1554 u32 err_int = I915_READ(GEN7_ERR_INT); 1555 enum i915_pipe pipe; 1556 1557 if (err_int & ERR_INT_POISON) 1558 DRM_ERROR("Poison interrupt\n"); 1559 1560 for_each_pipe(pipe) { 1561 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) { 1562 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 1563 false)) 1564 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", 1565 pipe_name(pipe)); 1566 } 1567 1568 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { 1569 if (IS_IVYBRIDGE(dev)) 1570 ivb_pipe_crc_irq_handler(dev, pipe); 1571 else 1572 hsw_pipe_crc_irq_handler(dev, pipe); 1573 } 1574 } 1575 1576 I915_WRITE(GEN7_ERR_INT, err_int); 1577 } 1578 1579 static void cpt_serr_int_handler(struct drm_device *dev) 1580 { 1581 struct drm_i915_private *dev_priv = dev->dev_private; 1582 u32 serr_int = I915_READ(SERR_INT); 1583 1584 if (serr_int & SERR_INT_POISON) 1585 DRM_ERROR("PCH poison interrupt\n"); 1586 1587 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) 1588 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, 1589 false)) 1590 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n"); 1591 1592 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) 1593 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B, 1594 false)) 1595 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n"); 1596 1597 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) 1598 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C, 1599 false)) 1600 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n"); 1601 1602 I915_WRITE(SERR_INT, serr_int); 1603 } 1604 1605 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) 1606 { 1607 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1608 int pipe; 1609 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; 1610 1611 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); 1612 1613 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { 1614 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> 1615 SDE_AUDIO_POWER_SHIFT_CPT); 1616 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", 1617 port_name(port)); 1618 } 1619 1620 if (pch_iir & SDE_AUX_MASK_CPT) 1621 dp_aux_irq_handler(dev); 1622 1623 if (pch_iir & SDE_GMBUS_CPT) 1624 gmbus_irq_handler(dev); 1625 1626 if (pch_iir & SDE_AUDIO_CP_REQ_CPT) 1627 DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); 1628 1629 if (pch_iir & SDE_AUDIO_CP_CHG_CPT) 1630 DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); 1631 1632 if (pch_iir & SDE_FDI_MASK_CPT) 1633 for_each_pipe(pipe) 1634 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", 1635 pipe_name(pipe), 1636 I915_READ(FDI_RX_IIR(pipe))); 1637 1638 if (pch_iir & SDE_ERROR_CPT) 1639 cpt_serr_int_handler(dev); 1640 } 1641 1642 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) 1643 { 1644 struct drm_i915_private *dev_priv = dev->dev_private; 1645 enum i915_pipe pipe; 1646 1647 if (de_iir & DE_AUX_CHANNEL_A) 1648 dp_aux_irq_handler(dev); 1649 1650 if (de_iir & DE_GSE) 1651 intel_opregion_asle_intr(dev); 1652 1653 if (de_iir & DE_POISON) 1654 DRM_ERROR("Poison interrupt\n"); 1655 1656 for_each_pipe(pipe) { 1657 if (de_iir & DE_PIPE_VBLANK(pipe)) 1658 drm_handle_vblank(dev, pipe); 1659 1660 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) 1661 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false)) 1662 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", 1663 pipe_name(pipe)); 1664 1665 if (de_iir & DE_PIPE_CRC_DONE(pipe)) 1666 i9xx_pipe_crc_irq_handler(dev, pipe); 1667 1668 /* plane/pipes map 1:1 on ilk+ */ 1669 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { 1670 intel_prepare_page_flip(dev, pipe); 1671 intel_finish_page_flip_plane(dev, pipe); 1672 } 1673 } 1674 1675 /* check event from PCH */ 1676 if (de_iir & DE_PCH_EVENT) { 1677 u32 pch_iir = I915_READ(SDEIIR); 1678 1679 if (HAS_PCH_CPT(dev)) 1680 cpt_irq_handler(dev, pch_iir); 1681 else 1682 ibx_irq_handler(dev, pch_iir); 1683 1684 /* should clear PCH hotplug event before clear CPU irq */ 1685 I915_WRITE(SDEIIR, pch_iir); 1686 } 1687 1688 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) 1689 ironlake_rps_change_irq_handler(dev); 1690 } 1691 1692 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) 1693 { 1694 struct drm_i915_private *dev_priv = dev->dev_private; 1695 enum i915_pipe i; 1696 1697 if (de_iir & DE_ERR_INT_IVB) 1698 ivb_err_int_handler(dev); 1699 1700 if (de_iir & DE_AUX_CHANNEL_A_IVB) 1701 dp_aux_irq_handler(dev); 1702 1703 if (de_iir & DE_GSE_IVB) 1704 intel_opregion_asle_intr(dev); 1705 1706 for_each_pipe(i) { 1707 if (de_iir & (DE_PIPE_VBLANK_IVB(i))) 1708 drm_handle_vblank(dev, i); 1709 1710 /* plane/pipes map 1:1 on ilk+ */ 1711 if (de_iir & DE_PLANE_FLIP_DONE_IVB(i)) { 1712 intel_prepare_page_flip(dev, i); 1713 intel_finish_page_flip_plane(dev, i); 1714 } 1715 } 1716 1717 /* check event from PCH */ 1718 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { 1719 u32 pch_iir = I915_READ(SDEIIR); 1720 1721 cpt_irq_handler(dev, pch_iir); 1722 1723 /* clear PCH hotplug event before clear CPU irq */ 1724 I915_WRITE(SDEIIR, pch_iir); 1725 } 1726 } 1727 1728 static irqreturn_t ironlake_irq_handler(void *arg) 1729 { 1730 struct drm_device *dev = (struct drm_device *) arg; 1731 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 1732 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 1733 1734 atomic_inc(&dev_priv->irq_received); 1735 1736 /* We get interrupts on unclaimed registers, so check for this before we 1737 * do any I915_{READ,WRITE}. */ 1738 intel_uncore_check_errors(dev); 1739 1740 /* disable master interrupt before clearing iir */ 1741 de_ier = I915_READ(DEIER); 1742 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); 1743 POSTING_READ(DEIER); 1744 1745 /* Disable south interrupts. We'll only write to SDEIIR once, so further 1746 * interrupts will will be stored on its back queue, and then we'll be 1747 * able to process them after we restore SDEIER (as soon as we restore 1748 * it, we'll get an interrupt if SDEIIR still has something to process 1749 * due to its back queue). */ 1750 if (!HAS_PCH_NOP(dev)) { 1751 sde_ier = I915_READ(SDEIER); 1752 I915_WRITE(SDEIER, 0); 1753 POSTING_READ(SDEIER); 1754 } 1755 1756 gt_iir = I915_READ(GTIIR); 1757 if (gt_iir) { 1758 if (INTEL_INFO(dev)->gen >= 6) 1759 snb_gt_irq_handler(dev, dev_priv, gt_iir); 1760 else 1761 ilk_gt_irq_handler(dev, dev_priv, gt_iir); 1762 I915_WRITE(GTIIR, gt_iir); 1763 } 1764 1765 de_iir = I915_READ(DEIIR); 1766 if (de_iir) { 1767 if (INTEL_INFO(dev)->gen >= 7) 1768 ivb_display_irq_handler(dev, de_iir); 1769 else 1770 ilk_display_irq_handler(dev, de_iir); 1771 I915_WRITE(DEIIR, de_iir); 1772 } 1773 1774 if (INTEL_INFO(dev)->gen >= 6) { 1775 u32 pm_iir = I915_READ(GEN6_PMIIR); 1776 if (pm_iir) { 1777 gen6_rps_irq_handler(dev_priv, pm_iir); 1778 I915_WRITE(GEN6_PMIIR, pm_iir); 1779 } 1780 } 1781 1782 I915_WRITE(DEIER, de_ier); 1783 POSTING_READ(DEIER); 1784 if (!HAS_PCH_NOP(dev)) { 1785 I915_WRITE(SDEIER, sde_ier); 1786 POSTING_READ(SDEIER); 1787 } 1788 1789 } 1790 1791 static irqreturn_t gen8_irq_handler(void *arg) 1792 { 1793 struct drm_device *dev = arg; 1794 struct drm_i915_private *dev_priv = dev->dev_private; 1795 u32 master_ctl; 1796 uint32_t tmp = 0; 1797 enum i915_pipe pipe; 1798 1799 atomic_inc(&dev_priv->irq_received); 1800 1801 master_ctl = I915_READ(GEN8_MASTER_IRQ); 1802 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; 1803 if (!master_ctl) 1804 return; 1805 1806 I915_WRITE(GEN8_MASTER_IRQ, 0); 1807 POSTING_READ(GEN8_MASTER_IRQ); 1808 1809 gen8_gt_irq_handler(dev, dev_priv, master_ctl); 1810 1811 if (master_ctl & GEN8_DE_MISC_IRQ) { 1812 tmp = I915_READ(GEN8_DE_MISC_IIR); 1813 if (tmp & GEN8_DE_MISC_GSE) 1814 intel_opregion_asle_intr(dev); 1815 else if (tmp) 1816 DRM_ERROR("Unexpected DE Misc interrupt\n"); 1817 else 1818 DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); 1819 1820 if (tmp) { 1821 I915_WRITE(GEN8_DE_MISC_IIR, tmp); 1822 } 1823 } 1824 1825 if (master_ctl & GEN8_DE_PORT_IRQ) { 1826 tmp = I915_READ(GEN8_DE_PORT_IIR); 1827 if (tmp & GEN8_AUX_CHANNEL_A) 1828 dp_aux_irq_handler(dev); 1829 else if (tmp) 1830 DRM_ERROR("Unexpected DE Port interrupt\n"); 1831 else 1832 DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); 1833 1834 if (tmp) { 1835 I915_WRITE(GEN8_DE_PORT_IIR, tmp); 1836 } 1837 } 1838 1839 for_each_pipe(pipe) { 1840 uint32_t pipe_iir; 1841 1842 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) 1843 continue; 1844 1845 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); 1846 if (pipe_iir & GEN8_PIPE_VBLANK) 1847 drm_handle_vblank(dev, pipe); 1848 1849 if (pipe_iir & GEN8_PIPE_FLIP_DONE) { 1850 intel_prepare_page_flip(dev, pipe); 1851 intel_finish_page_flip_plane(dev, pipe); 1852 } 1853 1854 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) 1855 hsw_pipe_crc_irq_handler(dev, pipe); 1856 1857 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) { 1858 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, 1859 false)) 1860 DRM_DEBUG_DRIVER("Pipe %c FIFO underrun\n", 1861 pipe_name(pipe)); 1862 } 1863 1864 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) { 1865 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", 1866 pipe_name(pipe), 1867 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); 1868 } 1869 1870 if (pipe_iir) { 1871 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); 1872 } else 1873 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); 1874 } 1875 1876 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) { 1877 /* 1878 * FIXME(BDW): Assume for now that the new interrupt handling 1879 * scheme also closed the SDE interrupt handling race we've seen 1880 * on older pch-split platforms. But this needs testing. 1881 */ 1882 u32 pch_iir = I915_READ(SDEIIR); 1883 1884 cpt_irq_handler(dev, pch_iir); 1885 1886 if (pch_iir) { 1887 I915_WRITE(SDEIIR, pch_iir); 1888 } 1889 } 1890 1891 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); 1892 POSTING_READ(GEN8_MASTER_IRQ); 1893 1894 } 1895 1896 static void i915_error_wake_up(struct drm_i915_private *dev_priv, 1897 bool reset_completed) 1898 { 1899 struct intel_ring_buffer *ring; 1900 int i; 1901 1902 /* 1903 * Notify all waiters for GPU completion events that reset state has 1904 * been changed, and that they need to restart their wait after 1905 * checking for potential errors (and bail out to drop locks if there is 1906 * a gpu reset pending so that i915_error_work_func can acquire them). 1907 */ 1908 1909 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ 1910 for_each_ring(ring, dev_priv, i) 1911 wake_up_all(&ring->irq_queue); 1912 1913 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ 1914 wake_up_all(&dev_priv->pending_flip_queue); 1915 1916 /* 1917 * Signal tasks blocked in i915_gem_wait_for_error that the pending 1918 * reset state is cleared. 1919 */ 1920 if (reset_completed) 1921 wake_up_all(&dev_priv->gpu_error.reset_queue); 1922 } 1923 1924 /** 1925 * i915_error_work_func - do process context error handling work 1926 * @work: work struct 1927 * 1928 * Fire an error uevent so userspace can see that a hang or error 1929 * was detected. 1930 */ 1931 static void i915_error_work_func(struct work_struct *work) 1932 { 1933 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error, 1934 work); 1935 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t, 1936 gpu_error); 1937 struct drm_device *dev = dev_priv->dev; 1938 #if 0 1939 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; 1940 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; 1941 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; 1942 #endif 1943 int ret; 1944 1945 /* kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); */ 1946 1947 /* 1948 * Note that there's only one work item which does gpu resets, so we 1949 * need not worry about concurrent gpu resets potentially incrementing 1950 * error->reset_counter twice. We only need to take care of another 1951 * racing irq/hangcheck declaring the gpu dead for a second time. A 1952 * quick check for that is good enough: schedule_work ensures the 1953 * correct ordering between hang detection and this work item, and since 1954 * the reset in-progress bit is only ever set by code outside of this 1955 * work we don't need to worry about any other races. 1956 */ 1957 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { 1958 DRM_DEBUG_DRIVER("resetting chip\n"); 1959 #if 0 1960 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, 1961 reset_event); 1962 #endif 1963 1964 /* 1965 * All state reset _must_ be completed before we update the 1966 * reset counter, for otherwise waiters might miss the reset 1967 * pending state and not properly drop locks, resulting in 1968 * deadlocks with the reset work. 1969 */ 1970 ret = i915_reset(dev); 1971 1972 intel_display_handle_reset(dev); 1973 1974 if (ret == 0) { 1975 /* 1976 * After all the gem state is reset, increment the reset 1977 * counter and wake up everyone waiting for the reset to 1978 * complete. 1979 * 1980 * Since unlock operations are a one-sided barrier only, 1981 * we need to insert a barrier here to order any seqno 1982 * updates before 1983 * the counter increment. 1984 */ 1985 cpu_sfence(); 1986 atomic_inc(&dev_priv->gpu_error.reset_counter); 1987 1988 #if 0 1989 kobject_uevent_env(&dev->primary->kdev->kobj, 1990 KOBJ_CHANGE, reset_done_event); 1991 #endif 1992 } else { 1993 atomic_set_mask(I915_WEDGED, &error->reset_counter); 1994 } 1995 1996 /* 1997 * Note: The wake_up also serves as a memory barrier so that 1998 * waiters see the update value of the reset counter atomic_t. 1999 */ 2000 i915_error_wake_up(dev_priv, true); 2001 } 2002 } 2003 2004 static void i915_report_and_clear_eir(struct drm_device *dev) 2005 { 2006 struct drm_i915_private *dev_priv = dev->dev_private; 2007 uint32_t instdone[I915_NUM_INSTDONE_REG]; 2008 u32 eir = I915_READ(EIR); 2009 int pipe, i; 2010 2011 if (!eir) 2012 return; 2013 2014 pr_err("render error detected, EIR: 0x%08x\n", eir); 2015 2016 #if 0 2017 i915_get_extra_instdone(dev, instdone); 2018 #endif 2019 2020 if (IS_G4X(dev)) { 2021 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { 2022 u32 ipeir = I915_READ(IPEIR_I965); 2023 2024 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 2025 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 2026 for (i = 0; i < ARRAY_SIZE(instdone); i++) 2027 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 2028 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 2029 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 2030 I915_WRITE(IPEIR_I965, ipeir); 2031 POSTING_READ(IPEIR_I965); 2032 } 2033 if (eir & GM45_ERROR_PAGE_TABLE) { 2034 u32 pgtbl_err = I915_READ(PGTBL_ER); 2035 pr_err("page table error\n"); 2036 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 2037 I915_WRITE(PGTBL_ER, pgtbl_err); 2038 POSTING_READ(PGTBL_ER); 2039 } 2040 } 2041 2042 if (!IS_GEN2(dev)) { 2043 if (eir & I915_ERROR_PAGE_TABLE) { 2044 u32 pgtbl_err = I915_READ(PGTBL_ER); 2045 pr_err("page table error\n"); 2046 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); 2047 I915_WRITE(PGTBL_ER, pgtbl_err); 2048 POSTING_READ(PGTBL_ER); 2049 } 2050 } 2051 2052 if (eir & I915_ERROR_MEMORY_REFRESH) { 2053 pr_err("memory refresh error:\n"); 2054 for_each_pipe(pipe) 2055 pr_err("pipe %c stat: 0x%08x\n", 2056 pipe_name(pipe), I915_READ(PIPESTAT(pipe))); 2057 /* pipestat has already been acked */ 2058 } 2059 if (eir & I915_ERROR_INSTRUCTION) { 2060 pr_err("instruction error\n"); 2061 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); 2062 for (i = 0; i < ARRAY_SIZE(instdone); i++) 2063 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); 2064 if (INTEL_INFO(dev)->gen < 4) { 2065 u32 ipeir = I915_READ(IPEIR); 2066 2067 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); 2068 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); 2069 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); 2070 I915_WRITE(IPEIR, ipeir); 2071 POSTING_READ(IPEIR); 2072 } else { 2073 u32 ipeir = I915_READ(IPEIR_I965); 2074 2075 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); 2076 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); 2077 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); 2078 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); 2079 I915_WRITE(IPEIR_I965, ipeir); 2080 POSTING_READ(IPEIR_I965); 2081 } 2082 } 2083 2084 I915_WRITE(EIR, eir); 2085 POSTING_READ(EIR); 2086 eir = I915_READ(EIR); 2087 if (eir) { 2088 /* 2089 * some errors might have become stuck, 2090 * mask them. 2091 */ 2092 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); 2093 I915_WRITE(EMR, I915_READ(EMR) | eir); 2094 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 2095 } 2096 } 2097 2098 /** 2099 * i915_handle_error - handle an error interrupt 2100 * @dev: drm device 2101 * 2102 * Do some basic checking of regsiter state at error interrupt time and 2103 * dump it to the syslog. Also call i915_capture_error_state() to make 2104 * sure we get a record and make it available in debugfs. Fire a uevent 2105 * so userspace knows something bad happened (should trigger collection 2106 * of a ring dump etc.). 2107 */ 2108 void i915_handle_error(struct drm_device *dev, bool wedged) 2109 { 2110 struct drm_i915_private *dev_priv = dev->dev_private; 2111 2112 #if 0 2113 i915_capture_error_state(dev); 2114 #endif 2115 i915_report_and_clear_eir(dev); 2116 2117 if (wedged) { 2118 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, 2119 &dev_priv->gpu_error.reset_counter); 2120 2121 /* 2122 * Wakeup waiting processes so that the reset work function 2123 * i915_error_work_func doesn't deadlock trying to grab various 2124 * locks. By bumping the reset counter first, the woken 2125 * processes will see a reset in progress and back off, 2126 * releasing their locks and then wait for the reset completion. 2127 * We must do this for _all_ gpu waiters that might hold locks 2128 * that the reset work needs to acquire. 2129 * 2130 * Note: The wake_up serves as the required memory barrier to 2131 * ensure that the waiters see the updated value of the reset 2132 * counter atomic_t. 2133 */ 2134 i915_error_wake_up(dev_priv, false); 2135 } 2136 2137 /* 2138 * Our reset work can grab modeset locks (since it needs to reset the 2139 * state of outstanding pagelips). Hence it must not be run on our own 2140 * dev-priv->wq work queue for otherwise the flush_work in the pageflip 2141 * code will deadlock. 2142 */ 2143 schedule_work(&dev_priv->gpu_error.work); 2144 } 2145 2146 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe) 2147 { 2148 drm_i915_private_t *dev_priv = dev->dev_private; 2149 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; 2150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2151 struct drm_i915_gem_object *obj; 2152 struct intel_unpin_work *work; 2153 bool stall_detected; 2154 2155 /* Ignore early vblank irqs */ 2156 if (intel_crtc == NULL) 2157 return; 2158 2159 lockmgr(&dev->event_lock, LK_EXCLUSIVE); 2160 work = intel_crtc->unpin_work; 2161 2162 if (work == NULL || 2163 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE || 2164 !work->enable_stall_check) { 2165 /* Either the pending flip IRQ arrived, or we're too early. Don't check */ 2166 lockmgr(&dev->event_lock, LK_RELEASE); 2167 return; 2168 } 2169 2170 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ 2171 obj = work->pending_flip_obj; 2172 if (INTEL_INFO(dev)->gen >= 4) { 2173 int dspsurf = DSPSURF(intel_crtc->plane); 2174 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) == 2175 i915_gem_obj_ggtt_offset(obj); 2176 } else { 2177 int dspaddr = DSPADDR(intel_crtc->plane); 2178 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) + 2179 crtc->y * crtc->fb->pitches[0] + 2180 crtc->x * crtc->fb->bits_per_pixel/8); 2181 } 2182 2183 lockmgr(&dev->event_lock, LK_RELEASE); 2184 2185 if (stall_detected) { 2186 DRM_DEBUG_DRIVER("Pageflip stall detected\n"); 2187 intel_prepare_page_flip(dev, intel_crtc->plane); 2188 } 2189 } 2190 2191 /* Called from drm generic code, passed 'crtc' which 2192 * we use as a pipe index 2193 */ 2194 static int i915_enable_vblank(struct drm_device *dev, int pipe) 2195 { 2196 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2197 2198 if (!i915_pipe_enabled(dev, pipe)) 2199 return -EINVAL; 2200 2201 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2202 if (INTEL_INFO(dev)->gen >= 4) 2203 i915_enable_pipestat(dev_priv, pipe, 2204 PIPE_START_VBLANK_INTERRUPT_ENABLE); 2205 else 2206 i915_enable_pipestat(dev_priv, pipe, 2207 PIPE_VBLANK_INTERRUPT_ENABLE); 2208 2209 /* maintain vblank delivery even in deep C-states */ 2210 if (dev_priv->info->gen == 3) 2211 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS)); 2212 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2213 2214 return 0; 2215 } 2216 2217 static int ironlake_enable_vblank(struct drm_device *dev, int pipe) 2218 { 2219 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2220 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 2221 DE_PIPE_VBLANK(pipe); 2222 2223 if (!i915_pipe_enabled(dev, pipe)) 2224 return -EINVAL; 2225 2226 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2227 ironlake_enable_display_irq(dev_priv, bit); 2228 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2229 2230 return 0; 2231 } 2232 2233 static int valleyview_enable_vblank(struct drm_device *dev, int pipe) 2234 { 2235 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2236 u32 imr; 2237 2238 if (!i915_pipe_enabled(dev, pipe)) 2239 return -EINVAL; 2240 2241 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2242 imr = I915_READ(VLV_IMR); 2243 if (pipe == PIPE_A) 2244 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 2245 else 2246 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 2247 I915_WRITE(VLV_IMR, imr); 2248 i915_enable_pipestat(dev_priv, pipe, 2249 PIPE_START_VBLANK_INTERRUPT_ENABLE); 2250 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2251 2252 return 0; 2253 } 2254 2255 static int gen8_enable_vblank(struct drm_device *dev, int pipe) 2256 { 2257 struct drm_i915_private *dev_priv = dev->dev_private; 2258 2259 if (!i915_pipe_enabled(dev, pipe)) 2260 return -EINVAL; 2261 2262 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2263 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; 2264 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 2265 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 2266 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2267 return 0; 2268 } 2269 2270 /* Called from drm generic code, passed 'crtc' which 2271 * we use as a pipe index 2272 */ 2273 static void i915_disable_vblank(struct drm_device *dev, int pipe) 2274 { 2275 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2276 2277 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2278 if (dev_priv->info->gen == 3) 2279 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS)); 2280 2281 i915_disable_pipestat(dev_priv, pipe, 2282 PIPE_VBLANK_INTERRUPT_ENABLE | 2283 PIPE_START_VBLANK_INTERRUPT_ENABLE); 2284 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2285 } 2286 2287 static void ironlake_disable_vblank(struct drm_device *dev, int pipe) 2288 { 2289 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2290 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : 2291 DE_PIPE_VBLANK(pipe); 2292 2293 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2294 ironlake_disable_display_irq(dev_priv, bit); 2295 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2296 } 2297 2298 static void valleyview_disable_vblank(struct drm_device *dev, int pipe) 2299 { 2300 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2301 u32 imr; 2302 2303 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2304 i915_disable_pipestat(dev_priv, pipe, 2305 PIPE_START_VBLANK_INTERRUPT_ENABLE); 2306 imr = I915_READ(VLV_IMR); 2307 if (pipe == PIPE_A) 2308 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT; 2309 else 2310 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 2311 I915_WRITE(VLV_IMR, imr); 2312 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2313 } 2314 2315 static void gen8_disable_vblank(struct drm_device *dev, int pipe) 2316 { 2317 struct drm_i915_private *dev_priv = dev->dev_private; 2318 2319 if (!i915_pipe_enabled(dev, pipe)) 2320 return; 2321 2322 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2323 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; 2324 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 2325 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); 2326 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2327 } 2328 2329 static u32 2330 ring_last_seqno(struct intel_ring_buffer *ring) 2331 { 2332 return list_entry(ring->request_list.prev, 2333 struct drm_i915_gem_request, list)->seqno; 2334 } 2335 2336 static bool 2337 ring_idle(struct intel_ring_buffer *ring, u32 seqno) 2338 { 2339 return (list_empty(&ring->request_list) || 2340 i915_seqno_passed(seqno, ring_last_seqno(ring))); 2341 } 2342 2343 static struct intel_ring_buffer * 2344 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno) 2345 { 2346 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2347 u32 cmd, ipehr, acthd, acthd_min; 2348 2349 ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 2350 if ((ipehr & ~(0x3 << 16)) != 2351 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER)) 2352 return NULL; 2353 2354 /* ACTHD is likely pointing to the dword after the actual command, 2355 * so scan backwards until we find the MBOX. 2356 */ 2357 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR; 2358 acthd_min = max((int)acthd - 3 * 4, 0); 2359 do { 2360 cmd = ioread32(ring->virtual_start + acthd); 2361 if (cmd == ipehr) 2362 break; 2363 2364 acthd -= 4; 2365 if (acthd < acthd_min) 2366 return NULL; 2367 } while (1); 2368 2369 *seqno = ioread32(ring->virtual_start+acthd+4)+1; 2370 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3]; 2371 } 2372 2373 static int semaphore_passed(struct intel_ring_buffer *ring) 2374 { 2375 struct drm_i915_private *dev_priv = ring->dev->dev_private; 2376 struct intel_ring_buffer *signaller; 2377 u32 seqno, ctl; 2378 2379 ring->hangcheck.deadlock = true; 2380 2381 signaller = semaphore_waits_for(ring, &seqno); 2382 if (signaller == NULL || signaller->hangcheck.deadlock) 2383 return -1; 2384 2385 /* cursory check for an unkickable deadlock */ 2386 ctl = I915_READ_CTL(signaller); 2387 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0) 2388 return -1; 2389 2390 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno); 2391 } 2392 2393 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) 2394 { 2395 struct intel_ring_buffer *ring; 2396 int i; 2397 2398 for_each_ring(ring, dev_priv, i) 2399 ring->hangcheck.deadlock = false; 2400 } 2401 2402 static enum intel_ring_hangcheck_action 2403 ring_stuck(struct intel_ring_buffer *ring, u32 acthd) 2404 { 2405 struct drm_device *dev = ring->dev; 2406 struct drm_i915_private *dev_priv = dev->dev_private; 2407 u32 tmp; 2408 2409 if (ring->hangcheck.acthd != acthd) 2410 return HANGCHECK_ACTIVE; 2411 2412 if (IS_GEN2(dev)) 2413 return HANGCHECK_HUNG; 2414 2415 /* Is the chip hanging on a WAIT_FOR_EVENT? 2416 * If so we can simply poke the RB_WAIT bit 2417 * and break the hang. This should work on 2418 * all but the second generation chipsets. 2419 */ 2420 tmp = I915_READ_CTL(ring); 2421 if (tmp & RING_WAIT) { 2422 DRM_ERROR("Kicking stuck wait on %s\n", 2423 ring->name); 2424 i915_handle_error(dev, false); 2425 I915_WRITE_CTL(ring, tmp); 2426 return HANGCHECK_KICK; 2427 } 2428 2429 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { 2430 switch (semaphore_passed(ring)) { 2431 default: 2432 return HANGCHECK_HUNG; 2433 case 1: 2434 DRM_ERROR("Kicking stuck semaphore on %s\n", 2435 ring->name); 2436 i915_handle_error(dev, false); 2437 I915_WRITE_CTL(ring, tmp); 2438 return HANGCHECK_KICK; 2439 case 0: 2440 return HANGCHECK_WAIT; 2441 } 2442 } 2443 2444 return HANGCHECK_HUNG; 2445 } 2446 2447 /** 2448 * This is called when the chip hasn't reported back with completed 2449 * batchbuffers in a long time. We keep track per ring seqno progress and 2450 * if there are no progress, hangcheck score for that ring is increased. 2451 * Further, acthd is inspected to see if the ring is stuck. On stuck case 2452 * we kick the ring. If we see no progress on three subsequent calls 2453 * we assume chip is wedged and try to fix it by resetting the chip. 2454 */ 2455 static void i915_hangcheck_elapsed(unsigned long data) 2456 { 2457 struct drm_device *dev = (struct drm_device *)data; 2458 drm_i915_private_t *dev_priv = dev->dev_private; 2459 struct intel_ring_buffer *ring; 2460 int i; 2461 int busy_count = 0, rings_hung = 0; 2462 bool stuck[I915_NUM_RINGS] = { 0 }; 2463 #define BUSY 1 2464 #define KICK 5 2465 #define HUNG 20 2466 #define FIRE 30 2467 2468 if (!i915_enable_hangcheck) 2469 return; 2470 2471 for_each_ring(ring, dev_priv, i) { 2472 u32 seqno, acthd; 2473 bool busy = true; 2474 2475 semaphore_clear_deadlocks(dev_priv); 2476 2477 seqno = ring->get_seqno(ring, false); 2478 acthd = intel_ring_get_active_head(ring); 2479 2480 if (ring->hangcheck.seqno == seqno) { 2481 if (ring_idle(ring, seqno)) { 2482 ring->hangcheck.action = HANGCHECK_IDLE; 2483 2484 if (waitqueue_active(&ring->irq_queue)) { 2485 /* Issue a wake-up to catch stuck h/w. */ 2486 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { 2487 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) 2488 DRM_ERROR("Hangcheck timer elapsed... %s idle\n", 2489 ring->name); 2490 else 2491 DRM_INFO("Fake missed irq on %s\n", 2492 ring->name); 2493 wake_up_all(&ring->irq_queue); 2494 } 2495 /* Safeguard against driver failure */ 2496 ring->hangcheck.score += BUSY; 2497 } else 2498 busy = false; 2499 } else { 2500 /* We always increment the hangcheck score 2501 * if the ring is busy and still processing 2502 * the same request, so that no single request 2503 * can run indefinitely (such as a chain of 2504 * batches). The only time we do not increment 2505 * the hangcheck score on this ring, if this 2506 * ring is in a legitimate wait for another 2507 * ring. In that case the waiting ring is a 2508 * victim and we want to be sure we catch the 2509 * right culprit. Then every time we do kick 2510 * the ring, add a small increment to the 2511 * score so that we can catch a batch that is 2512 * being repeatedly kicked and so responsible 2513 * for stalling the machine. 2514 */ 2515 ring->hangcheck.action = ring_stuck(ring, 2516 acthd); 2517 2518 switch (ring->hangcheck.action) { 2519 case HANGCHECK_IDLE: 2520 case HANGCHECK_WAIT: 2521 break; 2522 case HANGCHECK_ACTIVE: 2523 ring->hangcheck.score += BUSY; 2524 break; 2525 case HANGCHECK_KICK: 2526 ring->hangcheck.score += KICK; 2527 break; 2528 case HANGCHECK_HUNG: 2529 ring->hangcheck.score += HUNG; 2530 stuck[i] = true; 2531 break; 2532 } 2533 } 2534 } else { 2535 ring->hangcheck.action = HANGCHECK_ACTIVE; 2536 2537 /* Gradually reduce the count so that we catch DoS 2538 * attempts across multiple batches. 2539 */ 2540 if (ring->hangcheck.score > 0) 2541 ring->hangcheck.score--; 2542 } 2543 2544 ring->hangcheck.seqno = seqno; 2545 ring->hangcheck.acthd = acthd; 2546 busy_count += busy; 2547 } 2548 2549 for_each_ring(ring, dev_priv, i) { 2550 if (ring->hangcheck.score > FIRE) { 2551 DRM_INFO("%s on %s\n", 2552 stuck[i] ? "stuck" : "no progress", 2553 ring->name); 2554 rings_hung++; 2555 } 2556 } 2557 2558 if (rings_hung) 2559 return i915_handle_error(dev, true); 2560 2561 if (busy_count) 2562 /* Reset timer case chip hangs without another request 2563 * being added */ 2564 i915_queue_hangcheck(dev); 2565 } 2566 2567 void i915_queue_hangcheck(struct drm_device *dev) 2568 { 2569 struct drm_i915_private *dev_priv = dev->dev_private; 2570 if (!i915_enable_hangcheck) 2571 return; 2572 2573 mod_timer(&dev_priv->gpu_error.hangcheck_timer, 2574 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); 2575 } 2576 2577 static void ibx_irq_preinstall(struct drm_device *dev) 2578 { 2579 struct drm_i915_private *dev_priv = dev->dev_private; 2580 2581 if (HAS_PCH_NOP(dev)) 2582 return; 2583 2584 /* south display irq */ 2585 I915_WRITE(SDEIMR, 0xffffffff); 2586 /* 2587 * SDEIER is also touched by the interrupt handler to work around missed 2588 * PCH interrupts. Hence we can't update it after the interrupt handler 2589 * is enabled - instead we unconditionally enable all PCH interrupt 2590 * sources here, but then only unmask them as needed with SDEIMR. 2591 */ 2592 I915_WRITE(SDEIER, 0xffffffff); 2593 POSTING_READ(SDEIER); 2594 } 2595 2596 static void gen5_gt_irq_preinstall(struct drm_device *dev) 2597 { 2598 struct drm_i915_private *dev_priv = dev->dev_private; 2599 2600 /* and GT */ 2601 I915_WRITE(GTIMR, 0xffffffff); 2602 I915_WRITE(GTIER, 0x0); 2603 POSTING_READ(GTIER); 2604 2605 if (INTEL_INFO(dev)->gen >= 6) { 2606 /* and PM */ 2607 I915_WRITE(GEN6_PMIMR, 0xffffffff); 2608 I915_WRITE(GEN6_PMIER, 0x0); 2609 POSTING_READ(GEN6_PMIER); 2610 } 2611 } 2612 2613 /* drm_dma.h hooks 2614 */ 2615 static void ironlake_irq_preinstall(struct drm_device *dev) 2616 { 2617 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2618 2619 atomic_set(&dev_priv->irq_received, 0); 2620 2621 I915_WRITE(HWSTAM, 0xeffe); 2622 2623 I915_WRITE(DEIMR, 0xffffffff); 2624 I915_WRITE(DEIER, 0x0); 2625 POSTING_READ(DEIER); 2626 2627 gen5_gt_irq_preinstall(dev); 2628 2629 ibx_irq_preinstall(dev); 2630 } 2631 2632 static void valleyview_irq_preinstall(struct drm_device *dev) 2633 { 2634 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2635 int pipe; 2636 2637 atomic_set(&dev_priv->irq_received, 0); 2638 2639 /* VLV magic */ 2640 I915_WRITE(VLV_IMR, 0); 2641 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); 2642 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); 2643 I915_WRITE(RING_IMR(BLT_RING_BASE), 0); 2644 2645 /* and GT */ 2646 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2647 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2648 2649 gen5_gt_irq_preinstall(dev); 2650 2651 I915_WRITE(DPINVGTT, 0xff); 2652 2653 I915_WRITE(PORT_HOTPLUG_EN, 0); 2654 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 2655 for_each_pipe(pipe) 2656 I915_WRITE(PIPESTAT(pipe), 0xffff); 2657 I915_WRITE(VLV_IIR, 0xffffffff); 2658 I915_WRITE(VLV_IMR, 0xffffffff); 2659 I915_WRITE(VLV_IER, 0x0); 2660 POSTING_READ(VLV_IER); 2661 } 2662 2663 static void gen8_irq_preinstall(struct drm_device *dev) 2664 { 2665 struct drm_i915_private *dev_priv = dev->dev_private; 2666 int pipe; 2667 2668 atomic_set(&dev_priv->irq_received, 0); 2669 2670 I915_WRITE(GEN8_MASTER_IRQ, 0); 2671 POSTING_READ(GEN8_MASTER_IRQ); 2672 2673 /* IIR can theoretically queue up two events. Be paranoid */ 2674 #define GEN8_IRQ_INIT_NDX(type, which) do { \ 2675 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ 2676 POSTING_READ(GEN8_##type##_IMR(which)); \ 2677 I915_WRITE(GEN8_##type##_IER(which), 0); \ 2678 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 2679 POSTING_READ(GEN8_##type##_IIR(which)); \ 2680 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 2681 } while (0) 2682 2683 #define GEN8_IRQ_INIT(type) do { \ 2684 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ 2685 POSTING_READ(GEN8_##type##_IMR); \ 2686 I915_WRITE(GEN8_##type##_IER, 0); \ 2687 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 2688 POSTING_READ(GEN8_##type##_IIR); \ 2689 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 2690 } while (0) 2691 2692 GEN8_IRQ_INIT_NDX(GT, 0); 2693 GEN8_IRQ_INIT_NDX(GT, 1); 2694 GEN8_IRQ_INIT_NDX(GT, 2); 2695 GEN8_IRQ_INIT_NDX(GT, 3); 2696 2697 for_each_pipe(pipe) { 2698 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe); 2699 } 2700 2701 GEN8_IRQ_INIT(DE_PORT); 2702 GEN8_IRQ_INIT(DE_MISC); 2703 GEN8_IRQ_INIT(PCU); 2704 #undef GEN8_IRQ_INIT 2705 #undef GEN8_IRQ_INIT_NDX 2706 2707 POSTING_READ(GEN8_PCU_IIR); 2708 2709 ibx_irq_preinstall(dev); 2710 } 2711 2712 static void ibx_hpd_irq_setup(struct drm_device *dev) 2713 { 2714 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2715 struct drm_mode_config *mode_config = &dev->mode_config; 2716 struct intel_encoder *intel_encoder; 2717 u32 hotplug_irqs, hotplug, enabled_irqs = 0; 2718 2719 if (HAS_PCH_IBX(dev)) { 2720 hotplug_irqs = SDE_HOTPLUG_MASK; 2721 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 2722 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 2723 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin]; 2724 } else { 2725 hotplug_irqs = SDE_HOTPLUG_MASK_CPT; 2726 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 2727 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 2728 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin]; 2729 } 2730 2731 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); 2732 2733 /* 2734 * Enable digital hotplug on the PCH, and configure the DP short pulse 2735 * duration to 2ms (which is the minimum in the Display Port spec) 2736 * 2737 * This register is the same on all known PCH chips. 2738 */ 2739 hotplug = I915_READ(PCH_PORT_HOTPLUG); 2740 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); 2741 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; 2742 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; 2743 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; 2744 I915_WRITE(PCH_PORT_HOTPLUG, hotplug); 2745 } 2746 2747 static void ibx_irq_postinstall(struct drm_device *dev) 2748 { 2749 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2750 u32 mask; 2751 2752 if (HAS_PCH_NOP(dev)) 2753 return; 2754 2755 if (HAS_PCH_IBX(dev)) { 2756 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; 2757 } else { 2758 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; 2759 2760 I915_WRITE(SERR_INT, I915_READ(SERR_INT)); 2761 } 2762 2763 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 2764 I915_WRITE(SDEIMR, ~mask); 2765 } 2766 2767 static void gen5_gt_irq_postinstall(struct drm_device *dev) 2768 { 2769 struct drm_i915_private *dev_priv = dev->dev_private; 2770 u32 pm_irqs, gt_irqs; 2771 2772 pm_irqs = gt_irqs = 0; 2773 2774 dev_priv->gt_irq_mask = ~0; 2775 if (HAS_L3_DPF(dev)) { 2776 /* L3 parity interrupt is always unmasked. */ 2777 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); 2778 gt_irqs |= GT_PARITY_ERROR(dev); 2779 } 2780 2781 gt_irqs |= GT_RENDER_USER_INTERRUPT; 2782 if (IS_GEN5(dev)) { 2783 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | 2784 ILK_BSD_USER_INTERRUPT; 2785 } else { 2786 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; 2787 } 2788 2789 I915_WRITE(GTIIR, I915_READ(GTIIR)); 2790 I915_WRITE(GTIMR, dev_priv->gt_irq_mask); 2791 I915_WRITE(GTIER, gt_irqs); 2792 POSTING_READ(GTIER); 2793 2794 if (INTEL_INFO(dev)->gen >= 6) { 2795 pm_irqs |= GEN6_PM_RPS_EVENTS; 2796 2797 if (HAS_VEBOX(dev)) 2798 pm_irqs |= PM_VEBOX_USER_INTERRUPT; 2799 2800 dev_priv->pm_irq_mask = 0xffffffff; 2801 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); 2802 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); 2803 I915_WRITE(GEN6_PMIER, pm_irqs); 2804 POSTING_READ(GEN6_PMIER); 2805 } 2806 } 2807 2808 static int ironlake_irq_postinstall(struct drm_device *dev) 2809 { 2810 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2811 u32 display_mask, extra_mask; 2812 2813 if (INTEL_INFO(dev)->gen >= 7) { 2814 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | 2815 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | 2816 DE_PLANEB_FLIP_DONE_IVB | 2817 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); 2818 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | 2819 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB); 2820 2821 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); 2822 } else { 2823 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | 2824 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | 2825 DE_AUX_CHANNEL_A | 2826 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | 2827 DE_POISON); 2828 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | 2829 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN; 2830 } 2831 2832 dev_priv->irq_mask = ~display_mask; 2833 2834 /* should always can generate irq */ 2835 I915_WRITE(DEIIR, I915_READ(DEIIR)); 2836 I915_WRITE(DEIMR, dev_priv->irq_mask); 2837 I915_WRITE(DEIER, display_mask | extra_mask); 2838 POSTING_READ(DEIER); 2839 2840 gen5_gt_irq_postinstall(dev); 2841 2842 ibx_irq_postinstall(dev); 2843 2844 if (IS_IRONLAKE_M(dev)) { 2845 /* Enable PCU event interrupts 2846 * 2847 * spinlocking not required here for correctness since interrupt 2848 * setup is guaranteed to run in single-threaded context. But we 2849 * need it to make the assert_spin_locked happy. */ 2850 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2851 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); 2852 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2853 } 2854 2855 return 0; 2856 } 2857 2858 static int valleyview_irq_postinstall(struct drm_device *dev) 2859 { 2860 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 2861 u32 enable_mask; 2862 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV | 2863 PIPE_CRC_DONE_ENABLE; 2864 2865 enable_mask = I915_DISPLAY_PORT_INTERRUPT; 2866 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 2867 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 2868 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 2869 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 2870 2871 /* 2872 *Leave vblank interrupts masked initially. enable/disable will 2873 * toggle them based on usage. 2874 */ 2875 dev_priv->irq_mask = (~enable_mask) | 2876 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | 2877 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT; 2878 2879 I915_WRITE(PORT_HOTPLUG_EN, 0); 2880 POSTING_READ(PORT_HOTPLUG_EN); 2881 2882 I915_WRITE(VLV_IMR, dev_priv->irq_mask); 2883 I915_WRITE(VLV_IER, enable_mask); 2884 I915_WRITE(VLV_IIR, 0xffffffff); 2885 I915_WRITE(PIPESTAT(0), 0xffff); 2886 I915_WRITE(PIPESTAT(1), 0xffff); 2887 POSTING_READ(VLV_IER); 2888 2889 /* Interrupt setup is already guaranteed to be single-threaded, this is 2890 * just to make the assert_spin_locked check happy. */ 2891 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 2892 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_enable); 2893 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); 2894 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_enable); 2895 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 2896 2897 I915_WRITE(VLV_IIR, 0xffffffff); 2898 I915_WRITE(VLV_IIR, 0xffffffff); 2899 2900 gen5_gt_irq_postinstall(dev); 2901 2902 /* ack & enable invalid PTE error interrupts */ 2903 #if 0 /* FIXME: add support to irq handler for checking these bits */ 2904 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); 2905 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); 2906 #endif 2907 2908 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); 2909 2910 return 0; 2911 } 2912 2913 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) 2914 { 2915 int i; 2916 2917 /* These are interrupts we'll toggle with the ring mask register */ 2918 uint32_t gt_interrupts[] = { 2919 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | 2920 GT_RENDER_L3_PARITY_ERROR_INTERRUPT | 2921 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT, 2922 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | 2923 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, 2924 0, 2925 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT 2926 }; 2927 2928 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++) { 2929 u32 tmp = I915_READ(GEN8_GT_IIR(i)); 2930 if (tmp) 2931 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", 2932 i, tmp); 2933 I915_WRITE(GEN8_GT_IMR(i), ~gt_interrupts[i]); 2934 I915_WRITE(GEN8_GT_IER(i), gt_interrupts[i]); 2935 } 2936 POSTING_READ(GEN8_GT_IER(0)); 2937 } 2938 2939 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) 2940 { 2941 struct drm_device *dev = dev_priv->dev; 2942 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE | 2943 GEN8_PIPE_CDCLK_CRC_DONE | 2944 GEN8_DE_PIPE_IRQ_FAULT_ERRORS; 2945 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | 2946 GEN8_PIPE_FIFO_UNDERRUN; 2947 int pipe; 2948 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; 2949 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; 2950 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; 2951 2952 for_each_pipe(pipe) { 2953 u32 tmp = I915_READ(GEN8_DE_PIPE_IIR(pipe)); 2954 if (tmp) 2955 DRM_ERROR("Interrupt (%d) should have been masked in pre-install 0x%08x\n", 2956 pipe, tmp); 2957 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); 2958 I915_WRITE(GEN8_DE_PIPE_IER(pipe), de_pipe_enables); 2959 } 2960 POSTING_READ(GEN8_DE_PIPE_ISR(0)); 2961 2962 I915_WRITE(GEN8_DE_PORT_IMR, ~GEN8_AUX_CHANNEL_A); 2963 I915_WRITE(GEN8_DE_PORT_IER, GEN8_AUX_CHANNEL_A); 2964 POSTING_READ(GEN8_DE_PORT_IER); 2965 } 2966 2967 static int gen8_irq_postinstall(struct drm_device *dev) 2968 { 2969 struct drm_i915_private *dev_priv = dev->dev_private; 2970 2971 gen8_gt_irq_postinstall(dev_priv); 2972 gen8_de_irq_postinstall(dev_priv); 2973 2974 ibx_irq_postinstall(dev); 2975 2976 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); 2977 POSTING_READ(GEN8_MASTER_IRQ); 2978 2979 return 0; 2980 } 2981 2982 static void gen8_irq_uninstall(struct drm_device *dev) 2983 { 2984 struct drm_i915_private *dev_priv = dev->dev_private; 2985 int pipe; 2986 2987 if (!dev_priv) 2988 return; 2989 2990 atomic_set(&dev_priv->irq_received, 0); 2991 2992 I915_WRITE(GEN8_MASTER_IRQ, 0); 2993 2994 #define GEN8_IRQ_FINI_NDX(type, which) do { \ 2995 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ 2996 I915_WRITE(GEN8_##type##_IER(which), 0); \ 2997 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ 2998 } while (0) 2999 3000 #define GEN8_IRQ_FINI(type) do { \ 3001 I915_WRITE(GEN8_##type##_IMR, 0xffffffff); \ 3002 I915_WRITE(GEN8_##type##_IER, 0); \ 3003 I915_WRITE(GEN8_##type##_IIR, 0xffffffff); \ 3004 } while (0) 3005 3006 GEN8_IRQ_FINI_NDX(GT, 0); 3007 GEN8_IRQ_FINI_NDX(GT, 1); 3008 GEN8_IRQ_FINI_NDX(GT, 2); 3009 GEN8_IRQ_FINI_NDX(GT, 3); 3010 3011 for_each_pipe(pipe) { 3012 GEN8_IRQ_FINI_NDX(DE_PIPE, pipe); 3013 } 3014 3015 GEN8_IRQ_FINI(DE_PORT); 3016 GEN8_IRQ_FINI(DE_MISC); 3017 GEN8_IRQ_FINI(PCU); 3018 #undef GEN8_IRQ_FINI 3019 #undef GEN8_IRQ_FINI_NDX 3020 3021 POSTING_READ(GEN8_PCU_IIR); 3022 } 3023 3024 static void valleyview_irq_uninstall(struct drm_device *dev) 3025 { 3026 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3027 int pipe; 3028 3029 if (!dev_priv) 3030 return; 3031 3032 del_timer_sync(&dev_priv->hotplug_reenable_timer); 3033 3034 for_each_pipe(pipe) 3035 I915_WRITE(PIPESTAT(pipe), 0xffff); 3036 3037 I915_WRITE(HWSTAM, 0xffffffff); 3038 I915_WRITE(PORT_HOTPLUG_EN, 0); 3039 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3040 for_each_pipe(pipe) 3041 I915_WRITE(PIPESTAT(pipe), 0xffff); 3042 I915_WRITE(VLV_IIR, 0xffffffff); 3043 I915_WRITE(VLV_IMR, 0xffffffff); 3044 I915_WRITE(VLV_IER, 0x0); 3045 POSTING_READ(VLV_IER); 3046 } 3047 3048 static void ironlake_irq_uninstall(struct drm_device *dev) 3049 { 3050 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3051 3052 if (!dev_priv) 3053 return; 3054 3055 del_timer_sync(&dev_priv->hotplug_reenable_timer); 3056 3057 I915_WRITE(HWSTAM, 0xffffffff); 3058 3059 I915_WRITE(DEIMR, 0xffffffff); 3060 I915_WRITE(DEIER, 0x0); 3061 I915_WRITE(DEIIR, I915_READ(DEIIR)); 3062 if (IS_GEN7(dev)) 3063 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT)); 3064 3065 I915_WRITE(GTIMR, 0xffffffff); 3066 I915_WRITE(GTIER, 0x0); 3067 I915_WRITE(GTIIR, I915_READ(GTIIR)); 3068 3069 if (HAS_PCH_NOP(dev)) 3070 return; 3071 3072 I915_WRITE(SDEIMR, 0xffffffff); 3073 I915_WRITE(SDEIER, 0x0); 3074 I915_WRITE(SDEIIR, I915_READ(SDEIIR)); 3075 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) 3076 I915_WRITE(SERR_INT, I915_READ(SERR_INT)); 3077 } 3078 3079 static void i8xx_irq_preinstall(struct drm_device * dev) 3080 { 3081 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3082 int pipe; 3083 3084 atomic_set(&dev_priv->irq_received, 0); 3085 3086 for_each_pipe(pipe) 3087 I915_WRITE(PIPESTAT(pipe), 0); 3088 I915_WRITE16(IMR, 0xffff); 3089 I915_WRITE16(IER, 0x0); 3090 POSTING_READ16(IER); 3091 } 3092 3093 static int i8xx_irq_postinstall(struct drm_device *dev) 3094 { 3095 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3096 3097 I915_WRITE16(EMR, 3098 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3099 3100 /* Unmask the interrupts that we always want on. */ 3101 dev_priv->irq_mask = 3102 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3103 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3104 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3105 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3106 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 3107 I915_WRITE16(IMR, dev_priv->irq_mask); 3108 3109 I915_WRITE16(IER, 3110 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3111 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3112 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 3113 I915_USER_INTERRUPT); 3114 POSTING_READ16(IER); 3115 3116 /* Interrupt setup is already guaranteed to be single-threaded, this is 3117 * just to make the assert_spin_locked check happy. */ 3118 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3119 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 3120 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3121 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3122 3123 return 0; 3124 } 3125 3126 /* 3127 * Returns true when a page flip has completed. 3128 */ 3129 static bool i8xx_handle_vblank(struct drm_device *dev, 3130 int plane, int pipe, u32 iir) 3131 { 3132 drm_i915_private_t *dev_priv = dev->dev_private; 3133 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); 3134 3135 if (!drm_handle_vblank(dev, pipe)) 3136 return false; 3137 3138 if ((iir & flip_pending) == 0) 3139 return false; 3140 3141 intel_prepare_page_flip(dev, plane); 3142 3143 /* We detect FlipDone by looking for the change in PendingFlip from '1' 3144 * to '0' on the following vblank, i.e. IIR has the Pendingflip 3145 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence 3146 * the flip is completed (no longer pending). Since this doesn't raise 3147 * an interrupt per se, we watch for the change at vblank. 3148 */ 3149 if (I915_READ16(ISR) & flip_pending) 3150 return false; 3151 3152 intel_finish_page_flip(dev, pipe); 3153 3154 return true; 3155 } 3156 3157 static irqreturn_t i8xx_irq_handler(void *arg) 3158 { 3159 struct drm_device *dev = (struct drm_device *) arg; 3160 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3161 u16 iir, new_iir; 3162 u32 pipe_stats[2]; 3163 int pipe; 3164 u16 flip_mask = 3165 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3166 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3167 3168 atomic_inc(&dev_priv->irq_received); 3169 3170 iir = I915_READ16(IIR); 3171 if (iir == 0) 3172 return; 3173 3174 while (iir & ~flip_mask) { 3175 /* Can't rely on pipestat interrupt bit in iir as it might 3176 * have been cleared after the pipestat interrupt was received. 3177 * It doesn't set the bit in iir again, but it still produces 3178 * interrupts (for non-MSI). 3179 */ 3180 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3181 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3182 i915_handle_error(dev, false); 3183 3184 for_each_pipe(pipe) { 3185 int reg = PIPESTAT(pipe); 3186 pipe_stats[pipe] = I915_READ(reg); 3187 3188 /* 3189 * Clear the PIPE*STAT regs before the IIR 3190 */ 3191 if (pipe_stats[pipe] & 0x8000ffff) { 3192 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 3193 DRM_DEBUG_DRIVER("pipe %c underrun\n", 3194 pipe_name(pipe)); 3195 I915_WRITE(reg, pipe_stats[pipe]); 3196 } 3197 } 3198 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3199 3200 I915_WRITE16(IIR, iir & ~flip_mask); 3201 new_iir = I915_READ16(IIR); /* Flush posted writes */ 3202 3203 i915_update_dri1_breadcrumb(dev); 3204 3205 if (iir & I915_USER_INTERRUPT) 3206 notify_ring(dev, &dev_priv->ring[RCS]); 3207 3208 for_each_pipe(pipe) { 3209 int plane = pipe; 3210 if (HAS_FBC(dev)) 3211 plane = !plane; 3212 3213 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 3214 i8xx_handle_vblank(dev, plane, pipe, iir)) 3215 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); 3216 3217 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3218 i9xx_pipe_crc_irq_handler(dev, pipe); 3219 } 3220 3221 iir = new_iir; 3222 } 3223 3224 } 3225 3226 static void i8xx_irq_uninstall(struct drm_device * dev) 3227 { 3228 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3229 int pipe; 3230 3231 for_each_pipe(pipe) { 3232 /* Clear enable bits; then clear status bits */ 3233 I915_WRITE(PIPESTAT(pipe), 0); 3234 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 3235 } 3236 I915_WRITE16(IMR, 0xffff); 3237 I915_WRITE16(IER, 0x0); 3238 I915_WRITE16(IIR, I915_READ16(IIR)); 3239 } 3240 3241 static void i915_irq_preinstall(struct drm_device * dev) 3242 { 3243 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3244 int pipe; 3245 3246 atomic_set(&dev_priv->irq_received, 0); 3247 3248 if (I915_HAS_HOTPLUG(dev)) { 3249 I915_WRITE(PORT_HOTPLUG_EN, 0); 3250 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3251 } 3252 3253 I915_WRITE16(HWSTAM, 0xeffe); 3254 for_each_pipe(pipe) 3255 I915_WRITE(PIPESTAT(pipe), 0); 3256 I915_WRITE(IMR, 0xffffffff); 3257 I915_WRITE(IER, 0x0); 3258 POSTING_READ(IER); 3259 } 3260 3261 static int i915_irq_postinstall(struct drm_device *dev) 3262 { 3263 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3264 u32 enable_mask; 3265 3266 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); 3267 3268 /* Unmask the interrupts that we always want on. */ 3269 dev_priv->irq_mask = 3270 ~(I915_ASLE_INTERRUPT | 3271 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3272 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3273 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3274 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3275 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 3276 3277 enable_mask = 3278 I915_ASLE_INTERRUPT | 3279 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3280 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3281 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | 3282 I915_USER_INTERRUPT; 3283 3284 if (I915_HAS_HOTPLUG(dev)) { 3285 I915_WRITE(PORT_HOTPLUG_EN, 0); 3286 POSTING_READ(PORT_HOTPLUG_EN); 3287 3288 /* Enable in IER... */ 3289 enable_mask |= I915_DISPLAY_PORT_INTERRUPT; 3290 /* and unmask in IMR */ 3291 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; 3292 } 3293 3294 I915_WRITE(IMR, dev_priv->irq_mask); 3295 I915_WRITE(IER, enable_mask); 3296 POSTING_READ(IER); 3297 3298 i915_enable_asle_pipestat(dev); 3299 3300 /* Interrupt setup is already guaranteed to be single-threaded, this is 3301 * just to make the assert_spin_locked check happy. */ 3302 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3303 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 3304 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3305 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3306 3307 return 0; 3308 } 3309 3310 /* 3311 * Returns true when a page flip has completed. 3312 */ 3313 static bool i915_handle_vblank(struct drm_device *dev, 3314 int plane, int pipe, u32 iir) 3315 { 3316 drm_i915_private_t *dev_priv = dev->dev_private; 3317 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); 3318 3319 if (!drm_handle_vblank(dev, pipe)) 3320 return false; 3321 3322 if ((iir & flip_pending) == 0) 3323 return false; 3324 3325 intel_prepare_page_flip(dev, plane); 3326 3327 /* We detect FlipDone by looking for the change in PendingFlip from '1' 3328 * to '0' on the following vblank, i.e. IIR has the Pendingflip 3329 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence 3330 * the flip is completed (no longer pending). Since this doesn't raise 3331 * an interrupt per se, we watch for the change at vblank. 3332 */ 3333 if (I915_READ(ISR) & flip_pending) 3334 return false; 3335 3336 intel_finish_page_flip(dev, pipe); 3337 3338 return true; 3339 } 3340 3341 static irqreturn_t i915_irq_handler(void *arg) 3342 { 3343 struct drm_device *dev = (struct drm_device *) arg; 3344 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3345 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; 3346 u32 flip_mask = 3347 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3348 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3349 int pipe; 3350 3351 atomic_inc(&dev_priv->irq_received); 3352 3353 iir = I915_READ(IIR); 3354 do { 3355 bool irq_received = (iir & ~flip_mask) != 0; 3356 bool blc_event = false; 3357 3358 /* Can't rely on pipestat interrupt bit in iir as it might 3359 * have been cleared after the pipestat interrupt was received. 3360 * It doesn't set the bit in iir again, but it still produces 3361 * interrupts (for non-MSI). 3362 */ 3363 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3364 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3365 i915_handle_error(dev, false); 3366 3367 for_each_pipe(pipe) { 3368 int reg = PIPESTAT(pipe); 3369 pipe_stats[pipe] = I915_READ(reg); 3370 3371 /* Clear the PIPE*STAT regs before the IIR */ 3372 if (pipe_stats[pipe] & 0x8000ffff) { 3373 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 3374 DRM_DEBUG_DRIVER("pipe %c underrun\n", 3375 pipe_name(pipe)); 3376 I915_WRITE(reg, pipe_stats[pipe]); 3377 irq_received = true; 3378 } 3379 } 3380 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3381 3382 if (!irq_received) 3383 break; 3384 3385 /* Consume port. Then clear IIR or we'll miss events */ 3386 if ((I915_HAS_HOTPLUG(dev)) && 3387 (iir & I915_DISPLAY_PORT_INTERRUPT)) { 3388 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 3389 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; 3390 3391 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 3392 hotplug_status); 3393 3394 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); 3395 3396 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 3397 POSTING_READ(PORT_HOTPLUG_STAT); 3398 } 3399 3400 I915_WRITE(IIR, iir & ~flip_mask); 3401 new_iir = I915_READ(IIR); /* Flush posted writes */ 3402 3403 if (iir & I915_USER_INTERRUPT) 3404 notify_ring(dev, &dev_priv->ring[RCS]); 3405 3406 for_each_pipe(pipe) { 3407 int plane = pipe; 3408 if (HAS_FBC(dev)) 3409 plane = !plane; 3410 3411 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && 3412 i915_handle_vblank(dev, plane, pipe, iir)) 3413 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); 3414 3415 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 3416 blc_event = true; 3417 3418 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3419 i9xx_pipe_crc_irq_handler(dev, pipe); 3420 } 3421 3422 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 3423 intel_opregion_asle_intr(dev); 3424 3425 /* With MSI, interrupts are only generated when iir 3426 * transitions from zero to nonzero. If another bit got 3427 * set while we were handling the existing iir bits, then 3428 * we would never get another interrupt. 3429 * 3430 * This is fine on non-MSI as well, as if we hit this path 3431 * we avoid exiting the interrupt handler only to generate 3432 * another one. 3433 * 3434 * Note that for MSI this could cause a stray interrupt report 3435 * if an interrupt landed in the time between writing IIR and 3436 * the posting read. This should be rare enough to never 3437 * trigger the 99% of 100,000 interrupts test for disabling 3438 * stray interrupts. 3439 */ 3440 iir = new_iir; 3441 } while (iir & ~flip_mask); 3442 3443 i915_update_dri1_breadcrumb(dev); 3444 3445 } 3446 3447 static void i915_irq_uninstall(struct drm_device * dev) 3448 { 3449 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3450 int pipe; 3451 3452 del_timer_sync(&dev_priv->hotplug_reenable_timer); 3453 3454 if (I915_HAS_HOTPLUG(dev)) { 3455 I915_WRITE(PORT_HOTPLUG_EN, 0); 3456 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3457 } 3458 3459 I915_WRITE16(HWSTAM, 0xffff); 3460 for_each_pipe(pipe) { 3461 /* Clear enable bits; then clear status bits */ 3462 I915_WRITE(PIPESTAT(pipe), 0); 3463 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); 3464 } 3465 I915_WRITE(IMR, 0xffffffff); 3466 I915_WRITE(IER, 0x0); 3467 3468 I915_WRITE(IIR, I915_READ(IIR)); 3469 } 3470 3471 static void i965_irq_preinstall(struct drm_device * dev) 3472 { 3473 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3474 int pipe; 3475 3476 atomic_set(&dev_priv->irq_received, 0); 3477 3478 I915_WRITE(PORT_HOTPLUG_EN, 0); 3479 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3480 3481 I915_WRITE(HWSTAM, 0xeffe); 3482 for_each_pipe(pipe) 3483 I915_WRITE(PIPESTAT(pipe), 0); 3484 I915_WRITE(IMR, 0xffffffff); 3485 I915_WRITE(IER, 0x0); 3486 POSTING_READ(IER); 3487 } 3488 3489 static int i965_irq_postinstall(struct drm_device *dev) 3490 { 3491 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3492 u32 enable_mask; 3493 u32 error_mask; 3494 3495 /* Unmask the interrupts that we always want on. */ 3496 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | 3497 I915_DISPLAY_PORT_INTERRUPT | 3498 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | 3499 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | 3500 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3501 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | 3502 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); 3503 3504 enable_mask = ~dev_priv->irq_mask; 3505 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3506 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); 3507 enable_mask |= I915_USER_INTERRUPT; 3508 3509 if (IS_G4X(dev)) 3510 enable_mask |= I915_BSD_USER_INTERRUPT; 3511 3512 /* Interrupt setup is already guaranteed to be single-threaded, this is 3513 * just to make the assert_spin_locked check happy. */ 3514 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3515 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_EVENT_ENABLE); 3516 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_ENABLE); 3517 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_ENABLE); 3518 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3519 3520 /* 3521 * Enable some error detection, note the instruction error mask 3522 * bit is reserved, so we leave it masked. 3523 */ 3524 if (IS_G4X(dev)) { 3525 error_mask = ~(GM45_ERROR_PAGE_TABLE | 3526 GM45_ERROR_MEM_PRIV | 3527 GM45_ERROR_CP_PRIV | 3528 I915_ERROR_MEMORY_REFRESH); 3529 } else { 3530 error_mask = ~(I915_ERROR_PAGE_TABLE | 3531 I915_ERROR_MEMORY_REFRESH); 3532 } 3533 I915_WRITE(EMR, error_mask); 3534 3535 I915_WRITE(IMR, dev_priv->irq_mask); 3536 I915_WRITE(IER, enable_mask); 3537 POSTING_READ(IER); 3538 3539 I915_WRITE(PORT_HOTPLUG_EN, 0); 3540 POSTING_READ(PORT_HOTPLUG_EN); 3541 3542 i915_enable_asle_pipestat(dev); 3543 3544 return 0; 3545 } 3546 3547 static void i915_hpd_irq_setup(struct drm_device *dev) 3548 { 3549 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3550 struct drm_mode_config *mode_config = &dev->mode_config; 3551 struct intel_encoder *intel_encoder; 3552 u32 hotplug_en; 3553 3554 assert_spin_locked(&dev_priv->irq_lock); 3555 3556 if (I915_HAS_HOTPLUG(dev)) { 3557 hotplug_en = I915_READ(PORT_HOTPLUG_EN); 3558 hotplug_en &= ~HOTPLUG_INT_EN_MASK; 3559 /* Note HDMI and DP share hotplug bits */ 3560 /* enable bits are the same for all generations */ 3561 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head) 3562 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED) 3563 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin]; 3564 /* Programming the CRT detection parameters tends 3565 to generate a spurious hotplug event about three 3566 seconds later. So just do it once. 3567 */ 3568 if (IS_G4X(dev)) 3569 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; 3570 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK; 3571 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; 3572 3573 /* Ignore TV since it's buggy */ 3574 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); 3575 } 3576 } 3577 3578 static irqreturn_t i965_irq_handler(void *arg) 3579 { 3580 struct drm_device *dev = (struct drm_device *) arg; 3581 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3582 u32 iir, new_iir; 3583 u32 pipe_stats[I915_MAX_PIPES]; 3584 int irq_received; 3585 int pipe; 3586 u32 flip_mask = 3587 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3588 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3589 3590 atomic_inc(&dev_priv->irq_received); 3591 3592 iir = I915_READ(IIR); 3593 3594 for (;;) { 3595 bool blc_event = false; 3596 3597 irq_received = (iir & ~flip_mask) != 0; 3598 3599 /* Can't rely on pipestat interrupt bit in iir as it might 3600 * have been cleared after the pipestat interrupt was received. 3601 * It doesn't set the bit in iir again, but it still produces 3602 * interrupts (for non-MSI). 3603 */ 3604 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3605 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) 3606 i915_handle_error(dev, false); 3607 3608 for_each_pipe(pipe) { 3609 int reg = PIPESTAT(pipe); 3610 pipe_stats[pipe] = I915_READ(reg); 3611 3612 /* 3613 * Clear the PIPE*STAT regs before the IIR 3614 */ 3615 if (pipe_stats[pipe] & 0x8000ffff) { 3616 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) 3617 DRM_DEBUG_DRIVER("pipe %c underrun\n", 3618 pipe_name(pipe)); 3619 I915_WRITE(reg, pipe_stats[pipe]); 3620 irq_received = 1; 3621 } 3622 } 3623 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3624 3625 if (!irq_received) 3626 break; 3627 3628 3629 /* Consume port. Then clear IIR or we'll miss events */ 3630 if (iir & I915_DISPLAY_PORT_INTERRUPT) { 3631 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); 3632 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ? 3633 HOTPLUG_INT_STATUS_G4X : 3634 HOTPLUG_INT_STATUS_I915); 3635 3636 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", 3637 hotplug_status); 3638 3639 intel_hpd_irq_handler(dev, hotplug_trigger, 3640 IS_G4X(dev) ? hpd_status_g4x : hpd_status_i915); 3641 3642 if (IS_G4X(dev) && 3643 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)) 3644 dp_aux_irq_handler(dev); 3645 3646 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 3647 I915_READ(PORT_HOTPLUG_STAT); 3648 } 3649 3650 I915_WRITE(IIR, iir & ~flip_mask); 3651 new_iir = I915_READ(IIR); /* Flush posted writes */ 3652 3653 if (iir & I915_USER_INTERRUPT) 3654 notify_ring(dev, &dev_priv->ring[RCS]); 3655 if (iir & I915_BSD_USER_INTERRUPT) 3656 notify_ring(dev, &dev_priv->ring[VCS]); 3657 3658 for_each_pipe(pipe) { 3659 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && 3660 i915_handle_vblank(dev, pipe, pipe, iir)) 3661 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); 3662 3663 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) 3664 blc_event = true; 3665 3666 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) 3667 i9xx_pipe_crc_irq_handler(dev, pipe); 3668 } 3669 3670 3671 if (blc_event || (iir & I915_ASLE_INTERRUPT)) 3672 intel_opregion_asle_intr(dev); 3673 3674 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) 3675 gmbus_irq_handler(dev); 3676 3677 /* With MSI, interrupts are only generated when iir 3678 * transitions from zero to nonzero. If another bit got 3679 * set while we were handling the existing iir bits, then 3680 * we would never get another interrupt. 3681 * 3682 * This is fine on non-MSI as well, as if we hit this path 3683 * we avoid exiting the interrupt handler only to generate 3684 * another one. 3685 * 3686 * Note that for MSI this could cause a stray interrupt report 3687 * if an interrupt landed in the time between writing IIR and 3688 * the posting read. This should be rare enough to never 3689 * trigger the 99% of 100,000 interrupts test for disabling 3690 * stray interrupts. 3691 */ 3692 iir = new_iir; 3693 } 3694 3695 i915_update_dri1_breadcrumb(dev); 3696 3697 } 3698 3699 static void i965_irq_uninstall(struct drm_device * dev) 3700 { 3701 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 3702 int pipe; 3703 3704 if (!dev_priv) 3705 return; 3706 3707 del_timer_sync(&dev_priv->hotplug_reenable_timer); 3708 3709 I915_WRITE(PORT_HOTPLUG_EN, 0); 3710 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); 3711 3712 I915_WRITE(HWSTAM, 0xffffffff); 3713 for_each_pipe(pipe) 3714 I915_WRITE(PIPESTAT(pipe), 0); 3715 I915_WRITE(IMR, 0xffffffff); 3716 I915_WRITE(IER, 0x0); 3717 3718 for_each_pipe(pipe) 3719 I915_WRITE(PIPESTAT(pipe), 3720 I915_READ(PIPESTAT(pipe)) & 0x8000ffff); 3721 I915_WRITE(IIR, I915_READ(IIR)); 3722 } 3723 3724 static void i915_reenable_hotplug_timer_func(unsigned long data) 3725 { 3726 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data; 3727 struct drm_device *dev = dev_priv->dev; 3728 struct drm_mode_config *mode_config = &dev->mode_config; 3729 int i; 3730 3731 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3732 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) { 3733 struct drm_connector *connector; 3734 3735 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED) 3736 continue; 3737 3738 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; 3739 3740 list_for_each_entry(connector, &mode_config->connector_list, head) { 3741 struct intel_connector *intel_connector = to_intel_connector(connector); 3742 3743 if (intel_connector->encoder->hpd_pin == i) { 3744 if (connector->polled != intel_connector->polled) 3745 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n", 3746 drm_get_connector_name(connector)); 3747 connector->polled = intel_connector->polled; 3748 if (!connector->polled) 3749 connector->polled = DRM_CONNECTOR_POLL_HPD; 3750 } 3751 } 3752 } 3753 if (dev_priv->display.hpd_irq_setup) 3754 dev_priv->display.hpd_irq_setup(dev); 3755 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3756 } 3757 3758 void intel_irq_init(struct drm_device *dev) 3759 { 3760 struct drm_i915_private *dev_priv = dev->dev_private; 3761 3762 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); 3763 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func); 3764 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); 3765 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); 3766 3767 setup_timer(&dev_priv->gpu_error.hangcheck_timer, 3768 i915_hangcheck_elapsed, 3769 (unsigned long) dev); 3770 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func, 3771 (unsigned long) dev_priv); 3772 3773 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); 3774 3775 if (IS_GEN2(dev)) { 3776 dev->max_vblank_count = 0; 3777 dev->driver->get_vblank_counter = i8xx_get_vblank_counter; 3778 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { 3779 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ 3780 dev->driver->get_vblank_counter = gm45_get_vblank_counter; 3781 } else { 3782 dev->driver->get_vblank_counter = i915_get_vblank_counter; 3783 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ 3784 } 3785 3786 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 3787 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; 3788 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; 3789 } 3790 3791 if (IS_VALLEYVIEW(dev)) { 3792 dev->driver->irq_handler = valleyview_irq_handler; 3793 dev->driver->irq_preinstall = valleyview_irq_preinstall; 3794 dev->driver->irq_postinstall = valleyview_irq_postinstall; 3795 dev->driver->irq_uninstall = valleyview_irq_uninstall; 3796 dev->driver->enable_vblank = valleyview_enable_vblank; 3797 dev->driver->disable_vblank = valleyview_disable_vblank; 3798 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 3799 } else if (IS_GEN8(dev)) { 3800 dev->driver->irq_handler = gen8_irq_handler; 3801 dev->driver->irq_preinstall = gen8_irq_preinstall; 3802 dev->driver->irq_postinstall = gen8_irq_postinstall; 3803 dev->driver->irq_uninstall = gen8_irq_uninstall; 3804 dev->driver->enable_vblank = gen8_enable_vblank; 3805 dev->driver->disable_vblank = gen8_disable_vblank; 3806 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; 3807 } else if (HAS_PCH_SPLIT(dev)) { 3808 dev->driver->irq_handler = ironlake_irq_handler; 3809 dev->driver->irq_preinstall = ironlake_irq_preinstall; 3810 dev->driver->irq_postinstall = ironlake_irq_postinstall; 3811 dev->driver->irq_uninstall = ironlake_irq_uninstall; 3812 dev->driver->enable_vblank = ironlake_enable_vblank; 3813 dev->driver->disable_vblank = ironlake_disable_vblank; 3814 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup; 3815 } else { 3816 if (INTEL_INFO(dev)->gen == 2) { 3817 dev->driver->irq_preinstall = i8xx_irq_preinstall; 3818 dev->driver->irq_postinstall = i8xx_irq_postinstall; 3819 dev->driver->irq_handler = i8xx_irq_handler; 3820 dev->driver->irq_uninstall = i8xx_irq_uninstall; 3821 } else if (INTEL_INFO(dev)->gen == 3) { 3822 dev->driver->irq_preinstall = i915_irq_preinstall; 3823 dev->driver->irq_postinstall = i915_irq_postinstall; 3824 dev->driver->irq_uninstall = i915_irq_uninstall; 3825 dev->driver->irq_handler = i915_irq_handler; 3826 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 3827 } else { 3828 dev->driver->irq_preinstall = i965_irq_preinstall; 3829 dev->driver->irq_postinstall = i965_irq_postinstall; 3830 dev->driver->irq_uninstall = i965_irq_uninstall; 3831 dev->driver->irq_handler = i965_irq_handler; 3832 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; 3833 } 3834 dev->driver->enable_vblank = i915_enable_vblank; 3835 dev->driver->disable_vblank = i915_disable_vblank; 3836 } 3837 } 3838 3839 void intel_hpd_init(struct drm_device *dev) 3840 { 3841 struct drm_i915_private *dev_priv = dev->dev_private; 3842 struct drm_mode_config *mode_config = &dev->mode_config; 3843 struct drm_connector *connector; 3844 int i; 3845 3846 for (i = 1; i < HPD_NUM_PINS; i++) { 3847 dev_priv->hpd_stats[i].hpd_cnt = 0; 3848 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED; 3849 } 3850 list_for_each_entry(connector, &mode_config->connector_list, head) { 3851 struct intel_connector *intel_connector = to_intel_connector(connector); 3852 connector->polled = intel_connector->polled; 3853 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE) 3854 connector->polled = DRM_CONNECTOR_POLL_HPD; 3855 } 3856 3857 /* Interrupt setup is already guaranteed to be single-threaded, this is 3858 * just to make the assert_spin_locked checks happy. */ 3859 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3860 if (dev_priv->display.hpd_irq_setup) 3861 dev_priv->display.hpd_irq_setup(dev); 3862 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3863 } 3864 3865 /* Disable interrupts so we can allow Package C8+. */ 3866 void hsw_pc8_disable_interrupts(struct drm_device *dev) 3867 { 3868 struct drm_i915_private *dev_priv = dev->dev_private; 3869 3870 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3871 3872 dev_priv->pc8.regsave.deimr = I915_READ(DEIMR); 3873 dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR); 3874 dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR); 3875 dev_priv->pc8.regsave.gtier = I915_READ(GTIER); 3876 dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR); 3877 3878 ironlake_disable_display_irq(dev_priv, 0xffffffff); 3879 ibx_disable_display_interrupt(dev_priv, 0xffffffff); 3880 ilk_disable_gt_irq(dev_priv, 0xffffffff); 3881 snb_disable_pm_irq(dev_priv, 0xffffffff); 3882 3883 dev_priv->pc8.irqs_disabled = true; 3884 3885 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3886 } 3887 3888 /* Restore interrupts so we can recover from Package C8+. */ 3889 void hsw_pc8_restore_interrupts(struct drm_device *dev) 3890 { 3891 struct drm_i915_private *dev_priv = dev->dev_private; 3892 uint32_t val; 3893 3894 lockmgr(&dev_priv->irq_lock, LK_EXCLUSIVE); 3895 3896 val = I915_READ(DEIMR); 3897 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val); 3898 3899 val = I915_READ(SDEIMR); 3900 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val); 3901 3902 val = I915_READ(GTIMR); 3903 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val); 3904 3905 val = I915_READ(GEN6_PMIMR); 3906 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val); 3907 3908 dev_priv->pc8.irqs_disabled = false; 3909 3910 ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr); 3911 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pc8.regsave.sdeimr); 3912 ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr); 3913 snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr); 3914 I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier); 3915 3916 lockmgr(&dev_priv->irq_lock, LK_RELEASE); 3917 } 3918