1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Mika Kuoppala <mika.kuoppala@intel.com> 25 * 26 */ 27 28 #include "i915_drv.h" 29 #include "intel_renderstate.h" 30 31 struct render_state { 32 const struct intel_renderstate_rodata *rodata; 33 struct drm_i915_gem_object *obj; 34 u64 ggtt_offset; 35 u32 aux_batch_size; 36 u32 aux_batch_offset; 37 }; 38 39 static const struct intel_renderstate_rodata * 40 render_state_get_rodata(const struct drm_i915_gem_request *req) 41 { 42 switch (INTEL_GEN(req->i915)) { 43 case 6: 44 return &gen6_null_state; 45 case 7: 46 return &gen7_null_state; 47 case 8: 48 return &gen8_null_state; 49 case 9: 50 return &gen9_null_state; 51 } 52 53 return NULL; 54 } 55 56 /* 57 * Macro to add commands to auxiliary batch. 58 * This macro only checks for page overflow before inserting the commands, 59 * this is sufficient as the null state generator makes the final batch 60 * with two passes to build command and state separately. At this point 61 * the size of both are known and it compacts them by relocating the state 62 * right after the commands taking care of aligment so we should sufficient 63 * space below them for adding new commands. 64 */ 65 #define OUT_BATCH(batch, i, val) \ 66 do { \ 67 if (WARN_ON((i) >= PAGE_SIZE / sizeof(u32))) { \ 68 ret = -ENOSPC; \ 69 goto err_out; \ 70 } \ 71 (batch)[(i)++] = (val); \ 72 } while(0) 73 74 static int render_state_setup(struct render_state *so) 75 { 76 struct drm_device *dev = so->obj->base.dev; 77 const struct intel_renderstate_rodata *rodata = so->rodata; 78 const bool has_64bit_reloc = INTEL_GEN(dev) >= 8; 79 unsigned int i = 0, reloc_index = 0; 80 struct page *page; 81 u32 *d; 82 int ret; 83 84 ret = i915_gem_object_set_to_cpu_domain(so->obj, true); 85 if (ret) 86 return ret; 87 88 page = i915_gem_object_get_dirty_page(so->obj, 0); 89 d = kmap(page); 90 91 while (i < rodata->batch_items) { 92 u32 s = rodata->batch[i]; 93 94 if (i * 4 == rodata->reloc[reloc_index]) { 95 u64 r = s + so->ggtt_offset; 96 s = lower_32_bits(r); 97 if (has_64bit_reloc) { 98 if (i + 1 >= rodata->batch_items || 99 rodata->batch[i + 1] != 0) { 100 ret = -EINVAL; 101 goto err_out; 102 } 103 104 d[i++] = s; 105 s = upper_32_bits(r); 106 } 107 108 reloc_index++; 109 } 110 111 d[i++] = s; 112 } 113 114 while (i % CACHELINE_DWORDS) 115 OUT_BATCH(d, i, MI_NOOP); 116 117 so->aux_batch_offset = i * sizeof(u32); 118 119 if (HAS_POOLED_EU(dev)) { 120 /* 121 * We always program 3x6 pool config but depending upon which 122 * subslice is disabled HW drops down to appropriate config 123 * shown below. 124 * 125 * In the below table 2x6 config always refers to 126 * fused-down version, native 2x6 is not available and can 127 * be ignored 128 * 129 * SNo subslices config eu pool configuration 130 * ----------------------------------------------------------- 131 * 1 3 subslices enabled (3x6) - 0x00777000 (9+9) 132 * 2 ss0 disabled (2x6) - 0x00777000 (3+9) 133 * 3 ss1 disabled (2x6) - 0x00770000 (6+6) 134 * 4 ss2 disabled (2x6) - 0x00007000 (9+3) 135 */ 136 u32 eu_pool_config = 0x00777000; 137 138 OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE); 139 OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE); 140 OUT_BATCH(d, i, eu_pool_config); 141 OUT_BATCH(d, i, 0); 142 OUT_BATCH(d, i, 0); 143 OUT_BATCH(d, i, 0); 144 } 145 146 OUT_BATCH(d, i, MI_BATCH_BUFFER_END); 147 so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset; 148 149 /* 150 * Since we are sending length, we need to strictly conform to 151 * all requirements. For Gen2 this must be a multiple of 8. 152 */ 153 so->aux_batch_size = ALIGN(so->aux_batch_size, 8); 154 155 kunmap(page); 156 157 ret = i915_gem_object_set_to_gtt_domain(so->obj, false); 158 if (ret) 159 return ret; 160 161 if (rodata->reloc[reloc_index] != -1) { 162 DRM_ERROR("only %d relocs resolved\n", reloc_index); 163 return -EINVAL; 164 } 165 166 return 0; 167 168 err_out: 169 kunmap(page); 170 return ret; 171 } 172 173 #undef OUT_BATCH 174 175 int i915_gem_render_state_init(struct drm_i915_gem_request *req) 176 { 177 struct render_state so; 178 int ret; 179 180 if (WARN_ON(req->engine->id != RCS)) 181 return -ENOENT; 182 183 so.rodata = render_state_get_rodata(req); 184 if (!so.rodata) 185 return 0; 186 187 if (so.rodata->batch_items * 4 > 4096) 188 return -EINVAL; 189 190 so.obj = i915_gem_object_create(&req->i915->drm, 4096); 191 if (IS_ERR(so.obj)) 192 return PTR_ERR(so.obj); 193 194 ret = i915_gem_object_ggtt_pin(so.obj, NULL, 0, 0, 0); 195 if (ret) 196 goto err_obj; 197 198 so.ggtt_offset = i915_gem_obj_ggtt_offset(so.obj); 199 200 ret = render_state_setup(&so); 201 if (ret) 202 goto err_unpin; 203 204 ret = req->engine->emit_bb_start(req, so.ggtt_offset, 205 so.rodata->batch_items * 4, 206 I915_DISPATCH_SECURE); 207 if (ret) 208 goto err_unpin; 209 210 if (so.aux_batch_size > 8) { 211 ret = req->engine->emit_bb_start(req, 212 (so.ggtt_offset + 213 so.aux_batch_offset), 214 so.aux_batch_size, 215 I915_DISPATCH_SECURE); 216 if (ret) 217 goto err_unpin; 218 } 219 220 i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req, 0); 221 err_unpin: 222 i915_gem_object_ggtt_unpin(so.obj); 223 err_obj: 224 i915_gem_object_put(so.obj); 225 return ret; 226 } 227