1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3 /* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 * $FreeBSD: src/sys/dev/drm2/i915/i915_drv.h,v 1.1 2012/05/22 11:07:44 kib Exp $ 29 */ 30 31 #ifndef _I915_DRV_H_ 32 #define _I915_DRV_H_ 33 34 #include <sys/eventhandler.h> 35 36 #include <dev/agp/agp_i810.h> 37 #include "i915_reg.h" 38 #include "intel_bios.h" 39 #include "intel_ringbuffer.h" 40 #include <linux/workqueue.h> 41 42 /* General customization: 43 */ 44 45 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 46 47 #define DRIVER_NAME "i915" 48 #define DRIVER_DESC "Intel Graphics" 49 #define DRIVER_DATE "20080730" 50 51 MALLOC_DECLARE(DRM_I915_GEM); 52 53 enum i915_pipe { 54 PIPE_A = 0, 55 PIPE_B, 56 PIPE_C, 57 I915_MAX_PIPES 58 }; 59 #define pipe_name(p) ((p) + 'A') 60 #define I915_NUM_PIPE 2 61 62 enum transcoder { 63 TRANSCODER_A = 0, 64 TRANSCODER_B, 65 TRANSCODER_C, 66 TRANSCODER_EDP = 0xF, 67 }; 68 #define transcoder_name(t) ((t) + 'A') 69 70 enum plane { 71 PLANE_A = 0, 72 PLANE_B, 73 PLANE_C, 74 }; 75 #define plane_name(p) ((p) + 'A') 76 77 enum port { 78 PORT_A = 0, 79 PORT_B, 80 PORT_C, 81 PORT_D, 82 PORT_E, 83 I915_MAX_PORTS 84 }; 85 #define port_name(p) ((p) + 'A') 86 87 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) 88 89 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) 90 91 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ 92 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ 93 if ((intel_encoder)->base.crtc == (__crtc)) 94 95 struct intel_pch_pll { 96 int refcount; /* count of number of CRTCs sharing this PLL */ 97 int active; /* count of number of active CRTCs (i.e. DPMS on) */ 98 bool on; /* is the PLL actually active? Disabled during modeset */ 99 int pll_reg; 100 int fp0_reg; 101 int fp1_reg; 102 }; 103 #define I915_NUM_PLLS 2 104 105 struct intel_ddi_plls { 106 int spll_refcount; 107 int wrpll1_refcount; 108 int wrpll2_refcount; 109 }; 110 111 /* Interface history: 112 * 113 * 1.1: Original. 114 * 1.2: Add Power Management 115 * 1.3: Add vblank support 116 * 1.4: Fix cmdbuffer path, add heap destroy 117 * 1.5: Add vblank pipe configuration 118 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank 119 * - Support vertical blank on secondary display pipe 120 */ 121 #define DRIVER_MAJOR 1 122 #define DRIVER_MINOR 6 123 #define DRIVER_PATCHLEVEL 0 124 125 #define WATCH_COHERENCY 0 126 #define WATCH_LISTS 0 127 #define WATCH_GTT 0 128 129 #define I915_GEM_PHYS_CURSOR_0 1 130 #define I915_GEM_PHYS_CURSOR_1 2 131 #define I915_GEM_PHYS_OVERLAY_REGS 3 132 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) 133 134 struct drm_i915_gem_phys_object { 135 int id; 136 drm_dma_handle_t *handle; 137 struct drm_i915_gem_object *cur_obj; 138 }; 139 140 struct opregion_header; 141 struct opregion_acpi; 142 struct opregion_swsci; 143 struct opregion_asle; 144 struct drm_i915_private; 145 146 struct intel_opregion { 147 struct opregion_header __iomem *header; 148 struct opregion_acpi __iomem *acpi; 149 struct opregion_swsci __iomem *swsci; 150 struct opregion_asle __iomem *asle; 151 void __iomem *vbt; 152 u32 __iomem *lid_state; 153 }; 154 #define OPREGION_SIZE (8*1024) 155 156 struct intel_overlay; 157 struct intel_overlay_error_state; 158 159 struct drm_i915_master_private { 160 drm_local_map_t *sarea; 161 struct _drm_i915_sarea *sarea_priv; 162 }; 163 #define I915_FENCE_REG_NONE -1 164 #define I915_MAX_NUM_FENCES 16 165 /* 16 fences + sign bit for FENCE_REG_NONE */ 166 #define I915_MAX_NUM_FENCE_BITS 5 167 168 struct drm_i915_fence_reg { 169 struct list_head lru_list; 170 struct drm_i915_gem_object *obj; 171 uint32_t setup_seqno; 172 int pin_count; 173 }; 174 175 struct sdvo_device_mapping { 176 u8 initialized; 177 u8 dvo_port; 178 u8 slave_addr; 179 u8 dvo_wiring; 180 u8 i2c_pin; 181 u8 ddc_pin; 182 }; 183 184 struct drm_i915_error_state { 185 u32 eir; 186 u32 pgtbl_er; 187 bool waiting[I915_NUM_RINGS]; 188 u32 pipestat[I915_MAX_PIPES]; 189 u32 tail[I915_NUM_RINGS]; 190 u32 head[I915_NUM_RINGS]; 191 u32 ipeir[I915_NUM_RINGS]; 192 u32 ipehr[I915_NUM_RINGS]; 193 u32 instdone[I915_NUM_RINGS]; 194 u32 acthd[I915_NUM_RINGS]; 195 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; 196 /* our own tracking of ring head and tail */ 197 u32 cpu_ring_head[I915_NUM_RINGS]; 198 u32 cpu_ring_tail[I915_NUM_RINGS]; 199 u32 error; /* gen6+ */ 200 u32 instpm[I915_NUM_RINGS]; 201 u32 instps[I915_NUM_RINGS]; 202 u32 instdone1; 203 u32 seqno[I915_NUM_RINGS]; 204 u64 bbaddr; 205 u32 fault_reg[I915_NUM_RINGS]; 206 u32 done_reg; 207 u32 faddr[I915_NUM_RINGS]; 208 u64 fence[I915_MAX_NUM_FENCES]; 209 struct timeval time; 210 struct drm_i915_error_ring { 211 struct drm_i915_error_object { 212 int page_count; 213 u32 gtt_offset; 214 u32 *pages[0]; 215 } *ringbuffer, *batchbuffer; 216 struct drm_i915_error_request { 217 long jiffies; 218 u32 seqno; 219 u32 tail; 220 } *requests; 221 int num_requests; 222 } ring[I915_NUM_RINGS]; 223 struct drm_i915_error_buffer { 224 u32 size; 225 u32 name; 226 u32 seqno; 227 u32 gtt_offset; 228 u32 read_domains; 229 u32 write_domain; 230 s32 fence_reg:I915_MAX_NUM_FENCE_BITS; 231 s32 pinned:2; 232 u32 tiling:2; 233 u32 dirty:1; 234 u32 purgeable:1; 235 s32 ring:4; 236 u32 cache_level:2; 237 } *active_bo, *pinned_bo; 238 u32 active_bo_count, pinned_bo_count; 239 struct intel_overlay_error_state *overlay; 240 struct intel_display_error_state *display; 241 }; 242 243 struct drm_i915_display_funcs { 244 void (*dpms)(struct drm_crtc *crtc, int mode); 245 bool (*fbc_enabled)(struct drm_device *dev); 246 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); 247 void (*disable_fbc)(struct drm_device *dev); 248 int (*get_display_clock_speed)(struct drm_device *dev); 249 int (*get_fifo_size)(struct drm_device *dev, int plane); 250 void (*update_wm)(struct drm_device *dev); 251 void (*update_sprite_wm)(struct drm_device *dev, int pipe, 252 uint32_t sprite_width, int pixel_size); 253 void (*update_linetime_wm)(struct drm_device *dev, int pipe, 254 struct drm_display_mode *mode); 255 int (*crtc_mode_set)(struct drm_crtc *crtc, 256 struct drm_display_mode *mode, 257 struct drm_display_mode *adjusted_mode, 258 int x, int y, 259 struct drm_framebuffer *old_fb); 260 void (*write_eld)(struct drm_connector *connector, 261 struct drm_crtc *crtc); 262 void (*fdi_link_train)(struct drm_crtc *crtc); 263 void (*init_clock_gating)(struct drm_device *dev); 264 void (*init_pch_clock_gating)(struct drm_device *dev); 265 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, 266 struct drm_framebuffer *fb, 267 struct drm_i915_gem_object *obj); 268 void (*force_wake_get)(struct drm_i915_private *dev_priv); 269 void (*force_wake_put)(struct drm_i915_private *dev_priv); 270 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, 271 int x, int y); 272 /* clock updates for mode set */ 273 /* cursor updates */ 274 /* render clock increase/decrease */ 275 /* display clock increase/decrease */ 276 /* pll clock increase/decrease */ 277 }; 278 279 struct drm_i915_gt_funcs { 280 void (*force_wake_get)(struct drm_i915_private *dev_priv); 281 void (*force_wake_put)(struct drm_i915_private *dev_priv); 282 }; 283 284 #define DEV_INFO_FLAGS \ 285 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \ 286 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \ 287 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \ 288 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \ 289 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \ 290 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \ 291 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \ 292 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \ 293 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \ 294 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \ 295 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \ 296 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \ 297 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \ 298 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \ 299 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \ 300 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \ 301 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \ 302 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \ 303 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \ 304 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \ 305 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \ 306 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \ 307 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \ 308 DEV_INFO_FLAG(has_llc) 309 310 struct intel_device_info { 311 u8 gen; 312 u8 is_mobile:1; 313 u8 is_i85x:1; 314 u8 is_i915g:1; 315 u8 is_i945gm:1; 316 u8 is_g33:1; 317 u8 need_gfx_hws:1; 318 u8 is_g4x:1; 319 u8 is_pineview:1; 320 u8 is_broadwater:1; 321 u8 is_crestline:1; 322 u8 is_ivybridge:1; 323 u8 is_valleyview:1; 324 u8 has_force_wake:1; 325 u8 is_haswell:1; 326 u8 has_fbc:1; 327 u8 has_pipe_cxsr:1; 328 u8 has_hotplug:1; 329 u8 cursor_needs_physical:1; 330 u8 has_overlay:1; 331 u8 overlay_needs_physical:1; 332 u8 supports_tv:1; 333 u8 has_bsd_ring:1; 334 u8 has_blt_ring:1; 335 u8 has_llc:1; 336 }; 337 338 #define I915_PPGTT_PD_ENTRIES 512 339 #define I915_PPGTT_PT_ENTRIES 1024 340 struct i915_hw_ppgtt { 341 unsigned num_pd_entries; 342 vm_page_t *pt_pages; 343 uint32_t pd_offset; 344 vm_paddr_t *pt_dma_addr; 345 vm_paddr_t scratch_page_dma_addr; 346 }; 347 348 enum no_fbc_reason { 349 FBC_NO_OUTPUT, /* no outputs enabled to compress */ 350 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ 351 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ 352 FBC_MODE_TOO_LARGE, /* mode too large for compression */ 353 FBC_BAD_PLANE, /* fbc not supported on plane */ 354 FBC_NOT_TILED, /* buffer not tiled */ 355 FBC_MULTIPLE_PIPES, /* more than one pipe active */ 356 FBC_MODULE_PARAM, 357 }; 358 359 /* defined intel_pm.c */ 360 extern struct lock mchdev_lock; 361 362 struct mem_block { 363 struct mem_block *next; 364 struct mem_block *prev; 365 int start; 366 int size; 367 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ 368 }; 369 370 struct opregion_header; 371 struct opregion_acpi; 372 struct opregion_swsci; 373 struct opregion_asle; 374 375 #define I915_FENCE_REG_NONE -1 376 #define I915_MAX_NUM_FENCES 16 377 /* 16 fences + sign bit for FENCE_REG_NONE */ 378 #define I915_MAX_NUM_FENCE_BITS 5 379 380 enum intel_pch { 381 PCH_NONE = 0, /* No PCH present */ 382 PCH_IBX, /* Ibexpeak PCH */ 383 PCH_CPT, /* Cougarpoint PCH */ 384 PCH_LPT, /* Lynxpoint PCH */ 385 }; 386 387 enum intel_sbi_destination { 388 SBI_ICLK, 389 SBI_MPHY, 390 }; 391 392 #define QUIRK_PIPEA_FORCE (1<<0) 393 #define QUIRK_LVDS_SSC_DISABLE (1<<1) 394 #define QUIRK_INVERT_BRIGHTNESS (1<<2) 395 396 struct intel_fbdev; 397 struct intel_fbc_work; 398 399 struct intel_gmbus { 400 u32 force_bit; 401 u32 reg0; 402 u32 gpio_reg; 403 struct drm_i915_private *dev_priv; 404 }; 405 406 struct i915_suspend_saved_registers { 407 u8 saveLBB; 408 u32 saveDSPACNTR; 409 u32 saveDSPBCNTR; 410 u32 saveDSPARB; 411 u32 savePIPEACONF; 412 u32 savePIPEBCONF; 413 u32 savePIPEASRC; 414 u32 savePIPEBSRC; 415 u32 saveFPA0; 416 u32 saveFPA1; 417 u32 saveDPLL_A; 418 u32 saveDPLL_A_MD; 419 u32 saveHTOTAL_A; 420 u32 saveHBLANK_A; 421 u32 saveHSYNC_A; 422 u32 saveVTOTAL_A; 423 u32 saveVBLANK_A; 424 u32 saveVSYNC_A; 425 u32 saveBCLRPAT_A; 426 u32 saveTRANSACONF; 427 u32 saveTRANS_HTOTAL_A; 428 u32 saveTRANS_HBLANK_A; 429 u32 saveTRANS_HSYNC_A; 430 u32 saveTRANS_VTOTAL_A; 431 u32 saveTRANS_VBLANK_A; 432 u32 saveTRANS_VSYNC_A; 433 u32 savePIPEASTAT; 434 u32 saveDSPASTRIDE; 435 u32 saveDSPASIZE; 436 u32 saveDSPAPOS; 437 u32 saveDSPAADDR; 438 u32 saveDSPASURF; 439 u32 saveDSPATILEOFF; 440 u32 savePFIT_PGM_RATIOS; 441 u32 saveBLC_HIST_CTL; 442 u32 saveBLC_PWM_CTL; 443 u32 saveBLC_PWM_CTL2; 444 u32 saveBLC_CPU_PWM_CTL; 445 u32 saveBLC_CPU_PWM_CTL2; 446 u32 saveFPB0; 447 u32 saveFPB1; 448 u32 saveDPLL_B; 449 u32 saveDPLL_B_MD; 450 u32 saveHTOTAL_B; 451 u32 saveHBLANK_B; 452 u32 saveHSYNC_B; 453 u32 saveVTOTAL_B; 454 u32 saveVBLANK_B; 455 u32 saveVSYNC_B; 456 u32 saveBCLRPAT_B; 457 u32 saveTRANSBCONF; 458 u32 saveTRANS_HTOTAL_B; 459 u32 saveTRANS_HBLANK_B; 460 u32 saveTRANS_HSYNC_B; 461 u32 saveTRANS_VTOTAL_B; 462 u32 saveTRANS_VBLANK_B; 463 u32 saveTRANS_VSYNC_B; 464 u32 savePIPEBSTAT; 465 u32 saveDSPBSTRIDE; 466 u32 saveDSPBSIZE; 467 u32 saveDSPBPOS; 468 u32 saveDSPBADDR; 469 u32 saveDSPBSURF; 470 u32 saveDSPBTILEOFF; 471 u32 saveVGA0; 472 u32 saveVGA1; 473 u32 saveVGA_PD; 474 u32 saveVGACNTRL; 475 u32 saveADPA; 476 u32 saveLVDS; 477 u32 savePP_ON_DELAYS; 478 u32 savePP_OFF_DELAYS; 479 u32 saveDVOA; 480 u32 saveDVOB; 481 u32 saveDVOC; 482 u32 savePP_ON; 483 u32 savePP_OFF; 484 u32 savePP_CONTROL; 485 u32 savePP_DIVISOR; 486 u32 savePFIT_CONTROL; 487 u32 save_palette_a[256]; 488 u32 save_palette_b[256]; 489 u32 saveDPFC_CB_BASE; 490 u32 saveFBC_CFB_BASE; 491 u32 saveFBC_LL_BASE; 492 u32 saveFBC_CONTROL; 493 u32 saveFBC_CONTROL2; 494 u32 saveIER; 495 u32 saveIIR; 496 u32 saveIMR; 497 u32 saveDEIER; 498 u32 saveDEIMR; 499 u32 saveGTIER; 500 u32 saveGTIMR; 501 u32 saveFDI_RXA_IMR; 502 u32 saveFDI_RXB_IMR; 503 u32 saveCACHE_MODE_0; 504 u32 saveMI_ARB_STATE; 505 u32 saveSWF0[16]; 506 u32 saveSWF1[16]; 507 u32 saveSWF2[3]; 508 u8 saveMSR; 509 u8 saveSR[8]; 510 u8 saveGR[25]; 511 u8 saveAR_INDEX; 512 u8 saveAR[21]; 513 u8 saveDACMASK; 514 u8 saveCR[37]; 515 uint64_t saveFENCE[I915_MAX_NUM_FENCES]; 516 u32 saveCURACNTR; 517 u32 saveCURAPOS; 518 u32 saveCURABASE; 519 u32 saveCURBCNTR; 520 u32 saveCURBPOS; 521 u32 saveCURBBASE; 522 u32 saveCURSIZE; 523 u32 saveDP_B; 524 u32 saveDP_C; 525 u32 saveDP_D; 526 u32 savePIPEA_GMCH_DATA_M; 527 u32 savePIPEB_GMCH_DATA_M; 528 u32 savePIPEA_GMCH_DATA_N; 529 u32 savePIPEB_GMCH_DATA_N; 530 u32 savePIPEA_DP_LINK_M; 531 u32 savePIPEB_DP_LINK_M; 532 u32 savePIPEA_DP_LINK_N; 533 u32 savePIPEB_DP_LINK_N; 534 u32 saveFDI_RXA_CTL; 535 u32 saveFDI_TXA_CTL; 536 u32 saveFDI_RXB_CTL; 537 u32 saveFDI_TXB_CTL; 538 u32 savePFA_CTL_1; 539 u32 savePFB_CTL_1; 540 u32 savePFA_WIN_SZ; 541 u32 savePFB_WIN_SZ; 542 u32 savePFA_WIN_POS; 543 u32 savePFB_WIN_POS; 544 u32 savePCH_DREF_CONTROL; 545 u32 saveDISP_ARB_CTL; 546 u32 savePIPEA_DATA_M1; 547 u32 savePIPEA_DATA_N1; 548 u32 savePIPEA_LINK_M1; 549 u32 savePIPEA_LINK_N1; 550 u32 savePIPEB_DATA_M1; 551 u32 savePIPEB_DATA_N1; 552 u32 savePIPEB_LINK_M1; 553 u32 savePIPEB_LINK_N1; 554 u32 saveMCHBAR_RENDER_STANDBY; 555 u32 savePCH_PORT_HOTPLUG; 556 }; 557 558 struct intel_gen6_power_mgmt { 559 struct work_struct work; 560 u32 pm_iir; 561 /* lock - irqsave spinlock that protectects the work_struct and 562 * pm_iir. */ 563 struct spinlock lock; 564 565 /* The below variables an all the rps hw state are protected by 566 * dev->struct mutext. */ 567 u8 cur_delay; 568 u8 min_delay; 569 u8 max_delay; 570 571 struct delayed_work delayed_resume_work; 572 573 /* 574 * Protects RPS/RC6 register access and PCU communication. 575 * Must be taken after struct_mutex if nested. 576 */ 577 struct lock hw_lock; 578 }; 579 580 struct intel_ilk_power_mgmt { 581 u8 cur_delay; 582 u8 min_delay; 583 u8 max_delay; 584 u8 fmax; 585 u8 fstart; 586 587 u64 last_count1; 588 unsigned long last_time1; 589 unsigned long chipset_power; 590 u64 last_count2; 591 struct timespec last_time2; 592 unsigned long gfx_power; 593 u8 corr; 594 595 int c_m; 596 int r_t; 597 598 struct drm_i915_gem_object *pwrctx; 599 struct drm_i915_gem_object *renderctx; 600 }; 601 602 struct i915_dri1_state { 603 unsigned allow_batchbuffer : 1; 604 u32 __iomem *gfx_hws_cpu_addr; 605 606 unsigned int cpp; 607 int back_offset; 608 int front_offset; 609 int current_page; 610 int page_flipping; 611 612 uint32_t counter; 613 }; 614 615 struct intel_l3_parity { 616 u32 *remap_info; 617 struct work_struct error_work; 618 }; 619 620 typedef struct drm_i915_private { 621 struct drm_device *dev; 622 623 device_t *gmbus_bridge; 624 device_t *bbbus_bridge; 625 device_t *gmbus; 626 device_t *bbbus; 627 628 /** gmbus_sx protects against concurrent usage of the single hw gmbus 629 * controller on different i2c buses. */ 630 struct lock gmbus_lock; 631 632 int relative_constants_mode; 633 634 drm_local_map_t *sarea; 635 drm_local_map_t *mmio_map; 636 637 struct drm_i915_gt_funcs gt; 638 /** gt_fifo_count and the subsequent register write are synchronized 639 * with dev->struct_mutex. */ 640 unsigned gt_fifo_count; 641 /** forcewake_count is protected by gt_lock */ 642 unsigned forcewake_count; 643 /** gt_lock is also taken in irq contexts. */ 644 struct lock gt_lock; 645 646 drm_i915_sarea_t *sarea_priv; 647 struct intel_ring_buffer ring[I915_NUM_RINGS]; 648 uint32_t next_seqno; 649 650 drm_dma_handle_t *status_page_dmah; 651 struct resource *mch_res; 652 653 void *hw_status_page; 654 dma_addr_t dma_status_page; 655 uint32_t counter; 656 unsigned int status_gfx_addr; 657 drm_local_map_t hws_map; 658 struct drm_gem_object *hws_obj; 659 660 struct drm_i915_gem_object *pwrctx; 661 struct drm_i915_gem_object *renderctx; 662 663 unsigned int cpp; 664 int back_offset; 665 int front_offset; 666 int current_page; 667 int page_flipping; 668 669 atomic_t irq_received; 670 u32 trace_irq_seqno; 671 672 /** Cached value of IER to avoid reads in updating the bitfield */ 673 u32 pipestat[2]; 674 u32 irq_mask; 675 u32 gt_irq_mask; 676 u32 pch_irq_mask; 677 struct lock irq_lock; 678 679 u32 hotplug_supported_mask; 680 681 int tex_lru_log_granularity; 682 int allow_batchbuffer; 683 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 684 int vblank_pipe; 685 686 int num_pipe; 687 int num_pch_pll; 688 689 /* For hangcheck timer */ 690 #define DRM_I915_HANGCHECK_PERIOD ((1500 /* in ms */ * hz) / 1000) 691 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) 692 struct timer_list hangcheck_timer; 693 int hangcheck_count; 694 uint32_t last_acthd[I915_NUM_RINGS]; 695 uint32_t prev_instdone[I915_NUM_INSTDONE_REG]; 696 697 uint32_t last_acthd_bsd; 698 uint32_t last_acthd_blt; 699 uint32_t last_instdone; 700 uint32_t last_instdone1; 701 702 unsigned int stop_rings; 703 704 struct intel_opregion opregion; 705 706 /* overlay */ 707 struct intel_overlay *overlay; 708 bool sprite_scaling_enabled; 709 710 /* LVDS info */ 711 int backlight_level; /* restore backlight to this value */ 712 bool backlight_enabled; 713 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ 714 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ 715 716 /* Feature bits from the VBIOS */ 717 unsigned int int_tv_support:1; 718 unsigned int lvds_dither:1; 719 unsigned int lvds_vbt:1; 720 unsigned int int_crt_support:1; 721 unsigned int lvds_use_ssc:1; 722 unsigned int display_clock_mode:1; 723 unsigned int fdi_rx_polarity_inverted:1; 724 int lvds_ssc_freq; 725 struct { 726 int rate; 727 int lanes; 728 int preemphasis; 729 int vswing; 730 731 bool initialized; 732 bool support; 733 int bpp; 734 struct edp_power_seq pps; 735 } edp; 736 bool no_aux_handshake; 737 738 int crt_ddc_pin; 739 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ 740 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ 741 int num_fence_regs; /* 8 on pre-965, 16 otherwise */ 742 743 unsigned int fsb_freq, mem_freq, is_ddr3; 744 745 /* Display functions */ 746 struct drm_i915_display_funcs display; 747 748 /* PCH chipset type */ 749 enum intel_pch pch_type; 750 unsigned short pch_id; 751 752 unsigned long quirks; 753 754 /* Register state */ 755 bool modeset_on_lid; 756 757 struct { 758 /** Bridge to intel-gtt-ko */ 759 const struct intel_gtt *gtt; 760 /** Memory allocator for GTT stolen memory */ 761 struct drm_mm stolen; 762 /** Memory allocator for GTT */ 763 struct drm_mm gtt_space; 764 /** List of all objects in gtt_space. Used to restore gtt 765 * mappings on resume */ 766 struct list_head gtt_list; 767 768 /** Usable portion of the GTT for GEM */ 769 unsigned long gtt_start; 770 unsigned long gtt_mappable_end; 771 unsigned long gtt_end; 772 773 /** PPGTT used for aliasing the PPGTT with the GTT */ 774 struct i915_hw_ppgtt *aliasing_ppgtt; 775 776 /** 777 * List of objects currently involved in rendering from the 778 * ringbuffer. 779 * 780 * Includes buffers having the contents of their GPU caches 781 * flushed, not necessarily primitives. last_rendering_seqno 782 * represents when the rendering involved will be completed. 783 * 784 * A reference is held on the buffer while on this list. 785 */ 786 struct list_head active_list; 787 788 /** 789 * List of objects which are not in the ringbuffer but which 790 * still have a write_domain which needs to be flushed before 791 * unbinding. 792 * 793 * A reference is held on the buffer while on this list. 794 */ 795 struct list_head flushing_list; 796 797 /** 798 * LRU list of objects which are not in the ringbuffer and 799 * are ready to unbind, but are still in the GTT. 800 * 801 * last_rendering_seqno is 0 while an object is in this list. 802 * 803 * A reference is not held on the buffer while on this list, 804 * as merely being GTT-bound shouldn't prevent its being 805 * freed, and we'll pull it off the list in the free path. 806 */ 807 struct list_head inactive_list; 808 809 /** 810 * LRU list of objects which are not in the ringbuffer but 811 * are still pinned in the GTT. 812 */ 813 struct list_head pinned_list; 814 815 /** LRU list of objects with fence regs on them. */ 816 struct list_head fence_list; 817 818 /** 819 * List of objects currently pending being freed. 820 * 821 * These objects are no longer in use, but due to a signal 822 * we were prevented from freeing them at the appointed time. 823 */ 824 struct list_head deferred_free_list; 825 826 /** 827 * We leave the user IRQ off as much as possible, 828 * but this means that requests will finish and never 829 * be retired once the system goes idle. Set a timer to 830 * fire periodically while the ring is running. When it 831 * fires, go retire requests. 832 */ 833 struct delayed_work retire_work; 834 835 /** 836 * Are we in a non-interruptible section of code like 837 * modesetting? 838 */ 839 bool interruptible; 840 841 uint32_t next_gem_seqno; 842 843 /** 844 * Waiting sequence number, if any 845 */ 846 uint32_t waiting_gem_seqno; 847 848 /** 849 * Last seq seen at irq time 850 */ 851 uint32_t irq_gem_seqno; 852 853 /** 854 * Flag if the X Server, and thus DRM, is not currently in 855 * control of the device. 856 * 857 * This is set between LeaveVT and EnterVT. It needs to be 858 * replaced with a semaphore. It also needs to be 859 * transitioned away from for kernel modesetting. 860 */ 861 int suspended; 862 863 /** 864 * Flag if the hardware appears to be wedged. 865 * 866 * This is set when attempts to idle the device timeout. 867 * It prevents command submission from occuring and makes 868 * every pending request fail 869 */ 870 atomic_t wedged; 871 872 /** Bit 6 swizzling required for X tiling */ 873 uint32_t bit_6_swizzle_x; 874 /** Bit 6 swizzling required for Y tiling */ 875 uint32_t bit_6_swizzle_y; 876 877 /* storage for physical objects */ 878 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 879 880 /* accounting, useful for userland debugging */ 881 size_t gtt_total; 882 size_t mappable_gtt_total; 883 size_t object_memory; 884 u32 object_count; 885 886 eventhandler_tag i915_lowmem; 887 } mm; 888 889 /* Kernel Modesetting */ 890 891 const struct intel_device_info *info; 892 893 struct sdvo_device_mapping sdvo_mappings[2]; 894 /* indicate whether the LVDS_BORDER should be enabled or not */ 895 unsigned int lvds_border_bits; 896 /* Panel fitter placement and size for Ironlake+ */ 897 u32 pch_pf_pos, pch_pf_size; 898 899 struct drm_crtc *plane_to_crtc_mapping[3]; 900 struct drm_crtc *pipe_to_crtc_mapping[3]; 901 /* wait_queue_head_t pending_flip_queue; XXXKIB */ 902 bool flip_pending_is_done; 903 904 struct intel_pch_pll pch_plls[I915_NUM_PLLS]; 905 struct intel_ddi_plls ddi_plls; 906 907 /* Reclocking support */ 908 bool render_reclock_avail; 909 bool lvds_downclock_avail; 910 /* indicates the reduced downclock for LVDS*/ 911 int lvds_downclock; 912 struct task idle_task; 913 struct callout idle_callout; 914 bool busy; 915 u16 orig_clock; 916 int child_dev_num; 917 struct child_device_config *child_dev; 918 struct drm_connector *int_lvds_connector; 919 struct drm_connector *int_edp_connector; 920 921 device_t bridge_dev; 922 bool mchbar_need_disable; 923 924 struct intel_l3_parity l3_parity; 925 926 int mch_res_rid; 927 928 /* gen6+ rps state */ 929 struct intel_gen6_power_mgmt rps; 930 931 /* ilk-only ips/rps state. Everything in here is protected by the global 932 * mchdev_lock in intel_pm.c */ 933 struct intel_ilk_power_mgmt ips; 934 935 enum no_fbc_reason no_fbc_reason; 936 937 struct lock *mchdev_lock; 938 939 unsigned long cfb_size; 940 unsigned int cfb_fb; 941 int cfb_plane; 942 int cfb_y; 943 struct intel_fbc_work *fbc_work; 944 945 struct lock error_lock; 946 /* Protected by dev->error_lock. */ 947 struct drm_i915_error_state *first_error; 948 struct work_struct error_work; 949 int error_completion; 950 struct lock error_completion_lock; 951 struct workqueue_struct *wq; 952 struct work_struct hotplug_work; 953 954 unsigned long last_gpu_reset; 955 956 struct intel_fbdev *fbdev; 957 958 struct drm_property *broadcast_rgb_property; 959 struct drm_property *force_audio_property; 960 961 struct i915_suspend_saved_registers regfile; 962 963 /* Old dri1 support infrastructure, beware the dragons ya fools entering 964 * here! */ 965 struct i915_dri1_state dri1; 966 } drm_i915_private_t; 967 968 /* Iterate over initialised rings */ 969 #define for_each_ring(ring__, dev_priv__, i__) \ 970 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ 971 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) 972 973 enum hdmi_force_audio { 974 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ 975 HDMI_AUDIO_OFF, /* force turn off HDMI audio */ 976 HDMI_AUDIO_AUTO, /* trust EDID */ 977 HDMI_AUDIO_ON, /* force turn on HDMI audio */ 978 }; 979 980 enum i915_cache_level { 981 I915_CACHE_NONE, 982 I915_CACHE_LLC, 983 I915_CACHE_LLC_MLC, /* gen6+ */ 984 }; 985 986 enum intel_chip_family { 987 CHIP_I8XX = 0x01, 988 CHIP_I9XX = 0x02, 989 CHIP_I915 = 0x04, 990 CHIP_I965 = 0x08, 991 }; 992 993 /** driver private structure attached to each drm_gem_object */ 994 struct drm_i915_gem_object { 995 struct drm_gem_object base; 996 997 /** Current space allocated to this object in the GTT, if any. */ 998 struct drm_mm_node *gtt_space; 999 struct list_head gtt_list; 1000 /** This object's place on the active/flushing/inactive lists */ 1001 struct list_head ring_list; 1002 struct list_head mm_list; 1003 /** This object's place on GPU write list */ 1004 struct list_head gpu_write_list; 1005 /** This object's place in the batchbuffer or on the eviction list */ 1006 struct list_head exec_list; 1007 1008 /** 1009 * This is set if the object is on the active or flushing lists 1010 * (has pending rendering), and is not set if it's on inactive (ready 1011 * to be unbound). 1012 */ 1013 unsigned int active:1; 1014 1015 /** 1016 * This is set if the object has been written to since last bound 1017 * to the GTT 1018 */ 1019 unsigned int dirty:1; 1020 1021 /** 1022 * This is set if the object has been written to since the last 1023 * GPU flush. 1024 */ 1025 unsigned int pending_gpu_write:1; 1026 1027 /** 1028 * Fence register bits (if any) for this object. Will be set 1029 * as needed when mapped into the GTT. 1030 * Protected by dev->struct_mutex. 1031 */ 1032 signed int fence_reg:I915_MAX_NUM_FENCE_BITS; 1033 1034 /** 1035 * Advice: are the backing pages purgeable? 1036 */ 1037 unsigned int madv:2; 1038 1039 /** 1040 * Current tiling mode for the object. 1041 */ 1042 unsigned int tiling_mode:2; 1043 unsigned int tiling_changed:1; 1044 1045 /** How many users have pinned this object in GTT space. The following 1046 * users can each hold at most one reference: pwrite/pread, pin_ioctl 1047 * (via user_pin_count), execbuffer (objects are not allowed multiple 1048 * times for the same batchbuffer), and the framebuffer code. When 1049 * switching/pageflipping, the framebuffer code has at most two buffers 1050 * pinned per crtc. 1051 * 1052 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 1053 * bits with absolutely no headroom. So use 4 bits. */ 1054 unsigned int pin_count:4; 1055 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf 1056 1057 /** 1058 * Is the object at the current location in the gtt mappable and 1059 * fenceable? Used to avoid costly recalculations. 1060 */ 1061 unsigned int map_and_fenceable:1; 1062 1063 /** 1064 * Whether the current gtt mapping needs to be mappable (and isn't just 1065 * mappable by accident). Track pin and fault separate for a more 1066 * accurate mappable working set. 1067 */ 1068 unsigned int fault_mappable:1; 1069 unsigned int pin_mappable:1; 1070 1071 /* 1072 * Is the GPU currently using a fence to access this buffer, 1073 */ 1074 unsigned int pending_fenced_gpu_access:1; 1075 unsigned int fenced_gpu_access:1; 1076 1077 unsigned int cache_level:2; 1078 1079 unsigned int has_aliasing_ppgtt_mapping:1; 1080 unsigned int has_global_gtt_mapping:1; 1081 1082 vm_page_t *pages; 1083 1084 /** 1085 * Used for performing relocations during execbuffer insertion. 1086 */ 1087 struct hlist_node exec_node; 1088 unsigned long exec_handle; 1089 struct drm_i915_gem_exec_object2 *exec_entry; 1090 1091 /** 1092 * Current offset of the object in GTT space. 1093 * 1094 * This is the same as gtt_space->start 1095 */ 1096 uint32_t gtt_offset; 1097 1098 /** Breadcrumb of last rendering to the buffer. */ 1099 uint32_t last_rendering_seqno; 1100 struct intel_ring_buffer *ring; 1101 1102 /** Breadcrumb of last fenced GPU access to the buffer. */ 1103 uint32_t last_fenced_seqno; 1104 struct intel_ring_buffer *last_fenced_ring; 1105 1106 /** Current tiling stride for the object, if it's tiled. */ 1107 uint32_t stride; 1108 1109 /** Record of address bit 17 of each page at last unbind. */ 1110 unsigned long *bit_17; 1111 1112 /** 1113 * If present, while GEM_DOMAIN_CPU is in the read domain this array 1114 * flags which individual pages are valid. 1115 */ 1116 uint8_t *page_cpu_valid; 1117 1118 /** User space pin count and filp owning the pin */ 1119 uint32_t user_pin_count; 1120 struct drm_file *pin_filp; 1121 1122 /** for phy allocated objects */ 1123 struct drm_i915_gem_phys_object *phys_obj; 1124 1125 /** 1126 * Number of crtcs where this object is currently the fb, but 1127 * will be page flipped away on the next vblank. When it 1128 * reaches 0, dev_priv->pending_flip_queue will be woken up. 1129 */ 1130 atomic_t pending_flip; 1131 }; 1132 1133 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) 1134 1135 /** 1136 * Request queue structure. 1137 * 1138 * The request queue allows us to note sequence numbers that have been emitted 1139 * and may be associated with active buffers to be retired. 1140 * 1141 * By keeping this list, we can avoid having to do questionable 1142 * sequence-number comparisons on buffer last_rendering_seqnos, and associate 1143 * an emission time with seqnos for tracking how far ahead of the GPU we are. 1144 */ 1145 struct drm_i915_gem_request { 1146 /** On Which ring this request was generated */ 1147 struct intel_ring_buffer *ring; 1148 1149 /** GEM sequence number associated with this request. */ 1150 uint32_t seqno; 1151 1152 /** Postion in the ringbuffer of the end of the request */ 1153 u32 tail; 1154 1155 /** Time at which this request was emitted, in jiffies. */ 1156 unsigned long emitted_jiffies; 1157 1158 /** global list entry for this request */ 1159 struct list_head list; 1160 1161 struct drm_i915_file_private *file_priv; 1162 /** file_priv list entry for this request */ 1163 struct list_head client_list; 1164 }; 1165 1166 struct drm_i915_file_private { 1167 struct { 1168 struct spinlock lock; 1169 struct list_head request_list; 1170 } mm; 1171 }; 1172 1173 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) 1174 1175 #define IS_I830(dev) ((dev)->pci_device == 0x3577) 1176 #define IS_845G(dev) ((dev)->pci_device == 0x2562) 1177 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) 1178 #define IS_I865G(dev) ((dev)->pci_device == 0x2572) 1179 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) 1180 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) 1181 #define IS_I945G(dev) ((dev)->pci_device == 0x2772) 1182 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) 1183 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) 1184 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) 1185 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) 1186 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) 1187 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) 1188 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) 1189 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) 1190 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) 1191 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) 1192 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) 1193 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) 1194 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \ 1195 (dev)->pci_device == 0x0152 || \ 1196 (dev)->pci_device == 0x015a) 1197 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \ 1198 (dev)->pci_device == 0x0106 || \ 1199 (dev)->pci_device == 0x010A) 1200 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) 1201 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) 1202 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1203 #define IS_ULT(dev) (IS_HASWELL(dev) && \ 1204 ((dev)->pci_device & 0xFF00) == 0x0A00) 1205 1206 /* 1207 * The genX designation typically refers to the render engine, so render 1208 * capability related checks should use IS_GEN, while display and other checks 1209 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular 1210 * chips, etc.). 1211 */ 1212 1213 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) 1214 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) 1215 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) 1216 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) 1217 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) 1218 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) 1219 1220 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) 1221 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) 1222 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) 1223 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1224 1225 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) 1226 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) 1227 1228 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) 1229 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) 1230 1231 /* Early gen2 have a totally busted CS tlb and require pinned batches. */ 1232 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) 1233 1234 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1235 * rows, which changed the alignment requirements and fence programming. 1236 */ 1237 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ 1238 IS_I915GM(dev))) 1239 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) 1240 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1241 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) 1242 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) 1243 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) 1244 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) 1245 /* dsparb controlled by hw only */ 1246 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) 1247 1248 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) 1249 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) 1250 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) 1251 1252 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) 1253 1254 #define INTEL_PCH_DEVICE_ID_MASK 0xff00 1255 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 1256 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 1257 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 1258 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 1259 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 1260 1261 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) 1262 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) 1263 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) 1264 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) 1265 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) 1266 1267 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) 1268 1269 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) 1270 1271 #define GT_FREQUENCY_MULTIPLIER 50 1272 1273 /** 1274 * RC6 is a special power stage which allows the GPU to enter an very 1275 * low-voltage mode when idle, using down to 0V while at this stage. This 1276 * stage is entered automatically when the GPU is idle when RC6 support is 1277 * enabled, and as soon as new workload arises GPU wakes up automatically as well. 1278 * 1279 * There are different RC6 modes available in Intel GPU, which differentiate 1280 * among each other with the latency required to enter and leave RC6 and 1281 * voltage consumed by the GPU in different states. 1282 * 1283 * The combination of the following flags define which states GPU is allowed 1284 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and 1285 * RC6pp is deepest RC6. Their support by hardware varies according to the 1286 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one 1287 * which brings the most power savings; deeper states save more power, but 1288 * require higher latency to switch to and wake up. 1289 */ 1290 #define INTEL_RC6_ENABLE (1<<0) 1291 #define INTEL_RC6p_ENABLE (1<<1) 1292 #define INTEL_RC6pp_ENABLE (1<<2) 1293 1294 extern int intel_iommu_enabled; 1295 extern struct drm_ioctl_desc i915_ioctls[]; 1296 extern struct drm_driver i915_driver_info; 1297 extern struct cdev_pager_ops i915_gem_pager_ops; 1298 extern int i915_panel_ignore_lid; 1299 extern unsigned int i915_powersave; 1300 extern int i915_semaphores; 1301 extern unsigned int i915_lvds_downclock; 1302 extern int i915_panel_use_ssc; 1303 extern int i915_vbt_sdvo_panel_type; 1304 extern int i915_enable_rc6; 1305 extern int i915_enable_fbc; 1306 extern int i915_enable_ppgtt; 1307 extern int i915_enable_hangcheck; 1308 1309 void i915_sysctl_cleanup(struct drm_device *dev); 1310 1311 /* i915_dma.c */ 1312 void i915_update_dri1_breadcrumb(struct drm_device *dev); 1313 extern void i915_kernel_lost_context(struct drm_device * dev); 1314 extern int i915_driver_load(struct drm_device *, unsigned long flags); 1315 extern int i915_driver_unload(struct drm_device *); 1316 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); 1317 extern void i915_driver_lastclose(struct drm_device * dev); 1318 extern void i915_driver_preclose(struct drm_device *dev, 1319 struct drm_file *file_priv); 1320 extern void i915_driver_postclose(struct drm_device *dev, 1321 struct drm_file *file_priv); 1322 extern int i915_driver_device_is_agp(struct drm_device * dev); 1323 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 1324 unsigned long arg); 1325 extern int i915_emit_box(struct drm_device *dev, 1326 struct drm_clip_rect __user *boxes, 1327 int i, int DR1, int DR4); 1328 int i915_emit_box_p(struct drm_device *dev, struct drm_clip_rect *box, 1329 int DR1, int DR4); 1330 extern int intel_gpu_reset(struct drm_device *dev); 1331 extern int i915_reset(struct drm_device *dev); 1332 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); 1333 unsigned long i915_mch_val(struct drm_i915_private *dev_priv); 1334 void i915_update_gfx_val(struct drm_i915_private *dev_priv); 1335 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); 1336 1337 /* i915_irq.c */ 1338 extern int i915_irq_emit(struct drm_device *dev, void *data, 1339 struct drm_file *file_priv); 1340 extern int i915_irq_wait(struct drm_device *dev, void *data, 1341 struct drm_file *file_priv); 1342 1343 extern void intel_irq_init(struct drm_device *dev); 1344 extern void intel_gt_init(struct drm_device *dev); 1345 extern void intel_gt_reset(struct drm_device *dev); 1346 1347 void intel_enable_asle(struct drm_device *dev); 1348 void i915_hangcheck_elapsed(unsigned long data); 1349 void i915_handle_error(struct drm_device *dev, bool wedged); 1350 1351 void i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1352 void i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); 1353 1354 #ifdef CONFIG_DEBUG_FS 1355 extern void i915_destroy_error_state(struct drm_device *dev); 1356 #else 1357 #define i915_destroy_error_state(x) 1358 #endif 1359 1360 /* i915_gem.c */ 1361 int i915_gem_create(struct drm_file *file, struct drm_device *dev, uint64_t size, 1362 uint32_t *handle_p); 1363 int i915_gem_init_ioctl(struct drm_device *dev, void *data, 1364 struct drm_file *file_priv); 1365 int i915_gem_create_ioctl(struct drm_device *dev, void *data, 1366 struct drm_file *file_priv); 1367 int i915_gem_pread_ioctl(struct drm_device *dev, void *data, 1368 struct drm_file *file_priv); 1369 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, 1370 struct drm_file *file_priv); 1371 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, 1372 struct drm_file *file_priv); 1373 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, 1374 struct drm_file *file_priv); 1375 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, 1376 struct drm_file *file_priv); 1377 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, 1378 struct drm_file *file_priv); 1379 int i915_gem_execbuffer(struct drm_device *dev, void *data, 1380 struct drm_file *file_priv); 1381 int i915_gem_execbuffer2(struct drm_device *dev, void *data, 1382 struct drm_file *file_priv); 1383 int i915_gem_pin_ioctl(struct drm_device *dev, void *data, 1384 struct drm_file *file_priv); 1385 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, 1386 struct drm_file *file_priv); 1387 int i915_gem_busy_ioctl(struct drm_device *dev, void *data, 1388 struct drm_file *file_priv); 1389 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, 1390 struct drm_file *file_priv); 1391 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, 1392 struct drm_file *file_priv); 1393 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, 1394 struct drm_file *file_priv); 1395 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, 1396 struct drm_file *file_priv); 1397 int i915_gem_set_tiling(struct drm_device *dev, void *data, 1398 struct drm_file *file_priv); 1399 int i915_gem_get_tiling(struct drm_device *dev, void *data, 1400 struct drm_file *file_priv); 1401 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 1402 struct drm_file *file_priv); 1403 void i915_gem_load(struct drm_device *dev); 1404 void i915_gem_unload(struct drm_device *dev); 1405 int i915_gem_init_object(struct drm_gem_object *obj); 1406 void i915_gem_free_object(struct drm_gem_object *obj); 1407 int i915_gem_object_pin(struct drm_i915_gem_object *obj, uint32_t alignment, 1408 bool map_and_fenceable); 1409 void i915_gem_object_unpin(struct drm_i915_gem_object *obj); 1410 int i915_gem_object_unbind(struct drm_i915_gem_object *obj); 1411 void i915_gem_lastclose(struct drm_device *dev); 1412 uint32_t i915_get_gem_seqno(struct drm_device *dev); 1413 1414 static inline void 1415 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) 1416 { 1417 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1418 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1419 dev_priv->fence_regs[obj->fence_reg].pin_count++; 1420 } 1421 } 1422 1423 static inline void 1424 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) 1425 { 1426 if (obj->fence_reg != I915_FENCE_REG_NONE) { 1427 struct drm_i915_private *dev_priv = obj->base.dev->dev_private; 1428 dev_priv->fence_regs[obj->fence_reg].pin_count--; 1429 } 1430 } 1431 1432 void i915_gem_retire_requests(struct drm_device *dev); 1433 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); 1434 void i915_gem_clflush_object(struct drm_i915_gem_object *obj); 1435 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, 1436 size_t size); 1437 int i915_gem_do_init(struct drm_device *dev, unsigned long start, 1438 unsigned long mappable_end, unsigned long end); 1439 uint32_t i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, 1440 uint32_t size, int tiling_mode); 1441 int i915_mutex_lock_interruptible(struct drm_device *dev); 1442 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, 1443 bool write); 1444 int __must_check 1445 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); 1446 int __must_check 1447 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, 1448 u32 alignment, 1449 struct intel_ring_buffer *pipelined); 1450 int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); 1451 int i915_gem_flush_ring(struct intel_ring_buffer *ring, 1452 uint32_t invalidate_domains, uint32_t flush_domains); 1453 void i915_gem_release_mmap(struct drm_i915_gem_object *obj); 1454 int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); 1455 int i915_gem_object_put_fence(struct drm_i915_gem_object *obj); 1456 int i915_gem_idle(struct drm_device *dev); 1457 int i915_gem_init_hw(struct drm_device *dev); 1458 void i915_gem_init_swizzling(struct drm_device *dev); 1459 void i915_gem_init_ppgtt(struct drm_device *dev); 1460 void i915_gem_cleanup_ringbuffer(struct drm_device *dev); 1461 int __must_check i915_gpu_idle(struct drm_device *dev); 1462 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, 1463 struct intel_ring_buffer *ring, uint32_t seqno); 1464 int i915_add_request(struct intel_ring_buffer *ring, struct drm_file *file, 1465 struct drm_i915_gem_request *request); 1466 int i915_wait_seqno(struct intel_ring_buffer *ring, 1467 uint32_t seqno); 1468 int i915_gem_object_get_fence(struct drm_i915_gem_object *obj, 1469 struct intel_ring_buffer *pipelined); 1470 void i915_gem_reset(struct drm_device *dev); 1471 int i915_gem_mmap(struct drm_device *dev, uint64_t offset, int prot); 1472 int i915_gem_fault(struct drm_device *dev, uint64_t offset, int prot, 1473 uint64_t *phys); 1474 void i915_gem_release(struct drm_device *dev, struct drm_file *file); 1475 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, 1476 enum i915_cache_level cache_level); 1477 1478 void i915_gem_free_all_phys_object(struct drm_device *dev); 1479 void i915_gem_detach_phys_object(struct drm_device *dev, 1480 struct drm_i915_gem_object *obj); 1481 int i915_gem_attach_phys_object(struct drm_device *dev, 1482 struct drm_i915_gem_object *obj, int id, int align); 1483 1484 int i915_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, 1485 struct drm_mode_create_dumb *args); 1486 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, 1487 uint32_t handle, uint64_t *offset); 1488 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, 1489 uint32_t handle); 1490 1491 /* i915_gem_tiling.c */ 1492 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); 1493 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); 1494 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); 1495 1496 /* i915_gem_evict.c */ 1497 int i915_gem_evict_something(struct drm_device *dev, int min_size, 1498 unsigned alignment, bool mappable); 1499 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only); 1500 int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only); 1501 1502 /* i915_suspend.c */ 1503 extern int i915_save_state(struct drm_device *dev); 1504 extern int i915_restore_state(struct drm_device *dev); 1505 1506 /* intel_iic.c */ 1507 extern int intel_setup_gmbus(struct drm_device *dev); 1508 extern void intel_teardown_gmbus(struct drm_device *dev); 1509 extern void intel_gmbus_set_speed(device_t idev, int speed); 1510 extern void intel_gmbus_force_bit(device_t idev, bool force_bit); 1511 extern void intel_iic_reset(struct drm_device *dev); 1512 1513 /* i915_gem_context.c */ 1514 void i915_gem_context_init(struct drm_device *dev); 1515 1516 /* i915_gem_gtt.c */ 1517 int i915_gem_init_aliasing_ppgtt(struct drm_device *dev); 1518 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); 1519 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, 1520 struct drm_i915_gem_object *obj, enum i915_cache_level cache_level); 1521 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, 1522 struct drm_i915_gem_object *obj); 1523 1524 void i915_gem_restore_gtt_mappings(struct drm_device *dev); 1525 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, 1526 enum i915_cache_level cache_level); 1527 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); 1528 1529 /* intel_opregion.c */ 1530 extern int intel_opregion_setup(struct drm_device *dev); 1531 #ifdef CONFIG_ACPI 1532 extern void intel_opregion_init(struct drm_device *dev); 1533 extern void intel_opregion_fini(struct drm_device *dev); 1534 extern void intel_opregion_asle_intr(struct drm_device *dev); 1535 extern void intel_opregion_gse_intr(struct drm_device *dev); 1536 extern void intel_opregion_enable_asle(struct drm_device *dev); 1537 #else 1538 static inline void intel_opregion_init(struct drm_device *dev) { return; } 1539 static inline void intel_opregion_fini(struct drm_device *dev) { return; } 1540 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } 1541 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } 1542 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } 1543 #endif 1544 1545 /* modesetting */ 1546 extern void intel_modeset_init_hw(struct drm_device *dev); 1547 extern void intel_modeset_init(struct drm_device *dev); 1548 extern void intel_modeset_gem_init(struct drm_device *dev); 1549 extern void intel_modeset_cleanup(struct drm_device *dev); 1550 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); 1551 extern void intel_disable_fbc(struct drm_device *dev); 1552 extern bool ironlake_set_drps(struct drm_device *dev, u8 val); 1553 extern void ironlake_init_pch_refclk(struct drm_device *dev); 1554 extern void ironlake_enable_rc6(struct drm_device *dev); 1555 extern void gen6_set_rps(struct drm_device *dev, u8 val); 1556 extern void intel_detect_pch(struct drm_device *dev); 1557 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); 1558 extern int intel_enable_rc6(const struct drm_device *dev); 1559 1560 extern struct intel_overlay_error_state *intel_overlay_capture_error_state( 1561 struct drm_device *dev); 1562 extern void intel_overlay_print_error_state(struct sbuf *m, 1563 struct intel_overlay_error_state *error); 1564 extern struct intel_display_error_state *intel_display_capture_error_state( 1565 struct drm_device *dev); 1566 extern void intel_display_print_error_state(struct sbuf *m, 1567 struct drm_device *dev, struct intel_display_error_state *error); 1568 1569 static inline void 1570 trace_i915_reg_rw(boolean_t rw, int reg, uint64_t val, int sz) 1571 { 1572 return; 1573 } 1574 1575 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) 1576 1577 #define BEGIN_LP_RING(n) \ 1578 intel_ring_begin(LP_RING(dev_priv), (n)) 1579 1580 #define OUT_RING(x) \ 1581 intel_ring_emit(LP_RING(dev_priv), x) 1582 1583 #define ADVANCE_LP_RING() \ 1584 intel_ring_advance(LP_RING(dev_priv)) 1585 1586 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ 1587 if (LP_RING(dev->dev_private)->obj == NULL) \ 1588 LOCK_TEST_WITH_RETURN(dev, file); \ 1589 } while (0) 1590 1591 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 1592 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) 1593 #define I915_GEM_HWS_INDEX 0x20 1594 #define I915_BREADCRUMB_INDEX 0x21 1595 1596 const struct intel_device_info *i915_get_device_id(int device); 1597 1598 /* i915_debug.c */ 1599 int i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx, 1600 struct sysctl_oid *top); 1601 1602 static inline bool 1603 i915_seqno_passed(uint32_t seq1, uint32_t seq2) 1604 { 1605 1606 return ((int32_t)(seq1 - seq2) >= 0); 1607 } 1608 1609 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring); 1610 1611 /* On SNB platform, before reading ring registers forcewake bit 1612 * must be set to prevent GT core from power down and stale values being 1613 * returned. 1614 */ 1615 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 1616 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 1617 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); 1618 1619 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 1620 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 1621 1622 #define __i915_read(x, y) \ 1623 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); 1624 1625 __i915_read(8, 8) 1626 __i915_read(16, 16) 1627 __i915_read(32, 32) 1628 __i915_read(64, 64) 1629 #undef __i915_read 1630 1631 #define __i915_write(x, y) \ 1632 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); 1633 1634 __i915_write(8, 8) 1635 __i915_write(16, 16) 1636 __i915_write(32, 32) 1637 __i915_write(64, 64) 1638 #undef __i915_write 1639 1640 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) 1641 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) 1642 1643 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) 1644 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) 1645 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 1646 #define I915_WRITE16_NOTRACE(reg, val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 1647 1648 #define I915_READ(reg) i915_read32(dev_priv, (reg)) 1649 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) 1650 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 1651 #define I915_WRITE_NOTRACE(reg, val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 1652 1653 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) 1654 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) 1655 1656 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) 1657 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) 1658 1659 1660 #endif 1661