1 /* 2 * Copyright © 2006 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 * 26 * Minor modifications (Dithering enable): 27 * Thomas Richter <thor@math.tu-berlin.de> 28 * 29 */ 30 31 #include "dvo.h" 32 33 /* 34 * register definitions for the i82807aa. 35 * 36 * Documentation on this chipset can be found in datasheet #29069001 at 37 * intel.com. 38 */ 39 40 /* 41 * VCH Revision & GMBus Base Addr 42 */ 43 #define VR00 0x00 44 # define VR00_BASE_ADDRESS_MASK 0x007f 45 46 /* 47 * Functionality Enable 48 */ 49 #define VR01 0x01 50 51 /* 52 * Enable the panel fitter 53 */ 54 # define VR01_PANEL_FIT_ENABLE (1 << 3) 55 /* 56 * Enables the LCD display. 57 * 58 * This must not be set while VR01_DVO_BYPASS_ENABLE is set. 59 */ 60 # define VR01_LCD_ENABLE (1 << 2) 61 /** Enables the DVO repeater. */ 62 # define VR01_DVO_BYPASS_ENABLE (1 << 1) 63 /** Enables the DVO clock */ 64 # define VR01_DVO_ENABLE (1 << 0) 65 /** Enable dithering for 18bpp panels. Not documented. */ 66 # define VR01_DITHER_ENABLE (1 << 4) 67 68 /* 69 * LCD Interface Format 70 */ 71 #define VR10 0x10 72 /** Enables LVDS output instead of CMOS */ 73 # define VR10_LVDS_ENABLE (1 << 4) 74 /** Enables 18-bit LVDS output. */ 75 # define VR10_INTERFACE_1X18 (0 << 2) 76 /** Enables 24-bit LVDS or CMOS output */ 77 # define VR10_INTERFACE_1X24 (1 << 2) 78 /** Enables 2x18-bit LVDS or CMOS output. */ 79 # define VR10_INTERFACE_2X18 (2 << 2) 80 /** Enables 2x24-bit LVDS output */ 81 # define VR10_INTERFACE_2X24 (3 << 2) 82 /** Mask that defines the depth of the pipeline */ 83 # define VR10_INTERFACE_DEPTH_MASK (3 << 2) 84 85 /* 86 * VR20 LCD Horizontal Display Size 87 */ 88 #define VR20 0x20 89 90 /* 91 * LCD Vertical Display Size 92 */ 93 #define VR21 0x20 94 95 /* 96 * Panel power down status 97 */ 98 #define VR30 0x30 99 /** Read only bit indicating that the panel is not in a safe poweroff state. */ 100 # define VR30_PANEL_ON (1 << 15) 101 102 #define VR40 0x40 103 # define VR40_STALL_ENABLE (1 << 13) 104 # define VR40_VERTICAL_INTERP_ENABLE (1 << 12) 105 # define VR40_ENHANCED_PANEL_FITTING (1 << 11) 106 # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10) 107 # define VR40_AUTO_RATIO_ENABLE (1 << 9) 108 # define VR40_CLOCK_GATING_ENABLE (1 << 8) 109 110 /* 111 * Panel Fitting Vertical Ratio 112 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2 113 */ 114 #define VR41 0x41 115 116 /* 117 * Panel Fitting Horizontal Ratio 118 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2 119 */ 120 #define VR42 0x42 121 122 /* 123 * Horizontal Image Size 124 */ 125 #define VR43 0x43 126 127 /* VR80 GPIO 0 128 */ 129 #define VR80 0x80 130 #define VR81 0x81 131 #define VR82 0x82 132 #define VR83 0x83 133 #define VR84 0x84 134 #define VR85 0x85 135 #define VR86 0x86 136 #define VR87 0x87 137 138 /* VR88 GPIO 8 139 */ 140 #define VR88 0x88 141 142 /* Graphics BIOS scratch 0 143 */ 144 #define VR8E 0x8E 145 # define VR8E_PANEL_TYPE_MASK (0xf << 0) 146 # define VR8E_PANEL_INTERFACE_CMOS (0 << 4) 147 # define VR8E_PANEL_INTERFACE_LVDS (1 << 4) 148 # define VR8E_FORCE_DEFAULT_PANEL (1 << 5) 149 150 /* Graphics BIOS scratch 1 151 */ 152 #define VR8F 0x8F 153 # define VR8F_VCH_PRESENT (1 << 0) 154 # define VR8F_DISPLAY_CONN (1 << 1) 155 # define VR8F_POWER_MASK (0x3c) 156 # define VR8F_POWER_POS (2) 157 158 159 struct ivch_priv { 160 bool quiet; 161 162 uint16_t width, height; 163 }; 164 165 166 static void ivch_dump_regs(struct intel_dvo_device *dvo); 167 168 /** 169 * Reads a register on the ivch. 170 * 171 * Each of the 256 registers are 16 bits long. 172 */ 173 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data) 174 { 175 struct intel_iic_softc *sc; 176 struct ivch_priv *priv = dvo->dev_priv; 177 struct i2c_adapter *adapter = dvo->i2c_bus; 178 u8 out_buf[1]; 179 u8 in_buf[2]; 180 181 struct i2c_msg msgs[] = { 182 { 183 .slave = dvo->slave_addr << 1, 184 .flags = I2C_M_RD, 185 .len = 0, 186 }, 187 { 188 .slave = 0 << 1, 189 .flags = I2C_M_NOSTART, 190 .len = 1, 191 .buf = out_buf, 192 }, 193 { 194 .slave = dvo->slave_addr << 1, 195 .flags = I2C_M_RD | I2C_M_NOSTART, 196 .len = 2, 197 .buf = in_buf, 198 } 199 }; 200 201 out_buf[0] = addr; 202 203 sc = device_get_softc(adapter); 204 205 if (iicbus_transfer(adapter, msgs, 3) == 0) { 206 *data = (in_buf[1] << 8) | in_buf[0]; 207 return true; 208 } 209 210 if (!priv->quiet) { 211 DRM_DEBUG_KMS("Unable to read register 0x%02x from " 212 "%s:%02x.\n", 213 addr, sc->name, dvo->slave_addr); 214 } 215 return false; 216 } 217 218 /** Writes a 16-bit register on the ivch */ 219 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data) 220 { 221 struct intel_iic_softc *sc; 222 struct ivch_priv *priv = dvo->dev_priv; 223 struct i2c_adapter *adapter = dvo->i2c_bus; 224 u8 out_buf[3]; 225 struct i2c_msg msg = { 226 .slave = dvo->slave_addr << 1, 227 .flags = 0, 228 .len = 3, 229 .buf = out_buf, 230 }; 231 232 out_buf[0] = addr; 233 out_buf[1] = data & 0xff; 234 out_buf[2] = data >> 8; 235 236 sc = device_get_softc(adapter); 237 238 if (iicbus_transfer(adapter, &msg, 1) == 0) 239 return true; 240 241 if (!priv->quiet) { 242 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n", 243 addr, sc->name, dvo->slave_addr); 244 } 245 246 return false; 247 } 248 249 /** Probes the given bus and slave address for an ivch */ 250 static bool ivch_init(struct intel_dvo_device *dvo, 251 struct i2c_adapter *adapter) 252 { 253 struct ivch_priv *priv; 254 uint16_t temp; 255 256 priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL); 257 if (priv == NULL) 258 return false; 259 260 dvo->i2c_bus = adapter; 261 dvo->dev_priv = priv; 262 priv->quiet = true; 263 264 if (!ivch_read(dvo, VR00, &temp)) 265 goto out; 266 priv->quiet = false; 267 268 /* Since the identification bits are probably zeroes, which doesn't seem 269 * very unique, check that the value in the base address field matches 270 * the address it's responding on. 271 */ 272 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) { 273 DRM_DEBUG_KMS("ivch detect failed due to address mismatch " 274 "(%d vs %d)\n", 275 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr); 276 goto out; 277 } 278 279 ivch_read(dvo, VR20, &priv->width); 280 ivch_read(dvo, VR21, &priv->height); 281 282 return true; 283 284 out: 285 kfree(priv); 286 return false; 287 } 288 289 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo) 290 { 291 return connector_status_connected; 292 } 293 294 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo, 295 struct drm_display_mode *mode) 296 { 297 if (mode->clock > 112000) 298 return MODE_CLOCK_HIGH; 299 300 return MODE_OK; 301 } 302 303 /** Sets the power state of the panel connected to the ivch */ 304 static void ivch_dpms(struct intel_dvo_device *dvo, bool enable) 305 { 306 int i; 307 uint16_t vr01, vr30, backlight; 308 309 /* Set the new power state of the panel. */ 310 if (!ivch_read(dvo, VR01, &vr01)) 311 return; 312 313 if (enable) 314 backlight = 1; 315 else 316 backlight = 0; 317 ivch_write(dvo, VR80, backlight); 318 319 if (enable) 320 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE; 321 else 322 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE); 323 324 ivch_write(dvo, VR01, vr01); 325 326 /* Wait for the panel to make its state transition */ 327 for (i = 0; i < 100; i++) { 328 if (!ivch_read(dvo, VR30, &vr30)) 329 break; 330 331 if (((vr30 & VR30_PANEL_ON) != 0) == enable) 332 break; 333 udelay(1000); 334 } 335 /* wait some more; vch may fail to resync sometimes without this */ 336 udelay(16 * 1000); 337 } 338 339 static bool ivch_get_hw_state(struct intel_dvo_device *dvo) 340 { 341 uint16_t vr01; 342 343 /* Set the new power state of the panel. */ 344 if (!ivch_read(dvo, VR01, &vr01)) 345 return false; 346 347 if (vr01 & VR01_LCD_ENABLE) 348 return true; 349 else 350 return false; 351 } 352 353 static void ivch_mode_set(struct intel_dvo_device *dvo, 354 struct drm_display_mode *mode, 355 struct drm_display_mode *adjusted_mode) 356 { 357 uint16_t vr40 = 0; 358 uint16_t vr01 = 0; 359 uint16_t vr10; 360 361 ivch_read(dvo, VR10, &vr10); 362 /* Enable dithering for 18 bpp pipelines */ 363 vr10 &= VR10_INTERFACE_DEPTH_MASK; 364 if (vr10 == VR10_INTERFACE_2X18 || vr10 == VR10_INTERFACE_1X18) 365 vr01 = VR01_DITHER_ENABLE; 366 367 vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE | 368 VR40_HORIZONTAL_INTERP_ENABLE); 369 370 if (mode->hdisplay != adjusted_mode->hdisplay || 371 mode->vdisplay != adjusted_mode->vdisplay) { 372 uint16_t x_ratio, y_ratio; 373 374 vr01 |= VR01_PANEL_FIT_ENABLE; 375 vr40 |= VR40_CLOCK_GATING_ENABLE | VR40_ENHANCED_PANEL_FITTING; 376 x_ratio = (((mode->hdisplay - 1) << 16) / 377 (adjusted_mode->hdisplay - 1)) >> 2; 378 y_ratio = (((mode->vdisplay - 1) << 16) / 379 (adjusted_mode->vdisplay - 1)) >> 2; 380 ivch_write(dvo, VR42, x_ratio); 381 ivch_write(dvo, VR41, y_ratio); 382 } else { 383 vr01 &= ~VR01_PANEL_FIT_ENABLE; 384 vr40 &= ~VR40_CLOCK_GATING_ENABLE; 385 } 386 vr40 &= ~VR40_AUTO_RATIO_ENABLE; 387 388 ivch_write(dvo, VR01, vr01); 389 ivch_write(dvo, VR40, vr40); 390 391 ivch_dump_regs(dvo); 392 } 393 394 static void ivch_dump_regs(struct intel_dvo_device *dvo) 395 { 396 uint16_t val; 397 398 ivch_read(dvo, VR00, &val); 399 DRM_DEBUG_KMS("VR00: 0x%04x\n", val); 400 ivch_read(dvo, VR01, &val); 401 DRM_DEBUG_KMS("VR01: 0x%04x\n", val); 402 ivch_read(dvo, VR10, &val); 403 DRM_DEBUG_KMS("VR10: 0x%04x\n", val); 404 ivch_read(dvo, VR30, &val); 405 DRM_DEBUG_KMS("VR30: 0x%04x\n", val); 406 ivch_read(dvo, VR40, &val); 407 DRM_DEBUG_KMS("VR40: 0x%04x\n", val); 408 409 /* GPIO registers */ 410 ivch_read(dvo, VR80, &val); 411 DRM_DEBUG_KMS("VR80: 0x%04x\n", val); 412 ivch_read(dvo, VR81, &val); 413 DRM_DEBUG_KMS("VR81: 0x%04x\n", val); 414 ivch_read(dvo, VR82, &val); 415 DRM_DEBUG_KMS("VR82: 0x%04x\n", val); 416 ivch_read(dvo, VR83, &val); 417 DRM_DEBUG_KMS("VR83: 0x%04x\n", val); 418 ivch_read(dvo, VR84, &val); 419 DRM_DEBUG_KMS("VR84: 0x%04x\n", val); 420 ivch_read(dvo, VR85, &val); 421 DRM_DEBUG_KMS("VR85: 0x%04x\n", val); 422 ivch_read(dvo, VR86, &val); 423 DRM_DEBUG_KMS("VR86: 0x%04x\n", val); 424 ivch_read(dvo, VR87, &val); 425 DRM_DEBUG_KMS("VR87: 0x%04x\n", val); 426 ivch_read(dvo, VR88, &val); 427 DRM_DEBUG_KMS("VR88: 0x%04x\n", val); 428 429 /* Scratch register 0 - AIM Panel type */ 430 ivch_read(dvo, VR8E, &val); 431 DRM_DEBUG_KMS("VR8E: 0x%04x\n", val); 432 433 /* Scratch register 1 - Status register */ 434 ivch_read(dvo, VR8F, &val); 435 DRM_DEBUG_KMS("VR8F: 0x%04x\n", val); 436 } 437 438 static void ivch_destroy(struct intel_dvo_device *dvo) 439 { 440 struct ivch_priv *priv = dvo->dev_priv; 441 442 if (priv) { 443 kfree(priv); 444 dvo->dev_priv = NULL; 445 } 446 } 447 448 struct intel_dvo_dev_ops ivch_ops = { 449 .init = ivch_init, 450 .dpms = ivch_dpms, 451 .get_hw_state = ivch_get_hw_state, 452 .mode_valid = ivch_mode_valid, 453 .mode_set = ivch_mode_set, 454 .detect = ivch_detect, 455 .dump_regs = ivch_dump_regs, 456 .destroy = ivch_destroy, 457 }; 458