xref: /dflybsd-src/sys/dev/drm/amd/powerplay/inc/smu8_fusion.h (revision b843c749addef9340ee7d4e250b09fdd492602a1)
1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev  * Copyright 2014 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev  *
4*b843c749SSergey Zigachev  * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev  * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev  * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev  * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev  * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev  *
11*b843c749SSergey Zigachev  * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev  * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev  *
14*b843c749SSergey Zigachev  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*b843c749SSergey Zigachev  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev  * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev  *
22*b843c749SSergey Zigachev  */
23*b843c749SSergey Zigachev 
24*b843c749SSergey Zigachev #ifndef SMU8_FUSION_H
25*b843c749SSergey Zigachev #define SMU8_FUSION_H
26*b843c749SSergey Zigachev 
27*b843c749SSergey Zigachev #include "smu8.h"
28*b843c749SSergey Zigachev 
29*b843c749SSergey Zigachev #pragma pack(push, 1)
30*b843c749SSergey Zigachev 
31*b843c749SSergey Zigachev #define SMU8_MAX_CUS 2
32*b843c749SSergey Zigachev #define SMU8_PSMS_PER_CU 4
33*b843c749SSergey Zigachev #define SMU8_CACS_PER_CU 4
34*b843c749SSergey Zigachev 
35*b843c749SSergey Zigachev struct SMU8_GfxCuPgScoreboard {
36*b843c749SSergey Zigachev     uint8_t Enabled;
37*b843c749SSergey Zigachev     uint8_t spare[3];
38*b843c749SSergey Zigachev };
39*b843c749SSergey Zigachev 
40*b843c749SSergey Zigachev struct SMU8_Port80MonitorTable {
41*b843c749SSergey Zigachev 	uint32_t MmioAddress;
42*b843c749SSergey Zigachev 	uint32_t MemoryBaseHi;
43*b843c749SSergey Zigachev 	uint32_t MemoryBaseLo;
44*b843c749SSergey Zigachev 	uint16_t MemoryBufferSize;
45*b843c749SSergey Zigachev 	uint16_t MemoryPosition;
46*b843c749SSergey Zigachev 	uint16_t PollingInterval;
47*b843c749SSergey Zigachev 	uint8_t  EnableCsrShadow;
48*b843c749SSergey Zigachev 	uint8_t  EnableDramShadow;
49*b843c749SSergey Zigachev };
50*b843c749SSergey Zigachev 
51*b843c749SSergey Zigachev /*  Display specific power management parameters */
52*b843c749SSergey Zigachev #define PWRMGT_SEPARATION_TIME_SHIFT            0
53*b843c749SSergey Zigachev #define PWRMGT_SEPARATION_TIME_MASK             0xFFFF
54*b843c749SSergey Zigachev #define PWRMGT_DISABLE_CPU_CSTATES_SHIFT        16
55*b843c749SSergey Zigachev #define PWRMGT_DISABLE_CPU_CSTATES_MASK         0x1
56*b843c749SSergey Zigachev #define PWRMGT_DISABLE_CPU_PSTATES_SHIFT        24
57*b843c749SSergey Zigachev #define PWRMGT_DISABLE_CPU_PSTATES_MASK         0x1
58*b843c749SSergey Zigachev 
59*b843c749SSergey Zigachev /* Clock Table Definitions */
60*b843c749SSergey Zigachev #define NUM_SCLK_LEVELS     8
61*b843c749SSergey Zigachev #define NUM_LCLK_LEVELS     8
62*b843c749SSergey Zigachev #define NUM_UVD_LEVELS      8
63*b843c749SSergey Zigachev #define NUM_ECLK_LEVELS     8
64*b843c749SSergey Zigachev #define NUM_ACLK_LEVELS     8
65*b843c749SSergey Zigachev 
66*b843c749SSergey Zigachev struct SMU8_Fusion_ClkLevel {
67*b843c749SSergey Zigachev 	uint8_t		GnbVid;
68*b843c749SSergey Zigachev 	uint8_t		GfxVid;
69*b843c749SSergey Zigachev 	uint8_t		DfsDid;
70*b843c749SSergey Zigachev 	uint8_t		DeepSleepDid;
71*b843c749SSergey Zigachev 	uint32_t	DfsBypass;
72*b843c749SSergey Zigachev 	uint32_t	Frequency;
73*b843c749SSergey Zigachev };
74*b843c749SSergey Zigachev 
75*b843c749SSergey Zigachev struct SMU8_Fusion_SclkBreakdownTable {
76*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_SCLK_LEVELS];
77*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
78*b843c749SSergey Zigachev 	/* SMU8_Fusion_ClkLevel PwrOffLevel; */
79*b843c749SSergey Zigachev 	uint32_t    SclkValidMask;
80*b843c749SSergey Zigachev 	uint32_t    MaxSclkIndex;
81*b843c749SSergey Zigachev };
82*b843c749SSergey Zigachev 
83*b843c749SSergey Zigachev struct SMU8_Fusion_LclkBreakdownTable {
84*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_LCLK_LEVELS];
85*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
86*b843c749SSergey Zigachev     /* SMU8_Fusion_ClkLevel PwrOffLevel; */
87*b843c749SSergey Zigachev 	uint32_t    LclkValidMask;
88*b843c749SSergey Zigachev 	uint32_t    MaxLclkIndex;
89*b843c749SSergey Zigachev };
90*b843c749SSergey Zigachev 
91*b843c749SSergey Zigachev struct SMU8_Fusion_EclkBreakdownTable {
92*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ECLK_LEVELS];
93*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
94*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel PwrOffLevel;
95*b843c749SSergey Zigachev 	uint32_t    EclkValidMask;
96*b843c749SSergey Zigachev 	uint32_t    MaxEclkIndex;
97*b843c749SSergey Zigachev };
98*b843c749SSergey Zigachev 
99*b843c749SSergey Zigachev struct SMU8_Fusion_VclkBreakdownTable {
100*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
101*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
102*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel PwrOffLevel;
103*b843c749SSergey Zigachev 	uint32_t    VclkValidMask;
104*b843c749SSergey Zigachev 	uint32_t    MaxVclkIndex;
105*b843c749SSergey Zigachev };
106*b843c749SSergey Zigachev 
107*b843c749SSergey Zigachev struct SMU8_Fusion_DclkBreakdownTable {
108*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_UVD_LEVELS];
109*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
110*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel PwrOffLevel;
111*b843c749SSergey Zigachev 	uint32_t    DclkValidMask;
112*b843c749SSergey Zigachev 	uint32_t    MaxDclkIndex;
113*b843c749SSergey Zigachev };
114*b843c749SSergey Zigachev 
115*b843c749SSergey Zigachev struct SMU8_Fusion_AclkBreakdownTable {
116*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel ClkLevel[NUM_ACLK_LEVELS];
117*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel DpmOffLevel;
118*b843c749SSergey Zigachev 	struct SMU8_Fusion_ClkLevel PwrOffLevel;
119*b843c749SSergey Zigachev 	uint32_t    AclkValidMask;
120*b843c749SSergey Zigachev 	uint32_t    MaxAclkIndex;
121*b843c749SSergey Zigachev };
122*b843c749SSergey Zigachev 
123*b843c749SSergey Zigachev 
124*b843c749SSergey Zigachev struct SMU8_Fusion_ClkTable {
125*b843c749SSergey Zigachev 	struct SMU8_Fusion_SclkBreakdownTable SclkBreakdownTable;
126*b843c749SSergey Zigachev 	struct SMU8_Fusion_LclkBreakdownTable LclkBreakdownTable;
127*b843c749SSergey Zigachev 	struct SMU8_Fusion_EclkBreakdownTable EclkBreakdownTable;
128*b843c749SSergey Zigachev 	struct SMU8_Fusion_VclkBreakdownTable VclkBreakdownTable;
129*b843c749SSergey Zigachev 	struct SMU8_Fusion_DclkBreakdownTable DclkBreakdownTable;
130*b843c749SSergey Zigachev 	struct SMU8_Fusion_AclkBreakdownTable AclkBreakdownTable;
131*b843c749SSergey Zigachev };
132*b843c749SSergey Zigachev 
133*b843c749SSergey Zigachev #pragma pack(pop)
134*b843c749SSergey Zigachev 
135*b843c749SSergey Zigachev #endif
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