1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev */
23*b843c749SSergey Zigachev #ifndef _HARDWARE_MANAGER_H_
24*b843c749SSergey Zigachev #define _HARDWARE_MANAGER_H_
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev
27*b843c749SSergey Zigachev
28*b843c749SSergey Zigachev struct pp_hwmgr;
29*b843c749SSergey Zigachev struct pp_hw_power_state;
30*b843c749SSergey Zigachev struct pp_power_state;
31*b843c749SSergey Zigachev enum amd_dpm_forced_level;
32*b843c749SSergey Zigachev struct PP_TemperatureRange;
33*b843c749SSergey Zigachev
34*b843c749SSergey Zigachev
35*b843c749SSergey Zigachev struct phm_fan_speed_info {
36*b843c749SSergey Zigachev uint32_t min_percent;
37*b843c749SSergey Zigachev uint32_t max_percent;
38*b843c749SSergey Zigachev uint32_t min_rpm;
39*b843c749SSergey Zigachev uint32_t max_rpm;
40*b843c749SSergey Zigachev bool supports_percent_read;
41*b843c749SSergey Zigachev bool supports_percent_write;
42*b843c749SSergey Zigachev bool supports_rpm_read;
43*b843c749SSergey Zigachev bool supports_rpm_write;
44*b843c749SSergey Zigachev };
45*b843c749SSergey Zigachev
46*b843c749SSergey Zigachev /* Automatic Power State Throttling */
47*b843c749SSergey Zigachev enum PHM_AutoThrottleSource
48*b843c749SSergey Zigachev {
49*b843c749SSergey Zigachev PHM_AutoThrottleSource_Thermal,
50*b843c749SSergey Zigachev PHM_AutoThrottleSource_External
51*b843c749SSergey Zigachev };
52*b843c749SSergey Zigachev
53*b843c749SSergey Zigachev typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
54*b843c749SSergey Zigachev
55*b843c749SSergey Zigachev enum phm_platform_caps {
56*b843c749SSergey Zigachev PHM_PlatformCaps_AtomBiosPpV1 = 0,
57*b843c749SSergey Zigachev PHM_PlatformCaps_PowerPlaySupport,
58*b843c749SSergey Zigachev PHM_PlatformCaps_ACOverdriveSupport,
59*b843c749SSergey Zigachev PHM_PlatformCaps_BacklightSupport,
60*b843c749SSergey Zigachev PHM_PlatformCaps_ThermalController,
61*b843c749SSergey Zigachev PHM_PlatformCaps_BiosPowerSourceControl,
62*b843c749SSergey Zigachev PHM_PlatformCaps_DisableVoltageTransition,
63*b843c749SSergey Zigachev PHM_PlatformCaps_DisableEngineTransition,
64*b843c749SSergey Zigachev PHM_PlatformCaps_DisableMemoryTransition,
65*b843c749SSergey Zigachev PHM_PlatformCaps_DynamicPowerManagement,
66*b843c749SSergey Zigachev PHM_PlatformCaps_EnableASPML0s,
67*b843c749SSergey Zigachev PHM_PlatformCaps_EnableASPML1,
68*b843c749SSergey Zigachev PHM_PlatformCaps_OD5inACSupport,
69*b843c749SSergey Zigachev PHM_PlatformCaps_OD5inDCSupport,
70*b843c749SSergey Zigachev PHM_PlatformCaps_SoftStateOD5,
71*b843c749SSergey Zigachev PHM_PlatformCaps_NoOD5Support,
72*b843c749SSergey Zigachev PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
73*b843c749SSergey Zigachev PHM_PlatformCaps_ActivityReporting,
74*b843c749SSergey Zigachev PHM_PlatformCaps_EnableBackbias,
75*b843c749SSergey Zigachev PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
76*b843c749SSergey Zigachev PHM_PlatformCaps_ShowPowerBudgetWarning,
77*b843c749SSergey Zigachev PHM_PlatformCaps_PowerBudgetWaiverAvailable,
78*b843c749SSergey Zigachev PHM_PlatformCaps_GFXClockGatingSupport,
79*b843c749SSergey Zigachev PHM_PlatformCaps_MMClockGatingSupport,
80*b843c749SSergey Zigachev PHM_PlatformCaps_AutomaticDCTransition,
81*b843c749SSergey Zigachev PHM_PlatformCaps_GeminiPrimary,
82*b843c749SSergey Zigachev PHM_PlatformCaps_MemorySpreadSpectrumSupport,
83*b843c749SSergey Zigachev PHM_PlatformCaps_EngineSpreadSpectrumSupport,
84*b843c749SSergey Zigachev PHM_PlatformCaps_StepVddc,
85*b843c749SSergey Zigachev PHM_PlatformCaps_DynamicPCIEGen2Support,
86*b843c749SSergey Zigachev PHM_PlatformCaps_SMC,
87*b843c749SSergey Zigachev PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */
88*b843c749SSergey Zigachev PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */
89*b843c749SSergey Zigachev PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */
90*b843c749SSergey Zigachev PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */
91*b843c749SSergey Zigachev PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */
92*b843c749SSergey Zigachev PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overridden/automated mode. */
93*b843c749SSergey Zigachev PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */
94*b843c749SSergey Zigachev PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */
95*b843c749SSergey Zigachev PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */
96*b843c749SSergey Zigachev PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */
97*b843c749SSergey Zigachev PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */
98*b843c749SSergey Zigachev PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
99*b843c749SSergey Zigachev PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */
100*b843c749SSergey Zigachev PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
101*b843c749SSergey Zigachev PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
102*b843c749SSergey Zigachev PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */
103*b843c749SSergey Zigachev PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
104*b843c749SSergey Zigachev PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */
105*b843c749SSergey Zigachev PHM_PlatformCaps_ABM, /* ABM support.*/
106*b843c749SSergey Zigachev PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */
107*b843c749SSergey Zigachev PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */
108*b843c749SSergey Zigachev PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */
109*b843c749SSergey Zigachev PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */
110*b843c749SSergey Zigachev PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */
111*b843c749SSergey Zigachev PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */
112*b843c749SSergey Zigachev PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */
113*b843c749SSergey Zigachev PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */
114*b843c749SSergey Zigachev PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */
115*b843c749SSergey Zigachev PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
116*b843c749SSergey Zigachev PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
117*b843c749SSergey Zigachev PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */
118*b843c749SSergey Zigachev PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */
119*b843c749SSergey Zigachev PHM_PlatformCaps_AdjustUVDPriorityForSP,
120*b843c749SSergey Zigachev PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */
121*b843c749SSergey Zigachev PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */
122*b843c749SSergey Zigachev PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */
123*b843c749SSergey Zigachev PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */
124*b843c749SSergey Zigachev PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */
125*b843c749SSergey Zigachev PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */
126*b843c749SSergey Zigachev PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */
127*b843c749SSergey Zigachev PHM_PlatformCaps_DynamicPatchPowerState, /* this ASIC supports to patch power state dynamically */
128*b843c749SSergey Zigachev PHM_PlatformCaps_ThermalAutoThrottling, /* enabling auto thermal throttling, */
129*b843c749SSergey Zigachev PHM_PlatformCaps_SumoThermalPolicy, /* A thermal policy specific for Sumo */
130*b843c749SSergey Zigachev PHM_PlatformCaps_PCIEPerformanceRequest, /* support to change RC voltage */
131*b843c749SSergey Zigachev PHM_PlatformCaps_BLControlledByGPU, /* support varibright */
132*b843c749SSergey Zigachev PHM_PlatformCaps_PowerContainment, /* support DPM2 power containment (AKA TDP clamping) */
133*b843c749SSergey Zigachev PHM_PlatformCaps_SQRamping, /* support DPM2 SQ power throttle */
134*b843c749SSergey Zigachev PHM_PlatformCaps_CAC, /* support Capacitance * Activity power estimation */
135*b843c749SSergey Zigachev PHM_PlatformCaps_NIChipsets, /* Northern Island and beyond chipsets */
136*b843c749SSergey Zigachev PHM_PlatformCaps_TrinityChipsets, /* Trinity chipset */
137*b843c749SSergey Zigachev PHM_PlatformCaps_EvergreenChipsets, /* Evergreen family chipset */
138*b843c749SSergey Zigachev PHM_PlatformCaps_PowerControl, /* Cayman and beyond chipsets */
139*b843c749SSergey Zigachev PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP memories */
140*b843c749SSergey Zigachev PHM_PlatformCaps_BoostState, /* this ASIC supports boost state */
141*b843c749SSergey Zigachev PHM_PlatformCaps_UserMaxClockForMultiDisplays, /* indicates if max memory clock is used for all status when multiple displays are connected */
142*b843c749SSergey Zigachev PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write delay is required */
143*b843c749SSergey Zigachev PHM_PlatformCaps_NonABMSupportInPPLib, /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
144*b843c749SSergey Zigachev PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinity */
145*b843c749SSergey Zigachev PHM_PlatformCaps_DisableSMUUVDHandshake, /* Disable SMU UVD Handshake */
146*b843c749SSergey Zigachev PHM_PlatformCaps_DTE, /* Support Digital Temperature Estimation */
147*b843c749SSergey Zigachev PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE, /* This is for the feature requested by David B., and Tonny W.*/
148*b843c749SSergey Zigachev PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from Llano */
149*b843c749SSergey Zigachev PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, supported from UVD5 */
150*b843c749SSergey Zigachev PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for TN and later ASICs */
151*b843c749SSergey Zigachev PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for KV and later ASICs */
152*b843c749SSergey Zigachev PHM_PlatformCaps_UVDDPM, /* UVD clock DPM */
153*b843c749SSergey Zigachev PHM_PlatformCaps_VCEDPM, /* VCE clock DPM */
154*b843c749SSergey Zigachev PHM_PlatformCaps_SamuDPM, /* SAMU clock DPM */
155*b843c749SSergey Zigachev PHM_PlatformCaps_AcpDPM, /* ACP clock DPM */
156*b843c749SSergey Zigachev PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM states */
157*b843c749SSergey Zigachev PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */
158*b843c749SSergey Zigachev PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
159*b843c749SSergey Zigachev PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */
160*b843c749SSergey Zigachev PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */
161*b843c749SSergey Zigachev PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
162*b843c749SSergey Zigachev PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end supports OD6 */
163*b843c749SSergey Zigachev PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end supports OD6 in DC */
164*b843c749SSergey Zigachev PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */
165*b843c749SSergey Zigachev PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */
166*b843c749SSergey Zigachev PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */
167*b843c749SSergey Zigachev PHM_PlatformCaps_DiDtSupport, /* for dI/dT feature */
168*b843c749SSergey Zigachev PHM_PlatformCaps_DBRamping, /* for dI/dT feature */
169*b843c749SSergey Zigachev PHM_PlatformCaps_TDRamping, /* for dI/dT feature */
170*b843c749SSergey Zigachev PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */
171*b843c749SSergey Zigachev PHM_PlatformCaps_DBRRamping, /* for dI/dT feature */
172*b843c749SSergey Zigachev PHM_PlatformCaps_DiDtEDCEnable, /* for dI/dT feature */
173*b843c749SSergey Zigachev PHM_PlatformCaps_GCEDC, /* for dI/dT feature */
174*b843c749SSergey Zigachev PHM_PlatformCaps_PSM, /* for dI/dT feature */
175*b843c749SSergey Zigachev PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */
176*b843c749SSergey Zigachev PHM_PlatformCaps_FPS, /* FPS support */
177*b843c749SSergey Zigachev PHM_PlatformCaps_ACP, /* ACP support */
178*b843c749SSergey Zigachev PHM_PlatformCaps_SclkThrottleLowNotification, /* SCLK Throttle Low Notification */
179*b843c749SSergey Zigachev PHM_PlatformCaps_XDMAEnabled, /* XDMA engine is enabled */
180*b843c749SSergey Zigachev PHM_PlatformCaps_UseDummyBackEnd, /* use dummy back end */
181*b843c749SSergey Zigachev PHM_PlatformCaps_EnableDFSBypass, /* Enable DFS bypass */
182*b843c749SSergey Zigachev PHM_PlatformCaps_VddNBDirectRequest,
183*b843c749SSergey Zigachev PHM_PlatformCaps_PauseMMSessions,
184*b843c749SSergey Zigachev PHM_PlatformCaps_UnTabledHardwareInterface, /* Tableless/direct call hardware interface for CI and newer ASICs */
185*b843c749SSergey Zigachev PHM_PlatformCaps_SMU7, /* indicates that vpuRecoveryBegin without SMU shutdown */
186*b843c749SSergey Zigachev PHM_PlatformCaps_RevertGPIO5Polarity, /* indicates revert GPIO5 plarity table support */
187*b843c749SSergey Zigachev PHM_PlatformCaps_Thermal2GPIO17, /* indicates thermal2GPIO17 table support */
188*b843c749SSergey Zigachev PHM_PlatformCaps_ThermalOutGPIO, /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
189*b843c749SSergey Zigachev PHM_PlatformCaps_DisableMclkSwitchingForFrameLock, /* Disable memory clock switch during Framelock */
190*b843c749SSergey Zigachev PHM_PlatformCaps_ForceMclkHigh, /* Disable memory clock switching by forcing memory clock high */
191*b843c749SSergey Zigachev PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates VR_HOT GPIO configurable */
192*b843c749SSergey Zigachev PHM_PlatformCaps_TempInversion, /* enable Temp Inversion feature */
193*b843c749SSergey Zigachev PHM_PlatformCaps_IOIC3,
194*b843c749SSergey Zigachev PHM_PlatformCaps_ConnectedStandby,
195*b843c749SSergey Zigachev PHM_PlatformCaps_EVV,
196*b843c749SSergey Zigachev PHM_PlatformCaps_EnableLongIdleBACOSupport,
197*b843c749SSergey Zigachev PHM_PlatformCaps_CombinePCCWithThermalSignal,
198*b843c749SSergey Zigachev PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
199*b843c749SSergey Zigachev PHM_PlatformCaps_StablePState,
200*b843c749SSergey Zigachev PHM_PlatformCaps_OD6PlusinACSupport,
201*b843c749SSergey Zigachev PHM_PlatformCaps_OD6PlusinDCSupport,
202*b843c749SSergey Zigachev PHM_PlatformCaps_ODThermalLimitUnlock,
203*b843c749SSergey Zigachev PHM_PlatformCaps_ReducePowerLimit,
204*b843c749SSergey Zigachev PHM_PlatformCaps_ODFuzzyFanControlSupport,
205*b843c749SSergey Zigachev PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
206*b843c749SSergey Zigachev PHM_PlatformCaps_ControlVDDGFX,
207*b843c749SSergey Zigachev PHM_PlatformCaps_BBBSupported,
208*b843c749SSergey Zigachev PHM_PlatformCaps_DisableVoltageIsland,
209*b843c749SSergey Zigachev PHM_PlatformCaps_FanSpeedInTableIsRPM,
210*b843c749SSergey Zigachev PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
211*b843c749SSergey Zigachev PHM_PlatformCaps_IcelandULPSSWWorkAround,
212*b843c749SSergey Zigachev PHM_PlatformCaps_FPSEnhancement,
213*b843c749SSergey Zigachev PHM_PlatformCaps_LoadPostProductionFirmware,
214*b843c749SSergey Zigachev PHM_PlatformCaps_VpuRecoveryInProgress,
215*b843c749SSergey Zigachev PHM_PlatformCaps_Falcon_QuickTransition,
216*b843c749SSergey Zigachev PHM_PlatformCaps_AVFS,
217*b843c749SSergey Zigachev PHM_PlatformCaps_ClockStretcher,
218*b843c749SSergey Zigachev PHM_PlatformCaps_TablelessHardwareInterface,
219*b843c749SSergey Zigachev PHM_PlatformCaps_EnableDriverEVV,
220*b843c749SSergey Zigachev PHM_PlatformCaps_SPLLShutdownSupport,
221*b843c749SSergey Zigachev PHM_PlatformCaps_VirtualBatteryState,
222*b843c749SSergey Zigachev PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
223*b843c749SSergey Zigachev PHM_PlatformCaps_DisableMclkSwitchForVR,
224*b843c749SSergey Zigachev PHM_PlatformCaps_SMU8,
225*b843c749SSergey Zigachev PHM_PlatformCaps_VRHotPolarityHigh,
226*b843c749SSergey Zigachev PHM_PlatformCaps_IPS_UlpsExclusive,
227*b843c749SSergey Zigachev PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
228*b843c749SSergey Zigachev PHM_PlatformCaps_GeminiAsymmetricPower,
229*b843c749SSergey Zigachev PHM_PlatformCaps_OCLPowerOptimization,
230*b843c749SSergey Zigachev PHM_PlatformCaps_MaxPCIEBandWidth,
231*b843c749SSergey Zigachev PHM_PlatformCaps_PerfPerWattOptimizationSupport,
232*b843c749SSergey Zigachev PHM_PlatformCaps_UVDClientMCTuning,
233*b843c749SSergey Zigachev PHM_PlatformCaps_ODNinACSupport,
234*b843c749SSergey Zigachev PHM_PlatformCaps_ODNinDCSupport,
235*b843c749SSergey Zigachev PHM_PlatformCaps_UMDPState,
236*b843c749SSergey Zigachev PHM_PlatformCaps_AutoWattmanSupport,
237*b843c749SSergey Zigachev PHM_PlatformCaps_AutoWattmanEnable_CCCState,
238*b843c749SSergey Zigachev PHM_PlatformCaps_FreeSyncActive,
239*b843c749SSergey Zigachev PHM_PlatformCaps_EnableShadowPstate,
240*b843c749SSergey Zigachev PHM_PlatformCaps_customThermalManagement,
241*b843c749SSergey Zigachev PHM_PlatformCaps_staticFanControl,
242*b843c749SSergey Zigachev PHM_PlatformCaps_Virtual_System,
243*b843c749SSergey Zigachev PHM_PlatformCaps_LowestUclkReservedForUlv,
244*b843c749SSergey Zigachev PHM_PlatformCaps_EnableBoostState,
245*b843c749SSergey Zigachev PHM_PlatformCaps_AVFSSupport,
246*b843c749SSergey Zigachev PHM_PlatformCaps_ThermalPolicyDelay,
247*b843c749SSergey Zigachev PHM_PlatformCaps_CustomFanControlSupport,
248*b843c749SSergey Zigachev PHM_PlatformCaps_BAMACO,
249*b843c749SSergey Zigachev PHM_PlatformCaps_Max
250*b843c749SSergey Zigachev };
251*b843c749SSergey Zigachev
252*b843c749SSergey Zigachev #define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
253*b843c749SSergey Zigachev
254*b843c749SSergey Zigachev /* Number of uint32_t entries used by CAPS table */
255*b843c749SSergey Zigachev #define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
256*b843c749SSergey Zigachev ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
257*b843c749SSergey Zigachev
258*b843c749SSergey Zigachev struct pp_hw_descriptor {
259*b843c749SSergey Zigachev uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
260*b843c749SSergey Zigachev };
261*b843c749SSergey Zigachev
262*b843c749SSergey Zigachev enum PHM_PerformanceLevelDesignation {
263*b843c749SSergey Zigachev PHM_PerformanceLevelDesignation_Activity,
264*b843c749SSergey Zigachev PHM_PerformanceLevelDesignation_PowerContainment
265*b843c749SSergey Zigachev };
266*b843c749SSergey Zigachev
267*b843c749SSergey Zigachev typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
268*b843c749SSergey Zigachev
269*b843c749SSergey Zigachev struct PHM_PerformanceLevel {
270*b843c749SSergey Zigachev uint32_t coreClock;
271*b843c749SSergey Zigachev uint32_t memory_clock;
272*b843c749SSergey Zigachev uint32_t vddc;
273*b843c749SSergey Zigachev uint32_t vddci;
274*b843c749SSergey Zigachev uint32_t nonLocalMemoryFreq;
275*b843c749SSergey Zigachev uint32_t nonLocalMemoryWidth;
276*b843c749SSergey Zigachev };
277*b843c749SSergey Zigachev
278*b843c749SSergey Zigachev typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
279*b843c749SSergey Zigachev
280*b843c749SSergey Zigachev /* Function for setting a platform cap */
phm_cap_set(uint32_t * caps,enum phm_platform_caps c)281*b843c749SSergey Zigachev static inline void phm_cap_set(uint32_t *caps,
282*b843c749SSergey Zigachev enum phm_platform_caps c)
283*b843c749SSergey Zigachev {
284*b843c749SSergey Zigachev caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
285*b843c749SSergey Zigachev (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
286*b843c749SSergey Zigachev }
287*b843c749SSergey Zigachev
phm_cap_unset(uint32_t * caps,enum phm_platform_caps c)288*b843c749SSergey Zigachev static inline void phm_cap_unset(uint32_t *caps,
289*b843c749SSergey Zigachev enum phm_platform_caps c)
290*b843c749SSergey Zigachev {
291*b843c749SSergey Zigachev caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
292*b843c749SSergey Zigachev }
293*b843c749SSergey Zigachev
phm_cap_enabled(const uint32_t * caps,enum phm_platform_caps c)294*b843c749SSergey Zigachev static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
295*b843c749SSergey Zigachev {
296*b843c749SSergey Zigachev return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
297*b843c749SSergey Zigachev (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
298*b843c749SSergey Zigachev }
299*b843c749SSergey Zigachev
300*b843c749SSergey Zigachev #define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
301*b843c749SSergey Zigachev
302*b843c749SSergey Zigachev #define PP_PCIEGenInvalid 0xffff
303*b843c749SSergey Zigachev enum PP_PCIEGen {
304*b843c749SSergey Zigachev PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
305*b843c749SSergey Zigachev PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
306*b843c749SSergey Zigachev PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
307*b843c749SSergey Zigachev };
308*b843c749SSergey Zigachev
309*b843c749SSergey Zigachev typedef enum PP_PCIEGen PP_PCIEGen;
310*b843c749SSergey Zigachev
311*b843c749SSergey Zigachev #define PP_Min_PCIEGen PP_PCIEGen1
312*b843c749SSergey Zigachev #define PP_Max_PCIEGen PP_PCIEGen3
313*b843c749SSergey Zigachev #define PP_Min_PCIELane 1
314*b843c749SSergey Zigachev #define PP_Max_PCIELane 16
315*b843c749SSergey Zigachev
316*b843c749SSergey Zigachev enum phm_clock_Type {
317*b843c749SSergey Zigachev PHM_DispClock = 1,
318*b843c749SSergey Zigachev PHM_SClock,
319*b843c749SSergey Zigachev PHM_MemClock
320*b843c749SSergey Zigachev };
321*b843c749SSergey Zigachev
322*b843c749SSergey Zigachev #define MAX_NUM_CLOCKS 16
323*b843c749SSergey Zigachev
324*b843c749SSergey Zigachev struct PP_Clocks {
325*b843c749SSergey Zigachev uint32_t engineClock;
326*b843c749SSergey Zigachev uint32_t memoryClock;
327*b843c749SSergey Zigachev uint32_t BusBandwidth;
328*b843c749SSergey Zigachev uint32_t engineClockInSR;
329*b843c749SSergey Zigachev uint32_t dcefClock;
330*b843c749SSergey Zigachev uint32_t dcefClockInSR;
331*b843c749SSergey Zigachev };
332*b843c749SSergey Zigachev
333*b843c749SSergey Zigachev struct pp_clock_info {
334*b843c749SSergey Zigachev uint32_t min_mem_clk;
335*b843c749SSergey Zigachev uint32_t max_mem_clk;
336*b843c749SSergey Zigachev uint32_t min_eng_clk;
337*b843c749SSergey Zigachev uint32_t max_eng_clk;
338*b843c749SSergey Zigachev uint32_t min_bus_bandwidth;
339*b843c749SSergey Zigachev uint32_t max_bus_bandwidth;
340*b843c749SSergey Zigachev };
341*b843c749SSergey Zigachev
342*b843c749SSergey Zigachev struct phm_platform_descriptor {
343*b843c749SSergey Zigachev uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
344*b843c749SSergey Zigachev uint32_t vbiosInterruptId;
345*b843c749SSergey Zigachev struct PP_Clocks overdriveLimit;
346*b843c749SSergey Zigachev struct PP_Clocks clockStep;
347*b843c749SSergey Zigachev uint32_t hardwareActivityPerformanceLevels;
348*b843c749SSergey Zigachev uint32_t minimumClocksReductionPercentage;
349*b843c749SSergey Zigachev uint32_t minOverdriveVDDC;
350*b843c749SSergey Zigachev uint32_t maxOverdriveVDDC;
351*b843c749SSergey Zigachev uint32_t overdriveVDDCStep;
352*b843c749SSergey Zigachev uint32_t hardwarePerformanceLevels;
353*b843c749SSergey Zigachev uint16_t powerBudget;
354*b843c749SSergey Zigachev uint32_t TDPLimit;
355*b843c749SSergey Zigachev uint32_t nearTDPLimit;
356*b843c749SSergey Zigachev uint32_t nearTDPLimitAdjusted;
357*b843c749SSergey Zigachev uint32_t SQRampingThreshold;
358*b843c749SSergey Zigachev uint32_t CACLeakage;
359*b843c749SSergey Zigachev uint16_t TDPODLimit;
360*b843c749SSergey Zigachev uint32_t TDPAdjustment;
361*b843c749SSergey Zigachev bool TDPAdjustmentPolarity;
362*b843c749SSergey Zigachev uint16_t LoadLineSlope;
363*b843c749SSergey Zigachev uint32_t VidMinLimit;
364*b843c749SSergey Zigachev uint32_t VidMaxLimit;
365*b843c749SSergey Zigachev uint32_t VidStep;
366*b843c749SSergey Zigachev uint32_t VidAdjustment;
367*b843c749SSergey Zigachev bool VidAdjustmentPolarity;
368*b843c749SSergey Zigachev };
369*b843c749SSergey Zigachev
370*b843c749SSergey Zigachev struct phm_clocks {
371*b843c749SSergey Zigachev uint32_t num_of_entries;
372*b843c749SSergey Zigachev uint32_t clock[MAX_NUM_CLOCKS];
373*b843c749SSergey Zigachev };
374*b843c749SSergey Zigachev
375*b843c749SSergey Zigachev #define DPMTABLE_OD_UPDATE_SCLK 0x00000001
376*b843c749SSergey Zigachev #define DPMTABLE_OD_UPDATE_MCLK 0x00000002
377*b843c749SSergey Zigachev #define DPMTABLE_UPDATE_SCLK 0x00000004
378*b843c749SSergey Zigachev #define DPMTABLE_UPDATE_MCLK 0x00000008
379*b843c749SSergey Zigachev #define DPMTABLE_OD_UPDATE_VDDC 0x00000010
380*b843c749SSergey Zigachev #define DPMTABLE_UPDATE_SOCCLK 0x00000020
381*b843c749SSergey Zigachev
382*b843c749SSergey Zigachev struct phm_odn_performance_level {
383*b843c749SSergey Zigachev uint32_t clock;
384*b843c749SSergey Zigachev uint32_t vddc;
385*b843c749SSergey Zigachev bool enabled;
386*b843c749SSergey Zigachev };
387*b843c749SSergey Zigachev
388*b843c749SSergey Zigachev struct phm_odn_clock_levels {
389*b843c749SSergey Zigachev uint32_t size;
390*b843c749SSergey Zigachev uint32_t options;
391*b843c749SSergey Zigachev uint32_t flags;
392*b843c749SSergey Zigachev uint32_t num_of_pl;
393*b843c749SSergey Zigachev /* variable-sized array, specify by num_of_pl. */
394*b843c749SSergey Zigachev struct phm_odn_performance_level entries[8];
395*b843c749SSergey Zigachev };
396*b843c749SSergey Zigachev
397*b843c749SSergey Zigachev extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
398*b843c749SSergey Zigachev extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
399*b843c749SSergey Zigachev extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
400*b843c749SSergey Zigachev extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
401*b843c749SSergey Zigachev extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
402*b843c749SSergey Zigachev extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
403*b843c749SSergey Zigachev extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
404*b843c749SSergey Zigachev extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
405*b843c749SSergey Zigachev extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
406*b843c749SSergey Zigachev const struct pp_hw_power_state *pcurrent_state,
407*b843c749SSergey Zigachev const struct pp_hw_power_state *pnew_power_state);
408*b843c749SSergey Zigachev
409*b843c749SSergey Zigachev extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
410*b843c749SSergey Zigachev struct pp_power_state *adjusted_ps,
411*b843c749SSergey Zigachev const struct pp_power_state *current_ps);
412*b843c749SSergey Zigachev
413*b843c749SSergey Zigachev extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr);
414*b843c749SSergey Zigachev
415*b843c749SSergey Zigachev extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
416*b843c749SSergey Zigachev extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr);
417*b843c749SSergey Zigachev extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
418*b843c749SSergey Zigachev extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
419*b843c749SSergey Zigachev extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr);
420*b843c749SSergey Zigachev extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr);
421*b843c749SSergey Zigachev extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
422*b843c749SSergey Zigachev extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
423*b843c749SSergey Zigachev
424*b843c749SSergey Zigachev extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
425*b843c749SSergey Zigachev const struct pp_hw_power_state *pstate1,
426*b843c749SSergey Zigachev const struct pp_hw_power_state *pstate2,
427*b843c749SSergey Zigachev bool *equal);
428*b843c749SSergey Zigachev
429*b843c749SSergey Zigachev extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
430*b843c749SSergey Zigachev const struct amd_pp_display_configuration *display_config);
431*b843c749SSergey Zigachev
432*b843c749SSergey Zigachev extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
433*b843c749SSergey Zigachev struct amd_pp_simple_clock_info *info);
434*b843c749SSergey Zigachev
435*b843c749SSergey Zigachev extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
436*b843c749SSergey Zigachev
437*b843c749SSergey Zigachev extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
438*b843c749SSergey Zigachev
439*b843c749SSergey Zigachev extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
440*b843c749SSergey Zigachev PHM_PerformanceLevelDesignation designation, uint32_t index,
441*b843c749SSergey Zigachev PHM_PerformanceLevel *level);
442*b843c749SSergey Zigachev
443*b843c749SSergey Zigachev extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
444*b843c749SSergey Zigachev struct pp_clock_info *pclock_info,
445*b843c749SSergey Zigachev PHM_PerformanceLevelDesignation designation);
446*b843c749SSergey Zigachev
447*b843c749SSergey Zigachev extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
448*b843c749SSergey Zigachev
449*b843c749SSergey Zigachev extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
450*b843c749SSergey Zigachev
451*b843c749SSergey Zigachev extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
452*b843c749SSergey Zigachev enum amd_pp_clock_type type,
453*b843c749SSergey Zigachev struct pp_clock_levels_with_latency *clocks);
454*b843c749SSergey Zigachev extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
455*b843c749SSergey Zigachev enum amd_pp_clock_type type,
456*b843c749SSergey Zigachev struct pp_clock_levels_with_voltage *clocks);
457*b843c749SSergey Zigachev extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
458*b843c749SSergey Zigachev void *clock_ranges);
459*b843c749SSergey Zigachev extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
460*b843c749SSergey Zigachev struct pp_display_clock_request *clock);
461*b843c749SSergey Zigachev
462*b843c749SSergey Zigachev extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
463*b843c749SSergey Zigachev extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
464*b843c749SSergey Zigachev #endif /* _HARDWARE_MANAGER_H_ */
465*b843c749SSergey Zigachev
466