1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2017 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef __IRQSRCS_DCN_1_0_H__ 27*b843c749SSergey Zigachev #define __IRQSRCS_DCN_1_0_H__ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 31*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 34*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 37*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 38*b843c749SSergey Zigachev 39*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 40*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 41*b843c749SSergey Zigachev 42*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 43*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 44*b843c749SSergey Zigachev 45*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 46*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 47*b843c749SSergey Zigachev 48*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 49*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 52*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 53*b843c749SSergey Zigachev 54*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 55*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 58*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 59*b843c749SSergey Zigachev 60*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 61*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 62*b843c749SSergey Zigachev 63*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 64*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 65*b843c749SSergey Zigachev 66*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 67*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 68*b843c749SSergey Zigachev 69*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 70*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 73*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 74*b843c749SSergey Zigachev 75*b843c749SSergey Zigachev #define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 76*b843c749SSergey Zigachev #define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 77*b843c749SSergey Zigachev 78*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 79*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 82*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 83*b843c749SSergey Zigachev 84*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 85*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 86*b843c749SSergey Zigachev 87*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 88*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 89*b843c749SSergey Zigachev 90*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 91*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 92*b843c749SSergey Zigachev 93*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 94*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 95*b843c749SSergey Zigachev 96*b843c749SSergey Zigachev #define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level 97*b843c749SSergey Zigachev #define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 98*b843c749SSergey Zigachev 99*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level 100*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 101*b843c749SSergey Zigachev 102*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level 103*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMCU_SCP_INT 14 104*b843c749SSergey Zigachev 105*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 106*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 109*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 110*b843c749SSergey Zigachev 111*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level 112*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 113*b843c749SSergey Zigachev 114*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level 115*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 116*b843c749SSergey Zigachev 117*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level 118*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 119*b843c749SSergey Zigachev 120*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level 121*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 122*b843c749SSergey Zigachev 123*b843c749SSergey Zigachev #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse 124*b843c749SSergey Zigachev #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 125*b843c749SSergey Zigachev 126*b843c749SSergey Zigachev #define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level 127*b843c749SSergey Zigachev #define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 128*b843c749SSergey Zigachev 129*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse 130*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 133*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 134*b843c749SSergey Zigachev 135*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 136*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 137*b843c749SSergey Zigachev 138*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 139*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 140*b843c749SSergey Zigachev 141*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 142*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 143*b843c749SSergey Zigachev 144*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 145*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 146*b843c749SSergey Zigachev 147*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 148*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 149*b843c749SSergey Zigachev 150*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 151*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 152*b843c749SSergey Zigachev 153*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 154*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 155*b843c749SSergey Zigachev 156*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level 157*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD1_INT 0 158*b843c749SSergey Zigachev 159*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 160*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD2_INT 1 161*b843c749SSergey Zigachev 162*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 163*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD3_INT 2 164*b843c749SSergey Zigachev 165*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 166*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD4_INT 3 167*b843c749SSergey Zigachev 168*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 169*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD5_INT 4 170*b843c749SSergey Zigachev 171*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 172*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD6_INT 5 173*b843c749SSergey Zigachev 174*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level 175*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 176*b843c749SSergey Zigachev 177*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 178*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 179*b843c749SSergey Zigachev 180*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 181*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 182*b843c749SSergey Zigachev 183*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 184*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 185*b843c749SSergey Zigachev 186*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 187*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 188*b843c749SSergey Zigachev 189*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 190*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 191*b843c749SSergey Zigachev 192*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level 193*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 194*b843c749SSergey Zigachev 195*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 196*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 197*b843c749SSergey Zigachev 198*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 199*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 200*b843c749SSergey Zigachev 201*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 202*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 203*b843c749SSergey Zigachev 204*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 205*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 206*b843c749SSergey Zigachev 207*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 208*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 209*b843c749SSergey Zigachev 210*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 211*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 212*b843c749SSergey Zigachev 213*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 214*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 215*b843c749SSergey Zigachev 216*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 217*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 218*b843c749SSergey Zigachev 219*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 220*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 221*b843c749SSergey Zigachev 222*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 223*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 224*b843c749SSergey Zigachev 225*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 226*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 227*b843c749SSergey Zigachev 228*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 229*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 230*b843c749SSergey Zigachev 231*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 232*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 233*b843c749SSergey Zigachev 234*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 235*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 236*b843c749SSergey Zigachev 237*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 238*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 239*b843c749SSergey Zigachev 240*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 241*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 242*b843c749SSergey Zigachev 243*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 244*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 245*b843c749SSergey Zigachev 246*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 247*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 248*b843c749SSergey Zigachev 249*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 250*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 251*b843c749SSergey Zigachev 252*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 253*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 254*b843c749SSergey Zigachev 255*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 256*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 257*b843c749SSergey Zigachev 258*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 259*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 260*b843c749SSergey Zigachev 261*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 262*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 263*b843c749SSergey Zigachev 264*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse 265*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 266*b843c749SSergey Zigachev 267*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 268*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 269*b843c749SSergey Zigachev 270*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 271*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 272*b843c749SSergey Zigachev 273*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 274*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 275*b843c749SSergey Zigachev 276*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 277*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 278*b843c749SSergey Zigachev 279*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 280*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 281*b843c749SSergey Zigachev 282*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 283*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 284*b843c749SSergey Zigachev 285*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level 286*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 287*b843c749SSergey Zigachev 288*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 289*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 290*b843c749SSergey Zigachev 291*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 292*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 293*b843c749SSergey Zigachev 294*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 295*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 296*b843c749SSergey Zigachev 297*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 298*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 299*b843c749SSergey Zigachev 300*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 301*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 302*b843c749SSergey Zigachev 303*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level 304*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 305*b843c749SSergey Zigachev 306*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 307*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 308*b843c749SSergey Zigachev 309*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level 310*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 311*b843c749SSergey Zigachev 312*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 313*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 314*b843c749SSergey Zigachev 315*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 316*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 317*b843c749SSergey Zigachev 318*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 319*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 320*b843c749SSergey Zigachev 321*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 322*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 323*b843c749SSergey Zigachev 324*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 325*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 326*b843c749SSergey Zigachev 327*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level 328*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 329*b843c749SSergey Zigachev 330*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level 331*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 332*b843c749SSergey Zigachev 333*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 334*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 335*b843c749SSergey Zigachev 336*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level 337*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 338*b843c749SSergey Zigachev 339*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 340*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 341*b843c749SSergey Zigachev 342*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 343*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 344*b843c749SSergey Zigachev 345*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 346*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 347*b843c749SSergey Zigachev 348*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 349*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 350*b843c749SSergey Zigachev 351*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 352*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 353*b843c749SSergey Zigachev 354*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 355*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 356*b843c749SSergey Zigachev 357*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 358*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 359*b843c749SSergey Zigachev 360*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 361*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 362*b843c749SSergey Zigachev 363*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 364*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 365*b843c749SSergey Zigachev 366*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level 367*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 368*b843c749SSergey Zigachev 369*b843c749SSergey Zigachev #define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 370*b843c749SSergey Zigachev #define DCN_1_0__CTXID__VGA_CRT_INT 12 371*b843c749SSergey Zigachev 372*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 373*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 374*b843c749SSergey Zigachev 375*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level 376*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 377*b843c749SSergey Zigachev 378*b843c749SSergey Zigachev #define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 379*b843c749SSergey Zigachev #define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 380*b843c749SSergey Zigachev 381*b843c749SSergey Zigachev #define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 382*b843c749SSergey Zigachev #define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 383*b843c749SSergey Zigachev 384*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 385*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 386*b843c749SSergey Zigachev 387*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 388*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 389*b843c749SSergey Zigachev 390*b843c749SSergey Zigachev #define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 391*b843c749SSergey Zigachev #define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 392*b843c749SSergey Zigachev 393*b843c749SSergey Zigachev #define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 394*b843c749SSergey Zigachev #define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 395*b843c749SSergey Zigachev 396*b843c749SSergey Zigachev #define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 397*b843c749SSergey Zigachev #define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 398*b843c749SSergey Zigachev 399*b843c749SSergey Zigachev #define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 400*b843c749SSergey Zigachev #define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 401*b843c749SSergey Zigachev 402*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 403*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 404*b843c749SSergey Zigachev 405*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 406*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 407*b843c749SSergey Zigachev 408*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 409*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 410*b843c749SSergey Zigachev 411*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 412*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 413*b843c749SSergey Zigachev 414*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 415*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 416*b843c749SSergey Zigachev 417*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level 418*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 419*b843c749SSergey Zigachev 420*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 421*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 422*b843c749SSergey Zigachev 423*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 424*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 425*b843c749SSergey Zigachev 426*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 427*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 428*b843c749SSergey Zigachev 429*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 430*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 431*b843c749SSergey Zigachev 432*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 433*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 434*b843c749SSergey Zigachev 435*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 436*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 437*b843c749SSergey Zigachev 438*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 439*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 440*b843c749SSergey Zigachev 441*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 442*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 443*b843c749SSergey Zigachev 444*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 445*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 446*b843c749SSergey Zigachev 447*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 448*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 449*b843c749SSergey Zigachev 450*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 451*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 452*b843c749SSergey Zigachev 453*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 454*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 455*b843c749SSergey Zigachev 456*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 457*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 458*b843c749SSergey Zigachev 459*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 460*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 461*b843c749SSergey Zigachev 462*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 463*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 464*b843c749SSergey Zigachev 465*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 466*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 467*b843c749SSergey Zigachev 468*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 469*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 470*b843c749SSergey Zigachev 471*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 472*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 473*b843c749SSergey Zigachev 474*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 475*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 476*b843c749SSergey Zigachev 477*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 478*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 479*b843c749SSergey Zigachev 480*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 481*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 482*b843c749SSergey Zigachev 483*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level 484*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 485*b843c749SSergey Zigachev 486*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level 487*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 488*b843c749SSergey Zigachev 489*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level 490*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 491*b843c749SSergey Zigachev 492*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level 493*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 494*b843c749SSergey Zigachev 495*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level 496*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 497*b843c749SSergey Zigachev 498*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 499*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 500*b843c749SSergey Zigachev 501*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level 502*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 503*b843c749SSergey Zigachev 504*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 505*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 506*b843c749SSergey Zigachev 507*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 508*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 509*b843c749SSergey Zigachev 510*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 511*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 512*b843c749SSergey Zigachev 513*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 514*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 515*b843c749SSergey Zigachev 516*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 517*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 518*b843c749SSergey Zigachev 519*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 520*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 521*b843c749SSergey Zigachev 522*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 523*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 524*b843c749SSergey Zigachev 525*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 526*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 527*b843c749SSergey Zigachev 528*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 529*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 530*b843c749SSergey Zigachev 531*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 532*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 533*b843c749SSergey Zigachev 534*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 535*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 536*b843c749SSergey Zigachev 537*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 538*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 539*b843c749SSergey Zigachev 540*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 541*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 542*b843c749SSergey Zigachev 543*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 544*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 545*b843c749SSergey Zigachev 546*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 547*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 548*b843c749SSergey Zigachev 549*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 550*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 551*b843c749SSergey Zigachev 552*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 553*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 554*b843c749SSergey Zigachev 555*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 556*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 557*b843c749SSergey Zigachev 558*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 559*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 560*b843c749SSergey Zigachev 561*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse 562*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 563*b843c749SSergey Zigachev 564*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 565*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 566*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 567*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 568*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 569*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 570*b843c749SSergey Zigachev 571*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 572*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 573*b843c749SSergey Zigachev 574*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 575*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 576*b843c749SSergey Zigachev 577*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 578*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 579*b843c749SSergey Zigachev 580*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 581*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 582*b843c749SSergey Zigachev 583*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 584*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 585*b843c749SSergey Zigachev 586*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 587*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 588*b843c749SSergey Zigachev 589*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 590*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 591*b843c749SSergey Zigachev 592*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 593*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 594*b843c749SSergey Zigachev 595*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 596*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 597*b843c749SSergey Zigachev 598*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 599*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 600*b843c749SSergey Zigachev 601*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 602*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 603*b843c749SSergey Zigachev 604*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 605*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 606*b843c749SSergey Zigachev 607*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse 608*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 609*b843c749SSergey Zigachev 610*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 611*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 612*b843c749SSergey Zigachev 613*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 614*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 615*b843c749SSergey Zigachev 616*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 617*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 618*b843c749SSergey Zigachev 619*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 620*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 621*b843c749SSergey Zigachev 622*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 623*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 624*b843c749SSergey Zigachev 625*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 626*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 627*b843c749SSergey Zigachev 628*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 629*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 630*b843c749SSergey Zigachev 631*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 632*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 633*b843c749SSergey Zigachev 634*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 635*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 636*b843c749SSergey Zigachev 637*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 638*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 639*b843c749SSergey Zigachev 640*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 641*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 642*b843c749SSergey Zigachev 643*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 644*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 645*b843c749SSergey Zigachev 646*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 647*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 648*b843c749SSergey Zigachev 649*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 650*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 651*b843c749SSergey Zigachev 652*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 653*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 654*b843c749SSergey Zigachev 655*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 656*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 657*b843c749SSergey Zigachev 658*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 659*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 660*b843c749SSergey Zigachev 661*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 662*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 663*b843c749SSergey Zigachev 664*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 665*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 666*b843c749SSergey Zigachev 667*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 668*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 669*b843c749SSergey Zigachev 670*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 671*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 672*b843c749SSergey Zigachev 673*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 674*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 675*b843c749SSergey Zigachev 676*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 677*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 678*b843c749SSergey Zigachev 679*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 680*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 681*b843c749SSergey Zigachev 682*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 683*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 684*b843c749SSergey Zigachev 685*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 686*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 687*b843c749SSergey Zigachev 688*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 689*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 690*b843c749SSergey Zigachev 691*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 692*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 693*b843c749SSergey Zigachev 694*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 695*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 696*b843c749SSergey Zigachev 697*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 698*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 699*b843c749SSergey Zigachev 700*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 701*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 702*b843c749SSergey Zigachev 703*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 704*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 705*b843c749SSergey Zigachev 706*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 707*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 708*b843c749SSergey Zigachev 709*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 710*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 711*b843c749SSergey Zigachev 712*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 713*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 714*b843c749SSergey Zigachev 715*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 716*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 717*b843c749SSergey Zigachev 718*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 719*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 720*b843c749SSergey Zigachev 721*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 722*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 723*b843c749SSergey Zigachev 724*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 725*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 726*b843c749SSergey Zigachev 727*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 728*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 729*b843c749SSergey Zigachev 730*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 731*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 732*b843c749SSergey Zigachev 733*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 734*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 735*b843c749SSergey Zigachev 736*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 737*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 738*b843c749SSergey Zigachev 739*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 740*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 741*b843c749SSergey Zigachev 742*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 743*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 744*b843c749SSergey Zigachev 745*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 746*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 747*b843c749SSergey Zigachev 748*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 749*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 750*b843c749SSergey Zigachev 751*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 752*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 753*b843c749SSergey Zigachev 754*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 755*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 756*b843c749SSergey Zigachev 757*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 758*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 759*b843c749SSergey Zigachev 760*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 761*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 762*b843c749SSergey Zigachev 763*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 764*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 765*b843c749SSergey Zigachev 766*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 767*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_VBLANK 0 768*b843c749SSergey Zigachev 769*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 770*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_VLINE1 1 771*b843c749SSergey Zigachev 772*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 773*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D1_VLINE2 2 774*b843c749SSergey Zigachev 775*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 776*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_VBLANK 3 777*b843c749SSergey Zigachev 778*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 779*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_VLINE1 4 780*b843c749SSergey Zigachev 781*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 782*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D2_VLINE2 5 783*b843c749SSergey Zigachev 784*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 785*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 786*b843c749SSergey Zigachev 787*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 788*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 789*b843c749SSergey Zigachev 790*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 791*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 792*b843c749SSergey Zigachev 793*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 794*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 795*b843c749SSergey Zigachev 796*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 797*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 798*b843c749SSergey Zigachev 799*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 800*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 801*b843c749SSergey Zigachev 802*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 803*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 804*b843c749SSergey Zigachev 805*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 806*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 807*b843c749SSergey Zigachev 808*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 809*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 810*b843c749SSergey Zigachev 811*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 812*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 813*b843c749SSergey Zigachev 814*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 815*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_VBLANK 9 816*b843c749SSergey Zigachev 817*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 818*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_VLINE1 10 819*b843c749SSergey Zigachev 820*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 821*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D3_VLINE2 11 822*b843c749SSergey Zigachev 823*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 824*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_VBLANK 12 825*b843c749SSergey Zigachev 826*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 827*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_VLINE1 13 828*b843c749SSergey Zigachev 829*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 830*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D4_VLINE2 14 831*b843c749SSergey Zigachev 832*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 833*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 834*b843c749SSergey Zigachev 835*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 836*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 837*b843c749SSergey Zigachev 838*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 839*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_VBLANK 9 840*b843c749SSergey Zigachev 841*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 842*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_VLINE1 10 843*b843c749SSergey Zigachev 844*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 845*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D5_VLINE2 11 846*b843c749SSergey Zigachev 847*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 848*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_VBLANK 12 849*b843c749SSergey Zigachev 850*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 851*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_VLINE1 13 852*b843c749SSergey Zigachev 853*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 854*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_VLINE2 14 855*b843c749SSergey Zigachev 856*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse 857*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 858*b843c749SSergey Zigachev 859*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level 860*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 861*b843c749SSergey Zigachev 862*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 863*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D7_VBLANK 9 864*b843c749SSergey Zigachev 865*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 866*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D7_VLINE1 10 867*b843c749SSergey Zigachev 868*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 869*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D7_VLINE2 11 870*b843c749SSergey Zigachev 871*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 872*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D8_VBLANK 12 873*b843c749SSergey Zigachev 874*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 875*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D8_VLINE1 13 876*b843c749SSergey Zigachev 877*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 878*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D8_VLINE2 14 879*b843c749SSergey Zigachev 880*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 881*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 882*b843c749SSergey Zigachev 883*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 884*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 885*b843c749SSergey Zigachev 886*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 887*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 888*b843c749SSergey Zigachev 889*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 890*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 891*b843c749SSergey Zigachev 892*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse 893*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 894*b843c749SSergey Zigachev 895*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level 896*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 897*b843c749SSergey Zigachev 898*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 899*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 900*b843c749SSergey Zigachev 901*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 902*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 903*b843c749SSergey Zigachev 904*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 905*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 906*b843c749SSergey Zigachev 907*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 908*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 909*b843c749SSergey Zigachev 910*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 911*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 912*b843c749SSergey Zigachev 913*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 914*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 915*b843c749SSergey Zigachev 916*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 917*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 918*b843c749SSergey Zigachev 919*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 920*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 921*b843c749SSergey Zigachev 922*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 923*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 924*b843c749SSergey Zigachev 925*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 926*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 927*b843c749SSergey Zigachev 928*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse 929*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 930*b843c749SSergey Zigachev 931*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level 932*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 933*b843c749SSergey Zigachev 934*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 935*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 936*b843c749SSergey Zigachev 937*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 938*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 939*b843c749SSergey Zigachev 940*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 941*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 942*b843c749SSergey Zigachev 943*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 944*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 945*b843c749SSergey Zigachev 946*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse 947*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 948*b843c749SSergey Zigachev 949*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level 950*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 951*b843c749SSergey Zigachev 952*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse 953*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 954*b843c749SSergey Zigachev 955*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level 956*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 957*b843c749SSergey Zigachev 958*b843c749SSergey Zigachev #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse 959*b843c749SSergey Zigachev #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 960*b843c749SSergey Zigachev 961*b843c749SSergey Zigachev #define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level 962*b843c749SSergey Zigachev #define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 963*b843c749SSergey Zigachev 964*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse 965*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 966*b843c749SSergey Zigachev 967*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level 968*b843c749SSergey Zigachev #define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 969*b843c749SSergey Zigachev 970*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse 971*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 972*b843c749SSergey Zigachev 973*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level 974*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 975*b843c749SSergey Zigachev 976*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 977*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 978*b843c749SSergey Zigachev 979*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 980*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 981*b843c749SSergey Zigachev 982*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 983*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 984*b843c749SSergey Zigachev 985*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 986*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 987*b843c749SSergey Zigachev 988*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 989*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 990*b843c749SSergey Zigachev 991*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 992*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 993*b843c749SSergey Zigachev 994*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 995*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 996*b843c749SSergey Zigachev 997*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 998*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 999*b843c749SSergey Zigachev 1000*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1001*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 1002*b843c749SSergey Zigachev 1003*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1004*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 1005*b843c749SSergey Zigachev 1006*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1007*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 1008*b843c749SSergey Zigachev 1009*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1010*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 1011*b843c749SSergey Zigachev 1012*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1013*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 1014*b843c749SSergey Zigachev 1015*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1016*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 1017*b843c749SSergey Zigachev 1018*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1019*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 1020*b843c749SSergey Zigachev 1021*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1022*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 1023*b843c749SSergey Zigachev 1024*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 1025*b843c749SSergey Zigachev #define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 1026*b843c749SSergey Zigachev 1027*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1028*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 1029*b843c749SSergey Zigachev 1030*b843c749SSergey Zigachev #define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level 1031*b843c749SSergey Zigachev #define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 1032*b843c749SSergey Zigachev 1033*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse 1034*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 1035*b843c749SSergey Zigachev 1036*b843c749SSergey Zigachev #define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level 1037*b843c749SSergey Zigachev #define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 1038*b843c749SSergey Zigachev 1039*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1040*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1041*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1042*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1043*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1044*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1045*b843c749SSergey Zigachev 1046*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1047*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1048*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1049*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1050*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1051*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse 1052*b843c749SSergey Zigachev 1053*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse 1054*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse 1055*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse 1056*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse 1057*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse 1058*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse 1059*b843c749SSergey Zigachev 1060*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1061*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 1062*b843c749SSergey Zigachev 1063*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1064*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 1065*b843c749SSergey Zigachev 1066*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1067*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 1068*b843c749SSergey Zigachev 1069*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1070*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 1071*b843c749SSergey Zigachev 1072*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1073*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 1074*b843c749SSergey Zigachev 1075*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1076*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 1077*b843c749SSergey Zigachev 1078*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1079*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 1080*b843c749SSergey Zigachev 1081*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1082*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 1083*b843c749SSergey Zigachev 1084*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1085*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 1086*b843c749SSergey Zigachev 1087*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1088*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 1089*b843c749SSergey Zigachev 1090*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1091*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 1092*b843c749SSergey Zigachev 1093*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1094*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 1095*b843c749SSergey Zigachev 1096*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1097*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 1098*b843c749SSergey Zigachev 1099*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1100*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 1101*b843c749SSergey Zigachev 1102*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1103*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 1104*b843c749SSergey Zigachev 1105*b843c749SSergey Zigachev #define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level 1106*b843c749SSergey Zigachev #define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 1107*b843c749SSergey Zigachev 1108*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1109*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1110*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1111*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1112*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1113*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1114*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1115*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1116*b843c749SSergey Zigachev 1117*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1118*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1119*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1120*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1121*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1122*b843c749SSergey Zigachev #define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse 1123*b843c749SSergey Zigachev 1124*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1125*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1126*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1127*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1128*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1129*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1130*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1131*b843c749SSergey Zigachev #define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse 1132*b843c749SSergey Zigachev 1133*b843c749SSergey Zigachev 1134*b843c749SSergey Zigachev #endif // __IRQSRCS_DCN_1_0_H__ 1135