xref: /dflybsd-src/sys/dev/drm/amd/include/amd_pcie.h (revision d78d3a2272f5ecf9e0b570e362128240417a1b85)
1*d78d3a22SFrançois Tigeot /*
2*d78d3a22SFrançois Tigeot  * Copyright 2015 Advanced Micro Devices, Inc.
3*d78d3a22SFrançois Tigeot  *
4*d78d3a22SFrançois Tigeot  * Permission is hereby granted, free of charge, to any person obtaining a
5*d78d3a22SFrançois Tigeot  * copy of this software and associated documentation files (the "Software"),
6*d78d3a22SFrançois Tigeot  * to deal in the Software without restriction, including without limitation
7*d78d3a22SFrançois Tigeot  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*d78d3a22SFrançois Tigeot  * and/or sell copies of the Software, and to permit persons to whom the
9*d78d3a22SFrançois Tigeot  * Software is furnished to do so, subject to the following conditions:
10*d78d3a22SFrançois Tigeot  *
11*d78d3a22SFrançois Tigeot  * The above copyright notice and this permission notice shall be included in
12*d78d3a22SFrançois Tigeot  * all copies or substantial portions of the Software.
13*d78d3a22SFrançois Tigeot  *
14*d78d3a22SFrançois Tigeot  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*d78d3a22SFrançois Tigeot  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*d78d3a22SFrançois Tigeot  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*d78d3a22SFrançois Tigeot  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*d78d3a22SFrançois Tigeot  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*d78d3a22SFrançois Tigeot  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*d78d3a22SFrançois Tigeot  * OTHER DEALINGS IN THE SOFTWARE.
21*d78d3a22SFrançois Tigeot  */
22*d78d3a22SFrançois Tigeot 
23*d78d3a22SFrançois Tigeot #ifndef __AMD_PCIE_H__
24*d78d3a22SFrançois Tigeot #define __AMD_PCIE_H__
25*d78d3a22SFrançois Tigeot 
26*d78d3a22SFrançois Tigeot /* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */
27*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1        0x00010000
28*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2        0x00020000
29*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3        0x00040000
30*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK        0xFFFF0000
31*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT       16
32*d78d3a22SFrançois Tigeot 
33*d78d3a22SFrançois Tigeot /* Following flags shows PCIe link speed supported by ASIC H/W.*/
34*d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1   0x00000001
35*d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2   0x00000002
36*d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3   0x00000004
37*d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK   0x0000FFFF
38*d78d3a22SFrançois Tigeot #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT  0
39*d78d3a22SFrançois Tigeot 
40*d78d3a22SFrançois Tigeot /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */
41*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1          0x00010000
42*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2          0x00020000
43*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4          0x00040000
44*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8          0x00080000
45*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12         0x00100000
46*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16         0x00200000
47*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32         0x00400000
48*d78d3a22SFrançois Tigeot #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT       16
49*d78d3a22SFrançois Tigeot 
50*d78d3a22SFrançois Tigeot #endif
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