1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef __DAL_GRPH_OBJECT_DEFS_H__ 27*b843c749SSergey Zigachev #define __DAL_GRPH_OBJECT_DEFS_H__ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #include "grph_object_id.h" 30*b843c749SSergey Zigachev 31*b843c749SSergey Zigachev /* ******************************************************************** 32*b843c749SSergey Zigachev * ******************************************************************** 33*b843c749SSergey Zigachev * 34*b843c749SSergey Zigachev * These defines shared between All Graphics Objects 35*b843c749SSergey Zigachev * 36*b843c749SSergey Zigachev * ******************************************************************** 37*b843c749SSergey Zigachev * ******************************************************************** 38*b843c749SSergey Zigachev */ 39*b843c749SSergey Zigachev 40*b843c749SSergey Zigachev #define MAX_CONNECTOR_NUMBER_PER_SLOT (16) 41*b843c749SSergey Zigachev #define MAX_BOARD_SLOTS (4) 42*b843c749SSergey Zigachev #define INVALID_CONNECTOR_INDEX ((unsigned int)(-1)) 43*b843c749SSergey Zigachev 44*b843c749SSergey Zigachev /* HPD unit id - HW direct translation */ 45*b843c749SSergey Zigachev enum hpd_source_id { 46*b843c749SSergey Zigachev HPD_SOURCEID1 = 0, 47*b843c749SSergey Zigachev HPD_SOURCEID2, 48*b843c749SSergey Zigachev HPD_SOURCEID3, 49*b843c749SSergey Zigachev HPD_SOURCEID4, 50*b843c749SSergey Zigachev HPD_SOURCEID5, 51*b843c749SSergey Zigachev HPD_SOURCEID6, 52*b843c749SSergey Zigachev 53*b843c749SSergey Zigachev HPD_SOURCEID_COUNT, 54*b843c749SSergey Zigachev HPD_SOURCEID_UNKNOWN 55*b843c749SSergey Zigachev }; 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev /* DDC unit id - HW direct translation */ 58*b843c749SSergey Zigachev enum channel_id { 59*b843c749SSergey Zigachev CHANNEL_ID_UNKNOWN = 0, 60*b843c749SSergey Zigachev CHANNEL_ID_DDC1, 61*b843c749SSergey Zigachev CHANNEL_ID_DDC2, 62*b843c749SSergey Zigachev CHANNEL_ID_DDC3, 63*b843c749SSergey Zigachev CHANNEL_ID_DDC4, 64*b843c749SSergey Zigachev CHANNEL_ID_DDC5, 65*b843c749SSergey Zigachev CHANNEL_ID_DDC6, 66*b843c749SSergey Zigachev CHANNEL_ID_DDC_VGA, 67*b843c749SSergey Zigachev CHANNEL_ID_I2C_PAD, 68*b843c749SSergey Zigachev CHANNEL_ID_COUNT 69*b843c749SSergey Zigachev }; 70*b843c749SSergey Zigachev 71*b843c749SSergey Zigachev #define DECODE_CHANNEL_ID(ch_id) \ 72*b843c749SSergey Zigachev (ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \ 73*b843c749SSergey Zigachev (ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \ 74*b843c749SSergey Zigachev (ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \ 75*b843c749SSergey Zigachev (ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \ 76*b843c749SSergey Zigachev (ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \ 77*b843c749SSergey Zigachev (ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \ 78*b843c749SSergey Zigachev (ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \ 79*b843c749SSergey Zigachev (ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid" 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev enum transmitter { 82*b843c749SSergey Zigachev TRANSMITTER_UNKNOWN = (-1L), 83*b843c749SSergey Zigachev TRANSMITTER_UNIPHY_A, 84*b843c749SSergey Zigachev TRANSMITTER_UNIPHY_B, 85*b843c749SSergey Zigachev TRANSMITTER_UNIPHY_C, 86*b843c749SSergey Zigachev TRANSMITTER_UNIPHY_D, 87*b843c749SSergey Zigachev TRANSMITTER_UNIPHY_E, 88*b843c749SSergey Zigachev TRANSMITTER_UNIPHY_F, 89*b843c749SSergey Zigachev TRANSMITTER_NUTMEG_CRT, 90*b843c749SSergey Zigachev TRANSMITTER_TRAVIS_CRT, 91*b843c749SSergey Zigachev TRANSMITTER_TRAVIS_LCD, 92*b843c749SSergey Zigachev TRANSMITTER_UNIPHY_G, 93*b843c749SSergey Zigachev TRANSMITTER_COUNT 94*b843c749SSergey Zigachev }; 95*b843c749SSergey Zigachev 96*b843c749SSergey Zigachev /* Generic source of the synchronisation input/output signal */ 97*b843c749SSergey Zigachev /* Can be used for flow control, stereo sync, timing sync, frame sync, etc */ 98*b843c749SSergey Zigachev enum sync_source { 99*b843c749SSergey Zigachev SYNC_SOURCE_NONE = 0, 100*b843c749SSergey Zigachev 101*b843c749SSergey Zigachev /* Source based on controllers */ 102*b843c749SSergey Zigachev SYNC_SOURCE_CONTROLLER0, 103*b843c749SSergey Zigachev SYNC_SOURCE_CONTROLLER1, 104*b843c749SSergey Zigachev SYNC_SOURCE_CONTROLLER2, 105*b843c749SSergey Zigachev SYNC_SOURCE_CONTROLLER3, 106*b843c749SSergey Zigachev SYNC_SOURCE_CONTROLLER4, 107*b843c749SSergey Zigachev SYNC_SOURCE_CONTROLLER5, 108*b843c749SSergey Zigachev 109*b843c749SSergey Zigachev /* Source based on GSL group */ 110*b843c749SSergey Zigachev SYNC_SOURCE_GSL_GROUP0, 111*b843c749SSergey Zigachev SYNC_SOURCE_GSL_GROUP1, 112*b843c749SSergey Zigachev SYNC_SOURCE_GSL_GROUP2, 113*b843c749SSergey Zigachev 114*b843c749SSergey Zigachev /* Source based on GSL IOs */ 115*b843c749SSergey Zigachev /* These IOs normally used as GSL input/output */ 116*b843c749SSergey Zigachev SYNC_SOURCE_GSL_IO_FIRST, 117*b843c749SSergey Zigachev SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST, 118*b843c749SSergey Zigachev SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC, 119*b843c749SSergey Zigachev SYNC_SOURCE_GSL_IO_SWAPLOCK_A, 120*b843c749SSergey Zigachev SYNC_SOURCE_GSL_IO_SWAPLOCK_B, 121*b843c749SSergey Zigachev SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B, 122*b843c749SSergey Zigachev 123*b843c749SSergey Zigachev /* Source based on regular IOs */ 124*b843c749SSergey Zigachev SYNC_SOURCE_IO_FIRST, 125*b843c749SSergey Zigachev SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST, 126*b843c749SSergey Zigachev SYNC_SOURCE_IO_GENERIC_B, 127*b843c749SSergey Zigachev SYNC_SOURCE_IO_GENERIC_C, 128*b843c749SSergey Zigachev SYNC_SOURCE_IO_GENERIC_D, 129*b843c749SSergey Zigachev SYNC_SOURCE_IO_GENERIC_E, 130*b843c749SSergey Zigachev SYNC_SOURCE_IO_GENERIC_F, 131*b843c749SSergey Zigachev SYNC_SOURCE_IO_HPD1, 132*b843c749SSergey Zigachev SYNC_SOURCE_IO_HPD2, 133*b843c749SSergey Zigachev SYNC_SOURCE_IO_HSYNC_A, 134*b843c749SSergey Zigachev SYNC_SOURCE_IO_VSYNC_A, 135*b843c749SSergey Zigachev SYNC_SOURCE_IO_HSYNC_B, 136*b843c749SSergey Zigachev SYNC_SOURCE_IO_VSYNC_B, 137*b843c749SSergey Zigachev SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B, 138*b843c749SSergey Zigachev 139*b843c749SSergey Zigachev /* Misc. flow control sources */ 140*b843c749SSergey Zigachev SYNC_SOURCE_DUAL_GPU_PIN 141*b843c749SSergey Zigachev }; 142*b843c749SSergey Zigachev 143*b843c749SSergey Zigachev /* connector sizes in millimeters - from BiosParserTypes.hpp */ 144*b843c749SSergey Zigachev #define CONNECTOR_SIZE_DVI 40 145*b843c749SSergey Zigachev #define CONNECTOR_SIZE_VGA 32 146*b843c749SSergey Zigachev #define CONNECTOR_SIZE_HDMI 16 147*b843c749SSergey Zigachev #define CONNECTOR_SIZE_DP 16 148*b843c749SSergey Zigachev #define CONNECTOR_SIZE_MINI_DP 9 149*b843c749SSergey Zigachev #define CONNECTOR_SIZE_UNKNOWN 30 150*b843c749SSergey Zigachev 151*b843c749SSergey Zigachev enum connector_layout_type { 152*b843c749SSergey Zigachev CONNECTOR_LAYOUT_TYPE_UNKNOWN, 153*b843c749SSergey Zigachev CONNECTOR_LAYOUT_TYPE_DVI_D, 154*b843c749SSergey Zigachev CONNECTOR_LAYOUT_TYPE_DVI_I, 155*b843c749SSergey Zigachev CONNECTOR_LAYOUT_TYPE_VGA, 156*b843c749SSergey Zigachev CONNECTOR_LAYOUT_TYPE_HDMI, 157*b843c749SSergey Zigachev CONNECTOR_LAYOUT_TYPE_DP, 158*b843c749SSergey Zigachev CONNECTOR_LAYOUT_TYPE_MINI_DP, 159*b843c749SSergey Zigachev }; 160*b843c749SSergey Zigachev struct connector_layout_info { 161*b843c749SSergey Zigachev struct graphics_object_id connector_id; 162*b843c749SSergey Zigachev enum connector_layout_type connector_type; 163*b843c749SSergey Zigachev unsigned int length; 164*b843c749SSergey Zigachev unsigned int position; /* offset in mm from right side of the board */ 165*b843c749SSergey Zigachev }; 166*b843c749SSergey Zigachev 167*b843c749SSergey Zigachev /* length and width in mm */ 168*b843c749SSergey Zigachev struct slot_layout_info { 169*b843c749SSergey Zigachev unsigned int length; 170*b843c749SSergey Zigachev unsigned int width; 171*b843c749SSergey Zigachev unsigned int num_of_connectors; 172*b843c749SSergey Zigachev struct connector_layout_info connectors[MAX_CONNECTOR_NUMBER_PER_SLOT]; 173*b843c749SSergey Zigachev }; 174*b843c749SSergey Zigachev 175*b843c749SSergey Zigachev struct board_layout_info { 176*b843c749SSergey Zigachev unsigned int num_of_slots; 177*b843c749SSergey Zigachev 178*b843c749SSergey Zigachev /* indicates valid information in bracket layout structure. */ 179*b843c749SSergey Zigachev unsigned int is_number_of_slots_valid : 1; 180*b843c749SSergey Zigachev unsigned int is_slots_size_valid : 1; 181*b843c749SSergey Zigachev unsigned int is_connector_offsets_valid : 1; 182*b843c749SSergey Zigachev unsigned int is_connector_lengths_valid : 1; 183*b843c749SSergey Zigachev 184*b843c749SSergey Zigachev struct slot_layout_info slots[MAX_BOARD_SLOTS]; 185*b843c749SSergey Zigachev }; 186*b843c749SSergey Zigachev #endif 187