xref: /dflybsd-src/sys/dev/drm/amd/display/dc/inc/reg_helper.h (revision b843c749addef9340ee7d4e250b09fdd492602a1)
1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev  * Copyright 2016 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev  *
4*b843c749SSergey Zigachev  * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev  * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev  * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev  * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev  * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev  *
11*b843c749SSergey Zigachev  * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev  * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev  *
14*b843c749SSergey Zigachev  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*b843c749SSergey Zigachev  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev  * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev  *
22*b843c749SSergey Zigachev  * Authors: AMD
23*b843c749SSergey Zigachev  */
24*b843c749SSergey Zigachev 
25*b843c749SSergey Zigachev #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
26*b843c749SSergey Zigachev #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_
27*b843c749SSergey Zigachev 
28*b843c749SSergey Zigachev #include "dm_services.h"
29*b843c749SSergey Zigachev 
30*b843c749SSergey Zigachev /* macro for register read/write
31*b843c749SSergey Zigachev  * user of macro need to define
32*b843c749SSergey Zigachev  *
33*b843c749SSergey Zigachev  * CTX ==> macro to ptr to dc_context
34*b843c749SSergey Zigachev  *    eg. aud110->base.ctx
35*b843c749SSergey Zigachev  *
36*b843c749SSergey Zigachev  * REG ==> macro to location of register offset
37*b843c749SSergey Zigachev  *    eg. aud110->regs->reg
38*b843c749SSergey Zigachev  */
39*b843c749SSergey Zigachev #define REG_READ(reg_name) \
40*b843c749SSergey Zigachev 		dm_read_reg(CTX, REG(reg_name))
41*b843c749SSergey Zigachev 
42*b843c749SSergey Zigachev #define REG_WRITE(reg_name, value) \
43*b843c749SSergey Zigachev 		dm_write_reg(CTX, REG(reg_name), value)
44*b843c749SSergey Zigachev 
45*b843c749SSergey Zigachev #ifdef REG_SET
46*b843c749SSergey Zigachev #undef REG_SET
47*b843c749SSergey Zigachev #endif
48*b843c749SSergey Zigachev 
49*b843c749SSergey Zigachev #ifdef REG_GET
50*b843c749SSergey Zigachev #undef REG_GET
51*b843c749SSergey Zigachev #endif
52*b843c749SSergey Zigachev 
53*b843c749SSergey Zigachev /* macro to set register fields. */
54*b843c749SSergey Zigachev #define REG_SET_N(reg_name, n, initial_val, ...)	\
55*b843c749SSergey Zigachev 		generic_reg_update_ex(CTX, \
56*b843c749SSergey Zigachev 				REG(reg_name), \
57*b843c749SSergey Zigachev 				initial_val, \
58*b843c749SSergey Zigachev 				n, __VA_ARGS__)
59*b843c749SSergey Zigachev 
60*b843c749SSergey Zigachev #define FN(reg_name, field) \
61*b843c749SSergey Zigachev 	FD(reg_name##__##field)
62*b843c749SSergey Zigachev 
63*b843c749SSergey Zigachev #define REG_SET(reg_name, initial_val, field, val)	\
64*b843c749SSergey Zigachev 		REG_SET_N(reg_name, 1, initial_val, \
65*b843c749SSergey Zigachev 				FN(reg_name, field), val)
66*b843c749SSergey Zigachev 
67*b843c749SSergey Zigachev #define REG_SET_2(reg, init_value, f1, v1, f2, v2)	\
68*b843c749SSergey Zigachev 		REG_SET_N(reg, 2, init_value, \
69*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
70*b843c749SSergey Zigachev 				FN(reg, f2), v2)
71*b843c749SSergey Zigachev 
72*b843c749SSergey Zigachev #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3)	\
73*b843c749SSergey Zigachev 		REG_SET_N(reg, 3, init_value, \
74*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
75*b843c749SSergey Zigachev 				FN(reg, f2), v2,\
76*b843c749SSergey Zigachev 				FN(reg, f3), v3)
77*b843c749SSergey Zigachev 
78*b843c749SSergey Zigachev #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4)	\
79*b843c749SSergey Zigachev 		REG_SET_N(reg, 4, init_value, \
80*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
81*b843c749SSergey Zigachev 				FN(reg, f2), v2,\
82*b843c749SSergey Zigachev 				FN(reg, f3), v3,\
83*b843c749SSergey Zigachev 				FN(reg, f4), v4)
84*b843c749SSergey Zigachev 
85*b843c749SSergey Zigachev #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
86*b843c749SSergey Zigachev 		f5, v5)	\
87*b843c749SSergey Zigachev 		REG_SET_N(reg, 5, init_value, \
88*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
89*b843c749SSergey Zigachev 				FN(reg, f2), v2,\
90*b843c749SSergey Zigachev 				FN(reg, f3), v3,\
91*b843c749SSergey Zigachev 				FN(reg, f4), v4,\
92*b843c749SSergey Zigachev 				FN(reg, f5), v5)
93*b843c749SSergey Zigachev 
94*b843c749SSergey Zigachev #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
95*b843c749SSergey Zigachev 		f5, v5, f6, v6)	\
96*b843c749SSergey Zigachev 		REG_SET_N(reg, 6, init_value, \
97*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
98*b843c749SSergey Zigachev 				FN(reg, f2), v2,\
99*b843c749SSergey Zigachev 				FN(reg, f3), v3,\
100*b843c749SSergey Zigachev 				FN(reg, f4), v4,\
101*b843c749SSergey Zigachev 				FN(reg, f5), v5,\
102*b843c749SSergey Zigachev 				FN(reg, f6), v6)
103*b843c749SSergey Zigachev 
104*b843c749SSergey Zigachev #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
105*b843c749SSergey Zigachev 		f5, v5, f6, v6, f7, v7)	\
106*b843c749SSergey Zigachev 		REG_SET_N(reg, 7, init_value, \
107*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
108*b843c749SSergey Zigachev 				FN(reg, f2), v2,\
109*b843c749SSergey Zigachev 				FN(reg, f3), v3,\
110*b843c749SSergey Zigachev 				FN(reg, f4), v4,\
111*b843c749SSergey Zigachev 				FN(reg, f5), v5,\
112*b843c749SSergey Zigachev 				FN(reg, f6), v6,\
113*b843c749SSergey Zigachev 				FN(reg, f7), v7)
114*b843c749SSergey Zigachev 
115*b843c749SSergey Zigachev #define REG_SET_8(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4,	\
116*b843c749SSergey Zigachev 		f5, v5, f6, v6, f7, v7, f8, v8)	\
117*b843c749SSergey Zigachev 		REG_SET_N(reg, 8, init_value, \
118*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
119*b843c749SSergey Zigachev 				FN(reg, f2), v2,\
120*b843c749SSergey Zigachev 				FN(reg, f3), v3,\
121*b843c749SSergey Zigachev 				FN(reg, f4), v4,\
122*b843c749SSergey Zigachev 				FN(reg, f5), v5,\
123*b843c749SSergey Zigachev 				FN(reg, f6), v6,\
124*b843c749SSergey Zigachev 				FN(reg, f7), v7,\
125*b843c749SSergey Zigachev 				FN(reg, f8), v8)
126*b843c749SSergey Zigachev 
127*b843c749SSergey Zigachev #define REG_SET_9(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
128*b843c749SSergey Zigachev 		v5, f6, v6, f7, v7, f8, v8, f9, v9)	\
129*b843c749SSergey Zigachev 		REG_SET_N(reg, 9, init_value, \
130*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
131*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
132*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
133*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
134*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
135*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
136*b843c749SSergey Zigachev 				FN(reg, f7), v7, \
137*b843c749SSergey Zigachev 				FN(reg, f8), v8, \
138*b843c749SSergey Zigachev 				FN(reg, f9), v9)
139*b843c749SSergey Zigachev 
140*b843c749SSergey Zigachev #define REG_SET_10(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, f5, \
141*b843c749SSergey Zigachev 		v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)	\
142*b843c749SSergey Zigachev 		REG_SET_N(reg, 10, init_value, \
143*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
144*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
145*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
146*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
147*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
148*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
149*b843c749SSergey Zigachev 				FN(reg, f7), v7, \
150*b843c749SSergey Zigachev 				FN(reg, f8), v8, \
151*b843c749SSergey Zigachev 				FN(reg, f9), v9, \
152*b843c749SSergey Zigachev 				FN(reg, f10), v10)
153*b843c749SSergey Zigachev 
154*b843c749SSergey Zigachev /* macro to get register fields
155*b843c749SSergey Zigachev  * read given register and fill in field value in output parameter */
156*b843c749SSergey Zigachev #define REG_GET(reg_name, field, val)	\
157*b843c749SSergey Zigachev 		generic_reg_get(CTX, REG(reg_name), \
158*b843c749SSergey Zigachev 				FN(reg_name, field), val)
159*b843c749SSergey Zigachev 
160*b843c749SSergey Zigachev #define REG_GET_2(reg_name, f1, v1, f2, v2)	\
161*b843c749SSergey Zigachev 		generic_reg_get2(CTX, REG(reg_name), \
162*b843c749SSergey Zigachev 				FN(reg_name, f1), v1, \
163*b843c749SSergey Zigachev 				FN(reg_name, f2), v2)
164*b843c749SSergey Zigachev 
165*b843c749SSergey Zigachev #define REG_GET_3(reg_name, f1, v1, f2, v2, f3, v3)	\
166*b843c749SSergey Zigachev 		generic_reg_get3(CTX, REG(reg_name), \
167*b843c749SSergey Zigachev 				FN(reg_name, f1), v1, \
168*b843c749SSergey Zigachev 				FN(reg_name, f2), v2, \
169*b843c749SSergey Zigachev 				FN(reg_name, f3), v3)
170*b843c749SSergey Zigachev 
171*b843c749SSergey Zigachev #define REG_GET_4(reg_name, f1, v1, f2, v2, f3, v3, f4, v4)	\
172*b843c749SSergey Zigachev 		generic_reg_get4(CTX, REG(reg_name), \
173*b843c749SSergey Zigachev 				FN(reg_name, f1), v1, \
174*b843c749SSergey Zigachev 				FN(reg_name, f2), v2, \
175*b843c749SSergey Zigachev 				FN(reg_name, f3), v3, \
176*b843c749SSergey Zigachev 				FN(reg_name, f4), v4)
177*b843c749SSergey Zigachev 
178*b843c749SSergey Zigachev #define REG_GET_5(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)	\
179*b843c749SSergey Zigachev 		generic_reg_get5(CTX, REG(reg_name), \
180*b843c749SSergey Zigachev 				FN(reg_name, f1), v1, \
181*b843c749SSergey Zigachev 				FN(reg_name, f2), v2, \
182*b843c749SSergey Zigachev 				FN(reg_name, f3), v3, \
183*b843c749SSergey Zigachev 				FN(reg_name, f4), v4, \
184*b843c749SSergey Zigachev 				FN(reg_name, f5), v5)
185*b843c749SSergey Zigachev 
186*b843c749SSergey Zigachev #define REG_GET_6(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)	\
187*b843c749SSergey Zigachev 		generic_reg_get6(CTX, REG(reg_name), \
188*b843c749SSergey Zigachev 				FN(reg_name, f1), v1, \
189*b843c749SSergey Zigachev 				FN(reg_name, f2), v2, \
190*b843c749SSergey Zigachev 				FN(reg_name, f3), v3, \
191*b843c749SSergey Zigachev 				FN(reg_name, f4), v4, \
192*b843c749SSergey Zigachev 				FN(reg_name, f5), v5, \
193*b843c749SSergey Zigachev 				FN(reg_name, f6), v6)
194*b843c749SSergey Zigachev 
195*b843c749SSergey Zigachev #define REG_GET_7(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)	\
196*b843c749SSergey Zigachev 		generic_reg_get7(CTX, REG(reg_name), \
197*b843c749SSergey Zigachev 				FN(reg_name, f1), v1, \
198*b843c749SSergey Zigachev 				FN(reg_name, f2), v2, \
199*b843c749SSergey Zigachev 				FN(reg_name, f3), v3, \
200*b843c749SSergey Zigachev 				FN(reg_name, f4), v4, \
201*b843c749SSergey Zigachev 				FN(reg_name, f5), v5, \
202*b843c749SSergey Zigachev 				FN(reg_name, f6), v6, \
203*b843c749SSergey Zigachev 				FN(reg_name, f7), v7)
204*b843c749SSergey Zigachev 
205*b843c749SSergey Zigachev #define REG_GET_8(reg_name, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)	\
206*b843c749SSergey Zigachev 		generic_reg_get8(CTX, REG(reg_name), \
207*b843c749SSergey Zigachev 				FN(reg_name, f1), v1, \
208*b843c749SSergey Zigachev 				FN(reg_name, f2), v2, \
209*b843c749SSergey Zigachev 				FN(reg_name, f3), v3, \
210*b843c749SSergey Zigachev 				FN(reg_name, f4), v4, \
211*b843c749SSergey Zigachev 				FN(reg_name, f5), v5, \
212*b843c749SSergey Zigachev 				FN(reg_name, f6), v6, \
213*b843c749SSergey Zigachev 				FN(reg_name, f7), v7, \
214*b843c749SSergey Zigachev 				FN(reg_name, f8), v8)
215*b843c749SSergey Zigachev 
216*b843c749SSergey Zigachev /* macro to poll and wait for a register field to read back given value */
217*b843c749SSergey Zigachev 
218*b843c749SSergey Zigachev #define REG_WAIT(reg_name, field, val, delay_between_poll_us, max_try)	\
219*b843c749SSergey Zigachev 		generic_reg_wait(CTX, \
220*b843c749SSergey Zigachev 				REG(reg_name), FN(reg_name, field), val,\
221*b843c749SSergey Zigachev 				delay_between_poll_us, max_try, __func__, __LINE__)
222*b843c749SSergey Zigachev 
223*b843c749SSergey Zigachev /* macro to update (read, modify, write) register fields
224*b843c749SSergey Zigachev  */
225*b843c749SSergey Zigachev #define REG_UPDATE_N(reg_name, n, ...)	\
226*b843c749SSergey Zigachev 		generic_reg_update_ex(CTX, \
227*b843c749SSergey Zigachev 				REG(reg_name), \
228*b843c749SSergey Zigachev 				REG_READ(reg_name), \
229*b843c749SSergey Zigachev 				n, __VA_ARGS__)
230*b843c749SSergey Zigachev 
231*b843c749SSergey Zigachev #define REG_UPDATE(reg_name, field, val)	\
232*b843c749SSergey Zigachev 		REG_UPDATE_N(reg_name, 1, \
233*b843c749SSergey Zigachev 				FN(reg_name, field), val)
234*b843c749SSergey Zigachev 
235*b843c749SSergey Zigachev #define REG_UPDATE_2(reg, f1, v1, f2, v2)	\
236*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 2,\
237*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
238*b843c749SSergey Zigachev 				FN(reg, f2), v2)
239*b843c749SSergey Zigachev 
240*b843c749SSergey Zigachev #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3)	\
241*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 3, \
242*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
243*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
244*b843c749SSergey Zigachev 				FN(reg, f3), v3)
245*b843c749SSergey Zigachev 
246*b843c749SSergey Zigachev #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4)	\
247*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 4, \
248*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
249*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
250*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
251*b843c749SSergey Zigachev 				FN(reg, f4), v4)
252*b843c749SSergey Zigachev 
253*b843c749SSergey Zigachev #define REG_UPDATE_5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5)	\
254*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 5, \
255*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
256*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
257*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
258*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
259*b843c749SSergey Zigachev 				FN(reg, f5), v5)
260*b843c749SSergey Zigachev 
261*b843c749SSergey Zigachev #define REG_UPDATE_6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6)	\
262*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 6, \
263*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
264*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
265*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
266*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
267*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
268*b843c749SSergey Zigachev 				FN(reg, f6), v6)
269*b843c749SSergey Zigachev 
270*b843c749SSergey Zigachev #define REG_UPDATE_7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7)	\
271*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 7, \
272*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
273*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
274*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
275*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
276*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
277*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
278*b843c749SSergey Zigachev 				FN(reg, f7), v7)
279*b843c749SSergey Zigachev 
280*b843c749SSergey Zigachev #define REG_UPDATE_8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8)	\
281*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 8, \
282*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
283*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
284*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
285*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
286*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
287*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
288*b843c749SSergey Zigachev 				FN(reg, f7), v7, \
289*b843c749SSergey Zigachev 				FN(reg, f8), v8)
290*b843c749SSergey Zigachev 
291*b843c749SSergey Zigachev #define REG_UPDATE_9(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9)	\
292*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 9, \
293*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
294*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
295*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
296*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
297*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
298*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
299*b843c749SSergey Zigachev 				FN(reg, f7), v7, \
300*b843c749SSergey Zigachev 				FN(reg, f8), v8, \
301*b843c749SSergey Zigachev 				FN(reg, f9), v9)
302*b843c749SSergey Zigachev 
303*b843c749SSergey Zigachev #define REG_UPDATE_10(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10, v10)\
304*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 10, \
305*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
306*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
307*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
308*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
309*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
310*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
311*b843c749SSergey Zigachev 				FN(reg, f7), v7, \
312*b843c749SSergey Zigachev 				FN(reg, f8), v8, \
313*b843c749SSergey Zigachev 				FN(reg, f9), v9, \
314*b843c749SSergey Zigachev 				FN(reg, f10), v10)
315*b843c749SSergey Zigachev 
316*b843c749SSergey Zigachev #define REG_UPDATE_14(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
317*b843c749SSergey Zigachev 		v10, f11, v11, f12, v12, f13, v13, f14, v14)\
318*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 14, \
319*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
320*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
321*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
322*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
323*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
324*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
325*b843c749SSergey Zigachev 				FN(reg, f7), v7, \
326*b843c749SSergey Zigachev 				FN(reg, f8), v8, \
327*b843c749SSergey Zigachev 				FN(reg, f9), v9, \
328*b843c749SSergey Zigachev 				FN(reg, f10), v10, \
329*b843c749SSergey Zigachev 				FN(reg, f11), v11, \
330*b843c749SSergey Zigachev 				FN(reg, f12), v12, \
331*b843c749SSergey Zigachev 				FN(reg, f13), v13, \
332*b843c749SSergey Zigachev 				FN(reg, f14), v14)
333*b843c749SSergey Zigachev 
334*b843c749SSergey Zigachev #define REG_UPDATE_19(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
335*b843c749SSergey Zigachev 		v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19)\
336*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 19, \
337*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
338*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
339*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
340*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
341*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
342*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
343*b843c749SSergey Zigachev 				FN(reg, f7), v7, \
344*b843c749SSergey Zigachev 				FN(reg, f8), v8, \
345*b843c749SSergey Zigachev 				FN(reg, f9), v9, \
346*b843c749SSergey Zigachev 				FN(reg, f10), v10, \
347*b843c749SSergey Zigachev 				FN(reg, f11), v11, \
348*b843c749SSergey Zigachev 				FN(reg, f12), v12, \
349*b843c749SSergey Zigachev 				FN(reg, f13), v13, \
350*b843c749SSergey Zigachev 				FN(reg, f14), v14, \
351*b843c749SSergey Zigachev 				FN(reg, f15), v15, \
352*b843c749SSergey Zigachev 				FN(reg, f16), v16, \
353*b843c749SSergey Zigachev 				FN(reg, f17), v17, \
354*b843c749SSergey Zigachev 				FN(reg, f18), v18, \
355*b843c749SSergey Zigachev 				FN(reg, f19), v19)
356*b843c749SSergey Zigachev 
357*b843c749SSergey Zigachev #define REG_UPDATE_20(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8, f9, v9, f10,\
358*b843c749SSergey Zigachev 		v10, f11, v11, f12, v12, f13, v13, f14, v14, f15, v15, f16, v16, f17, v17, f18, v18, f19, v19, f20, v20)\
359*b843c749SSergey Zigachev 		REG_UPDATE_N(reg, 20, \
360*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
361*b843c749SSergey Zigachev 				FN(reg, f2), v2, \
362*b843c749SSergey Zigachev 				FN(reg, f3), v3, \
363*b843c749SSergey Zigachev 				FN(reg, f4), v4, \
364*b843c749SSergey Zigachev 				FN(reg, f5), v5, \
365*b843c749SSergey Zigachev 				FN(reg, f6), v6, \
366*b843c749SSergey Zigachev 				FN(reg, f7), v7, \
367*b843c749SSergey Zigachev 				FN(reg, f8), v8, \
368*b843c749SSergey Zigachev 				FN(reg, f9), v9, \
369*b843c749SSergey Zigachev 				FN(reg, f10), v10, \
370*b843c749SSergey Zigachev 				FN(reg, f11), v11, \
371*b843c749SSergey Zigachev 				FN(reg, f12), v12, \
372*b843c749SSergey Zigachev 				FN(reg, f13), v13, \
373*b843c749SSergey Zigachev 				FN(reg, f14), v14, \
374*b843c749SSergey Zigachev 				FN(reg, f15), v15, \
375*b843c749SSergey Zigachev 				FN(reg, f16), v16, \
376*b843c749SSergey Zigachev 				FN(reg, f17), v17, \
377*b843c749SSergey Zigachev 				FN(reg, f18), v18, \
378*b843c749SSergey Zigachev 				FN(reg, f19), v19, \
379*b843c749SSergey Zigachev 				FN(reg, f20), v20)
380*b843c749SSergey Zigachev /* macro to update a register field to specified values in given sequences.
381*b843c749SSergey Zigachev  * useful when toggling bits
382*b843c749SSergey Zigachev  */
383*b843c749SSergey Zigachev #define REG_UPDATE_SEQ(reg, field, value1, value2) \
384*b843c749SSergey Zigachev {	uint32_t val = REG_UPDATE(reg, field, value1); \
385*b843c749SSergey Zigachev 	REG_SET(reg, val, field, value2); }
386*b843c749SSergey Zigachev 
387*b843c749SSergey Zigachev /* macro to update fields in register 1 field at a time in given order */
388*b843c749SSergey Zigachev #define REG_UPDATE_1BY1_2(reg, f1, v1, f2, v2) \
389*b843c749SSergey Zigachev {	uint32_t val = REG_UPDATE(reg, f1, v1); \
390*b843c749SSergey Zigachev 	REG_SET(reg, val, f2, v2); }
391*b843c749SSergey Zigachev 
392*b843c749SSergey Zigachev #define REG_UPDATE_1BY1_3(reg, f1, v1, f2, v2, f3, v3) \
393*b843c749SSergey Zigachev {	uint32_t val = REG_UPDATE(reg, f1, v1); \
394*b843c749SSergey Zigachev 	val = REG_SET(reg, val, f2, v2); \
395*b843c749SSergey Zigachev 	REG_SET(reg, val, f3, v3); }
396*b843c749SSergey Zigachev 
397*b843c749SSergey Zigachev uint32_t generic_reg_get(const struct dc_context *ctx, uint32_t addr,
398*b843c749SSergey Zigachev 		uint8_t shift, uint32_t mask, uint32_t *field_value);
399*b843c749SSergey Zigachev 
400*b843c749SSergey Zigachev uint32_t generic_reg_get2(const struct dc_context *ctx, uint32_t addr,
401*b843c749SSergey Zigachev 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
402*b843c749SSergey Zigachev 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2);
403*b843c749SSergey Zigachev 
404*b843c749SSergey Zigachev uint32_t generic_reg_get3(const struct dc_context *ctx, uint32_t addr,
405*b843c749SSergey Zigachev 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
406*b843c749SSergey Zigachev 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
407*b843c749SSergey Zigachev 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3);
408*b843c749SSergey Zigachev 
409*b843c749SSergey Zigachev uint32_t generic_reg_get4(const struct dc_context *ctx, uint32_t addr,
410*b843c749SSergey Zigachev 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
411*b843c749SSergey Zigachev 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
412*b843c749SSergey Zigachev 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
413*b843c749SSergey Zigachev 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4);
414*b843c749SSergey Zigachev 
415*b843c749SSergey Zigachev uint32_t generic_reg_get5(const struct dc_context *ctx, uint32_t addr,
416*b843c749SSergey Zigachev 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
417*b843c749SSergey Zigachev 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
418*b843c749SSergey Zigachev 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
419*b843c749SSergey Zigachev 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
420*b843c749SSergey Zigachev 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
421*b843c749SSergey Zigachev 
422*b843c749SSergey Zigachev uint32_t generic_reg_get6(const struct dc_context *ctx, uint32_t addr,
423*b843c749SSergey Zigachev 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
424*b843c749SSergey Zigachev 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
425*b843c749SSergey Zigachev 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
426*b843c749SSergey Zigachev 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
427*b843c749SSergey Zigachev 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
428*b843c749SSergey Zigachev 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6);
429*b843c749SSergey Zigachev 
430*b843c749SSergey Zigachev uint32_t generic_reg_get7(const struct dc_context *ctx, uint32_t addr,
431*b843c749SSergey Zigachev 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
432*b843c749SSergey Zigachev 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
433*b843c749SSergey Zigachev 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
434*b843c749SSergey Zigachev 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
435*b843c749SSergey Zigachev 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
436*b843c749SSergey Zigachev 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
437*b843c749SSergey Zigachev 		uint8_t shift7, uint32_t mask7, uint32_t *field_value7);
438*b843c749SSergey Zigachev 
439*b843c749SSergey Zigachev uint32_t generic_reg_get8(const struct dc_context *ctx, uint32_t addr,
440*b843c749SSergey Zigachev 		uint8_t shift1, uint32_t mask1, uint32_t *field_value1,
441*b843c749SSergey Zigachev 		uint8_t shift2, uint32_t mask2, uint32_t *field_value2,
442*b843c749SSergey Zigachev 		uint8_t shift3, uint32_t mask3, uint32_t *field_value3,
443*b843c749SSergey Zigachev 		uint8_t shift4, uint32_t mask4, uint32_t *field_value4,
444*b843c749SSergey Zigachev 		uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
445*b843c749SSergey Zigachev 		uint8_t shift6, uint32_t mask6, uint32_t *field_value6,
446*b843c749SSergey Zigachev 		uint8_t shift7, uint32_t mask7, uint32_t *field_value7,
447*b843c749SSergey Zigachev 		uint8_t shift8, uint32_t mask8, uint32_t *field_value8);
448*b843c749SSergey Zigachev 
449*b843c749SSergey Zigachev 
450*b843c749SSergey Zigachev /* indirect register access */
451*b843c749SSergey Zigachev 
452*b843c749SSergey Zigachev #define IX_REG_SET_N(index_reg_name, data_reg_name, index, n, initial_val, ...)	\
453*b843c749SSergey Zigachev 		generic_indirect_reg_update_ex(CTX, \
454*b843c749SSergey Zigachev 				REG(index_reg_name), REG(data_reg_name), IND_REG(index), \
455*b843c749SSergey Zigachev 				initial_val, \
456*b843c749SSergey Zigachev 				n, __VA_ARGS__)
457*b843c749SSergey Zigachev 
458*b843c749SSergey Zigachev #define IX_REG_SET_2(index_reg_name, data_reg_name, index, init_value, f1, v1, f2, v2)	\
459*b843c749SSergey Zigachev 		IX_REG_SET_N(index_reg_name, data_reg_name, index, 2, init_value, \
460*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
461*b843c749SSergey Zigachev 				FN(reg, f2), v2)
462*b843c749SSergey Zigachev 
463*b843c749SSergey Zigachev 
464*b843c749SSergey Zigachev #define IX_REG_READ(index_reg_name, data_reg_name, index) \
465*b843c749SSergey Zigachev 		generic_read_indirect_reg(CTX, REG(index_reg_name), REG(data_reg_name), IND_REG(index))
466*b843c749SSergey Zigachev 
467*b843c749SSergey Zigachev 
468*b843c749SSergey Zigachev 
469*b843c749SSergey Zigachev #define IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, n, ...)	\
470*b843c749SSergey Zigachev 		generic_indirect_reg_update_ex(CTX, \
471*b843c749SSergey Zigachev 				REG(index_reg_name), REG(data_reg_name), IND_REG(index), \
472*b843c749SSergey Zigachev 				IX_REG_READ(index_reg_name, data_reg_name, index), \
473*b843c749SSergey Zigachev 				n, __VA_ARGS__)
474*b843c749SSergey Zigachev 
475*b843c749SSergey Zigachev #define IX_REG_UPDATE_2(index_reg_name, data_reg_name, index, f1, v1, f2, v2)	\
476*b843c749SSergey Zigachev 		IX_REG_UPDATE_N(index_reg_name, data_reg_name, index, 2,\
477*b843c749SSergey Zigachev 				FN(reg, f1), v1,\
478*b843c749SSergey Zigachev 				FN(reg, f2), v2)
479*b843c749SSergey Zigachev 
480*b843c749SSergey Zigachev void generic_write_indirect_reg(const struct dc_context *ctx,
481*b843c749SSergey Zigachev 		uint32_t addr_index, uint32_t addr_data,
482*b843c749SSergey Zigachev 		uint32_t index, uint32_t data);
483*b843c749SSergey Zigachev 
484*b843c749SSergey Zigachev uint32_t generic_read_indirect_reg(const struct dc_context *ctx,
485*b843c749SSergey Zigachev 		uint32_t addr_index, uint32_t addr_data,
486*b843c749SSergey Zigachev 		uint32_t index);
487*b843c749SSergey Zigachev 
488*b843c749SSergey Zigachev uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
489*b843c749SSergey Zigachev 		uint32_t addr_index, uint32_t addr_data,
490*b843c749SSergey Zigachev 		uint32_t index, uint32_t reg_val, int n,
491*b843c749SSergey Zigachev 		uint8_t shift1, uint32_t mask1, uint32_t field_value1,
492*b843c749SSergey Zigachev 		...);
493*b843c749SSergey Zigachev 
494*b843c749SSergey Zigachev #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_REG_HELPER_H_ */
495