xref: /dflybsd-src/sys/dev/drm/amd/display/dc/inc/hw/aux_engine.h (revision b843c749addef9340ee7d4e250b09fdd492602a1)
1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev  * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev  *
4*b843c749SSergey Zigachev  * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev  * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev  * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev  * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev  * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev  *
11*b843c749SSergey Zigachev  * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev  * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev  *
14*b843c749SSergey Zigachev  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*b843c749SSergey Zigachev  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev  * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev  *
22*b843c749SSergey Zigachev  * Authors: AMD
23*b843c749SSergey Zigachev  *
24*b843c749SSergey Zigachev  */
25*b843c749SSergey Zigachev 
26*b843c749SSergey Zigachev #ifndef __DAL_AUX_ENGINE_H__
27*b843c749SSergey Zigachev #define __DAL_AUX_ENGINE_H__
28*b843c749SSergey Zigachev 
29*b843c749SSergey Zigachev #include "dc_ddc_types.h"
30*b843c749SSergey Zigachev #include "include/i2caux_interface.h"
31*b843c749SSergey Zigachev 
32*b843c749SSergey Zigachev enum i2caux_transaction_operation {
33*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_READ,
34*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_WRITE
35*b843c749SSergey Zigachev };
36*b843c749SSergey Zigachev 
37*b843c749SSergey Zigachev enum i2caux_transaction_address_space {
38*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
39*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
40*b843c749SSergey Zigachev };
41*b843c749SSergey Zigachev 
42*b843c749SSergey Zigachev struct i2caux_transaction_payload {
43*b843c749SSergey Zigachev 	enum i2caux_transaction_address_space address_space;
44*b843c749SSergey Zigachev 	uint32_t address;
45*b843c749SSergey Zigachev 	uint32_t length;
46*b843c749SSergey Zigachev 	uint8_t *data;
47*b843c749SSergey Zigachev };
48*b843c749SSergey Zigachev 
49*b843c749SSergey Zigachev enum i2caux_transaction_status {
50*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
51*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
52*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
53*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
54*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
55*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
56*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
57*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
58*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
59*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW,
60*b843c749SSergey Zigachev 	I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON
61*b843c749SSergey Zigachev };
62*b843c749SSergey Zigachev 
63*b843c749SSergey Zigachev struct i2caux_transaction_request {
64*b843c749SSergey Zigachev 	enum i2caux_transaction_operation operation;
65*b843c749SSergey Zigachev 	struct i2caux_transaction_payload payload;
66*b843c749SSergey Zigachev 	enum i2caux_transaction_status status;
67*b843c749SSergey Zigachev };
68*b843c749SSergey Zigachev 
69*b843c749SSergey Zigachev enum i2caux_engine_type {
70*b843c749SSergey Zigachev 	I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
71*b843c749SSergey Zigachev 	I2CAUX_ENGINE_TYPE_AUX,
72*b843c749SSergey Zigachev 	I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
73*b843c749SSergey Zigachev 	I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
74*b843c749SSergey Zigachev 	I2CAUX_ENGINE_TYPE_I2C_SW
75*b843c749SSergey Zigachev };
76*b843c749SSergey Zigachev 
77*b843c749SSergey Zigachev enum i2c_default_speed {
78*b843c749SSergey Zigachev 	I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
79*b843c749SSergey Zigachev 	I2CAUX_DEFAULT_I2C_SW_SPEED = 50
80*b843c749SSergey Zigachev };
81*b843c749SSergey Zigachev 
82*b843c749SSergey Zigachev union aux_config;
83*b843c749SSergey Zigachev 
84*b843c749SSergey Zigachev struct aux_engine {
85*b843c749SSergey Zigachev 	uint32_t inst;
86*b843c749SSergey Zigachev 	struct ddc *ddc;
87*b843c749SSergey Zigachev 	struct dc_context *ctx;
88*b843c749SSergey Zigachev 	const struct aux_engine_funcs *funcs;
89*b843c749SSergey Zigachev 	/* following values are expressed in milliseconds */
90*b843c749SSergey Zigachev 	uint32_t delay;
91*b843c749SSergey Zigachev 	uint32_t max_defer_write_retry;
92*b843c749SSergey Zigachev 	bool acquire_reset;
93*b843c749SSergey Zigachev };
94*b843c749SSergey Zigachev 
95*b843c749SSergey Zigachev struct read_command_context {
96*b843c749SSergey Zigachev 	uint8_t *buffer;
97*b843c749SSergey Zigachev 	uint32_t current_read_length;
98*b843c749SSergey Zigachev 	uint32_t offset;
99*b843c749SSergey Zigachev 	enum i2caux_transaction_status status;
100*b843c749SSergey Zigachev 
101*b843c749SSergey Zigachev 	struct aux_request_transaction_data request;
102*b843c749SSergey Zigachev 	struct aux_reply_transaction_data reply;
103*b843c749SSergey Zigachev 
104*b843c749SSergey Zigachev 	uint8_t returned_byte;
105*b843c749SSergey Zigachev 
106*b843c749SSergey Zigachev 	uint32_t timed_out_retry_aux;
107*b843c749SSergey Zigachev 	uint32_t invalid_reply_retry_aux;
108*b843c749SSergey Zigachev 	uint32_t defer_retry_aux;
109*b843c749SSergey Zigachev 	uint32_t defer_retry_i2c;
110*b843c749SSergey Zigachev 	uint32_t invalid_reply_retry_aux_on_ack;
111*b843c749SSergey Zigachev 
112*b843c749SSergey Zigachev 	bool transaction_complete;
113*b843c749SSergey Zigachev 	bool operation_succeeded;
114*b843c749SSergey Zigachev };
115*b843c749SSergey Zigachev 
116*b843c749SSergey Zigachev struct write_command_context {
117*b843c749SSergey Zigachev 	bool mot;
118*b843c749SSergey Zigachev 
119*b843c749SSergey Zigachev 	uint8_t *buffer;
120*b843c749SSergey Zigachev 	uint32_t current_write_length;
121*b843c749SSergey Zigachev 	enum i2caux_transaction_status status;
122*b843c749SSergey Zigachev 
123*b843c749SSergey Zigachev 	struct aux_request_transaction_data request;
124*b843c749SSergey Zigachev 	struct aux_reply_transaction_data reply;
125*b843c749SSergey Zigachev 
126*b843c749SSergey Zigachev 	uint8_t returned_byte;
127*b843c749SSergey Zigachev 
128*b843c749SSergey Zigachev 	uint32_t timed_out_retry_aux;
129*b843c749SSergey Zigachev 	uint32_t invalid_reply_retry_aux;
130*b843c749SSergey Zigachev 	uint32_t defer_retry_aux;
131*b843c749SSergey Zigachev 	uint32_t defer_retry_i2c;
132*b843c749SSergey Zigachev 	uint32_t max_defer_retry;
133*b843c749SSergey Zigachev 	uint32_t ack_m_retry;
134*b843c749SSergey Zigachev 
135*b843c749SSergey Zigachev 	uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];
136*b843c749SSergey Zigachev 
137*b843c749SSergey Zigachev 	bool transaction_complete;
138*b843c749SSergey Zigachev 	bool operation_succeeded;
139*b843c749SSergey Zigachev };
140*b843c749SSergey Zigachev 
141*b843c749SSergey Zigachev 
142*b843c749SSergey Zigachev struct aux_engine_funcs {
143*b843c749SSergey Zigachev 	void (*destroy)(
144*b843c749SSergey Zigachev 		struct aux_engine **ptr);
145*b843c749SSergey Zigachev 	bool (*acquire_engine)(
146*b843c749SSergey Zigachev 		struct aux_engine *engine);
147*b843c749SSergey Zigachev 	void (*configure)(
148*b843c749SSergey Zigachev 		struct aux_engine *engine,
149*b843c749SSergey Zigachev 		union aux_config cfg);
150*b843c749SSergey Zigachev 	void (*submit_channel_request)(
151*b843c749SSergey Zigachev 		struct aux_engine *engine,
152*b843c749SSergey Zigachev 		struct aux_request_transaction_data *request);
153*b843c749SSergey Zigachev 	void (*process_channel_reply)(
154*b843c749SSergey Zigachev 		struct aux_engine *engine,
155*b843c749SSergey Zigachev 		struct aux_reply_transaction_data *reply);
156*b843c749SSergey Zigachev 	int (*read_channel_reply)(
157*b843c749SSergey Zigachev 		struct aux_engine *engine,
158*b843c749SSergey Zigachev 		uint32_t size,
159*b843c749SSergey Zigachev 		uint8_t *buffer,
160*b843c749SSergey Zigachev 		uint8_t *reply_result,
161*b843c749SSergey Zigachev 		uint32_t *sw_status);
162*b843c749SSergey Zigachev 	enum aux_channel_operation_result (*get_channel_status)(
163*b843c749SSergey Zigachev 		struct aux_engine *engine,
164*b843c749SSergey Zigachev 		uint8_t *returned_bytes);
165*b843c749SSergey Zigachev 	bool (*is_engine_available)(struct aux_engine *engine);
166*b843c749SSergey Zigachev 	enum i2caux_engine_type (*get_engine_type)(
167*b843c749SSergey Zigachev 		const struct aux_engine *engine);
168*b843c749SSergey Zigachev 	bool (*acquire)(
169*b843c749SSergey Zigachev 		struct aux_engine *engine,
170*b843c749SSergey Zigachev 		struct ddc *ddc);
171*b843c749SSergey Zigachev 	bool (*submit_request)(
172*b843c749SSergey Zigachev 		struct aux_engine *engine,
173*b843c749SSergey Zigachev 		struct i2caux_transaction_request *request,
174*b843c749SSergey Zigachev 		bool middle_of_transaction);
175*b843c749SSergey Zigachev 	void (*release_engine)(
176*b843c749SSergey Zigachev 		struct aux_engine *engine);
177*b843c749SSergey Zigachev 	void (*destroy_engine)(
178*b843c749SSergey Zigachev 		struct aux_engine **engine);
179*b843c749SSergey Zigachev };
180*b843c749SSergey Zigachev #endif
181