1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2015-2017 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev /** 27*b843c749SSergey Zigachev * Bandwidth and Watermark calculations interface. 28*b843c749SSergey Zigachev * (Refer to "DCEx_mode_support.xlsm" from Perforce.) 29*b843c749SSergey Zigachev */ 30*b843c749SSergey Zigachev #ifndef __DCE_CALCS_H__ 31*b843c749SSergey Zigachev #define __DCE_CALCS_H__ 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev #include "bw_fixed.h" 34*b843c749SSergey Zigachev 35*b843c749SSergey Zigachev struct pipe_ctx; 36*b843c749SSergey Zigachev struct dc; 37*b843c749SSergey Zigachev struct dc_state; 38*b843c749SSergey Zigachev struct dce_bw_output; 39*b843c749SSergey Zigachev 40*b843c749SSergey Zigachev enum bw_calcs_version { 41*b843c749SSergey Zigachev BW_CALCS_VERSION_INVALID, 42*b843c749SSergey Zigachev BW_CALCS_VERSION_CARRIZO, 43*b843c749SSergey Zigachev BW_CALCS_VERSION_POLARIS10, 44*b843c749SSergey Zigachev BW_CALCS_VERSION_POLARIS11, 45*b843c749SSergey Zigachev BW_CALCS_VERSION_POLARIS12, 46*b843c749SSergey Zigachev BW_CALCS_VERSION_VEGAM, 47*b843c749SSergey Zigachev BW_CALCS_VERSION_STONEY, 48*b843c749SSergey Zigachev BW_CALCS_VERSION_VEGA10 49*b843c749SSergey Zigachev }; 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev /******************************************************************************* 52*b843c749SSergey Zigachev * There are three types of input into Calculations: 53*b843c749SSergey Zigachev * 1. per-DCE static values - these are "hardcoded" properties of the DCEIP 54*b843c749SSergey Zigachev * 2. board-level values - these are generally coming from VBIOS parser 55*b843c749SSergey Zigachev * 3. mode/configuration values - depending Mode, Scaling number of Displays etc. 56*b843c749SSergey Zigachev ******************************************************************************/ 57*b843c749SSergey Zigachev 58*b843c749SSergey Zigachev enum bw_defines { 59*b843c749SSergey Zigachev //Common 60*b843c749SSergey Zigachev bw_def_no = 0, 61*b843c749SSergey Zigachev bw_def_none = 0, 62*b843c749SSergey Zigachev bw_def_yes = 1, 63*b843c749SSergey Zigachev bw_def_ok = 1, 64*b843c749SSergey Zigachev bw_def_high = 2, 65*b843c749SSergey Zigachev bw_def_mid = 1, 66*b843c749SSergey Zigachev bw_def_low = 0, 67*b843c749SSergey Zigachev 68*b843c749SSergey Zigachev //Internal 69*b843c749SSergey Zigachev bw_defs_start = 255, 70*b843c749SSergey Zigachev bw_def_underlay422, 71*b843c749SSergey Zigachev bw_def_underlay420_luma, 72*b843c749SSergey Zigachev bw_def_underlay420_chroma, 73*b843c749SSergey Zigachev bw_def_underlay444, 74*b843c749SSergey Zigachev bw_def_graphics, 75*b843c749SSergey Zigachev bw_def_display_write_back420_luma, 76*b843c749SSergey Zigachev bw_def_display_write_back420_chroma, 77*b843c749SSergey Zigachev bw_def_portrait, 78*b843c749SSergey Zigachev bw_def_hsr_mtn_4, 79*b843c749SSergey Zigachev bw_def_hsr_mtn_h_taps, 80*b843c749SSergey Zigachev bw_def_ceiling__h_taps_div_4___meq_hsr, 81*b843c749SSergey Zigachev bw_def_invalid_linear_or_stereo_mode, 82*b843c749SSergey Zigachev bw_def_invalid_rotation_or_bpp_or_stereo, 83*b843c749SSergey Zigachev bw_def_vsr_mtn_v_taps, 84*b843c749SSergey Zigachev bw_def_vsr_mtn_4, 85*b843c749SSergey Zigachev bw_def_auto, 86*b843c749SSergey Zigachev bw_def_manual, 87*b843c749SSergey Zigachev bw_def_exceeded_allowed_maximum_sclk, 88*b843c749SSergey Zigachev bw_def_exceeded_allowed_page_close_open, 89*b843c749SSergey Zigachev bw_def_exceeded_allowed_outstanding_pte_req_queue_size, 90*b843c749SSergey Zigachev bw_def_exceeded_allowed_maximum_bw, 91*b843c749SSergey Zigachev bw_def_landscape, 92*b843c749SSergey Zigachev 93*b843c749SSergey Zigachev //Panning and bezel 94*b843c749SSergey Zigachev bw_def_any_lines, 95*b843c749SSergey Zigachev 96*b843c749SSergey Zigachev //Underlay mode 97*b843c749SSergey Zigachev bw_def_underlay_only, 98*b843c749SSergey Zigachev bw_def_blended, 99*b843c749SSergey Zigachev bw_def_blend, 100*b843c749SSergey Zigachev 101*b843c749SSergey Zigachev //Stereo mode 102*b843c749SSergey Zigachev bw_def_mono, 103*b843c749SSergey Zigachev bw_def_side_by_side, 104*b843c749SSergey Zigachev bw_def_top_bottom, 105*b843c749SSergey Zigachev 106*b843c749SSergey Zigachev //Underlay surface type 107*b843c749SSergey Zigachev bw_def_420, 108*b843c749SSergey Zigachev bw_def_422, 109*b843c749SSergey Zigachev bw_def_444, 110*b843c749SSergey Zigachev 111*b843c749SSergey Zigachev //Tiling mode 112*b843c749SSergey Zigachev bw_def_linear, 113*b843c749SSergey Zigachev bw_def_tiled, 114*b843c749SSergey Zigachev bw_def_array_linear_general, 115*b843c749SSergey Zigachev bw_def_array_linear_aligned, 116*b843c749SSergey Zigachev bw_def_rotated_micro_tiling, 117*b843c749SSergey Zigachev bw_def_display_micro_tiling, 118*b843c749SSergey Zigachev 119*b843c749SSergey Zigachev //Memory type 120*b843c749SSergey Zigachev bw_def_gddr5, 121*b843c749SSergey Zigachev bw_def_hbm, 122*b843c749SSergey Zigachev 123*b843c749SSergey Zigachev //Voltage 124*b843c749SSergey Zigachev bw_def_high_no_nbp_state_change, 125*b843c749SSergey Zigachev bw_def_0_72, 126*b843c749SSergey Zigachev bw_def_0_8, 127*b843c749SSergey Zigachev bw_def_0_9, 128*b843c749SSergey Zigachev 129*b843c749SSergey Zigachev bw_def_notok = -1, 130*b843c749SSergey Zigachev bw_def_na = -1 131*b843c749SSergey Zigachev }; 132*b843c749SSergey Zigachev 133*b843c749SSergey Zigachev struct bw_calcs_dceip { 134*b843c749SSergey Zigachev enum bw_calcs_version version; 135*b843c749SSergey Zigachev uint32_t percent_of_ideal_port_bw_received_after_urgent_latency; 136*b843c749SSergey Zigachev uint32_t max_average_percent_of_ideal_port_bw_display_can_use_in_normal_system_operation; 137*b843c749SSergey Zigachev uint32_t max_average_percent_of_ideal_drambw_display_can_use_in_normal_system_operation; 138*b843c749SSergey Zigachev bool large_cursor; 139*b843c749SSergey Zigachev uint32_t cursor_max_outstanding_group_num; 140*b843c749SSergey Zigachev bool dmif_pipe_en_fbc_chunk_tracker; 141*b843c749SSergey Zigachev struct bw_fixed dmif_request_buffer_size; 142*b843c749SSergey Zigachev uint32_t lines_interleaved_into_lb; 143*b843c749SSergey Zigachev uint32_t low_power_tiling_mode; 144*b843c749SSergey Zigachev uint32_t chunk_width; 145*b843c749SSergey Zigachev uint32_t number_of_graphics_pipes; 146*b843c749SSergey Zigachev uint32_t number_of_underlay_pipes; 147*b843c749SSergey Zigachev bool display_write_back_supported; 148*b843c749SSergey Zigachev bool argb_compression_support; 149*b843c749SSergey Zigachev struct bw_fixed underlay_vscaler_efficiency6_bit_per_component; 150*b843c749SSergey Zigachev struct bw_fixed underlay_vscaler_efficiency8_bit_per_component; 151*b843c749SSergey Zigachev struct bw_fixed underlay_vscaler_efficiency10_bit_per_component; 152*b843c749SSergey Zigachev struct bw_fixed underlay_vscaler_efficiency12_bit_per_component; 153*b843c749SSergey Zigachev struct bw_fixed graphics_vscaler_efficiency6_bit_per_component; 154*b843c749SSergey Zigachev struct bw_fixed graphics_vscaler_efficiency8_bit_per_component; 155*b843c749SSergey Zigachev struct bw_fixed graphics_vscaler_efficiency10_bit_per_component; 156*b843c749SSergey Zigachev struct bw_fixed graphics_vscaler_efficiency12_bit_per_component; 157*b843c749SSergey Zigachev struct bw_fixed alpha_vscaler_efficiency; 158*b843c749SSergey Zigachev uint32_t max_dmif_buffer_allocated; 159*b843c749SSergey Zigachev uint32_t graphics_dmif_size; 160*b843c749SSergey Zigachev uint32_t underlay_luma_dmif_size; 161*b843c749SSergey Zigachev uint32_t underlay_chroma_dmif_size; 162*b843c749SSergey Zigachev bool pre_downscaler_enabled; 163*b843c749SSergey Zigachev bool underlay_downscale_prefetch_enabled; 164*b843c749SSergey Zigachev struct bw_fixed lb_write_pixels_per_dispclk; 165*b843c749SSergey Zigachev struct bw_fixed lb_size_per_component444; 166*b843c749SSergey Zigachev bool graphics_lb_nodownscaling_multi_line_prefetching; 167*b843c749SSergey Zigachev struct bw_fixed stutter_and_dram_clock_state_change_gated_before_cursor; 168*b843c749SSergey Zigachev struct bw_fixed underlay420_luma_lb_size_per_component; 169*b843c749SSergey Zigachev struct bw_fixed underlay420_chroma_lb_size_per_component; 170*b843c749SSergey Zigachev struct bw_fixed underlay422_lb_size_per_component; 171*b843c749SSergey Zigachev struct bw_fixed cursor_chunk_width; 172*b843c749SSergey Zigachev struct bw_fixed cursor_dcp_buffer_lines; 173*b843c749SSergey Zigachev struct bw_fixed underlay_maximum_width_efficient_for_tiling; 174*b843c749SSergey Zigachev struct bw_fixed underlay_maximum_height_efficient_for_tiling; 175*b843c749SSergey Zigachev struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display; 176*b843c749SSergey Zigachev struct bw_fixed peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation; 177*b843c749SSergey Zigachev struct bw_fixed minimum_outstanding_pte_request_limit; 178*b843c749SSergey Zigachev struct bw_fixed maximum_total_outstanding_pte_requests_allowed_by_saw; 179*b843c749SSergey Zigachev bool limit_excessive_outstanding_dmif_requests; 180*b843c749SSergey Zigachev struct bw_fixed linear_mode_line_request_alternation_slice; 181*b843c749SSergey Zigachev uint32_t scatter_gather_lines_of_pte_prefetching_in_linear_mode; 182*b843c749SSergey Zigachev uint32_t display_write_back420_luma_mcifwr_buffer_size; 183*b843c749SSergey Zigachev uint32_t display_write_back420_chroma_mcifwr_buffer_size; 184*b843c749SSergey Zigachev struct bw_fixed request_efficiency; 185*b843c749SSergey Zigachev struct bw_fixed dispclk_per_request; 186*b843c749SSergey Zigachev struct bw_fixed dispclk_ramping_factor; 187*b843c749SSergey Zigachev struct bw_fixed display_pipe_throughput_factor; 188*b843c749SSergey Zigachev uint32_t scatter_gather_pte_request_rows_in_tiling_mode; 189*b843c749SSergey Zigachev struct bw_fixed mcifwr_all_surfaces_burst_time; 190*b843c749SSergey Zigachev }; 191*b843c749SSergey Zigachev 192*b843c749SSergey Zigachev struct bw_calcs_vbios { 193*b843c749SSergey Zigachev enum bw_defines memory_type; 194*b843c749SSergey Zigachev uint32_t dram_channel_width_in_bits; 195*b843c749SSergey Zigachev uint32_t number_of_dram_channels; 196*b843c749SSergey Zigachev uint32_t number_of_dram_banks; 197*b843c749SSergey Zigachev struct bw_fixed low_yclk; /*m_hz*/ 198*b843c749SSergey Zigachev struct bw_fixed mid_yclk; /*m_hz*/ 199*b843c749SSergey Zigachev struct bw_fixed high_yclk; /*m_hz*/ 200*b843c749SSergey Zigachev struct bw_fixed low_sclk; /*m_hz*/ 201*b843c749SSergey Zigachev struct bw_fixed mid1_sclk; /*m_hz*/ 202*b843c749SSergey Zigachev struct bw_fixed mid2_sclk; /*m_hz*/ 203*b843c749SSergey Zigachev struct bw_fixed mid3_sclk; /*m_hz*/ 204*b843c749SSergey Zigachev struct bw_fixed mid4_sclk; /*m_hz*/ 205*b843c749SSergey Zigachev struct bw_fixed mid5_sclk; /*m_hz*/ 206*b843c749SSergey Zigachev struct bw_fixed mid6_sclk; /*m_hz*/ 207*b843c749SSergey Zigachev struct bw_fixed high_sclk; /*m_hz*/ 208*b843c749SSergey Zigachev struct bw_fixed low_voltage_max_dispclk; /*m_hz*/ 209*b843c749SSergey Zigachev struct bw_fixed mid_voltage_max_dispclk; /*m_hz*/ 210*b843c749SSergey Zigachev struct bw_fixed high_voltage_max_dispclk; /*m_hz*/ 211*b843c749SSergey Zigachev struct bw_fixed low_voltage_max_phyclk; 212*b843c749SSergey Zigachev struct bw_fixed mid_voltage_max_phyclk; 213*b843c749SSergey Zigachev struct bw_fixed high_voltage_max_phyclk; 214*b843c749SSergey Zigachev struct bw_fixed data_return_bus_width; 215*b843c749SSergey Zigachev struct bw_fixed trc; 216*b843c749SSergey Zigachev struct bw_fixed dmifmc_urgent_latency; 217*b843c749SSergey Zigachev struct bw_fixed stutter_self_refresh_exit_latency; 218*b843c749SSergey Zigachev struct bw_fixed stutter_self_refresh_entry_latency; 219*b843c749SSergey Zigachev struct bw_fixed nbp_state_change_latency; 220*b843c749SSergey Zigachev struct bw_fixed mcifwrmc_urgent_latency; 221*b843c749SSergey Zigachev bool scatter_gather_enable; 222*b843c749SSergey Zigachev struct bw_fixed down_spread_percentage; 223*b843c749SSergey Zigachev uint32_t cursor_width; 224*b843c749SSergey Zigachev uint32_t average_compression_rate; 225*b843c749SSergey Zigachev uint32_t number_of_request_slots_gmc_reserves_for_dmif_per_channel; 226*b843c749SSergey Zigachev struct bw_fixed blackout_duration; 227*b843c749SSergey Zigachev struct bw_fixed maximum_blackout_recovery_time; 228*b843c749SSergey Zigachev }; 229*b843c749SSergey Zigachev 230*b843c749SSergey Zigachev /******************************************************************************* 231*b843c749SSergey Zigachev * Temporary data structure(s). 232*b843c749SSergey Zigachev ******************************************************************************/ 233*b843c749SSergey Zigachev #define maximum_number_of_surfaces 12 234*b843c749SSergey Zigachev /*Units : MHz, us */ 235*b843c749SSergey Zigachev 236*b843c749SSergey Zigachev struct bw_calcs_data { 237*b843c749SSergey Zigachev /* data for all displays */ 238*b843c749SSergey Zigachev bool display_synchronization_enabled; 239*b843c749SSergey Zigachev uint32_t number_of_displays; 240*b843c749SSergey Zigachev enum bw_defines underlay_surface_type; 241*b843c749SSergey Zigachev enum bw_defines panning_and_bezel_adjustment; 242*b843c749SSergey Zigachev enum bw_defines graphics_tiling_mode; 243*b843c749SSergey Zigachev uint32_t graphics_lb_bpc; 244*b843c749SSergey Zigachev uint32_t underlay_lb_bpc; 245*b843c749SSergey Zigachev enum bw_defines underlay_tiling_mode; 246*b843c749SSergey Zigachev enum bw_defines d0_underlay_mode; 247*b843c749SSergey Zigachev bool d1_display_write_back_dwb_enable; 248*b843c749SSergey Zigachev enum bw_defines d1_underlay_mode; 249*b843c749SSergey Zigachev 250*b843c749SSergey Zigachev bool increase_voltage_to_support_mclk_switch; 251*b843c749SSergey Zigachev bool cpup_state_change_enable; 252*b843c749SSergey Zigachev bool cpuc_state_change_enable; 253*b843c749SSergey Zigachev bool nbp_state_change_enable; 254*b843c749SSergey Zigachev bool stutter_mode_enable; 255*b843c749SSergey Zigachev uint32_t y_clk_level; 256*b843c749SSergey Zigachev uint32_t sclk_level; 257*b843c749SSergey Zigachev uint32_t number_of_underlay_surfaces; 258*b843c749SSergey Zigachev uint32_t number_of_dram_wrchannels; 259*b843c749SSergey Zigachev uint32_t chunk_request_delay; 260*b843c749SSergey Zigachev uint32_t number_of_dram_channels; 261*b843c749SSergey Zigachev enum bw_defines underlay_micro_tile_mode; 262*b843c749SSergey Zigachev enum bw_defines graphics_micro_tile_mode; 263*b843c749SSergey Zigachev struct bw_fixed max_phyclk; 264*b843c749SSergey Zigachev struct bw_fixed dram_efficiency; 265*b843c749SSergey Zigachev struct bw_fixed src_width_after_surface_type; 266*b843c749SSergey Zigachev struct bw_fixed src_height_after_surface_type; 267*b843c749SSergey Zigachev struct bw_fixed hsr_after_surface_type; 268*b843c749SSergey Zigachev struct bw_fixed vsr_after_surface_type; 269*b843c749SSergey Zigachev struct bw_fixed src_width_after_rotation; 270*b843c749SSergey Zigachev struct bw_fixed src_height_after_rotation; 271*b843c749SSergey Zigachev struct bw_fixed hsr_after_rotation; 272*b843c749SSergey Zigachev struct bw_fixed vsr_after_rotation; 273*b843c749SSergey Zigachev struct bw_fixed source_height_pixels; 274*b843c749SSergey Zigachev struct bw_fixed hsr_after_stereo; 275*b843c749SSergey Zigachev struct bw_fixed vsr_after_stereo; 276*b843c749SSergey Zigachev struct bw_fixed source_width_in_lb; 277*b843c749SSergey Zigachev struct bw_fixed lb_line_pitch; 278*b843c749SSergey Zigachev struct bw_fixed underlay_maximum_source_efficient_for_tiling; 279*b843c749SSergey Zigachev struct bw_fixed num_lines_at_frame_start; 280*b843c749SSergey Zigachev struct bw_fixed min_dmif_size_in_time; 281*b843c749SSergey Zigachev struct bw_fixed min_mcifwr_size_in_time; 282*b843c749SSergey Zigachev struct bw_fixed total_requests_for_dmif_size; 283*b843c749SSergey Zigachev struct bw_fixed peak_pte_request_to_eviction_ratio_limiting; 284*b843c749SSergey Zigachev struct bw_fixed useful_pte_per_pte_request; 285*b843c749SSergey Zigachev struct bw_fixed scatter_gather_pte_request_rows; 286*b843c749SSergey Zigachev struct bw_fixed scatter_gather_row_height; 287*b843c749SSergey Zigachev struct bw_fixed scatter_gather_pte_requests_in_vblank; 288*b843c749SSergey Zigachev struct bw_fixed inefficient_linear_pitch_in_bytes; 289*b843c749SSergey Zigachev struct bw_fixed cursor_total_data; 290*b843c749SSergey Zigachev struct bw_fixed cursor_total_request_groups; 291*b843c749SSergey Zigachev struct bw_fixed scatter_gather_total_pte_requests; 292*b843c749SSergey Zigachev struct bw_fixed scatter_gather_total_pte_request_groups; 293*b843c749SSergey Zigachev struct bw_fixed tile_width_in_pixels; 294*b843c749SSergey Zigachev struct bw_fixed dmif_total_number_of_data_request_page_close_open; 295*b843c749SSergey Zigachev struct bw_fixed mcifwr_total_number_of_data_request_page_close_open; 296*b843c749SSergey Zigachev struct bw_fixed bytes_per_page_close_open; 297*b843c749SSergey Zigachev struct bw_fixed mcifwr_total_page_close_open_time; 298*b843c749SSergey Zigachev struct bw_fixed total_requests_for_adjusted_dmif_size; 299*b843c749SSergey Zigachev struct bw_fixed total_dmifmc_urgent_trips; 300*b843c749SSergey Zigachev struct bw_fixed total_dmifmc_urgent_latency; 301*b843c749SSergey Zigachev struct bw_fixed total_display_reads_required_data; 302*b843c749SSergey Zigachev struct bw_fixed total_display_reads_required_dram_access_data; 303*b843c749SSergey Zigachev struct bw_fixed total_display_writes_required_data; 304*b843c749SSergey Zigachev struct bw_fixed total_display_writes_required_dram_access_data; 305*b843c749SSergey Zigachev struct bw_fixed display_reads_required_data; 306*b843c749SSergey Zigachev struct bw_fixed display_reads_required_dram_access_data; 307*b843c749SSergey Zigachev struct bw_fixed dmif_total_page_close_open_time; 308*b843c749SSergey Zigachev struct bw_fixed min_cursor_memory_interface_buffer_size_in_time; 309*b843c749SSergey Zigachev struct bw_fixed min_read_buffer_size_in_time; 310*b843c749SSergey Zigachev struct bw_fixed display_reads_time_for_data_transfer; 311*b843c749SSergey Zigachev struct bw_fixed display_writes_time_for_data_transfer; 312*b843c749SSergey Zigachev struct bw_fixed dmif_required_dram_bandwidth; 313*b843c749SSergey Zigachev struct bw_fixed mcifwr_required_dram_bandwidth; 314*b843c749SSergey Zigachev struct bw_fixed required_dmifmc_urgent_latency_for_page_close_open; 315*b843c749SSergey Zigachev struct bw_fixed required_mcifmcwr_urgent_latency; 316*b843c749SSergey Zigachev struct bw_fixed required_dram_bandwidth_gbyte_per_second; 317*b843c749SSergey Zigachev struct bw_fixed dram_bandwidth; 318*b843c749SSergey Zigachev struct bw_fixed dmif_required_sclk; 319*b843c749SSergey Zigachev struct bw_fixed mcifwr_required_sclk; 320*b843c749SSergey Zigachev struct bw_fixed required_sclk; 321*b843c749SSergey Zigachev struct bw_fixed downspread_factor; 322*b843c749SSergey Zigachev struct bw_fixed v_scaler_efficiency; 323*b843c749SSergey Zigachev struct bw_fixed scaler_limits_factor; 324*b843c749SSergey Zigachev struct bw_fixed display_pipe_pixel_throughput; 325*b843c749SSergey Zigachev struct bw_fixed total_dispclk_required_with_ramping; 326*b843c749SSergey Zigachev struct bw_fixed total_dispclk_required_without_ramping; 327*b843c749SSergey Zigachev struct bw_fixed total_read_request_bandwidth; 328*b843c749SSergey Zigachev struct bw_fixed total_write_request_bandwidth; 329*b843c749SSergey Zigachev struct bw_fixed dispclk_required_for_total_read_request_bandwidth; 330*b843c749SSergey Zigachev struct bw_fixed total_dispclk_required_with_ramping_with_request_bandwidth; 331*b843c749SSergey Zigachev struct bw_fixed total_dispclk_required_without_ramping_with_request_bandwidth; 332*b843c749SSergey Zigachev struct bw_fixed dispclk; 333*b843c749SSergey Zigachev struct bw_fixed blackout_recovery_time; 334*b843c749SSergey Zigachev struct bw_fixed min_pixels_per_data_fifo_entry; 335*b843c749SSergey Zigachev struct bw_fixed sclk_deep_sleep; 336*b843c749SSergey Zigachev struct bw_fixed chunk_request_time; 337*b843c749SSergey Zigachev struct bw_fixed cursor_request_time; 338*b843c749SSergey Zigachev struct bw_fixed line_source_pixels_transfer_time; 339*b843c749SSergey Zigachev struct bw_fixed dmifdram_access_efficiency; 340*b843c749SSergey Zigachev struct bw_fixed mcifwrdram_access_efficiency; 341*b843c749SSergey Zigachev struct bw_fixed total_average_bandwidth_no_compression; 342*b843c749SSergey Zigachev struct bw_fixed total_average_bandwidth; 343*b843c749SSergey Zigachev struct bw_fixed total_stutter_cycle_duration; 344*b843c749SSergey Zigachev struct bw_fixed stutter_burst_time; 345*b843c749SSergey Zigachev struct bw_fixed time_in_self_refresh; 346*b843c749SSergey Zigachev struct bw_fixed stutter_efficiency; 347*b843c749SSergey Zigachev struct bw_fixed worst_number_of_trips_to_memory; 348*b843c749SSergey Zigachev struct bw_fixed immediate_flip_time; 349*b843c749SSergey Zigachev struct bw_fixed latency_for_non_dmif_clients; 350*b843c749SSergey Zigachev struct bw_fixed latency_for_non_mcifwr_clients; 351*b843c749SSergey Zigachev struct bw_fixed dmifmc_urgent_latency_supported_in_high_sclk_and_yclk; 352*b843c749SSergey Zigachev struct bw_fixed nbp_state_dram_speed_change_margin; 353*b843c749SSergey Zigachev struct bw_fixed display_reads_time_for_data_transfer_and_urgent_latency; 354*b843c749SSergey Zigachev struct bw_fixed dram_speed_change_margin; 355*b843c749SSergey Zigachev struct bw_fixed min_vblank_dram_speed_change_margin; 356*b843c749SSergey Zigachev struct bw_fixed min_stutter_refresh_duration; 357*b843c749SSergey Zigachev uint32_t total_stutter_dmif_buffer_size; 358*b843c749SSergey Zigachev uint32_t total_bytes_requested; 359*b843c749SSergey Zigachev uint32_t min_stutter_dmif_buffer_size; 360*b843c749SSergey Zigachev uint32_t num_stutter_bursts; 361*b843c749SSergey Zigachev struct bw_fixed v_blank_nbp_state_dram_speed_change_latency_supported; 362*b843c749SSergey Zigachev struct bw_fixed nbp_state_dram_speed_change_latency_supported; 363*b843c749SSergey Zigachev bool fbc_en[maximum_number_of_surfaces]; 364*b843c749SSergey Zigachev bool lpt_en[maximum_number_of_surfaces]; 365*b843c749SSergey Zigachev bool displays_match_flag[maximum_number_of_surfaces]; 366*b843c749SSergey Zigachev bool use_alpha[maximum_number_of_surfaces]; 367*b843c749SSergey Zigachev bool orthogonal_rotation[maximum_number_of_surfaces]; 368*b843c749SSergey Zigachev bool enable[maximum_number_of_surfaces]; 369*b843c749SSergey Zigachev bool access_one_channel_only[maximum_number_of_surfaces]; 370*b843c749SSergey Zigachev bool scatter_gather_enable_for_pipe[maximum_number_of_surfaces]; 371*b843c749SSergey Zigachev bool interlace_mode[maximum_number_of_surfaces]; 372*b843c749SSergey Zigachev bool display_pstate_change_enable[maximum_number_of_surfaces]; 373*b843c749SSergey Zigachev bool line_buffer_prefetch[maximum_number_of_surfaces]; 374*b843c749SSergey Zigachev uint32_t bytes_per_pixel[maximum_number_of_surfaces]; 375*b843c749SSergey Zigachev uint32_t max_chunks_non_fbc_mode[maximum_number_of_surfaces]; 376*b843c749SSergey Zigachev uint32_t lb_bpc[maximum_number_of_surfaces]; 377*b843c749SSergey Zigachev uint32_t output_bpphdmi[maximum_number_of_surfaces]; 378*b843c749SSergey Zigachev uint32_t output_bppdp4_lane_hbr[maximum_number_of_surfaces]; 379*b843c749SSergey Zigachev uint32_t output_bppdp4_lane_hbr2[maximum_number_of_surfaces]; 380*b843c749SSergey Zigachev uint32_t output_bppdp4_lane_hbr3[maximum_number_of_surfaces]; 381*b843c749SSergey Zigachev enum bw_defines stereo_mode[maximum_number_of_surfaces]; 382*b843c749SSergey Zigachev struct bw_fixed dmif_buffer_transfer_time[maximum_number_of_surfaces]; 383*b843c749SSergey Zigachev struct bw_fixed displays_with_same_mode[maximum_number_of_surfaces]; 384*b843c749SSergey Zigachev struct bw_fixed stutter_dmif_buffer_size[maximum_number_of_surfaces]; 385*b843c749SSergey Zigachev struct bw_fixed stutter_refresh_duration[maximum_number_of_surfaces]; 386*b843c749SSergey Zigachev struct bw_fixed stutter_exit_watermark[maximum_number_of_surfaces]; 387*b843c749SSergey Zigachev struct bw_fixed stutter_entry_watermark[maximum_number_of_surfaces]; 388*b843c749SSergey Zigachev struct bw_fixed h_total[maximum_number_of_surfaces]; 389*b843c749SSergey Zigachev struct bw_fixed v_total[maximum_number_of_surfaces]; 390*b843c749SSergey Zigachev struct bw_fixed pixel_rate[maximum_number_of_surfaces]; 391*b843c749SSergey Zigachev struct bw_fixed src_width[maximum_number_of_surfaces]; 392*b843c749SSergey Zigachev struct bw_fixed pitch_in_pixels[maximum_number_of_surfaces]; 393*b843c749SSergey Zigachev struct bw_fixed pitch_in_pixels_after_surface_type[maximum_number_of_surfaces]; 394*b843c749SSergey Zigachev struct bw_fixed src_height[maximum_number_of_surfaces]; 395*b843c749SSergey Zigachev struct bw_fixed scale_ratio[maximum_number_of_surfaces]; 396*b843c749SSergey Zigachev struct bw_fixed h_taps[maximum_number_of_surfaces]; 397*b843c749SSergey Zigachev struct bw_fixed v_taps[maximum_number_of_surfaces]; 398*b843c749SSergey Zigachev struct bw_fixed h_scale_ratio[maximum_number_of_surfaces]; 399*b843c749SSergey Zigachev struct bw_fixed v_scale_ratio[maximum_number_of_surfaces]; 400*b843c749SSergey Zigachev struct bw_fixed rotation_angle[maximum_number_of_surfaces]; 401*b843c749SSergey Zigachev struct bw_fixed compression_rate[maximum_number_of_surfaces]; 402*b843c749SSergey Zigachev struct bw_fixed hsr[maximum_number_of_surfaces]; 403*b843c749SSergey Zigachev struct bw_fixed vsr[maximum_number_of_surfaces]; 404*b843c749SSergey Zigachev struct bw_fixed source_width_rounded_up_to_chunks[maximum_number_of_surfaces]; 405*b843c749SSergey Zigachev struct bw_fixed source_width_pixels[maximum_number_of_surfaces]; 406*b843c749SSergey Zigachev struct bw_fixed source_height_rounded_up_to_chunks[maximum_number_of_surfaces]; 407*b843c749SSergey Zigachev struct bw_fixed display_bandwidth[maximum_number_of_surfaces]; 408*b843c749SSergey Zigachev struct bw_fixed request_bandwidth[maximum_number_of_surfaces]; 409*b843c749SSergey Zigachev struct bw_fixed bytes_per_request[maximum_number_of_surfaces]; 410*b843c749SSergey Zigachev struct bw_fixed useful_bytes_per_request[maximum_number_of_surfaces]; 411*b843c749SSergey Zigachev struct bw_fixed lines_interleaved_in_mem_access[maximum_number_of_surfaces]; 412*b843c749SSergey Zigachev struct bw_fixed latency_hiding_lines[maximum_number_of_surfaces]; 413*b843c749SSergey Zigachev struct bw_fixed lb_partitions[maximum_number_of_surfaces]; 414*b843c749SSergey Zigachev struct bw_fixed lb_partitions_max[maximum_number_of_surfaces]; 415*b843c749SSergey Zigachev struct bw_fixed dispclk_required_with_ramping[maximum_number_of_surfaces]; 416*b843c749SSergey Zigachev struct bw_fixed dispclk_required_without_ramping[maximum_number_of_surfaces]; 417*b843c749SSergey Zigachev struct bw_fixed data_buffer_size[maximum_number_of_surfaces]; 418*b843c749SSergey Zigachev struct bw_fixed outstanding_chunk_request_limit[maximum_number_of_surfaces]; 419*b843c749SSergey Zigachev struct bw_fixed urgent_watermark[maximum_number_of_surfaces]; 420*b843c749SSergey Zigachev struct bw_fixed nbp_state_change_watermark[maximum_number_of_surfaces]; 421*b843c749SSergey Zigachev struct bw_fixed v_filter_init[maximum_number_of_surfaces]; 422*b843c749SSergey Zigachev struct bw_fixed stutter_cycle_duration[maximum_number_of_surfaces]; 423*b843c749SSergey Zigachev struct bw_fixed average_bandwidth[maximum_number_of_surfaces]; 424*b843c749SSergey Zigachev struct bw_fixed average_bandwidth_no_compression[maximum_number_of_surfaces]; 425*b843c749SSergey Zigachev struct bw_fixed scatter_gather_pte_request_limit[maximum_number_of_surfaces]; 426*b843c749SSergey Zigachev struct bw_fixed lb_size_per_component[maximum_number_of_surfaces]; 427*b843c749SSergey Zigachev struct bw_fixed memory_chunk_size_in_bytes[maximum_number_of_surfaces]; 428*b843c749SSergey Zigachev struct bw_fixed pipe_chunk_size_in_bytes[maximum_number_of_surfaces]; 429*b843c749SSergey Zigachev struct bw_fixed number_of_trips_to_memory_for_getting_apte_row[maximum_number_of_surfaces]; 430*b843c749SSergey Zigachev struct bw_fixed adjusted_data_buffer_size[maximum_number_of_surfaces]; 431*b843c749SSergey Zigachev struct bw_fixed adjusted_data_buffer_size_in_memory[maximum_number_of_surfaces]; 432*b843c749SSergey Zigachev struct bw_fixed pixels_per_data_fifo_entry[maximum_number_of_surfaces]; 433*b843c749SSergey Zigachev struct bw_fixed scatter_gather_pte_requests_in_row[maximum_number_of_surfaces]; 434*b843c749SSergey Zigachev struct bw_fixed pte_request_per_chunk[maximum_number_of_surfaces]; 435*b843c749SSergey Zigachev struct bw_fixed scatter_gather_page_width[maximum_number_of_surfaces]; 436*b843c749SSergey Zigachev struct bw_fixed scatter_gather_page_height[maximum_number_of_surfaces]; 437*b843c749SSergey Zigachev struct bw_fixed lb_lines_in_per_line_out_in_beginning_of_frame[maximum_number_of_surfaces]; 438*b843c749SSergey Zigachev struct bw_fixed lb_lines_in_per_line_out_in_middle_of_frame[maximum_number_of_surfaces]; 439*b843c749SSergey Zigachev struct bw_fixed cursor_width_pixels[maximum_number_of_surfaces]; 440*b843c749SSergey Zigachev struct bw_fixed minimum_latency_hiding[maximum_number_of_surfaces]; 441*b843c749SSergey Zigachev struct bw_fixed maximum_latency_hiding[maximum_number_of_surfaces]; 442*b843c749SSergey Zigachev struct bw_fixed minimum_latency_hiding_with_cursor[maximum_number_of_surfaces]; 443*b843c749SSergey Zigachev struct bw_fixed maximum_latency_hiding_with_cursor[maximum_number_of_surfaces]; 444*b843c749SSergey Zigachev struct bw_fixed src_pixels_for_first_output_pixel[maximum_number_of_surfaces]; 445*b843c749SSergey Zigachev struct bw_fixed src_pixels_for_last_output_pixel[maximum_number_of_surfaces]; 446*b843c749SSergey Zigachev struct bw_fixed src_data_for_first_output_pixel[maximum_number_of_surfaces]; 447*b843c749SSergey Zigachev struct bw_fixed src_data_for_last_output_pixel[maximum_number_of_surfaces]; 448*b843c749SSergey Zigachev struct bw_fixed active_time[maximum_number_of_surfaces]; 449*b843c749SSergey Zigachev struct bw_fixed horizontal_blank_and_chunk_granularity_factor[maximum_number_of_surfaces]; 450*b843c749SSergey Zigachev struct bw_fixed cursor_latency_hiding[maximum_number_of_surfaces]; 451*b843c749SSergey Zigachev struct bw_fixed v_blank_dram_speed_change_margin[maximum_number_of_surfaces]; 452*b843c749SSergey Zigachev uint32_t num_displays_with_margin[3][8]; 453*b843c749SSergey Zigachev struct bw_fixed dmif_burst_time[3][8]; 454*b843c749SSergey Zigachev struct bw_fixed mcifwr_burst_time[3][8]; 455*b843c749SSergey Zigachev struct bw_fixed line_source_transfer_time[maximum_number_of_surfaces][3][8]; 456*b843c749SSergey Zigachev struct bw_fixed dram_speed_change_line_source_transfer_time[maximum_number_of_surfaces][3][8]; 457*b843c749SSergey Zigachev struct bw_fixed min_dram_speed_change_margin[3][8]; 458*b843c749SSergey Zigachev struct bw_fixed dispclk_required_for_dram_speed_change[3][8]; 459*b843c749SSergey Zigachev struct bw_fixed dispclk_required_for_dram_speed_change_pipe[3][8]; 460*b843c749SSergey Zigachev struct bw_fixed blackout_duration_margin[3][8]; 461*b843c749SSergey Zigachev struct bw_fixed dispclk_required_for_blackout_duration[3][8]; 462*b843c749SSergey Zigachev struct bw_fixed dispclk_required_for_blackout_recovery[3][8]; 463*b843c749SSergey Zigachev struct bw_fixed dmif_required_sclk_for_urgent_latency[6]; 464*b843c749SSergey Zigachev }; 465*b843c749SSergey Zigachev 466*b843c749SSergey Zigachev /** 467*b843c749SSergey Zigachev * Initialize structures with data which will NOT change at runtime. 468*b843c749SSergey Zigachev */ 469*b843c749SSergey Zigachev void bw_calcs_init( 470*b843c749SSergey Zigachev struct bw_calcs_dceip *bw_dceip, 471*b843c749SSergey Zigachev struct bw_calcs_vbios *bw_vbios, 472*b843c749SSergey Zigachev struct hw_asic_id asic_id); 473*b843c749SSergey Zigachev 474*b843c749SSergey Zigachev /** 475*b843c749SSergey Zigachev * Return: 476*b843c749SSergey Zigachev * true - Display(s) configuration supported. 477*b843c749SSergey Zigachev * In this case 'calcs_output' contains data for HW programming 478*b843c749SSergey Zigachev * false - Display(s) configuration not supported (not enough bandwidth). 479*b843c749SSergey Zigachev */ 480*b843c749SSergey Zigachev bool bw_calcs( 481*b843c749SSergey Zigachev struct dc_context *ctx, 482*b843c749SSergey Zigachev const struct bw_calcs_dceip *dceip, 483*b843c749SSergey Zigachev const struct bw_calcs_vbios *vbios, 484*b843c749SSergey Zigachev const struct pipe_ctx *pipe, 485*b843c749SSergey Zigachev int pipe_count, 486*b843c749SSergey Zigachev struct dce_bw_output *calcs_output); 487*b843c749SSergey Zigachev 488*b843c749SSergey Zigachev #endif /* __BANDWIDTH_CALCS_H__ */ 489*b843c749SSergey Zigachev 490