1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef __DAL_I2C_AUX_H__ 27*b843c749SSergey Zigachev #define __DAL_I2C_AUX_H__ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev uint32_t dal_i2caux_get_reference_clock( 30*b843c749SSergey Zigachev struct dc_bios *bios); 31*b843c749SSergey Zigachev 32*b843c749SSergey Zigachev struct i2caux; 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev struct engine; 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev struct i2caux_funcs { 37*b843c749SSergey Zigachev void (*destroy)(struct i2caux **ptr); 38*b843c749SSergey Zigachev struct i2c_engine * (*acquire_i2c_sw_engine)( 39*b843c749SSergey Zigachev struct i2caux *i2caux, 40*b843c749SSergey Zigachev struct ddc *ddc); 41*b843c749SSergey Zigachev struct i2c_engine * (*acquire_i2c_hw_engine)( 42*b843c749SSergey Zigachev struct i2caux *i2caux, 43*b843c749SSergey Zigachev struct ddc *ddc); 44*b843c749SSergey Zigachev struct aux_engine * (*acquire_aux_engine)( 45*b843c749SSergey Zigachev struct i2caux *i2caux, 46*b843c749SSergey Zigachev struct ddc *ddc); 47*b843c749SSergey Zigachev void (*release_engine)( 48*b843c749SSergey Zigachev struct i2caux *i2caux, 49*b843c749SSergey Zigachev struct engine *engine); 50*b843c749SSergey Zigachev }; 51*b843c749SSergey Zigachev 52*b843c749SSergey Zigachev struct i2c_engine; 53*b843c749SSergey Zigachev struct aux_engine; 54*b843c749SSergey Zigachev 55*b843c749SSergey Zigachev struct i2caux { 56*b843c749SSergey Zigachev struct dc_context *ctx; 57*b843c749SSergey Zigachev const struct i2caux_funcs *funcs; 58*b843c749SSergey Zigachev /* On ASIC we have certain amount of lines with HW DDC engine 59*b843c749SSergey Zigachev * (4, 6, or maybe more in the future). 60*b843c749SSergey Zigachev * For every such line, we create separate HW DDC engine 61*b843c749SSergey Zigachev * (since we have these engines in HW) and separate SW DDC engine 62*b843c749SSergey Zigachev * (to allow concurrent use of few lines). 63*b843c749SSergey Zigachev * In similar way we have AUX engines. */ 64*b843c749SSergey Zigachev 65*b843c749SSergey Zigachev /* I2C SW engines, per DDC line. 66*b843c749SSergey Zigachev * Only lines with HW DDC support will be initialized */ 67*b843c749SSergey Zigachev struct i2c_engine *i2c_sw_engines[GPIO_DDC_LINE_COUNT]; 68*b843c749SSergey Zigachev 69*b843c749SSergey Zigachev /* I2C HW engines, per DDC line. 70*b843c749SSergey Zigachev * Only lines with HW DDC support will be initialized */ 71*b843c749SSergey Zigachev struct i2c_engine *i2c_hw_engines[GPIO_DDC_LINE_COUNT]; 72*b843c749SSergey Zigachev 73*b843c749SSergey Zigachev /* AUX engines, per DDC line. 74*b843c749SSergey Zigachev * Only lines with HW AUX support will be initialized */ 75*b843c749SSergey Zigachev struct aux_engine *aux_engines[GPIO_DDC_LINE_COUNT]; 76*b843c749SSergey Zigachev 77*b843c749SSergey Zigachev /* For all other lines, we can use 78*b843c749SSergey Zigachev * single instance of generic I2C HW engine 79*b843c749SSergey Zigachev * (since in HW, there is single instance of it) 80*b843c749SSergey Zigachev * or single instance of generic I2C SW engine. 81*b843c749SSergey Zigachev * AUX is not supported for other lines. */ 82*b843c749SSergey Zigachev 83*b843c749SSergey Zigachev /* General-purpose I2C SW engine. 84*b843c749SSergey Zigachev * Can be assigned dynamically to any line per transaction */ 85*b843c749SSergey Zigachev struct i2c_engine *i2c_generic_sw_engine; 86*b843c749SSergey Zigachev 87*b843c749SSergey Zigachev /* General-purpose I2C generic HW engine. 88*b843c749SSergey Zigachev * Can be assigned dynamically to almost any line per transaction */ 89*b843c749SSergey Zigachev struct i2c_engine *i2c_generic_hw_engine; 90*b843c749SSergey Zigachev 91*b843c749SSergey Zigachev /* [anaumov] in DAL2, there is a Mutex */ 92*b843c749SSergey Zigachev 93*b843c749SSergey Zigachev uint32_t aux_timeout_period; 94*b843c749SSergey Zigachev 95*b843c749SSergey Zigachev /* expressed in KHz */ 96*b843c749SSergey Zigachev uint32_t default_i2c_sw_speed; 97*b843c749SSergey Zigachev uint32_t default_i2c_hw_speed; 98*b843c749SSergey Zigachev }; 99*b843c749SSergey Zigachev 100*b843c749SSergey Zigachev void dal_i2caux_construct( 101*b843c749SSergey Zigachev struct i2caux *i2caux, 102*b843c749SSergey Zigachev struct dc_context *ctx); 103*b843c749SSergey Zigachev 104*b843c749SSergey Zigachev void dal_i2caux_release_engine( 105*b843c749SSergey Zigachev struct i2caux *i2caux, 106*b843c749SSergey Zigachev struct engine *engine); 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev void dal_i2caux_destruct( 109*b843c749SSergey Zigachev struct i2caux *i2caux); 110*b843c749SSergey Zigachev 111*b843c749SSergey Zigachev struct i2c_engine *dal_i2caux_acquire_i2c_sw_engine( 112*b843c749SSergey Zigachev struct i2caux *i2caux, 113*b843c749SSergey Zigachev struct ddc *ddc); 114*b843c749SSergey Zigachev 115*b843c749SSergey Zigachev struct aux_engine *dal_i2caux_acquire_aux_engine( 116*b843c749SSergey Zigachev struct i2caux *i2caux, 117*b843c749SSergey Zigachev struct ddc *ddc); 118*b843c749SSergey Zigachev 119*b843c749SSergey Zigachev #endif 120