1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dm_services.h"
27*b843c749SSergey Zigachev
28*b843c749SSergey Zigachev /*
29*b843c749SSergey Zigachev * Pre-requisites: headers required by header of this unit
30*b843c749SSergey Zigachev */
31*b843c749SSergey Zigachev #include "include/i2caux_interface.h"
32*b843c749SSergey Zigachev #include "../i2caux.h"
33*b843c749SSergey Zigachev #include "../engine.h"
34*b843c749SSergey Zigachev #include "../i2c_engine.h"
35*b843c749SSergey Zigachev #include "../i2c_sw_engine.h"
36*b843c749SSergey Zigachev #include "../i2c_hw_engine.h"
37*b843c749SSergey Zigachev
38*b843c749SSergey Zigachev /*
39*b843c749SSergey Zigachev * Header of this unit
40*b843c749SSergey Zigachev */
41*b843c749SSergey Zigachev #include "i2caux_dce110.h"
42*b843c749SSergey Zigachev
43*b843c749SSergey Zigachev #include "i2c_sw_engine_dce110.h"
44*b843c749SSergey Zigachev #include "i2c_hw_engine_dce110.h"
45*b843c749SSergey Zigachev #include "aux_engine_dce110.h"
46*b843c749SSergey Zigachev #include "../../dc.h"
47*b843c749SSergey Zigachev #include "dc_types.h"
48*b843c749SSergey Zigachev
49*b843c749SSergey Zigachev
50*b843c749SSergey Zigachev /*
51*b843c749SSergey Zigachev * Post-requisites: headers required by this unit
52*b843c749SSergey Zigachev */
53*b843c749SSergey Zigachev
54*b843c749SSergey Zigachev /*
55*b843c749SSergey Zigachev * This unit
56*b843c749SSergey Zigachev */
57*b843c749SSergey Zigachev /*cast pointer to struct i2caux TO pointer to struct i2caux_dce110*/
58*b843c749SSergey Zigachev #define FROM_I2C_AUX(ptr) \
59*b843c749SSergey Zigachev container_of((ptr), struct i2caux_dce110, base)
60*b843c749SSergey Zigachev
destruct(struct i2caux_dce110 * i2caux_dce110)61*b843c749SSergey Zigachev static void destruct(
62*b843c749SSergey Zigachev struct i2caux_dce110 *i2caux_dce110)
63*b843c749SSergey Zigachev {
64*b843c749SSergey Zigachev dal_i2caux_destruct(&i2caux_dce110->base);
65*b843c749SSergey Zigachev }
66*b843c749SSergey Zigachev
destroy(struct i2caux ** i2c_engine)67*b843c749SSergey Zigachev static void destroy(
68*b843c749SSergey Zigachev struct i2caux **i2c_engine)
69*b843c749SSergey Zigachev {
70*b843c749SSergey Zigachev struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(*i2c_engine);
71*b843c749SSergey Zigachev
72*b843c749SSergey Zigachev destruct(i2caux_dce110);
73*b843c749SSergey Zigachev
74*b843c749SSergey Zigachev kfree(i2caux_dce110);
75*b843c749SSergey Zigachev
76*b843c749SSergey Zigachev *i2c_engine = NULL;
77*b843c749SSergey Zigachev }
78*b843c749SSergey Zigachev
acquire_i2c_hw_engine(struct i2caux * i2caux,struct ddc * ddc)79*b843c749SSergey Zigachev static struct i2c_engine *acquire_i2c_hw_engine(
80*b843c749SSergey Zigachev struct i2caux *i2caux,
81*b843c749SSergey Zigachev struct ddc *ddc)
82*b843c749SSergey Zigachev {
83*b843c749SSergey Zigachev struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
84*b843c749SSergey Zigachev
85*b843c749SSergey Zigachev struct i2c_engine *engine = NULL;
86*b843c749SSergey Zigachev /* generic hw engine is not used for EDID read
87*b843c749SSergey Zigachev * It may be needed for external i2c device, like thermal chip,
88*b843c749SSergey Zigachev * TODO will be implemented when needed.
89*b843c749SSergey Zigachev * check dce80 bool non_generic for generic hw engine;
90*b843c749SSergey Zigachev */
91*b843c749SSergey Zigachev
92*b843c749SSergey Zigachev if (!ddc)
93*b843c749SSergey Zigachev return NULL;
94*b843c749SSergey Zigachev
95*b843c749SSergey Zigachev if (ddc->hw_info.hw_supported) {
96*b843c749SSergey Zigachev enum gpio_ddc_line line = dal_ddc_get_line(ddc);
97*b843c749SSergey Zigachev
98*b843c749SSergey Zigachev if (line < GPIO_DDC_LINE_COUNT)
99*b843c749SSergey Zigachev engine = i2caux->i2c_hw_engines[line];
100*b843c749SSergey Zigachev }
101*b843c749SSergey Zigachev
102*b843c749SSergey Zigachev if (!engine)
103*b843c749SSergey Zigachev return NULL;
104*b843c749SSergey Zigachev
105*b843c749SSergey Zigachev if (!i2caux_dce110->i2c_hw_buffer_in_use &&
106*b843c749SSergey Zigachev engine->base.funcs->acquire(&engine->base, ddc)) {
107*b843c749SSergey Zigachev i2caux_dce110->i2c_hw_buffer_in_use = true;
108*b843c749SSergey Zigachev return engine;
109*b843c749SSergey Zigachev }
110*b843c749SSergey Zigachev
111*b843c749SSergey Zigachev return NULL;
112*b843c749SSergey Zigachev }
113*b843c749SSergey Zigachev
release_engine(struct i2caux * i2caux,struct engine * engine)114*b843c749SSergey Zigachev static void release_engine(
115*b843c749SSergey Zigachev struct i2caux *i2caux,
116*b843c749SSergey Zigachev struct engine *engine)
117*b843c749SSergey Zigachev {
118*b843c749SSergey Zigachev struct i2caux_dce110 *i2caux_dce110 = FROM_I2C_AUX(i2caux);
119*b843c749SSergey Zigachev
120*b843c749SSergey Zigachev if (engine->funcs->get_engine_type(engine) ==
121*b843c749SSergey Zigachev I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
122*b843c749SSergey Zigachev i2caux_dce110->i2c_hw_buffer_in_use = false;
123*b843c749SSergey Zigachev
124*b843c749SSergey Zigachev dal_i2caux_release_engine(i2caux, engine);
125*b843c749SSergey Zigachev }
126*b843c749SSergey Zigachev
127*b843c749SSergey Zigachev static const enum gpio_ddc_line hw_ddc_lines[] = {
128*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC1,
129*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC2,
130*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC3,
131*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC4,
132*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC5,
133*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC6,
134*b843c749SSergey Zigachev };
135*b843c749SSergey Zigachev
136*b843c749SSergey Zigachev static const enum gpio_ddc_line hw_aux_lines[] = {
137*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC1,
138*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC2,
139*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC3,
140*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC4,
141*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC5,
142*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC6,
143*b843c749SSergey Zigachev };
144*b843c749SSergey Zigachev
145*b843c749SSergey Zigachev /* function table */
146*b843c749SSergey Zigachev static const struct i2caux_funcs i2caux_funcs = {
147*b843c749SSergey Zigachev .destroy = destroy,
148*b843c749SSergey Zigachev .acquire_i2c_hw_engine = acquire_i2c_hw_engine,
149*b843c749SSergey Zigachev .release_engine = release_engine,
150*b843c749SSergey Zigachev .acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
151*b843c749SSergey Zigachev .acquire_aux_engine = dal_i2caux_acquire_aux_engine,
152*b843c749SSergey Zigachev };
153*b843c749SSergey Zigachev
154*b843c749SSergey Zigachev #include "dce/dce_11_0_d.h"
155*b843c749SSergey Zigachev #include "dce/dce_11_0_sh_mask.h"
156*b843c749SSergey Zigachev
157*b843c749SSergey Zigachev /* set register offset */
158*b843c749SSergey Zigachev #define SR(reg_name)\
159*b843c749SSergey Zigachev .reg_name = mm ## reg_name
160*b843c749SSergey Zigachev
161*b843c749SSergey Zigachev /* set register offset with instance */
162*b843c749SSergey Zigachev #define SRI(reg_name, block, id)\
163*b843c749SSergey Zigachev .reg_name = mm ## block ## id ## _ ## reg_name
164*b843c749SSergey Zigachev
165*b843c749SSergey Zigachev #define aux_regs(id)\
166*b843c749SSergey Zigachev [id] = {\
167*b843c749SSergey Zigachev AUX_COMMON_REG_LIST(id), \
168*b843c749SSergey Zigachev .AUX_RESET_MASK = AUX_CONTROL__AUX_RESET_MASK \
169*b843c749SSergey Zigachev }
170*b843c749SSergey Zigachev
171*b843c749SSergey Zigachev #define hw_engine_regs(id)\
172*b843c749SSergey Zigachev {\
173*b843c749SSergey Zigachev I2C_HW_ENGINE_COMMON_REG_LIST(id) \
174*b843c749SSergey Zigachev }
175*b843c749SSergey Zigachev
176*b843c749SSergey Zigachev static const struct dce110_aux_registers dce110_aux_regs[] = {
177*b843c749SSergey Zigachev aux_regs(0),
178*b843c749SSergey Zigachev aux_regs(1),
179*b843c749SSergey Zigachev aux_regs(2),
180*b843c749SSergey Zigachev aux_regs(3),
181*b843c749SSergey Zigachev aux_regs(4),
182*b843c749SSergey Zigachev aux_regs(5)
183*b843c749SSergey Zigachev };
184*b843c749SSergey Zigachev
185*b843c749SSergey Zigachev static const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[] = {
186*b843c749SSergey Zigachev hw_engine_regs(1),
187*b843c749SSergey Zigachev hw_engine_regs(2),
188*b843c749SSergey Zigachev hw_engine_regs(3),
189*b843c749SSergey Zigachev hw_engine_regs(4),
190*b843c749SSergey Zigachev hw_engine_regs(5),
191*b843c749SSergey Zigachev hw_engine_regs(6)
192*b843c749SSergey Zigachev };
193*b843c749SSergey Zigachev
194*b843c749SSergey Zigachev static const struct dce110_i2c_hw_engine_shift i2c_shift = {
195*b843c749SSergey Zigachev I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
196*b843c749SSergey Zigachev };
197*b843c749SSergey Zigachev
198*b843c749SSergey Zigachev static const struct dce110_i2c_hw_engine_mask i2c_mask = {
199*b843c749SSergey Zigachev I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
200*b843c749SSergey Zigachev };
201*b843c749SSergey Zigachev
dal_i2caux_dce110_construct(struct i2caux_dce110 * i2caux_dce110,struct dc_context * ctx,unsigned int num_i2caux_inst,const struct dce110_aux_registers aux_regs[],const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],const struct dce110_i2c_hw_engine_shift * i2c_shift,const struct dce110_i2c_hw_engine_mask * i2c_mask)202*b843c749SSergey Zigachev void dal_i2caux_dce110_construct(
203*b843c749SSergey Zigachev struct i2caux_dce110 *i2caux_dce110,
204*b843c749SSergey Zigachev struct dc_context *ctx,
205*b843c749SSergey Zigachev unsigned int num_i2caux_inst,
206*b843c749SSergey Zigachev const struct dce110_aux_registers aux_regs[],
207*b843c749SSergey Zigachev const struct dce110_i2c_hw_engine_registers i2c_hw_engine_regs[],
208*b843c749SSergey Zigachev const struct dce110_i2c_hw_engine_shift *i2c_shift,
209*b843c749SSergey Zigachev const struct dce110_i2c_hw_engine_mask *i2c_mask)
210*b843c749SSergey Zigachev {
211*b843c749SSergey Zigachev uint32_t i = 0;
212*b843c749SSergey Zigachev uint32_t reference_frequency = 0;
213*b843c749SSergey Zigachev bool use_i2c_sw_engine = false;
214*b843c749SSergey Zigachev struct i2caux *base = NULL;
215*b843c749SSergey Zigachev /*TODO: For CZ bring up, if dal_i2caux_get_reference_clock
216*b843c749SSergey Zigachev * does not return 48KHz, we need hard coded for 48Khz.
217*b843c749SSergey Zigachev * Some BIOS setting incorrect cause this
218*b843c749SSergey Zigachev * For production, we always get value from BIOS*/
219*b843c749SSergey Zigachev reference_frequency =
220*b843c749SSergey Zigachev dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
221*b843c749SSergey Zigachev
222*b843c749SSergey Zigachev base = &i2caux_dce110->base;
223*b843c749SSergey Zigachev
224*b843c749SSergey Zigachev dal_i2caux_construct(base, ctx);
225*b843c749SSergey Zigachev
226*b843c749SSergey Zigachev i2caux_dce110->base.funcs = &i2caux_funcs;
227*b843c749SSergey Zigachev i2caux_dce110->i2c_hw_buffer_in_use = false;
228*b843c749SSergey Zigachev /* Create I2C engines (DDC lines per connector)
229*b843c749SSergey Zigachev * different I2C/AUX usage cases, DDC, Generic GPIO, AUX.
230*b843c749SSergey Zigachev */
231*b843c749SSergey Zigachev do {
232*b843c749SSergey Zigachev enum gpio_ddc_line line_id = hw_ddc_lines[i];
233*b843c749SSergey Zigachev
234*b843c749SSergey Zigachev struct i2c_hw_engine_dce110_create_arg hw_arg_dce110;
235*b843c749SSergey Zigachev
236*b843c749SSergey Zigachev if (use_i2c_sw_engine) {
237*b843c749SSergey Zigachev struct i2c_sw_engine_dce110_create_arg sw_arg;
238*b843c749SSergey Zigachev
239*b843c749SSergey Zigachev sw_arg.engine_id = i;
240*b843c749SSergey Zigachev sw_arg.default_speed = base->default_i2c_sw_speed;
241*b843c749SSergey Zigachev sw_arg.ctx = ctx;
242*b843c749SSergey Zigachev base->i2c_sw_engines[line_id] =
243*b843c749SSergey Zigachev dal_i2c_sw_engine_dce110_create(&sw_arg);
244*b843c749SSergey Zigachev }
245*b843c749SSergey Zigachev
246*b843c749SSergey Zigachev hw_arg_dce110.engine_id = i;
247*b843c749SSergey Zigachev hw_arg_dce110.reference_frequency = reference_frequency;
248*b843c749SSergey Zigachev hw_arg_dce110.default_speed = base->default_i2c_hw_speed;
249*b843c749SSergey Zigachev hw_arg_dce110.ctx = ctx;
250*b843c749SSergey Zigachev hw_arg_dce110.regs = &i2c_hw_engine_regs[i];
251*b843c749SSergey Zigachev hw_arg_dce110.i2c_shift = i2c_shift;
252*b843c749SSergey Zigachev hw_arg_dce110.i2c_mask = i2c_mask;
253*b843c749SSergey Zigachev
254*b843c749SSergey Zigachev base->i2c_hw_engines[line_id] =
255*b843c749SSergey Zigachev dal_i2c_hw_engine_dce110_create(&hw_arg_dce110);
256*b843c749SSergey Zigachev if (base->i2c_hw_engines[line_id] != NULL) {
257*b843c749SSergey Zigachev switch (ctx->dce_version) {
258*b843c749SSergey Zigachev case DCN_VERSION_1_0:
259*b843c749SSergey Zigachev base->i2c_hw_engines[line_id]->setup_limit =
260*b843c749SSergey Zigachev I2C_SETUP_TIME_LIMIT_DCN;
261*b843c749SSergey Zigachev base->i2c_hw_engines[line_id]->send_reset_length = 0;
262*b843c749SSergey Zigachev break;
263*b843c749SSergey Zigachev default:
264*b843c749SSergey Zigachev base->i2c_hw_engines[line_id]->setup_limit =
265*b843c749SSergey Zigachev I2C_SETUP_TIME_LIMIT_DCE;
266*b843c749SSergey Zigachev base->i2c_hw_engines[line_id]->send_reset_length = 0;
267*b843c749SSergey Zigachev break;
268*b843c749SSergey Zigachev }
269*b843c749SSergey Zigachev }
270*b843c749SSergey Zigachev ++i;
271*b843c749SSergey Zigachev } while (i < num_i2caux_inst);
272*b843c749SSergey Zigachev
273*b843c749SSergey Zigachev /* Create AUX engines for all lines which has assisted HW AUX
274*b843c749SSergey Zigachev * 'i' (loop counter) used as DDC/AUX engine_id */
275*b843c749SSergey Zigachev
276*b843c749SSergey Zigachev i = 0;
277*b843c749SSergey Zigachev
278*b843c749SSergey Zigachev do {
279*b843c749SSergey Zigachev enum gpio_ddc_line line_id = hw_aux_lines[i];
280*b843c749SSergey Zigachev
281*b843c749SSergey Zigachev struct aux_engine_dce110_init_data aux_init_data;
282*b843c749SSergey Zigachev
283*b843c749SSergey Zigachev aux_init_data.engine_id = i;
284*b843c749SSergey Zigachev aux_init_data.timeout_period = base->aux_timeout_period;
285*b843c749SSergey Zigachev aux_init_data.ctx = ctx;
286*b843c749SSergey Zigachev aux_init_data.regs = &aux_regs[i];
287*b843c749SSergey Zigachev
288*b843c749SSergey Zigachev base->aux_engines[line_id] =
289*b843c749SSergey Zigachev dal_aux_engine_dce110_create(&aux_init_data);
290*b843c749SSergey Zigachev
291*b843c749SSergey Zigachev ++i;
292*b843c749SSergey Zigachev } while (i < num_i2caux_inst);
293*b843c749SSergey Zigachev
294*b843c749SSergey Zigachev /*TODO Generic I2C SW and HW*/
295*b843c749SSergey Zigachev }
296*b843c749SSergey Zigachev
297*b843c749SSergey Zigachev /*
298*b843c749SSergey Zigachev * dal_i2caux_dce110_create
299*b843c749SSergey Zigachev *
300*b843c749SSergey Zigachev * @brief
301*b843c749SSergey Zigachev * public interface to allocate memory for DCE11 I2CAUX
302*b843c749SSergey Zigachev *
303*b843c749SSergey Zigachev * @param
304*b843c749SSergey Zigachev * struct adapter_service *as - [in]
305*b843c749SSergey Zigachev * struct dc_context *ctx - [in]
306*b843c749SSergey Zigachev *
307*b843c749SSergey Zigachev * @return
308*b843c749SSergey Zigachev * pointer to the base struct of DCE11 I2CAUX
309*b843c749SSergey Zigachev */
dal_i2caux_dce110_create(struct dc_context * ctx)310*b843c749SSergey Zigachev struct i2caux *dal_i2caux_dce110_create(
311*b843c749SSergey Zigachev struct dc_context *ctx)
312*b843c749SSergey Zigachev {
313*b843c749SSergey Zigachev struct i2caux_dce110 *i2caux_dce110 =
314*b843c749SSergey Zigachev kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL);
315*b843c749SSergey Zigachev
316*b843c749SSergey Zigachev if (!i2caux_dce110) {
317*b843c749SSergey Zigachev ASSERT_CRITICAL(false);
318*b843c749SSergey Zigachev return NULL;
319*b843c749SSergey Zigachev }
320*b843c749SSergey Zigachev
321*b843c749SSergey Zigachev dal_i2caux_dce110_construct(i2caux_dce110,
322*b843c749SSergey Zigachev ctx,
323*b843c749SSergey Zigachev ARRAY_SIZE(dce110_aux_regs),
324*b843c749SSergey Zigachev dce110_aux_regs,
325*b843c749SSergey Zigachev i2c_hw_engine_regs,
326*b843c749SSergey Zigachev &i2c_shift,
327*b843c749SSergey Zigachev &i2c_mask);
328*b843c749SSergey Zigachev return &i2caux_dce110->base;
329*b843c749SSergey Zigachev }
330