1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2017 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef DM_PP_SMU_IF__H 27*b843c749SSergey Zigachev #define DM_PP_SMU_IF__H 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev /* 30*b843c749SSergey Zigachev * interface to PPLIB/SMU to setup clocks and pstate requirements on SoC 31*b843c749SSergey Zigachev */ 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev struct pp_smu { 35*b843c749SSergey Zigachev struct dc_context *ctx; 36*b843c749SSergey Zigachev }; 37*b843c749SSergey Zigachev 38*b843c749SSergey Zigachev enum wm_set_id { 39*b843c749SSergey Zigachev WM_A, 40*b843c749SSergey Zigachev WM_B, 41*b843c749SSergey Zigachev WM_C, 42*b843c749SSergey Zigachev WM_D, 43*b843c749SSergey Zigachev WM_SET_COUNT, 44*b843c749SSergey Zigachev }; 45*b843c749SSergey Zigachev 46*b843c749SSergey Zigachev struct pp_smu_wm_set_range { 47*b843c749SSergey Zigachev enum wm_set_id wm_inst; 48*b843c749SSergey Zigachev uint32_t min_fill_clk_khz; 49*b843c749SSergey Zigachev uint32_t max_fill_clk_khz; 50*b843c749SSergey Zigachev uint32_t min_drain_clk_khz; 51*b843c749SSergey Zigachev uint32_t max_drain_clk_khz; 52*b843c749SSergey Zigachev }; 53*b843c749SSergey Zigachev 54*b843c749SSergey Zigachev struct pp_smu_wm_range_sets { 55*b843c749SSergey Zigachev uint32_t num_reader_wm_sets; 56*b843c749SSergey Zigachev struct pp_smu_wm_set_range reader_wm_sets[WM_SET_COUNT]; 57*b843c749SSergey Zigachev 58*b843c749SSergey Zigachev uint32_t num_writer_wm_sets; 59*b843c749SSergey Zigachev struct pp_smu_wm_set_range writer_wm_sets[WM_SET_COUNT]; 60*b843c749SSergey Zigachev }; 61*b843c749SSergey Zigachev 62*b843c749SSergey Zigachev struct pp_smu_display_requirement_rv { 63*b843c749SSergey Zigachev /* PPSMC_MSG_SetDisplayCount: count 64*b843c749SSergey Zigachev * 0 triggers S0i2 optimization 65*b843c749SSergey Zigachev */ 66*b843c749SSergey Zigachev unsigned int display_count; 67*b843c749SSergey Zigachev 68*b843c749SSergey Zigachev /* PPSMC_MSG_SetHardMinFclkByFreq: khz 69*b843c749SSergey Zigachev * FCLK will vary with DPM, but never below requested hard min 70*b843c749SSergey Zigachev */ 71*b843c749SSergey Zigachev unsigned int hard_min_fclk_khz; 72*b843c749SSergey Zigachev 73*b843c749SSergey Zigachev /* PPSMC_MSG_SetHardMinDcefclkByFreq: khz 74*b843c749SSergey Zigachev * fixed clock at requested freq, either from FCH bypass or DFS 75*b843c749SSergey Zigachev */ 76*b843c749SSergey Zigachev unsigned int hard_min_dcefclk_khz; 77*b843c749SSergey Zigachev 78*b843c749SSergey Zigachev /* PPSMC_MSG_SetMinDeepSleepDcefclk: mhz 79*b843c749SSergey Zigachev * when DF is in cstate, dcf clock is further divided down 80*b843c749SSergey Zigachev * to just above given frequency 81*b843c749SSergey Zigachev */ 82*b843c749SSergey Zigachev unsigned int min_deep_sleep_dcefclk_mhz; 83*b843c749SSergey Zigachev }; 84*b843c749SSergey Zigachev 85*b843c749SSergey Zigachev struct pp_smu_funcs_rv { 86*b843c749SSergey Zigachev struct pp_smu pp_smu; 87*b843c749SSergey Zigachev 88*b843c749SSergey Zigachev void (*set_display_requirement)(struct pp_smu *pp, 89*b843c749SSergey Zigachev struct pp_smu_display_requirement_rv *req); 90*b843c749SSergey Zigachev 91*b843c749SSergey Zigachev /* which SMU message? are reader and writer WM separate SMU msg? */ 92*b843c749SSergey Zigachev void (*set_wm_ranges)(struct pp_smu *pp, 93*b843c749SSergey Zigachev struct pp_smu_wm_range_sets *ranges); 94*b843c749SSergey Zigachev /* PME w/a */ 95*b843c749SSergey Zigachev void (*set_pme_wa_enable)(struct pp_smu *pp); 96*b843c749SSergey Zigachev }; 97*b843c749SSergey Zigachev 98*b843c749SSergey Zigachev #if 0 99*b843c749SSergey Zigachev struct pp_smu_funcs_rv { 100*b843c749SSergey Zigachev 101*b843c749SSergey Zigachev /* PPSMC_MSG_SetDisplayCount 102*b843c749SSergey Zigachev * 0 triggers S0i2 optimization 103*b843c749SSergey Zigachev */ 104*b843c749SSergey Zigachev void (*set_display_count)(struct pp_smu *pp, int count); 105*b843c749SSergey Zigachev 106*b843c749SSergey Zigachev /* PPSMC_MSG_SetHardMinFclkByFreq 107*b843c749SSergey Zigachev * FCLK will vary with DPM, but never below requested hard min 108*b843c749SSergey Zigachev */ 109*b843c749SSergey Zigachev void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int khz); 110*b843c749SSergey Zigachev 111*b843c749SSergey Zigachev /* PPSMC_MSG_SetHardMinDcefclkByFreq 112*b843c749SSergey Zigachev * fixed clock at requested freq, either from FCH bypass or DFS 113*b843c749SSergey Zigachev */ 114*b843c749SSergey Zigachev void (*set_hard_min_dcefclk_by_freq)(struct pp_smu *pp, int khz); 115*b843c749SSergey Zigachev 116*b843c749SSergey Zigachev /* PPSMC_MSG_SetMinDeepSleepDcefclk 117*b843c749SSergey Zigachev * when DF is in cstate, dcf clock is further divided down 118*b843c749SSergey Zigachev * to just above given frequency 119*b843c749SSergey Zigachev */ 120*b843c749SSergey Zigachev void (*set_min_deep_sleep_dcefclk)(struct pp_smu *pp, int mhz); 121*b843c749SSergey Zigachev 122*b843c749SSergey Zigachev /* todo: aesthetic 123*b843c749SSergey Zigachev * watermark range table 124*b843c749SSergey Zigachev */ 125*b843c749SSergey Zigachev 126*b843c749SSergey Zigachev /* todo: functional/feature 127*b843c749SSergey Zigachev * PPSMC_MSG_SetHardMinSocclkByFreq: required to support DWB 128*b843c749SSergey Zigachev */ 129*b843c749SSergey Zigachev }; 130*b843c749SSergey Zigachev #endif 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev #endif /* DM_PP_SMU_IF__H */ 133