1*b843c749SSergey Zigachev /* Copyright 2012-15 Advanced Micro Devices, Inc. 2*b843c749SSergey Zigachev * 3*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 4*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 5*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 6*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 8*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 9*b843c749SSergey Zigachev * 10*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 11*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 12*b843c749SSergey Zigachev * 13*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 20*b843c749SSergey Zigachev * 21*b843c749SSergey Zigachev * Authors: AMD 22*b843c749SSergey Zigachev * 23*b843c749SSergey Zigachev */ 24*b843c749SSergey Zigachev 25*b843c749SSergey Zigachev #ifndef __DC_CLOCK_SOURCE_DCE_H__ 26*b843c749SSergey Zigachev #define __DC_CLOCK_SOURCE_DCE_H__ 27*b843c749SSergey Zigachev 28*b843c749SSergey Zigachev #include "../inc/clock_source.h" 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define TO_DCE110_CLK_SRC(clk_src)\ 31*b843c749SSergey Zigachev container_of(clk_src, struct dce110_clk_src, base) 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev #define CS_COMMON_REG_LIST_DCE_100_110(id) \ 34*b843c749SSergey Zigachev SRI(RESYNC_CNTL, PIXCLK, id), \ 35*b843c749SSergey Zigachev SRI(PLL_CNTL, BPHYC_PLL, id) 36*b843c749SSergey Zigachev 37*b843c749SSergey Zigachev #define CS_COMMON_REG_LIST_DCE_80(id) \ 38*b843c749SSergey Zigachev SRI(RESYNC_CNTL, PIXCLK, id), \ 39*b843c749SSergey Zigachev SRI(PLL_CNTL, DCCG_PLL, id) 40*b843c749SSergey Zigachev 41*b843c749SSergey Zigachev #define CS_COMMON_REG_LIST_DCE_112(id) \ 42*b843c749SSergey Zigachev SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) 43*b843c749SSergey Zigachev 44*b843c749SSergey Zigachev 45*b843c749SSergey Zigachev #define CS_SF(reg_name, field_name, post_fix)\ 46*b843c749SSergey Zigachev .field_name = reg_name ## __ ## field_name ## post_fix 47*b843c749SSergey Zigachev 48*b843c749SSergey Zigachev #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 49*b843c749SSergey Zigachev CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ 50*b843c749SSergey Zigachev CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ 51*b843c749SSergey Zigachev CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ 52*b843c749SSergey Zigachev CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) 53*b843c749SSergey Zigachev 54*b843c749SSergey Zigachev #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 55*b843c749SSergey Zigachev CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 56*b843c749SSergey Zigachev CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) 57*b843c749SSergey Zigachev 58*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 59*b843c749SSergey Zigachev 60*b843c749SSergey Zigachev #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ 61*b843c749SSergey Zigachev SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 62*b843c749SSergey Zigachev SRII(PHASE, DP_DTO, 0),\ 63*b843c749SSergey Zigachev SRII(PHASE, DP_DTO, 1),\ 64*b843c749SSergey Zigachev SRII(PHASE, DP_DTO, 2),\ 65*b843c749SSergey Zigachev SRII(PHASE, DP_DTO, 3),\ 66*b843c749SSergey Zigachev SRII(MODULO, DP_DTO, 0),\ 67*b843c749SSergey Zigachev SRII(MODULO, DP_DTO, 1),\ 68*b843c749SSergey Zigachev SRII(MODULO, DP_DTO, 2),\ 69*b843c749SSergey Zigachev SRII(MODULO, DP_DTO, 3),\ 70*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, OTG, 0), \ 71*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, OTG, 1), \ 72*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, OTG, 2), \ 73*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, OTG, 3) 74*b843c749SSergey Zigachev 75*b843c749SSergey Zigachev #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 76*b843c749SSergey Zigachev CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 77*b843c749SSergey Zigachev CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 78*b843c749SSergey Zigachev CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 79*b843c749SSergey Zigachev CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev #endif 82*b843c749SSergey Zigachev 83*b843c749SSergey Zigachev #define CS_REG_FIELD_LIST(type) \ 84*b843c749SSergey Zigachev type PLL_REF_DIV_SRC; \ 85*b843c749SSergey Zigachev type DCCG_DEEP_COLOR_CNTL1; \ 86*b843c749SSergey Zigachev type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \ 87*b843c749SSergey Zigachev type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ 88*b843c749SSergey Zigachev type PLL_POST_DIV_PIXCLK; \ 89*b843c749SSergey Zigachev type PLL_REF_DIV; \ 90*b843c749SSergey Zigachev type DP_DTO0_PHASE; \ 91*b843c749SSergey Zigachev type DP_DTO0_MODULO; \ 92*b843c749SSergey Zigachev type DP_DTO0_ENABLE; 93*b843c749SSergey Zigachev 94*b843c749SSergey Zigachev struct dce110_clk_src_shift { 95*b843c749SSergey Zigachev CS_REG_FIELD_LIST(uint8_t) 96*b843c749SSergey Zigachev }; 97*b843c749SSergey Zigachev 98*b843c749SSergey Zigachev struct dce110_clk_src_mask{ 99*b843c749SSergey Zigachev CS_REG_FIELD_LIST(uint32_t) 100*b843c749SSergey Zigachev }; 101*b843c749SSergey Zigachev 102*b843c749SSergey Zigachev struct dce110_clk_src_regs { 103*b843c749SSergey Zigachev uint32_t RESYNC_CNTL; 104*b843c749SSergey Zigachev uint32_t PIXCLK_RESYNC_CNTL; 105*b843c749SSergey Zigachev uint32_t PLL_CNTL; 106*b843c749SSergey Zigachev 107*b843c749SSergey Zigachev /* below are for DTO. 108*b843c749SSergey Zigachev * todo: should probably use different struct to not waste space 109*b843c749SSergey Zigachev */ 110*b843c749SSergey Zigachev uint32_t PHASE[MAX_PIPES]; 111*b843c749SSergey Zigachev uint32_t MODULO[MAX_PIPES]; 112*b843c749SSergey Zigachev uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; 113*b843c749SSergey Zigachev }; 114*b843c749SSergey Zigachev 115*b843c749SSergey Zigachev struct dce110_clk_src { 116*b843c749SSergey Zigachev struct clock_source base; 117*b843c749SSergey Zigachev const struct dce110_clk_src_regs *regs; 118*b843c749SSergey Zigachev const struct dce110_clk_src_mask *cs_mask; 119*b843c749SSergey Zigachev const struct dce110_clk_src_shift *cs_shift; 120*b843c749SSergey Zigachev struct dc_bios *bios; 121*b843c749SSergey Zigachev 122*b843c749SSergey Zigachev struct spread_spectrum_data *dp_ss_params; 123*b843c749SSergey Zigachev uint32_t dp_ss_params_cnt; 124*b843c749SSergey Zigachev struct spread_spectrum_data *hdmi_ss_params; 125*b843c749SSergey Zigachev uint32_t hdmi_ss_params_cnt; 126*b843c749SSergey Zigachev struct spread_spectrum_data *dvi_ss_params; 127*b843c749SSergey Zigachev uint32_t dvi_ss_params_cnt; 128*b843c749SSergey Zigachev 129*b843c749SSergey Zigachev uint32_t ext_clk_khz; 130*b843c749SSergey Zigachev uint32_t ref_freq_khz; 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev struct calc_pll_clock_source calc_pll; 133*b843c749SSergey Zigachev struct calc_pll_clock_source calc_pll_hdmi; 134*b843c749SSergey Zigachev }; 135*b843c749SSergey Zigachev 136*b843c749SSergey Zigachev bool dce110_clk_src_construct( 137*b843c749SSergey Zigachev struct dce110_clk_src *clk_src, 138*b843c749SSergey Zigachev struct dc_context *ctx, 139*b843c749SSergey Zigachev struct dc_bios *bios, 140*b843c749SSergey Zigachev enum clock_source_id, 141*b843c749SSergey Zigachev const struct dce110_clk_src_regs *regs, 142*b843c749SSergey Zigachev const struct dce110_clk_src_shift *cs_shift, 143*b843c749SSergey Zigachev const struct dce110_clk_src_mask *cs_mask); 144*b843c749SSergey Zigachev 145*b843c749SSergey Zigachev #endif 146