xref: /dflybsd-src/sys/dev/drm/amd/display/dc/dce/dce_clock_source.c (revision b843c749addef9340ee7d4e250b09fdd492602a1)
1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev  * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev  *
4*b843c749SSergey Zigachev  * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev  * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev  * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev  * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev  * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev  *
11*b843c749SSergey Zigachev  * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev  * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev  *
14*b843c749SSergey Zigachev  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*b843c749SSergey Zigachev  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev  * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev  *
22*b843c749SSergey Zigachev  * Authors: AMD
23*b843c749SSergey Zigachev  *
24*b843c749SSergey Zigachev  */
25*b843c749SSergey Zigachev 
26*b843c749SSergey Zigachev #include "dm_services.h"
27*b843c749SSergey Zigachev 
28*b843c749SSergey Zigachev 
29*b843c749SSergey Zigachev #include "dc_types.h"
30*b843c749SSergey Zigachev #include "core_types.h"
31*b843c749SSergey Zigachev 
32*b843c749SSergey Zigachev #include "include/grph_object_id.h"
33*b843c749SSergey Zigachev #include "include/logger_interface.h"
34*b843c749SSergey Zigachev 
35*b843c749SSergey Zigachev #include "dce_clock_source.h"
36*b843c749SSergey Zigachev 
37*b843c749SSergey Zigachev #include "reg_helper.h"
38*b843c749SSergey Zigachev 
39*b843c749SSergey Zigachev #define REG(reg)\
40*b843c749SSergey Zigachev 	(clk_src->regs->reg)
41*b843c749SSergey Zigachev 
42*b843c749SSergey Zigachev #define CTX \
43*b843c749SSergey Zigachev 	clk_src->base.ctx
44*b843c749SSergey Zigachev 
45*b843c749SSergey Zigachev #define DC_LOGGER_INIT()
46*b843c749SSergey Zigachev 
47*b843c749SSergey Zigachev #undef FN
48*b843c749SSergey Zigachev #define FN(reg_name, field_name) \
49*b843c749SSergey Zigachev 	clk_src->cs_shift->field_name, clk_src->cs_mask->field_name
50*b843c749SSergey Zigachev 
51*b843c749SSergey Zigachev #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6
52*b843c749SSergey Zigachev #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1
53*b843c749SSergey Zigachev #define MAX_PLL_CALC_ERROR 0xFFFFFFFF
54*b843c749SSergey Zigachev 
get_ss_data_entry(struct dce110_clk_src * clk_src,enum signal_type signal,uint32_t pix_clk_khz)55*b843c749SSergey Zigachev static const struct spread_spectrum_data *get_ss_data_entry(
56*b843c749SSergey Zigachev 		struct dce110_clk_src *clk_src,
57*b843c749SSergey Zigachev 		enum signal_type signal,
58*b843c749SSergey Zigachev 		uint32_t pix_clk_khz)
59*b843c749SSergey Zigachev {
60*b843c749SSergey Zigachev 
61*b843c749SSergey Zigachev 	uint32_t entrys_num;
62*b843c749SSergey Zigachev 	uint32_t i;
63*b843c749SSergey Zigachev 	struct spread_spectrum_data *ss_parm = NULL;
64*b843c749SSergey Zigachev 	struct spread_spectrum_data *ret = NULL;
65*b843c749SSergey Zigachev 
66*b843c749SSergey Zigachev 	switch (signal) {
67*b843c749SSergey Zigachev 	case SIGNAL_TYPE_DVI_SINGLE_LINK:
68*b843c749SSergey Zigachev 	case SIGNAL_TYPE_DVI_DUAL_LINK:
69*b843c749SSergey Zigachev 		ss_parm = clk_src->dvi_ss_params;
70*b843c749SSergey Zigachev 		entrys_num = clk_src->dvi_ss_params_cnt;
71*b843c749SSergey Zigachev 		break;
72*b843c749SSergey Zigachev 
73*b843c749SSergey Zigachev 	case SIGNAL_TYPE_HDMI_TYPE_A:
74*b843c749SSergey Zigachev 		ss_parm = clk_src->hdmi_ss_params;
75*b843c749SSergey Zigachev 		entrys_num = clk_src->hdmi_ss_params_cnt;
76*b843c749SSergey Zigachev 		break;
77*b843c749SSergey Zigachev 
78*b843c749SSergey Zigachev 	case SIGNAL_TYPE_DISPLAY_PORT:
79*b843c749SSergey Zigachev 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
80*b843c749SSergey Zigachev 	case SIGNAL_TYPE_EDP:
81*b843c749SSergey Zigachev 	case SIGNAL_TYPE_VIRTUAL:
82*b843c749SSergey Zigachev 		ss_parm = clk_src->dp_ss_params;
83*b843c749SSergey Zigachev 		entrys_num = clk_src->dp_ss_params_cnt;
84*b843c749SSergey Zigachev 		break;
85*b843c749SSergey Zigachev 
86*b843c749SSergey Zigachev 	default:
87*b843c749SSergey Zigachev 		ss_parm = NULL;
88*b843c749SSergey Zigachev 		entrys_num = 0;
89*b843c749SSergey Zigachev 		break;
90*b843c749SSergey Zigachev 	}
91*b843c749SSergey Zigachev 
92*b843c749SSergey Zigachev 	if (ss_parm == NULL)
93*b843c749SSergey Zigachev 		return ret;
94*b843c749SSergey Zigachev 
95*b843c749SSergey Zigachev 	for (i = 0; i < entrys_num; ++i, ++ss_parm) {
96*b843c749SSergey Zigachev 		if (ss_parm->freq_range_khz >= pix_clk_khz) {
97*b843c749SSergey Zigachev 			ret = ss_parm;
98*b843c749SSergey Zigachev 			break;
99*b843c749SSergey Zigachev 		}
100*b843c749SSergey Zigachev 	}
101*b843c749SSergey Zigachev 
102*b843c749SSergey Zigachev 	return ret;
103*b843c749SSergey Zigachev }
104*b843c749SSergey Zigachev 
105*b843c749SSergey Zigachev /**
106*b843c749SSergey Zigachev * Function: calculate_fb_and_fractional_fb_divider
107*b843c749SSergey Zigachev *
108*b843c749SSergey Zigachev * * DESCRIPTION: Calculates feedback and fractional feedback dividers values
109*b843c749SSergey Zigachev *
110*b843c749SSergey Zigachev *PARAMETERS:
111*b843c749SSergey Zigachev * targetPixelClock             Desired frequency in 10 KHz
112*b843c749SSergey Zigachev * ref_divider                  Reference divider (already known)
113*b843c749SSergey Zigachev * postDivider                  Post Divider (already known)
114*b843c749SSergey Zigachev * feedback_divider_param       Pointer where to store
115*b843c749SSergey Zigachev *					calculated feedback divider value
116*b843c749SSergey Zigachev * fract_feedback_divider_param Pointer where to store
117*b843c749SSergey Zigachev *					calculated fract feedback divider value
118*b843c749SSergey Zigachev *
119*b843c749SSergey Zigachev *RETURNS:
120*b843c749SSergey Zigachev * It fills the locations pointed by feedback_divider_param
121*b843c749SSergey Zigachev *					and fract_feedback_divider_param
122*b843c749SSergey Zigachev * It returns	- true if feedback divider not 0
123*b843c749SSergey Zigachev *		- false should never happen)
124*b843c749SSergey Zigachev */
calculate_fb_and_fractional_fb_divider(struct calc_pll_clock_source * calc_pll_cs,uint32_t target_pix_clk_khz,uint32_t ref_divider,uint32_t post_divider,uint32_t * feedback_divider_param,uint32_t * fract_feedback_divider_param)125*b843c749SSergey Zigachev static bool calculate_fb_and_fractional_fb_divider(
126*b843c749SSergey Zigachev 		struct calc_pll_clock_source *calc_pll_cs,
127*b843c749SSergey Zigachev 		uint32_t target_pix_clk_khz,
128*b843c749SSergey Zigachev 		uint32_t ref_divider,
129*b843c749SSergey Zigachev 		uint32_t post_divider,
130*b843c749SSergey Zigachev 		uint32_t *feedback_divider_param,
131*b843c749SSergey Zigachev 		uint32_t *fract_feedback_divider_param)
132*b843c749SSergey Zigachev {
133*b843c749SSergey Zigachev 	uint64_t feedback_divider;
134*b843c749SSergey Zigachev 
135*b843c749SSergey Zigachev 	feedback_divider =
136*b843c749SSergey Zigachev 		(uint64_t)target_pix_clk_khz * ref_divider * post_divider;
137*b843c749SSergey Zigachev 	feedback_divider *= 10;
138*b843c749SSergey Zigachev 	/* additional factor, since we divide by 10 afterwards */
139*b843c749SSergey Zigachev 	feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
140*b843c749SSergey Zigachev 	feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz);
141*b843c749SSergey Zigachev 
142*b843c749SSergey Zigachev /*Round to the number of precision
143*b843c749SSergey Zigachev  * The following code replace the old code (ullfeedbackDivider + 5)/10
144*b843c749SSergey Zigachev  * for example if the difference between the number
145*b843c749SSergey Zigachev  * of fractional feedback decimal point and the fractional FB Divider precision
146*b843c749SSergey Zigachev  * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
147*b843c749SSergey Zigachev 
148*b843c749SSergey Zigachev 	feedback_divider += 5ULL *
149*b843c749SSergey Zigachev 			    calc_pll_cs->fract_fb_divider_precision_factor;
150*b843c749SSergey Zigachev 	feedback_divider =
151*b843c749SSergey Zigachev 		div_u64(feedback_divider,
152*b843c749SSergey Zigachev 			calc_pll_cs->fract_fb_divider_precision_factor * 10);
153*b843c749SSergey Zigachev 	feedback_divider *= (uint64_t)
154*b843c749SSergey Zigachev 			(calc_pll_cs->fract_fb_divider_precision_factor);
155*b843c749SSergey Zigachev 
156*b843c749SSergey Zigachev 	*feedback_divider_param =
157*b843c749SSergey Zigachev 		div_u64_rem(
158*b843c749SSergey Zigachev 			feedback_divider,
159*b843c749SSergey Zigachev 			calc_pll_cs->fract_fb_divider_factor,
160*b843c749SSergey Zigachev 			fract_feedback_divider_param);
161*b843c749SSergey Zigachev 
162*b843c749SSergey Zigachev 	if (*feedback_divider_param != 0)
163*b843c749SSergey Zigachev 		return true;
164*b843c749SSergey Zigachev 	return false;
165*b843c749SSergey Zigachev }
166*b843c749SSergey Zigachev 
167*b843c749SSergey Zigachev /**
168*b843c749SSergey Zigachev *calc_fb_divider_checking_tolerance
169*b843c749SSergey Zigachev *
170*b843c749SSergey Zigachev *DESCRIPTION: Calculates Feedback and Fractional Feedback divider values
171*b843c749SSergey Zigachev *		for passed Reference and Post divider, checking for tolerance.
172*b843c749SSergey Zigachev *PARAMETERS:
173*b843c749SSergey Zigachev * pll_settings		Pointer to structure
174*b843c749SSergey Zigachev * ref_divider		Reference divider (already known)
175*b843c749SSergey Zigachev * postDivider		Post Divider (already known)
176*b843c749SSergey Zigachev * tolerance		Tolerance for Calculated Pixel Clock to be within
177*b843c749SSergey Zigachev *
178*b843c749SSergey Zigachev *RETURNS:
179*b843c749SSergey Zigachev * It fills the PLLSettings structure with PLL Dividers values
180*b843c749SSergey Zigachev * if calculated values are within required tolerance
181*b843c749SSergey Zigachev * It returns	- true if eror is within tolerance
182*b843c749SSergey Zigachev *		- false if eror is not within tolerance
183*b843c749SSergey Zigachev */
calc_fb_divider_checking_tolerance(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t ref_divider,uint32_t post_divider,uint32_t tolerance)184*b843c749SSergey Zigachev static bool calc_fb_divider_checking_tolerance(
185*b843c749SSergey Zigachev 		struct calc_pll_clock_source *calc_pll_cs,
186*b843c749SSergey Zigachev 		struct pll_settings *pll_settings,
187*b843c749SSergey Zigachev 		uint32_t ref_divider,
188*b843c749SSergey Zigachev 		uint32_t post_divider,
189*b843c749SSergey Zigachev 		uint32_t tolerance)
190*b843c749SSergey Zigachev {
191*b843c749SSergey Zigachev 	uint32_t feedback_divider;
192*b843c749SSergey Zigachev 	uint32_t fract_feedback_divider;
193*b843c749SSergey Zigachev 	uint32_t actual_calculated_clock_khz;
194*b843c749SSergey Zigachev 	uint32_t abs_err;
195*b843c749SSergey Zigachev 	uint64_t actual_calc_clk_khz;
196*b843c749SSergey Zigachev 
197*b843c749SSergey Zigachev 	calculate_fb_and_fractional_fb_divider(
198*b843c749SSergey Zigachev 			calc_pll_cs,
199*b843c749SSergey Zigachev 			pll_settings->adjusted_pix_clk,
200*b843c749SSergey Zigachev 			ref_divider,
201*b843c749SSergey Zigachev 			post_divider,
202*b843c749SSergey Zigachev 			&feedback_divider,
203*b843c749SSergey Zigachev 			&fract_feedback_divider);
204*b843c749SSergey Zigachev 
205*b843c749SSergey Zigachev 	/*Actual calculated value*/
206*b843c749SSergey Zigachev 	actual_calc_clk_khz = (uint64_t)feedback_divider *
207*b843c749SSergey Zigachev 					calc_pll_cs->fract_fb_divider_factor +
208*b843c749SSergey Zigachev 							fract_feedback_divider;
209*b843c749SSergey Zigachev 	actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
210*b843c749SSergey Zigachev 	actual_calc_clk_khz =
211*b843c749SSergey Zigachev 		div_u64(actual_calc_clk_khz,
212*b843c749SSergey Zigachev 			ref_divider * post_divider *
213*b843c749SSergey Zigachev 				calc_pll_cs->fract_fb_divider_factor);
214*b843c749SSergey Zigachev 
215*b843c749SSergey Zigachev 	actual_calculated_clock_khz = (uint32_t)(actual_calc_clk_khz);
216*b843c749SSergey Zigachev 
217*b843c749SSergey Zigachev 	abs_err = (actual_calculated_clock_khz >
218*b843c749SSergey Zigachev 					pll_settings->adjusted_pix_clk)
219*b843c749SSergey Zigachev 			? actual_calculated_clock_khz -
220*b843c749SSergey Zigachev 					pll_settings->adjusted_pix_clk
221*b843c749SSergey Zigachev 			: pll_settings->adjusted_pix_clk -
222*b843c749SSergey Zigachev 						actual_calculated_clock_khz;
223*b843c749SSergey Zigachev 
224*b843c749SSergey Zigachev 	if (abs_err <= tolerance) {
225*b843c749SSergey Zigachev 		/*found good values*/
226*b843c749SSergey Zigachev 		pll_settings->reference_freq = calc_pll_cs->ref_freq_khz;
227*b843c749SSergey Zigachev 		pll_settings->reference_divider = ref_divider;
228*b843c749SSergey Zigachev 		pll_settings->feedback_divider = feedback_divider;
229*b843c749SSergey Zigachev 		pll_settings->fract_feedback_divider = fract_feedback_divider;
230*b843c749SSergey Zigachev 		pll_settings->pix_clk_post_divider = post_divider;
231*b843c749SSergey Zigachev 		pll_settings->calculated_pix_clk =
232*b843c749SSergey Zigachev 			actual_calculated_clock_khz;
233*b843c749SSergey Zigachev 		pll_settings->vco_freq =
234*b843c749SSergey Zigachev 			actual_calculated_clock_khz * post_divider;
235*b843c749SSergey Zigachev 		return true;
236*b843c749SSergey Zigachev 	}
237*b843c749SSergey Zigachev 	return false;
238*b843c749SSergey Zigachev }
239*b843c749SSergey Zigachev 
calc_pll_dividers_in_range(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings,uint32_t min_ref_divider,uint32_t max_ref_divider,uint32_t min_post_divider,uint32_t max_post_divider,uint32_t err_tolerance)240*b843c749SSergey Zigachev static bool calc_pll_dividers_in_range(
241*b843c749SSergey Zigachev 		struct calc_pll_clock_source *calc_pll_cs,
242*b843c749SSergey Zigachev 		struct pll_settings *pll_settings,
243*b843c749SSergey Zigachev 		uint32_t min_ref_divider,
244*b843c749SSergey Zigachev 		uint32_t max_ref_divider,
245*b843c749SSergey Zigachev 		uint32_t min_post_divider,
246*b843c749SSergey Zigachev 		uint32_t max_post_divider,
247*b843c749SSergey Zigachev 		uint32_t err_tolerance)
248*b843c749SSergey Zigachev {
249*b843c749SSergey Zigachev 	uint32_t ref_divider;
250*b843c749SSergey Zigachev 	uint32_t post_divider;
251*b843c749SSergey Zigachev 	uint32_t tolerance;
252*b843c749SSergey Zigachev 
253*b843c749SSergey Zigachev /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25%
254*b843c749SSergey Zigachev  * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/
255*b843c749SSergey Zigachev 	tolerance = (pll_settings->adjusted_pix_clk * err_tolerance) /
256*b843c749SSergey Zigachev 									10000;
257*b843c749SSergey Zigachev 	if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE)
258*b843c749SSergey Zigachev 		tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE;
259*b843c749SSergey Zigachev 
260*b843c749SSergey Zigachev 	for (
261*b843c749SSergey Zigachev 			post_divider = max_post_divider;
262*b843c749SSergey Zigachev 			post_divider >= min_post_divider;
263*b843c749SSergey Zigachev 			--post_divider) {
264*b843c749SSergey Zigachev 		for (
265*b843c749SSergey Zigachev 				ref_divider = min_ref_divider;
266*b843c749SSergey Zigachev 				ref_divider <= max_ref_divider;
267*b843c749SSergey Zigachev 				++ref_divider) {
268*b843c749SSergey Zigachev 			if (calc_fb_divider_checking_tolerance(
269*b843c749SSergey Zigachev 					calc_pll_cs,
270*b843c749SSergey Zigachev 					pll_settings,
271*b843c749SSergey Zigachev 					ref_divider,
272*b843c749SSergey Zigachev 					post_divider,
273*b843c749SSergey Zigachev 					tolerance)) {
274*b843c749SSergey Zigachev 				return true;
275*b843c749SSergey Zigachev 			}
276*b843c749SSergey Zigachev 		}
277*b843c749SSergey Zigachev 	}
278*b843c749SSergey Zigachev 
279*b843c749SSergey Zigachev 	return false;
280*b843c749SSergey Zigachev }
281*b843c749SSergey Zigachev 
calculate_pixel_clock_pll_dividers(struct calc_pll_clock_source * calc_pll_cs,struct pll_settings * pll_settings)282*b843c749SSergey Zigachev static uint32_t calculate_pixel_clock_pll_dividers(
283*b843c749SSergey Zigachev 		struct calc_pll_clock_source *calc_pll_cs,
284*b843c749SSergey Zigachev 		struct pll_settings *pll_settings)
285*b843c749SSergey Zigachev {
286*b843c749SSergey Zigachev 	uint32_t err_tolerance;
287*b843c749SSergey Zigachev 	uint32_t min_post_divider;
288*b843c749SSergey Zigachev 	uint32_t max_post_divider;
289*b843c749SSergey Zigachev 	uint32_t min_ref_divider;
290*b843c749SSergey Zigachev 	uint32_t max_ref_divider;
291*b843c749SSergey Zigachev 
292*b843c749SSergey Zigachev 	if (pll_settings->adjusted_pix_clk == 0) {
293*b843c749SSergey Zigachev 		DC_LOG_ERROR(
294*b843c749SSergey Zigachev 			"%s Bad requested pixel clock", __func__);
295*b843c749SSergey Zigachev 		return MAX_PLL_CALC_ERROR;
296*b843c749SSergey Zigachev 	}
297*b843c749SSergey Zigachev 
298*b843c749SSergey Zigachev /* 1) Find Post divider ranges */
299*b843c749SSergey Zigachev 	if (pll_settings->pix_clk_post_divider) {
300*b843c749SSergey Zigachev 		min_post_divider = pll_settings->pix_clk_post_divider;
301*b843c749SSergey Zigachev 		max_post_divider = pll_settings->pix_clk_post_divider;
302*b843c749SSergey Zigachev 	} else {
303*b843c749SSergey Zigachev 		min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider;
304*b843c749SSergey Zigachev 		if (min_post_divider * pll_settings->adjusted_pix_clk <
305*b843c749SSergey Zigachev 						calc_pll_cs->min_vco_khz) {
306*b843c749SSergey Zigachev 			min_post_divider = calc_pll_cs->min_vco_khz /
307*b843c749SSergey Zigachev 					pll_settings->adjusted_pix_clk;
308*b843c749SSergey Zigachev 			if ((min_post_divider *
309*b843c749SSergey Zigachev 					pll_settings->adjusted_pix_clk) <
310*b843c749SSergey Zigachev 						calc_pll_cs->min_vco_khz)
311*b843c749SSergey Zigachev 				min_post_divider++;
312*b843c749SSergey Zigachev 		}
313*b843c749SSergey Zigachev 
314*b843c749SSergey Zigachev 		max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider;
315*b843c749SSergey Zigachev 		if (max_post_divider * pll_settings->adjusted_pix_clk
316*b843c749SSergey Zigachev 				> calc_pll_cs->max_vco_khz)
317*b843c749SSergey Zigachev 			max_post_divider = calc_pll_cs->max_vco_khz /
318*b843c749SSergey Zigachev 					pll_settings->adjusted_pix_clk;
319*b843c749SSergey Zigachev 	}
320*b843c749SSergey Zigachev 
321*b843c749SSergey Zigachev /* 2) Find Reference divider ranges
322*b843c749SSergey Zigachev  * When SS is enabled, or for Display Port even without SS,
323*b843c749SSergey Zigachev  * pll_settings->referenceDivider is not zero.
324*b843c749SSergey Zigachev  * So calculate PPLL FB and fractional FB divider
325*b843c749SSergey Zigachev  * using the passed reference divider*/
326*b843c749SSergey Zigachev 
327*b843c749SSergey Zigachev 	if (pll_settings->reference_divider) {
328*b843c749SSergey Zigachev 		min_ref_divider = pll_settings->reference_divider;
329*b843c749SSergey Zigachev 		max_ref_divider = pll_settings->reference_divider;
330*b843c749SSergey Zigachev 	} else {
331*b843c749SSergey Zigachev 		min_ref_divider = ((calc_pll_cs->ref_freq_khz
332*b843c749SSergey Zigachev 				/ calc_pll_cs->max_pll_input_freq_khz)
333*b843c749SSergey Zigachev 				> calc_pll_cs->min_pll_ref_divider)
334*b843c749SSergey Zigachev 			? calc_pll_cs->ref_freq_khz
335*b843c749SSergey Zigachev 					/ calc_pll_cs->max_pll_input_freq_khz
336*b843c749SSergey Zigachev 			: calc_pll_cs->min_pll_ref_divider;
337*b843c749SSergey Zigachev 
338*b843c749SSergey Zigachev 		max_ref_divider = ((calc_pll_cs->ref_freq_khz
339*b843c749SSergey Zigachev 				/ calc_pll_cs->min_pll_input_freq_khz)
340*b843c749SSergey Zigachev 				< calc_pll_cs->max_pll_ref_divider)
341*b843c749SSergey Zigachev 			? calc_pll_cs->ref_freq_khz /
342*b843c749SSergey Zigachev 					calc_pll_cs->min_pll_input_freq_khz
343*b843c749SSergey Zigachev 			: calc_pll_cs->max_pll_ref_divider;
344*b843c749SSergey Zigachev 	}
345*b843c749SSergey Zigachev 
346*b843c749SSergey Zigachev /* If some parameters are invalid we could have scenario when  "min">"max"
347*b843c749SSergey Zigachev  * which produced endless loop later.
348*b843c749SSergey Zigachev  * We should investigate why we get the wrong parameters.
349*b843c749SSergey Zigachev  * But to follow the similar logic when "adjustedPixelClock" is set to be 0
350*b843c749SSergey Zigachev  * it is better to return here than cause system hang/watchdog timeout later.
351*b843c749SSergey Zigachev  *  ## SVS Wed 15 Jul 2009 */
352*b843c749SSergey Zigachev 
353*b843c749SSergey Zigachev 	if (min_post_divider > max_post_divider) {
354*b843c749SSergey Zigachev 		DC_LOG_ERROR(
355*b843c749SSergey Zigachev 			"%s Post divider range is invalid", __func__);
356*b843c749SSergey Zigachev 		return MAX_PLL_CALC_ERROR;
357*b843c749SSergey Zigachev 	}
358*b843c749SSergey Zigachev 
359*b843c749SSergey Zigachev 	if (min_ref_divider > max_ref_divider) {
360*b843c749SSergey Zigachev 		DC_LOG_ERROR(
361*b843c749SSergey Zigachev 			"%s Reference divider range is invalid", __func__);
362*b843c749SSergey Zigachev 		return MAX_PLL_CALC_ERROR;
363*b843c749SSergey Zigachev 	}
364*b843c749SSergey Zigachev 
365*b843c749SSergey Zigachev /* 3) Try to find PLL dividers given ranges
366*b843c749SSergey Zigachev  * starting with minimal error tolerance.
367*b843c749SSergey Zigachev  * Increase error tolerance until PLL dividers found*/
368*b843c749SSergey Zigachev 	err_tolerance = MAX_PLL_CALC_ERROR;
369*b843c749SSergey Zigachev 
370*b843c749SSergey Zigachev 	while (!calc_pll_dividers_in_range(
371*b843c749SSergey Zigachev 			calc_pll_cs,
372*b843c749SSergey Zigachev 			pll_settings,
373*b843c749SSergey Zigachev 			min_ref_divider,
374*b843c749SSergey Zigachev 			max_ref_divider,
375*b843c749SSergey Zigachev 			min_post_divider,
376*b843c749SSergey Zigachev 			max_post_divider,
377*b843c749SSergey Zigachev 			err_tolerance))
378*b843c749SSergey Zigachev 		err_tolerance += (err_tolerance > 10)
379*b843c749SSergey Zigachev 				? (err_tolerance / 10)
380*b843c749SSergey Zigachev 				: 1;
381*b843c749SSergey Zigachev 
382*b843c749SSergey Zigachev 	return err_tolerance;
383*b843c749SSergey Zigachev }
384*b843c749SSergey Zigachev 
pll_adjust_pix_clk(struct dce110_clk_src * clk_src,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)385*b843c749SSergey Zigachev static bool pll_adjust_pix_clk(
386*b843c749SSergey Zigachev 		struct dce110_clk_src *clk_src,
387*b843c749SSergey Zigachev 		struct pixel_clk_params *pix_clk_params,
388*b843c749SSergey Zigachev 		struct pll_settings *pll_settings)
389*b843c749SSergey Zigachev {
390*b843c749SSergey Zigachev 	uint32_t actual_pix_clk_khz = 0;
391*b843c749SSergey Zigachev 	uint32_t requested_clk_khz = 0;
392*b843c749SSergey Zigachev 	struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = {
393*b843c749SSergey Zigachev 							0 };
394*b843c749SSergey Zigachev 	enum bp_result bp_result;
395*b843c749SSergey Zigachev 	switch (pix_clk_params->signal_type) {
396*b843c749SSergey Zigachev 	case SIGNAL_TYPE_HDMI_TYPE_A: {
397*b843c749SSergey Zigachev 		requested_clk_khz = pix_clk_params->requested_pix_clk;
398*b843c749SSergey Zigachev 		if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
399*b843c749SSergey Zigachev 			switch (pix_clk_params->color_depth) {
400*b843c749SSergey Zigachev 			case COLOR_DEPTH_101010:
401*b843c749SSergey Zigachev 				requested_clk_khz = (requested_clk_khz * 5) >> 2;
402*b843c749SSergey Zigachev 				break; /* x1.25*/
403*b843c749SSergey Zigachev 			case COLOR_DEPTH_121212:
404*b843c749SSergey Zigachev 				requested_clk_khz = (requested_clk_khz * 6) >> 2;
405*b843c749SSergey Zigachev 				break; /* x1.5*/
406*b843c749SSergey Zigachev 			case COLOR_DEPTH_161616:
407*b843c749SSergey Zigachev 				requested_clk_khz = requested_clk_khz * 2;
408*b843c749SSergey Zigachev 				break; /* x2.0*/
409*b843c749SSergey Zigachev 			default:
410*b843c749SSergey Zigachev 				break;
411*b843c749SSergey Zigachev 			}
412*b843c749SSergey Zigachev 		}
413*b843c749SSergey Zigachev 		actual_pix_clk_khz = requested_clk_khz;
414*b843c749SSergey Zigachev 	}
415*b843c749SSergey Zigachev 		break;
416*b843c749SSergey Zigachev 
417*b843c749SSergey Zigachev 	case SIGNAL_TYPE_DISPLAY_PORT:
418*b843c749SSergey Zigachev 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
419*b843c749SSergey Zigachev 	case SIGNAL_TYPE_EDP:
420*b843c749SSergey Zigachev 		requested_clk_khz = pix_clk_params->requested_sym_clk;
421*b843c749SSergey Zigachev 		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
422*b843c749SSergey Zigachev 		break;
423*b843c749SSergey Zigachev 
424*b843c749SSergey Zigachev 	default:
425*b843c749SSergey Zigachev 		requested_clk_khz = pix_clk_params->requested_pix_clk;
426*b843c749SSergey Zigachev 		actual_pix_clk_khz = pix_clk_params->requested_pix_clk;
427*b843c749SSergey Zigachev 		break;
428*b843c749SSergey Zigachev 	}
429*b843c749SSergey Zigachev 
430*b843c749SSergey Zigachev 	bp_adjust_pixel_clock_params.pixel_clock = requested_clk_khz;
431*b843c749SSergey Zigachev 	bp_adjust_pixel_clock_params.
432*b843c749SSergey Zigachev 		encoder_object_id = pix_clk_params->encoder_object_id;
433*b843c749SSergey Zigachev 	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
434*b843c749SSergey Zigachev 	bp_adjust_pixel_clock_params.
435*b843c749SSergey Zigachev 		ss_enable = pix_clk_params->flags.ENABLE_SS;
436*b843c749SSergey Zigachev 	bp_result = clk_src->bios->funcs->adjust_pixel_clock(
437*b843c749SSergey Zigachev 			clk_src->bios, &bp_adjust_pixel_clock_params);
438*b843c749SSergey Zigachev 	if (bp_result == BP_RESULT_OK) {
439*b843c749SSergey Zigachev 		pll_settings->actual_pix_clk = actual_pix_clk_khz;
440*b843c749SSergey Zigachev 		pll_settings->adjusted_pix_clk =
441*b843c749SSergey Zigachev 			bp_adjust_pixel_clock_params.adjusted_pixel_clock;
442*b843c749SSergey Zigachev 		pll_settings->reference_divider =
443*b843c749SSergey Zigachev 			bp_adjust_pixel_clock_params.reference_divider;
444*b843c749SSergey Zigachev 		pll_settings->pix_clk_post_divider =
445*b843c749SSergey Zigachev 			bp_adjust_pixel_clock_params.pixel_clock_post_divider;
446*b843c749SSergey Zigachev 
447*b843c749SSergey Zigachev 		return true;
448*b843c749SSergey Zigachev 	}
449*b843c749SSergey Zigachev 
450*b843c749SSergey Zigachev 	return false;
451*b843c749SSergey Zigachev }
452*b843c749SSergey Zigachev 
453*b843c749SSergey Zigachev /**
454*b843c749SSergey Zigachev  * Calculate PLL Dividers for given Clock Value.
455*b843c749SSergey Zigachev  * First will call VBIOS Adjust Exec table to check if requested Pixel clock
456*b843c749SSergey Zigachev  * will be Adjusted based on usage.
457*b843c749SSergey Zigachev  * Then it will calculate PLL Dividers for this Adjusted clock using preferred
458*b843c749SSergey Zigachev  * method (Maximum VCO frequency).
459*b843c749SSergey Zigachev  *
460*b843c749SSergey Zigachev  * \return
461*b843c749SSergey Zigachev  *     Calculation error in units of 0.01%
462*b843c749SSergey Zigachev  */
463*b843c749SSergey Zigachev 
dce110_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)464*b843c749SSergey Zigachev static uint32_t dce110_get_pix_clk_dividers_helper (
465*b843c749SSergey Zigachev 		struct dce110_clk_src *clk_src,
466*b843c749SSergey Zigachev 		struct pll_settings *pll_settings,
467*b843c749SSergey Zigachev 		struct pixel_clk_params *pix_clk_params)
468*b843c749SSergey Zigachev {
469*b843c749SSergey Zigachev 	uint32_t field = 0;
470*b843c749SSergey Zigachev 	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
471*b843c749SSergey Zigachev 	DC_LOGGER_INIT();
472*b843c749SSergey Zigachev 	/* Check if reference clock is external (not pcie/xtalin)
473*b843c749SSergey Zigachev 	* HW Dce80 spec:
474*b843c749SSergey Zigachev 	* 00 - PCIE_REFCLK, 01 - XTALIN,    02 - GENERICA,    03 - GENERICB
475*b843c749SSergey Zigachev 	* 04 - HSYNCA,      05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */
476*b843c749SSergey Zigachev 	REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field);
477*b843c749SSergey Zigachev 	pll_settings->use_external_clk = (field > 1);
478*b843c749SSergey Zigachev 
479*b843c749SSergey Zigachev 	/* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always
480*b843c749SSergey Zigachev 	 * (we do not care any more from SI for some older DP Sink which
481*b843c749SSergey Zigachev 	 * does not report SS support, no known issues) */
482*b843c749SSergey Zigachev 	if ((pix_clk_params->flags.ENABLE_SS) ||
483*b843c749SSergey Zigachev 			(dc_is_dp_signal(pix_clk_params->signal_type))) {
484*b843c749SSergey Zigachev 
485*b843c749SSergey Zigachev 		const struct spread_spectrum_data *ss_data = get_ss_data_entry(
486*b843c749SSergey Zigachev 					clk_src,
487*b843c749SSergey Zigachev 					pix_clk_params->signal_type,
488*b843c749SSergey Zigachev 					pll_settings->adjusted_pix_clk);
489*b843c749SSergey Zigachev 
490*b843c749SSergey Zigachev 		if (NULL != ss_data)
491*b843c749SSergey Zigachev 			pll_settings->ss_percentage = ss_data->percentage;
492*b843c749SSergey Zigachev 	}
493*b843c749SSergey Zigachev 
494*b843c749SSergey Zigachev 	/* Check VBIOS AdjustPixelClock Exec table */
495*b843c749SSergey Zigachev 	if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) {
496*b843c749SSergey Zigachev 		/* Should never happen, ASSERT and fill up values to be able
497*b843c749SSergey Zigachev 		 * to continue. */
498*b843c749SSergey Zigachev 		DC_LOG_ERROR(
499*b843c749SSergey Zigachev 			"%s: Failed to adjust pixel clock!!", __func__);
500*b843c749SSergey Zigachev 		pll_settings->actual_pix_clk =
501*b843c749SSergey Zigachev 				pix_clk_params->requested_pix_clk;
502*b843c749SSergey Zigachev 		pll_settings->adjusted_pix_clk =
503*b843c749SSergey Zigachev 				pix_clk_params->requested_pix_clk;
504*b843c749SSergey Zigachev 
505*b843c749SSergey Zigachev 		if (dc_is_dp_signal(pix_clk_params->signal_type))
506*b843c749SSergey Zigachev 			pll_settings->adjusted_pix_clk = 100000;
507*b843c749SSergey Zigachev 	}
508*b843c749SSergey Zigachev 
509*b843c749SSergey Zigachev 	/* Calculate Dividers */
510*b843c749SSergey Zigachev 	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A)
511*b843c749SSergey Zigachev 		/*Calculate Dividers by HDMI object, no SS case or SS case */
512*b843c749SSergey Zigachev 		pll_calc_error =
513*b843c749SSergey Zigachev 			calculate_pixel_clock_pll_dividers(
514*b843c749SSergey Zigachev 					&clk_src->calc_pll_hdmi,
515*b843c749SSergey Zigachev 					pll_settings);
516*b843c749SSergey Zigachev 	else
517*b843c749SSergey Zigachev 		/*Calculate Dividers by default object, no SS case or SS case */
518*b843c749SSergey Zigachev 		pll_calc_error =
519*b843c749SSergey Zigachev 			calculate_pixel_clock_pll_dividers(
520*b843c749SSergey Zigachev 					&clk_src->calc_pll,
521*b843c749SSergey Zigachev 					pll_settings);
522*b843c749SSergey Zigachev 
523*b843c749SSergey Zigachev 	return pll_calc_error;
524*b843c749SSergey Zigachev }
525*b843c749SSergey Zigachev 
dce112_get_pix_clk_dividers_helper(struct dce110_clk_src * clk_src,struct pll_settings * pll_settings,struct pixel_clk_params * pix_clk_params)526*b843c749SSergey Zigachev static void dce112_get_pix_clk_dividers_helper (
527*b843c749SSergey Zigachev 		struct dce110_clk_src *clk_src,
528*b843c749SSergey Zigachev 		struct pll_settings *pll_settings,
529*b843c749SSergey Zigachev 		struct pixel_clk_params *pix_clk_params)
530*b843c749SSergey Zigachev {
531*b843c749SSergey Zigachev 	uint32_t actualPixelClockInKHz;
532*b843c749SSergey Zigachev 
533*b843c749SSergey Zigachev 	actualPixelClockInKHz = pix_clk_params->requested_pix_clk;
534*b843c749SSergey Zigachev 	/* Calculate Dividers */
535*b843c749SSergey Zigachev 	if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
536*b843c749SSergey Zigachev 		switch (pix_clk_params->color_depth) {
537*b843c749SSergey Zigachev 		case COLOR_DEPTH_101010:
538*b843c749SSergey Zigachev 			actualPixelClockInKHz = (actualPixelClockInKHz * 5) >> 2;
539*b843c749SSergey Zigachev 			break;
540*b843c749SSergey Zigachev 		case COLOR_DEPTH_121212:
541*b843c749SSergey Zigachev 			actualPixelClockInKHz = (actualPixelClockInKHz * 6) >> 2;
542*b843c749SSergey Zigachev 			break;
543*b843c749SSergey Zigachev 		case COLOR_DEPTH_161616:
544*b843c749SSergey Zigachev 			actualPixelClockInKHz = actualPixelClockInKHz * 2;
545*b843c749SSergey Zigachev 			break;
546*b843c749SSergey Zigachev 		default:
547*b843c749SSergey Zigachev 			break;
548*b843c749SSergey Zigachev 		}
549*b843c749SSergey Zigachev 	}
550*b843c749SSergey Zigachev 	pll_settings->actual_pix_clk = actualPixelClockInKHz;
551*b843c749SSergey Zigachev 	pll_settings->adjusted_pix_clk = actualPixelClockInKHz;
552*b843c749SSergey Zigachev 	pll_settings->calculated_pix_clk = pix_clk_params->requested_pix_clk;
553*b843c749SSergey Zigachev }
554*b843c749SSergey Zigachev 
dce110_get_pix_clk_dividers(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)555*b843c749SSergey Zigachev static uint32_t dce110_get_pix_clk_dividers(
556*b843c749SSergey Zigachev 		struct clock_source *cs,
557*b843c749SSergey Zigachev 		struct pixel_clk_params *pix_clk_params,
558*b843c749SSergey Zigachev 		struct pll_settings *pll_settings)
559*b843c749SSergey Zigachev {
560*b843c749SSergey Zigachev 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
561*b843c749SSergey Zigachev 	uint32_t pll_calc_error = MAX_PLL_CALC_ERROR;
562*b843c749SSergey Zigachev 	DC_LOGGER_INIT();
563*b843c749SSergey Zigachev 
564*b843c749SSergey Zigachev 	if (pix_clk_params == NULL || pll_settings == NULL
565*b843c749SSergey Zigachev 			|| pix_clk_params->requested_pix_clk == 0) {
566*b843c749SSergey Zigachev 		DC_LOG_ERROR(
567*b843c749SSergey Zigachev 			"%s: Invalid parameters!!\n", __func__);
568*b843c749SSergey Zigachev 		return pll_calc_error;
569*b843c749SSergey Zigachev 	}
570*b843c749SSergey Zigachev 
571*b843c749SSergey Zigachev 	memset(pll_settings, 0, sizeof(*pll_settings));
572*b843c749SSergey Zigachev 
573*b843c749SSergey Zigachev 	if (cs->id == CLOCK_SOURCE_ID_DP_DTO ||
574*b843c749SSergey Zigachev 			cs->id == CLOCK_SOURCE_ID_EXTERNAL) {
575*b843c749SSergey Zigachev 		pll_settings->adjusted_pix_clk = clk_src->ext_clk_khz;
576*b843c749SSergey Zigachev 		pll_settings->calculated_pix_clk = clk_src->ext_clk_khz;
577*b843c749SSergey Zigachev 		pll_settings->actual_pix_clk =
578*b843c749SSergey Zigachev 					pix_clk_params->requested_pix_clk;
579*b843c749SSergey Zigachev 		return 0;
580*b843c749SSergey Zigachev 	}
581*b843c749SSergey Zigachev 
582*b843c749SSergey Zigachev 	switch (cs->ctx->dce_version) {
583*b843c749SSergey Zigachev 	case DCE_VERSION_8_0:
584*b843c749SSergey Zigachev 	case DCE_VERSION_8_1:
585*b843c749SSergey Zigachev 	case DCE_VERSION_8_3:
586*b843c749SSergey Zigachev 	case DCE_VERSION_10_0:
587*b843c749SSergey Zigachev 	case DCE_VERSION_11_0:
588*b843c749SSergey Zigachev 		pll_calc_error =
589*b843c749SSergey Zigachev 			dce110_get_pix_clk_dividers_helper(clk_src,
590*b843c749SSergey Zigachev 			pll_settings, pix_clk_params);
591*b843c749SSergey Zigachev 		break;
592*b843c749SSergey Zigachev 	case DCE_VERSION_11_2:
593*b843c749SSergey Zigachev 	case DCE_VERSION_11_22:
594*b843c749SSergey Zigachev 	case DCE_VERSION_12_0:
595*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
596*b843c749SSergey Zigachev 	case DCN_VERSION_1_0:
597*b843c749SSergey Zigachev #endif
598*b843c749SSergey Zigachev 
599*b843c749SSergey Zigachev 		dce112_get_pix_clk_dividers_helper(clk_src,
600*b843c749SSergey Zigachev 				pll_settings, pix_clk_params);
601*b843c749SSergey Zigachev 		break;
602*b843c749SSergey Zigachev 	default:
603*b843c749SSergey Zigachev 		break;
604*b843c749SSergey Zigachev 	}
605*b843c749SSergey Zigachev 
606*b843c749SSergey Zigachev 	return pll_calc_error;
607*b843c749SSergey Zigachev }
608*b843c749SSergey Zigachev 
dce110_get_pll_pixel_rate_in_hz(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)609*b843c749SSergey Zigachev static uint32_t dce110_get_pll_pixel_rate_in_hz(
610*b843c749SSergey Zigachev 	struct clock_source *cs,
611*b843c749SSergey Zigachev 	struct pixel_clk_params *pix_clk_params,
612*b843c749SSergey Zigachev 	struct pll_settings *pll_settings)
613*b843c749SSergey Zigachev {
614*b843c749SSergey Zigachev 	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
615*b843c749SSergey Zigachev 	struct dc *dc_core = cs->ctx->dc;
616*b843c749SSergey Zigachev 	struct dc_state *context = dc_core->current_state;
617*b843c749SSergey Zigachev 	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
618*b843c749SSergey Zigachev 
619*b843c749SSergey Zigachev 	/* This function need separate to different DCE version, before separate, just use pixel clock */
620*b843c749SSergey Zigachev 	return pipe_ctx->stream->phy_pix_clk;
621*b843c749SSergey Zigachev 
622*b843c749SSergey Zigachev }
623*b843c749SSergey Zigachev 
dce110_get_dp_pixel_rate_from_combo_phy_pll(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)624*b843c749SSergey Zigachev static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll(
625*b843c749SSergey Zigachev 	struct clock_source *cs,
626*b843c749SSergey Zigachev 	struct pixel_clk_params *pix_clk_params,
627*b843c749SSergey Zigachev 	struct pll_settings *pll_settings)
628*b843c749SSergey Zigachev {
629*b843c749SSergey Zigachev 	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
630*b843c749SSergey Zigachev 	struct dc *dc_core = cs->ctx->dc;
631*b843c749SSergey Zigachev 	struct dc_state *context = dc_core->current_state;
632*b843c749SSergey Zigachev 	struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
633*b843c749SSergey Zigachev 
634*b843c749SSergey Zigachev 	/* This function need separate to different DCE version, before separate, just use pixel clock */
635*b843c749SSergey Zigachev 	return pipe_ctx->stream->phy_pix_clk;
636*b843c749SSergey Zigachev }
637*b843c749SSergey Zigachev 
dce110_get_d_to_pixel_rate_in_hz(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)638*b843c749SSergey Zigachev static uint32_t dce110_get_d_to_pixel_rate_in_hz(
639*b843c749SSergey Zigachev 	struct clock_source *cs,
640*b843c749SSergey Zigachev 	struct pixel_clk_params *pix_clk_params,
641*b843c749SSergey Zigachev 	struct pll_settings *pll_settings)
642*b843c749SSergey Zigachev {
643*b843c749SSergey Zigachev 	uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
644*b843c749SSergey Zigachev 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs);
645*b843c749SSergey Zigachev 	int dto_enabled = 0;
646*b843c749SSergey Zigachev 	struct fixed31_32 pix_rate;
647*b843c749SSergey Zigachev 
648*b843c749SSergey Zigachev 	REG_GET(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, &dto_enabled);
649*b843c749SSergey Zigachev 
650*b843c749SSergey Zigachev 	if (dto_enabled) {
651*b843c749SSergey Zigachev 		uint32_t phase = 0;
652*b843c749SSergey Zigachev 		uint32_t modulo = 0;
653*b843c749SSergey Zigachev 		REG_GET(PHASE[inst], DP_DTO0_PHASE, &phase);
654*b843c749SSergey Zigachev 		REG_GET(MODULO[inst], DP_DTO0_MODULO, &modulo);
655*b843c749SSergey Zigachev 
656*b843c749SSergey Zigachev 		if (modulo == 0) {
657*b843c749SSergey Zigachev 			return 0;
658*b843c749SSergey Zigachev 		}
659*b843c749SSergey Zigachev 
660*b843c749SSergey Zigachev 		pix_rate = dc_fixpt_from_int(clk_src->ref_freq_khz);
661*b843c749SSergey Zigachev 		pix_rate = dc_fixpt_mul_int(pix_rate, 1000);
662*b843c749SSergey Zigachev 		pix_rate = dc_fixpt_mul_int(pix_rate, phase);
663*b843c749SSergey Zigachev 		pix_rate = dc_fixpt_div_int(pix_rate, modulo);
664*b843c749SSergey Zigachev 
665*b843c749SSergey Zigachev 		return dc_fixpt_round(pix_rate);
666*b843c749SSergey Zigachev 	} else {
667*b843c749SSergey Zigachev 		return dce110_get_dp_pixel_rate_from_combo_phy_pll(cs, pix_clk_params, pll_settings);
668*b843c749SSergey Zigachev 	}
669*b843c749SSergey Zigachev }
670*b843c749SSergey Zigachev 
dce110_get_pix_rate_in_hz(struct clock_source * cs,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)671*b843c749SSergey Zigachev static uint32_t dce110_get_pix_rate_in_hz(
672*b843c749SSergey Zigachev 	struct clock_source *cs,
673*b843c749SSergey Zigachev 	struct pixel_clk_params *pix_clk_params,
674*b843c749SSergey Zigachev 	struct pll_settings *pll_settings)
675*b843c749SSergey Zigachev {
676*b843c749SSergey Zigachev 	uint32_t pix_rate = 0;
677*b843c749SSergey Zigachev 	switch (pix_clk_params->signal_type) {
678*b843c749SSergey Zigachev 	case	SIGNAL_TYPE_DISPLAY_PORT:
679*b843c749SSergey Zigachev 	case	SIGNAL_TYPE_DISPLAY_PORT_MST:
680*b843c749SSergey Zigachev 	case	SIGNAL_TYPE_EDP:
681*b843c749SSergey Zigachev 	case	SIGNAL_TYPE_VIRTUAL:
682*b843c749SSergey Zigachev 		pix_rate = dce110_get_d_to_pixel_rate_in_hz(cs, pix_clk_params, pll_settings);
683*b843c749SSergey Zigachev 		break;
684*b843c749SSergey Zigachev 	case	SIGNAL_TYPE_HDMI_TYPE_A:
685*b843c749SSergey Zigachev 	default:
686*b843c749SSergey Zigachev 		pix_rate = dce110_get_pll_pixel_rate_in_hz(cs, pix_clk_params, pll_settings);
687*b843c749SSergey Zigachev 		break;
688*b843c749SSergey Zigachev 	}
689*b843c749SSergey Zigachev 
690*b843c749SSergey Zigachev 	return pix_rate;
691*b843c749SSergey Zigachev }
692*b843c749SSergey Zigachev 
disable_spread_spectrum(struct dce110_clk_src * clk_src)693*b843c749SSergey Zigachev static bool disable_spread_spectrum(struct dce110_clk_src *clk_src)
694*b843c749SSergey Zigachev {
695*b843c749SSergey Zigachev 	enum bp_result result;
696*b843c749SSergey Zigachev 	struct bp_spread_spectrum_parameters bp_ss_params = {0};
697*b843c749SSergey Zigachev 
698*b843c749SSergey Zigachev 	bp_ss_params.pll_id = clk_src->base.id;
699*b843c749SSergey Zigachev 
700*b843c749SSergey Zigachev 	/*Call ASICControl to process ATOMBIOS Exec table*/
701*b843c749SSergey Zigachev 	result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll(
702*b843c749SSergey Zigachev 			clk_src->bios,
703*b843c749SSergey Zigachev 			&bp_ss_params,
704*b843c749SSergey Zigachev 			false);
705*b843c749SSergey Zigachev 
706*b843c749SSergey Zigachev 	return result == BP_RESULT_OK;
707*b843c749SSergey Zigachev }
708*b843c749SSergey Zigachev 
calculate_ss(const struct pll_settings * pll_settings,const struct spread_spectrum_data * ss_data,struct delta_sigma_data * ds_data)709*b843c749SSergey Zigachev static bool calculate_ss(
710*b843c749SSergey Zigachev 		const struct pll_settings *pll_settings,
711*b843c749SSergey Zigachev 		const struct spread_spectrum_data *ss_data,
712*b843c749SSergey Zigachev 		struct delta_sigma_data *ds_data)
713*b843c749SSergey Zigachev {
714*b843c749SSergey Zigachev 	struct fixed31_32 fb_div;
715*b843c749SSergey Zigachev 	struct fixed31_32 ss_amount;
716*b843c749SSergey Zigachev 	struct fixed31_32 ss_nslip_amount;
717*b843c749SSergey Zigachev 	struct fixed31_32 ss_ds_frac_amount;
718*b843c749SSergey Zigachev 	struct fixed31_32 ss_step_size;
719*b843c749SSergey Zigachev 	struct fixed31_32 modulation_time;
720*b843c749SSergey Zigachev 
721*b843c749SSergey Zigachev 	if (ds_data == NULL)
722*b843c749SSergey Zigachev 		return false;
723*b843c749SSergey Zigachev 	if (ss_data == NULL)
724*b843c749SSergey Zigachev 		return false;
725*b843c749SSergey Zigachev 	if (ss_data->percentage == 0)
726*b843c749SSergey Zigachev 		return false;
727*b843c749SSergey Zigachev 	if (pll_settings == NULL)
728*b843c749SSergey Zigachev 		return false;
729*b843c749SSergey Zigachev 
730*b843c749SSergey Zigachev 	memset(ds_data, 0, sizeof(struct delta_sigma_data));
731*b843c749SSergey Zigachev 
732*b843c749SSergey Zigachev 	/* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/
733*b843c749SSergey Zigachev 	/* 6 decimal point support in fractional feedback divider */
734*b843c749SSergey Zigachev 	fb_div  = dc_fixpt_from_fraction(
735*b843c749SSergey Zigachev 		pll_settings->fract_feedback_divider, 1000000);
736*b843c749SSergey Zigachev 	fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider);
737*b843c749SSergey Zigachev 
738*b843c749SSergey Zigachev 	ds_data->ds_frac_amount = 0;
739*b843c749SSergey Zigachev 	/*spreadSpectrumPercentage is in the unit of .01%,
740*b843c749SSergey Zigachev 	 * so have to divided by 100 * 100*/
741*b843c749SSergey Zigachev 	ss_amount = dc_fixpt_mul(
742*b843c749SSergey Zigachev 		fb_div, dc_fixpt_from_fraction(ss_data->percentage,
743*b843c749SSergey Zigachev 					100 * ss_data->percentage_divider));
744*b843c749SSergey Zigachev 	ds_data->feedback_amount = dc_fixpt_floor(ss_amount);
745*b843c749SSergey Zigachev 
746*b843c749SSergey Zigachev 	ss_nslip_amount = dc_fixpt_sub(ss_amount,
747*b843c749SSergey Zigachev 		dc_fixpt_from_int(ds_data->feedback_amount));
748*b843c749SSergey Zigachev 	ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10);
749*b843c749SSergey Zigachev 	ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount);
750*b843c749SSergey Zigachev 
751*b843c749SSergey Zigachev 	ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount,
752*b843c749SSergey Zigachev 		dc_fixpt_from_int(ds_data->nfrac_amount));
753*b843c749SSergey Zigachev 	ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536);
754*b843c749SSergey Zigachev 	ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount);
755*b843c749SSergey Zigachev 
756*b843c749SSergey Zigachev 	/* compute SS_STEP_SIZE_DSFRAC */
757*b843c749SSergey Zigachev 	modulation_time = dc_fixpt_from_fraction(
758*b843c749SSergey Zigachev 		pll_settings->reference_freq * 1000,
759*b843c749SSergey Zigachev 		pll_settings->reference_divider * ss_data->modulation_freq_hz);
760*b843c749SSergey Zigachev 
761*b843c749SSergey Zigachev 	if (ss_data->flags.CENTER_SPREAD)
762*b843c749SSergey Zigachev 		modulation_time = dc_fixpt_div_int(modulation_time, 4);
763*b843c749SSergey Zigachev 	else
764*b843c749SSergey Zigachev 		modulation_time = dc_fixpt_div_int(modulation_time, 2);
765*b843c749SSergey Zigachev 
766*b843c749SSergey Zigachev 	ss_step_size = dc_fixpt_div(ss_amount, modulation_time);
767*b843c749SSergey Zigachev 	/* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/
768*b843c749SSergey Zigachev 	ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10);
769*b843c749SSergey Zigachev 	ds_data->ds_frac_size =  dc_fixpt_floor(ss_step_size);
770*b843c749SSergey Zigachev 
771*b843c749SSergey Zigachev 	return true;
772*b843c749SSergey Zigachev }
773*b843c749SSergey Zigachev 
enable_spread_spectrum(struct dce110_clk_src * clk_src,enum signal_type signal,struct pll_settings * pll_settings)774*b843c749SSergey Zigachev static bool enable_spread_spectrum(
775*b843c749SSergey Zigachev 		struct dce110_clk_src *clk_src,
776*b843c749SSergey Zigachev 		enum signal_type signal, struct pll_settings *pll_settings)
777*b843c749SSergey Zigachev {
778*b843c749SSergey Zigachev 	struct bp_spread_spectrum_parameters bp_params = {0};
779*b843c749SSergey Zigachev 	struct delta_sigma_data d_s_data;
780*b843c749SSergey Zigachev 	const struct spread_spectrum_data *ss_data = NULL;
781*b843c749SSergey Zigachev 
782*b843c749SSergey Zigachev 	ss_data = get_ss_data_entry(
783*b843c749SSergey Zigachev 			clk_src,
784*b843c749SSergey Zigachev 			signal,
785*b843c749SSergey Zigachev 			pll_settings->calculated_pix_clk);
786*b843c749SSergey Zigachev 
787*b843c749SSergey Zigachev /* Pixel clock PLL has been programmed to generate desired pixel clock,
788*b843c749SSergey Zigachev  * now enable SS on pixel clock */
789*b843c749SSergey Zigachev /* TODO is it OK to return true not doing anything ??*/
790*b843c749SSergey Zigachev 	if (ss_data != NULL && pll_settings->ss_percentage != 0) {
791*b843c749SSergey Zigachev 		if (calculate_ss(pll_settings, ss_data, &d_s_data)) {
792*b843c749SSergey Zigachev 			bp_params.ds.feedback_amount =
793*b843c749SSergey Zigachev 					d_s_data.feedback_amount;
794*b843c749SSergey Zigachev 			bp_params.ds.nfrac_amount =
795*b843c749SSergey Zigachev 					d_s_data.nfrac_amount;
796*b843c749SSergey Zigachev 			bp_params.ds.ds_frac_size = d_s_data.ds_frac_size;
797*b843c749SSergey Zigachev 			bp_params.ds_frac_amount =
798*b843c749SSergey Zigachev 					d_s_data.ds_frac_amount;
799*b843c749SSergey Zigachev 			bp_params.flags.DS_TYPE = 1;
800*b843c749SSergey Zigachev 			bp_params.pll_id = clk_src->base.id;
801*b843c749SSergey Zigachev 			bp_params.percentage = ss_data->percentage;
802*b843c749SSergey Zigachev 			if (ss_data->flags.CENTER_SPREAD)
803*b843c749SSergey Zigachev 				bp_params.flags.CENTER_SPREAD = 1;
804*b843c749SSergey Zigachev 			if (ss_data->flags.EXTERNAL_SS)
805*b843c749SSergey Zigachev 				bp_params.flags.EXTERNAL_SS = 1;
806*b843c749SSergey Zigachev 
807*b843c749SSergey Zigachev 			if (BP_RESULT_OK !=
808*b843c749SSergey Zigachev 				clk_src->bios->funcs->
809*b843c749SSergey Zigachev 					enable_spread_spectrum_on_ppll(
810*b843c749SSergey Zigachev 							clk_src->bios,
811*b843c749SSergey Zigachev 							&bp_params,
812*b843c749SSergey Zigachev 							true))
813*b843c749SSergey Zigachev 				return false;
814*b843c749SSergey Zigachev 		} else
815*b843c749SSergey Zigachev 			return false;
816*b843c749SSergey Zigachev 	}
817*b843c749SSergey Zigachev 	return true;
818*b843c749SSergey Zigachev }
819*b843c749SSergey Zigachev 
dce110_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth)820*b843c749SSergey Zigachev static void dce110_program_pixel_clk_resync(
821*b843c749SSergey Zigachev 		struct dce110_clk_src *clk_src,
822*b843c749SSergey Zigachev 		enum signal_type signal_type,
823*b843c749SSergey Zigachev 		enum dc_color_depth colordepth)
824*b843c749SSergey Zigachev {
825*b843c749SSergey Zigachev 	REG_UPDATE(RESYNC_CNTL,
826*b843c749SSergey Zigachev 			DCCG_DEEP_COLOR_CNTL1, 0);
827*b843c749SSergey Zigachev 	/*
828*b843c749SSergey Zigachev 	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
829*b843c749SSergey Zigachev 	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
830*b843c749SSergey Zigachev 	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
831*b843c749SSergey Zigachev 	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
832*b843c749SSergey Zigachev 	 */
833*b843c749SSergey Zigachev 	if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A)
834*b843c749SSergey Zigachev 		return;
835*b843c749SSergey Zigachev 
836*b843c749SSergey Zigachev 	switch (colordepth) {
837*b843c749SSergey Zigachev 	case COLOR_DEPTH_888:
838*b843c749SSergey Zigachev 		REG_UPDATE(RESYNC_CNTL,
839*b843c749SSergey Zigachev 				DCCG_DEEP_COLOR_CNTL1, 0);
840*b843c749SSergey Zigachev 		break;
841*b843c749SSergey Zigachev 	case COLOR_DEPTH_101010:
842*b843c749SSergey Zigachev 		REG_UPDATE(RESYNC_CNTL,
843*b843c749SSergey Zigachev 				DCCG_DEEP_COLOR_CNTL1, 1);
844*b843c749SSergey Zigachev 		break;
845*b843c749SSergey Zigachev 	case COLOR_DEPTH_121212:
846*b843c749SSergey Zigachev 		REG_UPDATE(RESYNC_CNTL,
847*b843c749SSergey Zigachev 				DCCG_DEEP_COLOR_CNTL1, 2);
848*b843c749SSergey Zigachev 		break;
849*b843c749SSergey Zigachev 	case COLOR_DEPTH_161616:
850*b843c749SSergey Zigachev 		REG_UPDATE(RESYNC_CNTL,
851*b843c749SSergey Zigachev 				DCCG_DEEP_COLOR_CNTL1, 3);
852*b843c749SSergey Zigachev 		break;
853*b843c749SSergey Zigachev 	default:
854*b843c749SSergey Zigachev 		break;
855*b843c749SSergey Zigachev 	}
856*b843c749SSergey Zigachev }
857*b843c749SSergey Zigachev 
dce112_program_pixel_clk_resync(struct dce110_clk_src * clk_src,enum signal_type signal_type,enum dc_color_depth colordepth,bool enable_ycbcr420)858*b843c749SSergey Zigachev static void dce112_program_pixel_clk_resync(
859*b843c749SSergey Zigachev 		struct dce110_clk_src *clk_src,
860*b843c749SSergey Zigachev 		enum signal_type signal_type,
861*b843c749SSergey Zigachev 		enum dc_color_depth colordepth,
862*b843c749SSergey Zigachev 		bool enable_ycbcr420)
863*b843c749SSergey Zigachev {
864*b843c749SSergey Zigachev 	uint32_t deep_color_cntl = 0;
865*b843c749SSergey Zigachev 	uint32_t double_rate_enable = 0;
866*b843c749SSergey Zigachev 
867*b843c749SSergey Zigachev 	/*
868*b843c749SSergey Zigachev 	 24 bit mode: TMDS clock = 1.0 x pixel clock  (1:1)
869*b843c749SSergey Zigachev 	 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4)
870*b843c749SSergey Zigachev 	 36 bit mode: TMDS clock = 1.5 x pixel clock  (3:2)
871*b843c749SSergey Zigachev 	 48 bit mode: TMDS clock = 2 x pixel clock    (2:1)
872*b843c749SSergey Zigachev 	 */
873*b843c749SSergey Zigachev 	if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) {
874*b843c749SSergey Zigachev 		double_rate_enable = enable_ycbcr420 ? 1 : 0;
875*b843c749SSergey Zigachev 
876*b843c749SSergey Zigachev 		switch (colordepth) {
877*b843c749SSergey Zigachev 		case COLOR_DEPTH_888:
878*b843c749SSergey Zigachev 			deep_color_cntl = 0;
879*b843c749SSergey Zigachev 			break;
880*b843c749SSergey Zigachev 		case COLOR_DEPTH_101010:
881*b843c749SSergey Zigachev 			deep_color_cntl = 1;
882*b843c749SSergey Zigachev 			break;
883*b843c749SSergey Zigachev 		case COLOR_DEPTH_121212:
884*b843c749SSergey Zigachev 			deep_color_cntl = 2;
885*b843c749SSergey Zigachev 			break;
886*b843c749SSergey Zigachev 		case COLOR_DEPTH_161616:
887*b843c749SSergey Zigachev 			deep_color_cntl = 3;
888*b843c749SSergey Zigachev 			break;
889*b843c749SSergey Zigachev 		default:
890*b843c749SSergey Zigachev 			break;
891*b843c749SSergey Zigachev 		}
892*b843c749SSergey Zigachev 	}
893*b843c749SSergey Zigachev 
894*b843c749SSergey Zigachev 	if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE)
895*b843c749SSergey Zigachev 		REG_UPDATE_2(PIXCLK_RESYNC_CNTL,
896*b843c749SSergey Zigachev 				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl,
897*b843c749SSergey Zigachev 				PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable);
898*b843c749SSergey Zigachev 	else
899*b843c749SSergey Zigachev 		REG_UPDATE(PIXCLK_RESYNC_CNTL,
900*b843c749SSergey Zigachev 				PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl);
901*b843c749SSergey Zigachev 
902*b843c749SSergey Zigachev }
903*b843c749SSergey Zigachev 
dce110_program_pix_clk(struct clock_source * clock_source,struct pixel_clk_params * pix_clk_params,struct pll_settings * pll_settings)904*b843c749SSergey Zigachev static bool dce110_program_pix_clk(
905*b843c749SSergey Zigachev 		struct clock_source *clock_source,
906*b843c749SSergey Zigachev 		struct pixel_clk_params *pix_clk_params,
907*b843c749SSergey Zigachev 		struct pll_settings *pll_settings)
908*b843c749SSergey Zigachev {
909*b843c749SSergey Zigachev 	struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
910*b843c749SSergey Zigachev 	struct bp_pixel_clock_parameters bp_pc_params = {0};
911*b843c749SSergey Zigachev 
912*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
913*b843c749SSergey Zigachev 	if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
914*b843c749SSergey Zigachev 		unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
915*b843c749SSergey Zigachev 		unsigned dp_dto_ref_kHz = 700000;
916*b843c749SSergey Zigachev 		unsigned clock_kHz = pll_settings->actual_pix_clk;
917*b843c749SSergey Zigachev 
918*b843c749SSergey Zigachev 		/* Set DTO values: phase = target clock, modulo = reference clock */
919*b843c749SSergey Zigachev 		REG_WRITE(PHASE[inst], clock_kHz);
920*b843c749SSergey Zigachev 		REG_WRITE(MODULO[inst], dp_dto_ref_kHz);
921*b843c749SSergey Zigachev 
922*b843c749SSergey Zigachev 		/* Enable DTO */
923*b843c749SSergey Zigachev 		REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1);
924*b843c749SSergey Zigachev 		return true;
925*b843c749SSergey Zigachev 	}
926*b843c749SSergey Zigachev #endif
927*b843c749SSergey Zigachev 	/* First disable SS
928*b843c749SSergey Zigachev 	 * ATOMBIOS will enable by default SS on PLL for DP,
929*b843c749SSergey Zigachev 	 * do not disable it here
930*b843c749SSergey Zigachev 	 */
931*b843c749SSergey Zigachev 	if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL &&
932*b843c749SSergey Zigachev 			!dc_is_dp_signal(pix_clk_params->signal_type) &&
933*b843c749SSergey Zigachev 			clock_source->ctx->dce_version <= DCE_VERSION_11_0)
934*b843c749SSergey Zigachev 		disable_spread_spectrum(clk_src);
935*b843c749SSergey Zigachev 
936*b843c749SSergey Zigachev 	/*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/
937*b843c749SSergey Zigachev 	bp_pc_params.controller_id = pix_clk_params->controller_id;
938*b843c749SSergey Zigachev 	bp_pc_params.pll_id = clock_source->id;
939*b843c749SSergey Zigachev 	bp_pc_params.target_pixel_clock = pll_settings->actual_pix_clk;
940*b843c749SSergey Zigachev 	bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id;
941*b843c749SSergey Zigachev 	bp_pc_params.signal_type = pix_clk_params->signal_type;
942*b843c749SSergey Zigachev 
943*b843c749SSergey Zigachev 	switch (clock_source->ctx->dce_version) {
944*b843c749SSergey Zigachev 	case DCE_VERSION_8_0:
945*b843c749SSergey Zigachev 	case DCE_VERSION_8_1:
946*b843c749SSergey Zigachev 	case DCE_VERSION_8_3:
947*b843c749SSergey Zigachev 	case DCE_VERSION_10_0:
948*b843c749SSergey Zigachev 	case DCE_VERSION_11_0:
949*b843c749SSergey Zigachev 		bp_pc_params.reference_divider = pll_settings->reference_divider;
950*b843c749SSergey Zigachev 		bp_pc_params.feedback_divider = pll_settings->feedback_divider;
951*b843c749SSergey Zigachev 		bp_pc_params.fractional_feedback_divider =
952*b843c749SSergey Zigachev 				pll_settings->fract_feedback_divider;
953*b843c749SSergey Zigachev 		bp_pc_params.pixel_clock_post_divider =
954*b843c749SSergey Zigachev 				pll_settings->pix_clk_post_divider;
955*b843c749SSergey Zigachev 		bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC =
956*b843c749SSergey Zigachev 						pll_settings->use_external_clk;
957*b843c749SSergey Zigachev 
958*b843c749SSergey Zigachev 		if (clk_src->bios->funcs->set_pixel_clock(
959*b843c749SSergey Zigachev 				clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
960*b843c749SSergey Zigachev 			return false;
961*b843c749SSergey Zigachev 		/* Enable SS
962*b843c749SSergey Zigachev 		 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock),
963*b843c749SSergey Zigachev 		 * based on HW display PLL team, SS control settings should be programmed
964*b843c749SSergey Zigachev 		 * during PLL Reset, but they do not have effect
965*b843c749SSergey Zigachev 		 * until SS_EN is asserted.*/
966*b843c749SSergey Zigachev 		if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL
967*b843c749SSergey Zigachev 				&& !dc_is_dp_signal(pix_clk_params->signal_type)) {
968*b843c749SSergey Zigachev 
969*b843c749SSergey Zigachev 			if (pix_clk_params->flags.ENABLE_SS)
970*b843c749SSergey Zigachev 				if (!enable_spread_spectrum(clk_src,
971*b843c749SSergey Zigachev 								pix_clk_params->signal_type,
972*b843c749SSergey Zigachev 								pll_settings))
973*b843c749SSergey Zigachev 					return false;
974*b843c749SSergey Zigachev 
975*b843c749SSergey Zigachev 			/* Resync deep color DTO */
976*b843c749SSergey Zigachev 			dce110_program_pixel_clk_resync(clk_src,
977*b843c749SSergey Zigachev 						pix_clk_params->signal_type,
978*b843c749SSergey Zigachev 						pix_clk_params->color_depth);
979*b843c749SSergey Zigachev 		}
980*b843c749SSergey Zigachev 
981*b843c749SSergey Zigachev 		break;
982*b843c749SSergey Zigachev 	case DCE_VERSION_11_2:
983*b843c749SSergey Zigachev 	case DCE_VERSION_11_22:
984*b843c749SSergey Zigachev 	case DCE_VERSION_12_0:
985*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
986*b843c749SSergey Zigachev 	case DCN_VERSION_1_0:
987*b843c749SSergey Zigachev #endif
988*b843c749SSergey Zigachev 
989*b843c749SSergey Zigachev 		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
990*b843c749SSergey Zigachev 			bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC =
991*b843c749SSergey Zigachev 							pll_settings->use_external_clk;
992*b843c749SSergey Zigachev 			bp_pc_params.flags.SET_XTALIN_REF_SRC =
993*b843c749SSergey Zigachev 							!pll_settings->use_external_clk;
994*b843c749SSergey Zigachev 			if (pix_clk_params->flags.SUPPORT_YCBCR420) {
995*b843c749SSergey Zigachev 				bp_pc_params.flags.SUPPORT_YUV_420 = 1;
996*b843c749SSergey Zigachev 			}
997*b843c749SSergey Zigachev 		}
998*b843c749SSergey Zigachev 		if (clk_src->bios->funcs->set_pixel_clock(
999*b843c749SSergey Zigachev 				clk_src->bios, &bp_pc_params) != BP_RESULT_OK)
1000*b843c749SSergey Zigachev 			return false;
1001*b843c749SSergey Zigachev 		/* Resync deep color DTO */
1002*b843c749SSergey Zigachev 		if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO)
1003*b843c749SSergey Zigachev 			dce112_program_pixel_clk_resync(clk_src,
1004*b843c749SSergey Zigachev 						pix_clk_params->signal_type,
1005*b843c749SSergey Zigachev 						pix_clk_params->color_depth,
1006*b843c749SSergey Zigachev 						pix_clk_params->flags.SUPPORT_YCBCR420);
1007*b843c749SSergey Zigachev 		break;
1008*b843c749SSergey Zigachev 	default:
1009*b843c749SSergey Zigachev 		break;
1010*b843c749SSergey Zigachev 	}
1011*b843c749SSergey Zigachev 
1012*b843c749SSergey Zigachev 	return true;
1013*b843c749SSergey Zigachev }
1014*b843c749SSergey Zigachev 
dce110_clock_source_power_down(struct clock_source * clk_src)1015*b843c749SSergey Zigachev static bool dce110_clock_source_power_down(
1016*b843c749SSergey Zigachev 		struct clock_source *clk_src)
1017*b843c749SSergey Zigachev {
1018*b843c749SSergey Zigachev 	struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src);
1019*b843c749SSergey Zigachev 	enum bp_result bp_result;
1020*b843c749SSergey Zigachev 	struct bp_pixel_clock_parameters bp_pixel_clock_params = {0};
1021*b843c749SSergey Zigachev 
1022*b843c749SSergey Zigachev 	if (clk_src->dp_clk_src)
1023*b843c749SSergey Zigachev 		return true;
1024*b843c749SSergey Zigachev 
1025*b843c749SSergey Zigachev 	/* If Pixel Clock is 0 it means Power Down Pll*/
1026*b843c749SSergey Zigachev 	bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED;
1027*b843c749SSergey Zigachev 	bp_pixel_clock_params.pll_id = clk_src->id;
1028*b843c749SSergey Zigachev 	bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1;
1029*b843c749SSergey Zigachev 
1030*b843c749SSergey Zigachev 	/*Call ASICControl to process ATOMBIOS Exec table*/
1031*b843c749SSergey Zigachev 	bp_result = dce110_clk_src->bios->funcs->set_pixel_clock(
1032*b843c749SSergey Zigachev 			dce110_clk_src->bios,
1033*b843c749SSergey Zigachev 			&bp_pixel_clock_params);
1034*b843c749SSergey Zigachev 
1035*b843c749SSergey Zigachev 	return bp_result == BP_RESULT_OK;
1036*b843c749SSergey Zigachev }
1037*b843c749SSergey Zigachev 
1038*b843c749SSergey Zigachev /*****************************************/
1039*b843c749SSergey Zigachev /* Constructor                           */
1040*b843c749SSergey Zigachev /*****************************************/
1041*b843c749SSergey Zigachev static const struct clock_source_funcs dce110_clk_src_funcs = {
1042*b843c749SSergey Zigachev 	.cs_power_down = dce110_clock_source_power_down,
1043*b843c749SSergey Zigachev 	.program_pix_clk = dce110_program_pix_clk,
1044*b843c749SSergey Zigachev 	.get_pix_clk_dividers = dce110_get_pix_clk_dividers,
1045*b843c749SSergey Zigachev 	.get_pix_rate_in_hz = dce110_get_pix_rate_in_hz
1046*b843c749SSergey Zigachev };
1047*b843c749SSergey Zigachev 
get_ss_info_from_atombios(struct dce110_clk_src * clk_src,enum as_signal_type as_signal,struct spread_spectrum_data * spread_spectrum_data[],uint32_t * ss_entries_num)1048*b843c749SSergey Zigachev static void get_ss_info_from_atombios(
1049*b843c749SSergey Zigachev 		struct dce110_clk_src *clk_src,
1050*b843c749SSergey Zigachev 		enum as_signal_type as_signal,
1051*b843c749SSergey Zigachev 		struct spread_spectrum_data *spread_spectrum_data[],
1052*b843c749SSergey Zigachev 		uint32_t *ss_entries_num)
1053*b843c749SSergey Zigachev {
1054*b843c749SSergey Zigachev 	enum bp_result bp_result = BP_RESULT_FAILURE;
1055*b843c749SSergey Zigachev 	struct spread_spectrum_info *ss_info;
1056*b843c749SSergey Zigachev 	struct spread_spectrum_data *ss_data;
1057*b843c749SSergey Zigachev 	struct spread_spectrum_info *ss_info_cur;
1058*b843c749SSergey Zigachev 	struct spread_spectrum_data *ss_data_cur;
1059*b843c749SSergey Zigachev 	uint32_t i;
1060*b843c749SSergey Zigachev 	DC_LOGGER_INIT();
1061*b843c749SSergey Zigachev 	if (ss_entries_num == NULL) {
1062*b843c749SSergey Zigachev 		DC_LOG_SYNC(
1063*b843c749SSergey Zigachev 			"Invalid entry !!!\n");
1064*b843c749SSergey Zigachev 		return;
1065*b843c749SSergey Zigachev 	}
1066*b843c749SSergey Zigachev 	if (spread_spectrum_data == NULL) {
1067*b843c749SSergey Zigachev 		DC_LOG_SYNC(
1068*b843c749SSergey Zigachev 			"Invalid array pointer!!!\n");
1069*b843c749SSergey Zigachev 		return;
1070*b843c749SSergey Zigachev 	}
1071*b843c749SSergey Zigachev 
1072*b843c749SSergey Zigachev 	spread_spectrum_data[0] = NULL;
1073*b843c749SSergey Zigachev 	*ss_entries_num = 0;
1074*b843c749SSergey Zigachev 
1075*b843c749SSergey Zigachev 	*ss_entries_num = clk_src->bios->funcs->get_ss_entry_number(
1076*b843c749SSergey Zigachev 			clk_src->bios,
1077*b843c749SSergey Zigachev 			as_signal);
1078*b843c749SSergey Zigachev 
1079*b843c749SSergey Zigachev 	if (*ss_entries_num == 0)
1080*b843c749SSergey Zigachev 		return;
1081*b843c749SSergey Zigachev 
1082*b843c749SSergey Zigachev 	ss_info = kcalloc(*ss_entries_num,
1083*b843c749SSergey Zigachev 			  sizeof(struct spread_spectrum_info),
1084*b843c749SSergey Zigachev 			  GFP_KERNEL);
1085*b843c749SSergey Zigachev 	ss_info_cur = ss_info;
1086*b843c749SSergey Zigachev 	if (ss_info == NULL)
1087*b843c749SSergey Zigachev 		return;
1088*b843c749SSergey Zigachev 
1089*b843c749SSergey Zigachev 	ss_data = kcalloc(*ss_entries_num,
1090*b843c749SSergey Zigachev 			  sizeof(struct spread_spectrum_data),
1091*b843c749SSergey Zigachev 			  GFP_KERNEL);
1092*b843c749SSergey Zigachev 	if (ss_data == NULL)
1093*b843c749SSergey Zigachev 		goto out_free_info;
1094*b843c749SSergey Zigachev 
1095*b843c749SSergey Zigachev 	for (i = 0, ss_info_cur = ss_info;
1096*b843c749SSergey Zigachev 		i < (*ss_entries_num);
1097*b843c749SSergey Zigachev 		++i, ++ss_info_cur) {
1098*b843c749SSergey Zigachev 
1099*b843c749SSergey Zigachev 		bp_result = clk_src->bios->funcs->get_spread_spectrum_info(
1100*b843c749SSergey Zigachev 				clk_src->bios,
1101*b843c749SSergey Zigachev 				as_signal,
1102*b843c749SSergey Zigachev 				i,
1103*b843c749SSergey Zigachev 				ss_info_cur);
1104*b843c749SSergey Zigachev 
1105*b843c749SSergey Zigachev 		if (bp_result != BP_RESULT_OK)
1106*b843c749SSergey Zigachev 			goto out_free_data;
1107*b843c749SSergey Zigachev 	}
1108*b843c749SSergey Zigachev 
1109*b843c749SSergey Zigachev 	for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data;
1110*b843c749SSergey Zigachev 		i < (*ss_entries_num);
1111*b843c749SSergey Zigachev 		++i, ++ss_info_cur, ++ss_data_cur) {
1112*b843c749SSergey Zigachev 
1113*b843c749SSergey Zigachev 		if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) {
1114*b843c749SSergey Zigachev 			DC_LOG_SYNC(
1115*b843c749SSergey Zigachev 				"Invalid ATOMBIOS SS Table!!!\n");
1116*b843c749SSergey Zigachev 			goto out_free_data;
1117*b843c749SSergey Zigachev 		}
1118*b843c749SSergey Zigachev 
1119*b843c749SSergey Zigachev 		/* for HDMI check SS percentage,
1120*b843c749SSergey Zigachev 		 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/
1121*b843c749SSergey Zigachev 		if (as_signal == AS_SIGNAL_TYPE_HDMI
1122*b843c749SSergey Zigachev 				&& ss_info_cur->spread_spectrum_percentage > 6){
1123*b843c749SSergey Zigachev 			/* invalid input, do nothing */
1124*b843c749SSergey Zigachev 			DC_LOG_SYNC(
1125*b843c749SSergey Zigachev 				"Invalid SS percentage ");
1126*b843c749SSergey Zigachev 			DC_LOG_SYNC(
1127*b843c749SSergey Zigachev 				"for HDMI in ATOMBIOS info Table!!!\n");
1128*b843c749SSergey Zigachev 			continue;
1129*b843c749SSergey Zigachev 		}
1130*b843c749SSergey Zigachev 		if (ss_info_cur->spread_percentage_divider == 1000) {
1131*b843c749SSergey Zigachev 			/* Keep previous precision from ATOMBIOS for these
1132*b843c749SSergey Zigachev 			* in case new precision set by ATOMBIOS for these
1133*b843c749SSergey Zigachev 			* (otherwise all code in DCE specific classes
1134*b843c749SSergey Zigachev 			* for all previous ASICs would need
1135*b843c749SSergey Zigachev 			* to be updated for SS calculations,
1136*b843c749SSergey Zigachev 			* Audio SS compensation and DP DTO SS compensation
1137*b843c749SSergey Zigachev 			* which assumes fixed SS percentage Divider = 100)*/
1138*b843c749SSergey Zigachev 			ss_info_cur->spread_spectrum_percentage /= 10;
1139*b843c749SSergey Zigachev 			ss_info_cur->spread_percentage_divider = 100;
1140*b843c749SSergey Zigachev 		}
1141*b843c749SSergey Zigachev 
1142*b843c749SSergey Zigachev 		ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range;
1143*b843c749SSergey Zigachev 		ss_data_cur->percentage =
1144*b843c749SSergey Zigachev 				ss_info_cur->spread_spectrum_percentage;
1145*b843c749SSergey Zigachev 		ss_data_cur->percentage_divider =
1146*b843c749SSergey Zigachev 				ss_info_cur->spread_percentage_divider;
1147*b843c749SSergey Zigachev 		ss_data_cur->modulation_freq_hz =
1148*b843c749SSergey Zigachev 				ss_info_cur->spread_spectrum_range;
1149*b843c749SSergey Zigachev 
1150*b843c749SSergey Zigachev 		if (ss_info_cur->type.CENTER_MODE)
1151*b843c749SSergey Zigachev 			ss_data_cur->flags.CENTER_SPREAD = 1;
1152*b843c749SSergey Zigachev 
1153*b843c749SSergey Zigachev 		if (ss_info_cur->type.EXTERNAL)
1154*b843c749SSergey Zigachev 			ss_data_cur->flags.EXTERNAL_SS = 1;
1155*b843c749SSergey Zigachev 
1156*b843c749SSergey Zigachev 	}
1157*b843c749SSergey Zigachev 
1158*b843c749SSergey Zigachev 	*spread_spectrum_data = ss_data;
1159*b843c749SSergey Zigachev 	kfree(ss_info);
1160*b843c749SSergey Zigachev 	return;
1161*b843c749SSergey Zigachev 
1162*b843c749SSergey Zigachev out_free_data:
1163*b843c749SSergey Zigachev 	kfree(ss_data);
1164*b843c749SSergey Zigachev 	*ss_entries_num = 0;
1165*b843c749SSergey Zigachev out_free_info:
1166*b843c749SSergey Zigachev 	kfree(ss_info);
1167*b843c749SSergey Zigachev }
1168*b843c749SSergey Zigachev 
ss_info_from_atombios_create(struct dce110_clk_src * clk_src)1169*b843c749SSergey Zigachev static void ss_info_from_atombios_create(
1170*b843c749SSergey Zigachev 	struct dce110_clk_src *clk_src)
1171*b843c749SSergey Zigachev {
1172*b843c749SSergey Zigachev 	get_ss_info_from_atombios(
1173*b843c749SSergey Zigachev 		clk_src,
1174*b843c749SSergey Zigachev 		AS_SIGNAL_TYPE_DISPLAY_PORT,
1175*b843c749SSergey Zigachev 		&clk_src->dp_ss_params,
1176*b843c749SSergey Zigachev 		&clk_src->dp_ss_params_cnt);
1177*b843c749SSergey Zigachev 	get_ss_info_from_atombios(
1178*b843c749SSergey Zigachev 		clk_src,
1179*b843c749SSergey Zigachev 		AS_SIGNAL_TYPE_HDMI,
1180*b843c749SSergey Zigachev 		&clk_src->hdmi_ss_params,
1181*b843c749SSergey Zigachev 		&clk_src->hdmi_ss_params_cnt);
1182*b843c749SSergey Zigachev 	get_ss_info_from_atombios(
1183*b843c749SSergey Zigachev 		clk_src,
1184*b843c749SSergey Zigachev 		AS_SIGNAL_TYPE_DVI,
1185*b843c749SSergey Zigachev 		&clk_src->dvi_ss_params,
1186*b843c749SSergey Zigachev 		&clk_src->dvi_ss_params_cnt);
1187*b843c749SSergey Zigachev }
1188*b843c749SSergey Zigachev 
calc_pll_max_vco_construct(struct calc_pll_clock_source * calc_pll_cs,struct calc_pll_clock_source_init_data * init_data)1189*b843c749SSergey Zigachev static bool calc_pll_max_vco_construct(
1190*b843c749SSergey Zigachev 			struct calc_pll_clock_source *calc_pll_cs,
1191*b843c749SSergey Zigachev 			struct calc_pll_clock_source_init_data *init_data)
1192*b843c749SSergey Zigachev {
1193*b843c749SSergey Zigachev 	uint32_t i;
1194*b843c749SSergey Zigachev 	struct dc_firmware_info fw_info = { { 0 } };
1195*b843c749SSergey Zigachev 	if (calc_pll_cs == NULL ||
1196*b843c749SSergey Zigachev 			init_data == NULL ||
1197*b843c749SSergey Zigachev 			init_data->bp == NULL)
1198*b843c749SSergey Zigachev 		return false;
1199*b843c749SSergey Zigachev 
1200*b843c749SSergey Zigachev 	if (init_data->bp->funcs->get_firmware_info(
1201*b843c749SSergey Zigachev 				init_data->bp,
1202*b843c749SSergey Zigachev 				&fw_info) != BP_RESULT_OK)
1203*b843c749SSergey Zigachev 		return false;
1204*b843c749SSergey Zigachev 
1205*b843c749SSergey Zigachev 	calc_pll_cs->ctx = init_data->ctx;
1206*b843c749SSergey Zigachev 	calc_pll_cs->ref_freq_khz = fw_info.pll_info.crystal_frequency;
1207*b843c749SSergey Zigachev 	calc_pll_cs->min_vco_khz =
1208*b843c749SSergey Zigachev 			fw_info.pll_info.min_output_pxl_clk_pll_frequency;
1209*b843c749SSergey Zigachev 	calc_pll_cs->max_vco_khz =
1210*b843c749SSergey Zigachev 			fw_info.pll_info.max_output_pxl_clk_pll_frequency;
1211*b843c749SSergey Zigachev 
1212*b843c749SSergey Zigachev 	if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0)
1213*b843c749SSergey Zigachev 		calc_pll_cs->max_pll_input_freq_khz =
1214*b843c749SSergey Zigachev 			init_data->max_override_input_pxl_clk_pll_freq_khz;
1215*b843c749SSergey Zigachev 	else
1216*b843c749SSergey Zigachev 		calc_pll_cs->max_pll_input_freq_khz =
1217*b843c749SSergey Zigachev 			fw_info.pll_info.max_input_pxl_clk_pll_frequency;
1218*b843c749SSergey Zigachev 
1219*b843c749SSergey Zigachev 	if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0)
1220*b843c749SSergey Zigachev 		calc_pll_cs->min_pll_input_freq_khz =
1221*b843c749SSergey Zigachev 			init_data->min_override_input_pxl_clk_pll_freq_khz;
1222*b843c749SSergey Zigachev 	else
1223*b843c749SSergey Zigachev 		calc_pll_cs->min_pll_input_freq_khz =
1224*b843c749SSergey Zigachev 			fw_info.pll_info.min_input_pxl_clk_pll_frequency;
1225*b843c749SSergey Zigachev 
1226*b843c749SSergey Zigachev 	calc_pll_cs->min_pix_clock_pll_post_divider =
1227*b843c749SSergey Zigachev 			init_data->min_pix_clk_pll_post_divider;
1228*b843c749SSergey Zigachev 	calc_pll_cs->max_pix_clock_pll_post_divider =
1229*b843c749SSergey Zigachev 			init_data->max_pix_clk_pll_post_divider;
1230*b843c749SSergey Zigachev 	calc_pll_cs->min_pll_ref_divider =
1231*b843c749SSergey Zigachev 			init_data->min_pll_ref_divider;
1232*b843c749SSergey Zigachev 	calc_pll_cs->max_pll_ref_divider =
1233*b843c749SSergey Zigachev 			init_data->max_pll_ref_divider;
1234*b843c749SSergey Zigachev 
1235*b843c749SSergey Zigachev 	if (init_data->num_fract_fb_divider_decimal_point == 0 ||
1236*b843c749SSergey Zigachev 		init_data->num_fract_fb_divider_decimal_point_precision >
1237*b843c749SSergey Zigachev 				init_data->num_fract_fb_divider_decimal_point) {
1238*b843c749SSergey Zigachev 		DC_LOG_ERROR(
1239*b843c749SSergey Zigachev 			"The dec point num or precision is incorrect!");
1240*b843c749SSergey Zigachev 		return false;
1241*b843c749SSergey Zigachev 	}
1242*b843c749SSergey Zigachev 	if (init_data->num_fract_fb_divider_decimal_point_precision == 0) {
1243*b843c749SSergey Zigachev 		DC_LOG_ERROR(
1244*b843c749SSergey Zigachev 			"Incorrect fract feedback divider precision num!");
1245*b843c749SSergey Zigachev 		return false;
1246*b843c749SSergey Zigachev 	}
1247*b843c749SSergey Zigachev 
1248*b843c749SSergey Zigachev 	calc_pll_cs->fract_fb_divider_decimal_points_num =
1249*b843c749SSergey Zigachev 				init_data->num_fract_fb_divider_decimal_point;
1250*b843c749SSergey Zigachev 	calc_pll_cs->fract_fb_divider_precision =
1251*b843c749SSergey Zigachev 			init_data->num_fract_fb_divider_decimal_point_precision;
1252*b843c749SSergey Zigachev 	calc_pll_cs->fract_fb_divider_factor = 1;
1253*b843c749SSergey Zigachev 	for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i)
1254*b843c749SSergey Zigachev 		calc_pll_cs->fract_fb_divider_factor *= 10;
1255*b843c749SSergey Zigachev 
1256*b843c749SSergey Zigachev 	calc_pll_cs->fract_fb_divider_precision_factor = 1;
1257*b843c749SSergey Zigachev 	for (
1258*b843c749SSergey Zigachev 		i = 0;
1259*b843c749SSergey Zigachev 		i < (calc_pll_cs->fract_fb_divider_decimal_points_num -
1260*b843c749SSergey Zigachev 				calc_pll_cs->fract_fb_divider_precision);
1261*b843c749SSergey Zigachev 		++i)
1262*b843c749SSergey Zigachev 		calc_pll_cs->fract_fb_divider_precision_factor *= 10;
1263*b843c749SSergey Zigachev 
1264*b843c749SSergey Zigachev 	return true;
1265*b843c749SSergey Zigachev }
1266*b843c749SSergey Zigachev 
dce110_clk_src_construct(struct dce110_clk_src * clk_src,struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,const struct dce110_clk_src_shift * cs_shift,const struct dce110_clk_src_mask * cs_mask)1267*b843c749SSergey Zigachev bool dce110_clk_src_construct(
1268*b843c749SSergey Zigachev 	struct dce110_clk_src *clk_src,
1269*b843c749SSergey Zigachev 	struct dc_context *ctx,
1270*b843c749SSergey Zigachev 	struct dc_bios *bios,
1271*b843c749SSergey Zigachev 	enum clock_source_id id,
1272*b843c749SSergey Zigachev 	const struct dce110_clk_src_regs *regs,
1273*b843c749SSergey Zigachev 	const struct dce110_clk_src_shift *cs_shift,
1274*b843c749SSergey Zigachev 	const struct dce110_clk_src_mask *cs_mask)
1275*b843c749SSergey Zigachev {
1276*b843c749SSergey Zigachev 	struct dc_firmware_info fw_info = { { 0 } };
1277*b843c749SSergey Zigachev 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi;
1278*b843c749SSergey Zigachev 	struct calc_pll_clock_source_init_data calc_pll_cs_init_data;
1279*b843c749SSergey Zigachev 
1280*b843c749SSergey Zigachev 	clk_src->base.ctx = ctx;
1281*b843c749SSergey Zigachev 	clk_src->bios = bios;
1282*b843c749SSergey Zigachev 	clk_src->base.id = id;
1283*b843c749SSergey Zigachev 	clk_src->base.funcs = &dce110_clk_src_funcs;
1284*b843c749SSergey Zigachev 
1285*b843c749SSergey Zigachev 	clk_src->regs = regs;
1286*b843c749SSergey Zigachev 	clk_src->cs_shift = cs_shift;
1287*b843c749SSergey Zigachev 	clk_src->cs_mask = cs_mask;
1288*b843c749SSergey Zigachev 
1289*b843c749SSergey Zigachev 	if (clk_src->bios->funcs->get_firmware_info(
1290*b843c749SSergey Zigachev 			clk_src->bios, &fw_info) != BP_RESULT_OK) {
1291*b843c749SSergey Zigachev 		ASSERT_CRITICAL(false);
1292*b843c749SSergey Zigachev 		goto unexpected_failure;
1293*b843c749SSergey Zigachev 	}
1294*b843c749SSergey Zigachev 
1295*b843c749SSergey Zigachev 	clk_src->ext_clk_khz =
1296*b843c749SSergey Zigachev 			fw_info.external_clock_source_frequency_for_dp;
1297*b843c749SSergey Zigachev 
1298*b843c749SSergey Zigachev 	switch (clk_src->base.ctx->dce_version) {
1299*b843c749SSergey Zigachev 	case DCE_VERSION_8_0:
1300*b843c749SSergey Zigachev 	case DCE_VERSION_8_1:
1301*b843c749SSergey Zigachev 	case DCE_VERSION_8_3:
1302*b843c749SSergey Zigachev 	case DCE_VERSION_10_0:
1303*b843c749SSergey Zigachev 	case DCE_VERSION_11_0:
1304*b843c749SSergey Zigachev 
1305*b843c749SSergey Zigachev 		/* structure normally used with PLL ranges from ATOMBIOS; DS on by default */
1306*b843c749SSergey Zigachev 		calc_pll_cs_init_data.bp = bios;
1307*b843c749SSergey Zigachev 		calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1;
1308*b843c749SSergey Zigachev 		calc_pll_cs_init_data.max_pix_clk_pll_post_divider =
1309*b843c749SSergey Zigachev 				clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1310*b843c749SSergey Zigachev 		calc_pll_cs_init_data.min_pll_ref_divider =	1;
1311*b843c749SSergey Zigachev 		calc_pll_cs_init_data.max_pll_ref_divider =	clk_src->cs_mask->PLL_REF_DIV;
1312*b843c749SSergey Zigachev 		/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1313*b843c749SSergey Zigachev 		calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz =	0;
1314*b843c749SSergey Zigachev 		/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1315*b843c749SSergey Zigachev 		calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz =	0;
1316*b843c749SSergey Zigachev 		/*numberOfFractFBDividerDecimalPoints*/
1317*b843c749SSergey Zigachev 		calc_pll_cs_init_data.num_fract_fb_divider_decimal_point =
1318*b843c749SSergey Zigachev 				FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1319*b843c749SSergey Zigachev 		/*number of decimal point to round off for fractional feedback divider value*/
1320*b843c749SSergey Zigachev 		calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision =
1321*b843c749SSergey Zigachev 				FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1322*b843c749SSergey Zigachev 		calc_pll_cs_init_data.ctx =	ctx;
1323*b843c749SSergey Zigachev 
1324*b843c749SSergey Zigachev 		/*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */
1325*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.bp = bios;
1326*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1;
1327*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider =
1328*b843c749SSergey Zigachev 				clk_src->cs_mask->PLL_POST_DIV_PIXCLK;
1329*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1;
1330*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV;
1331*b843c749SSergey Zigachev 		/* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1332*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500;
1333*b843c749SSergey Zigachev 		/* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/
1334*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000;
1335*b843c749SSergey Zigachev 		/*numberOfFractFBDividerDecimalPoints*/
1336*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point =
1337*b843c749SSergey Zigachev 				FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1338*b843c749SSergey Zigachev 		/*number of decimal point to round off for fractional feedback divider value*/
1339*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision =
1340*b843c749SSergey Zigachev 				FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM;
1341*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.ctx = ctx;
1342*b843c749SSergey Zigachev 
1343*b843c749SSergey Zigachev 		clk_src->ref_freq_khz = fw_info.pll_info.crystal_frequency;
1344*b843c749SSergey Zigachev 
1345*b843c749SSergey Zigachev 		if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL)
1346*b843c749SSergey Zigachev 			return true;
1347*b843c749SSergey Zigachev 
1348*b843c749SSergey Zigachev 		/* PLL only from here on */
1349*b843c749SSergey Zigachev 		ss_info_from_atombios_create(clk_src);
1350*b843c749SSergey Zigachev 
1351*b843c749SSergey Zigachev 		if (!calc_pll_max_vco_construct(
1352*b843c749SSergey Zigachev 				&clk_src->calc_pll,
1353*b843c749SSergey Zigachev 				&calc_pll_cs_init_data)) {
1354*b843c749SSergey Zigachev 			ASSERT_CRITICAL(false);
1355*b843c749SSergey Zigachev 			goto unexpected_failure;
1356*b843c749SSergey Zigachev 		}
1357*b843c749SSergey Zigachev 
1358*b843c749SSergey Zigachev 
1359*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.
1360*b843c749SSergey Zigachev 				min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2;
1361*b843c749SSergey Zigachev 		calc_pll_cs_init_data_hdmi.
1362*b843c749SSergey Zigachev 				max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz;
1363*b843c749SSergey Zigachev 
1364*b843c749SSergey Zigachev 
1365*b843c749SSergey Zigachev 		if (!calc_pll_max_vco_construct(
1366*b843c749SSergey Zigachev 				&clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) {
1367*b843c749SSergey Zigachev 			ASSERT_CRITICAL(false);
1368*b843c749SSergey Zigachev 			goto unexpected_failure;
1369*b843c749SSergey Zigachev 		}
1370*b843c749SSergey Zigachev 		break;
1371*b843c749SSergey Zigachev 	default:
1372*b843c749SSergey Zigachev 		break;
1373*b843c749SSergey Zigachev 	}
1374*b843c749SSergey Zigachev 
1375*b843c749SSergey Zigachev 	return true;
1376*b843c749SSergey Zigachev 
1377*b843c749SSergey Zigachev unexpected_failure:
1378*b843c749SSergey Zigachev 	return false;
1379*b843c749SSergey Zigachev }
1380*b843c749SSergey Zigachev 
1381