1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef __AMDGPU_DM_IRQ_H__ 25*b843c749SSergey Zigachev #define __AMDGPU_DM_IRQ_H__ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include "irq_types.h" /* DAL irq definitions */ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev /* 30*b843c749SSergey Zigachev * Display Manager IRQ-related interfaces (for use by DAL). 31*b843c749SSergey Zigachev */ 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev /** 34*b843c749SSergey Zigachev * amdgpu_dm_irq_init - Initialize internal structures of 'amdgpu_dm_irq'. 35*b843c749SSergey Zigachev * 36*b843c749SSergey Zigachev * This function should be called exactly once - during DM initialization. 37*b843c749SSergey Zigachev * 38*b843c749SSergey Zigachev * Returns: 39*b843c749SSergey Zigachev * 0 - success 40*b843c749SSergey Zigachev * non-zero - error 41*b843c749SSergey Zigachev */ 42*b843c749SSergey Zigachev int amdgpu_dm_irq_init(struct amdgpu_device *adev); 43*b843c749SSergey Zigachev 44*b843c749SSergey Zigachev /** 45*b843c749SSergey Zigachev * amdgpu_dm_irq_fini - deallocate internal structures of 'amdgpu_dm_irq'. 46*b843c749SSergey Zigachev * 47*b843c749SSergey Zigachev * This function should be called exactly once - during DM destruction. 48*b843c749SSergey Zigachev * 49*b843c749SSergey Zigachev */ 50*b843c749SSergey Zigachev void amdgpu_dm_irq_fini(struct amdgpu_device *adev); 51*b843c749SSergey Zigachev 52*b843c749SSergey Zigachev /** 53*b843c749SSergey Zigachev * amdgpu_dm_irq_register_interrupt - register irq handler for Display block. 54*b843c749SSergey Zigachev * 55*b843c749SSergey Zigachev * @adev: AMD DRM device 56*b843c749SSergey Zigachev * @int_params: parameters for the irq 57*b843c749SSergey Zigachev * @ih: pointer to the irq hander function 58*b843c749SSergey Zigachev * @handler_args: arguments which will be passed to ih 59*b843c749SSergey Zigachev * 60*b843c749SSergey Zigachev * Returns: 61*b843c749SSergey Zigachev * IRQ Handler Index on success. 62*b843c749SSergey Zigachev * NULL on failure. 63*b843c749SSergey Zigachev * 64*b843c749SSergey Zigachev * Cannot be called from an interrupt handler. 65*b843c749SSergey Zigachev */ 66*b843c749SSergey Zigachev void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev, 67*b843c749SSergey Zigachev struct dc_interrupt_params *int_params, 68*b843c749SSergey Zigachev void (*ih)(void *), 69*b843c749SSergey Zigachev void *handler_args); 70*b843c749SSergey Zigachev 71*b843c749SSergey Zigachev /** 72*b843c749SSergey Zigachev * amdgpu_dm_irq_unregister_interrupt - unregister handler which was registered 73*b843c749SSergey Zigachev * by amdgpu_dm_irq_register_interrupt(). 74*b843c749SSergey Zigachev * 75*b843c749SSergey Zigachev * @adev: AMD DRM device. 76*b843c749SSergey Zigachev * @ih_index: irq handler index which was returned by 77*b843c749SSergey Zigachev * amdgpu_dm_irq_register_interrupt 78*b843c749SSergey Zigachev */ 79*b843c749SSergey Zigachev void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev, 80*b843c749SSergey Zigachev enum dc_irq_source irq_source, 81*b843c749SSergey Zigachev void *ih_index); 82*b843c749SSergey Zigachev 83*b843c749SSergey Zigachev void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev); 84*b843c749SSergey Zigachev 85*b843c749SSergey Zigachev void amdgpu_dm_hpd_init(struct amdgpu_device *adev); 86*b843c749SSergey Zigachev void amdgpu_dm_hpd_fini(struct amdgpu_device *adev); 87*b843c749SSergey Zigachev 88*b843c749SSergey Zigachev /** 89*b843c749SSergey Zigachev * amdgpu_dm_irq_suspend - disable ASIC interrupt during suspend. 90*b843c749SSergey Zigachev * 91*b843c749SSergey Zigachev */ 92*b843c749SSergey Zigachev int amdgpu_dm_irq_suspend(struct amdgpu_device *adev); 93*b843c749SSergey Zigachev 94*b843c749SSergey Zigachev /** 95*b843c749SSergey Zigachev * amdgpu_dm_irq_resume_early - enable HPDRX ASIC interrupts during resume. 96*b843c749SSergey Zigachev * amdgpu_dm_irq_resume - enable ASIC interrupt during resume. 97*b843c749SSergey Zigachev * 98*b843c749SSergey Zigachev */ 99*b843c749SSergey Zigachev int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev); 100*b843c749SSergey Zigachev int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev); 101*b843c749SSergey Zigachev 102*b843c749SSergey Zigachev #endif /* __AMDGPU_DM_IRQ_H__ */ 103