1b843c749SSergey Zigachev /*
2b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc.
3b843c749SSergey Zigachev *
4b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10b843c749SSergey Zigachev *
11b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13b843c749SSergey Zigachev *
14b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21b843c749SSergey Zigachev *
22b843c749SSergey Zigachev * Author: Huang Rui
23b843c749SSergey Zigachev *
24b843c749SSergey Zigachev */
25b843c749SSergey Zigachev
26b843c749SSergey Zigachev #include <linux/firmware.h>
27b843c749SSergey Zigachev #include "amdgpu.h"
28b843c749SSergey Zigachev #include "amdgpu_psp.h"
29b843c749SSergey Zigachev #include "amdgpu_ucode.h"
30b843c749SSergey Zigachev #include "soc15_common.h"
31b843c749SSergey Zigachev #include "psp_v10_0.h"
32b843c749SSergey Zigachev
33b843c749SSergey Zigachev #include "mp/mp_10_0_offset.h"
34b843c749SSergey Zigachev #include "gc/gc_9_1_offset.h"
35b843c749SSergey Zigachev #include "sdma0/sdma0_4_1_offset.h"
36b843c749SSergey Zigachev
37*809f3802SSergey Zigachev MODULE_FIRMWARE("amdgpufw_raven_asd");
38b843c749SSergey Zigachev
39b843c749SSergey Zigachev static int
psp_v10_0_get_fw_type(struct amdgpu_firmware_info * ucode,enum psp_gfx_fw_type * type)40b843c749SSergey Zigachev psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *type)
41b843c749SSergey Zigachev {
42b843c749SSergey Zigachev switch(ucode->ucode_id) {
43b843c749SSergey Zigachev case AMDGPU_UCODE_ID_SDMA0:
44b843c749SSergey Zigachev *type = GFX_FW_TYPE_SDMA0;
45b843c749SSergey Zigachev break;
46b843c749SSergey Zigachev case AMDGPU_UCODE_ID_SDMA1:
47b843c749SSergey Zigachev *type = GFX_FW_TYPE_SDMA1;
48b843c749SSergey Zigachev break;
49b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_CE:
50b843c749SSergey Zigachev *type = GFX_FW_TYPE_CP_CE;
51b843c749SSergey Zigachev break;
52b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_PFP:
53b843c749SSergey Zigachev *type = GFX_FW_TYPE_CP_PFP;
54b843c749SSergey Zigachev break;
55b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_ME:
56b843c749SSergey Zigachev *type = GFX_FW_TYPE_CP_ME;
57b843c749SSergey Zigachev break;
58b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_MEC1:
59b843c749SSergey Zigachev *type = GFX_FW_TYPE_CP_MEC;
60b843c749SSergey Zigachev break;
61b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_MEC1_JT:
62b843c749SSergey Zigachev *type = GFX_FW_TYPE_CP_MEC_ME1;
63b843c749SSergey Zigachev break;
64b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_MEC2:
65b843c749SSergey Zigachev *type = GFX_FW_TYPE_CP_MEC;
66b843c749SSergey Zigachev break;
67b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_MEC2_JT:
68b843c749SSergey Zigachev *type = GFX_FW_TYPE_CP_MEC_ME2;
69b843c749SSergey Zigachev break;
70b843c749SSergey Zigachev case AMDGPU_UCODE_ID_RLC_G:
71b843c749SSergey Zigachev *type = GFX_FW_TYPE_RLC_G;
72b843c749SSergey Zigachev break;
73b843c749SSergey Zigachev case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
74b843c749SSergey Zigachev *type = GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL;
75b843c749SSergey Zigachev break;
76b843c749SSergey Zigachev case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
77b843c749SSergey Zigachev *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
78b843c749SSergey Zigachev break;
79b843c749SSergey Zigachev case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
80b843c749SSergey Zigachev *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
81b843c749SSergey Zigachev break;
82b843c749SSergey Zigachev case AMDGPU_UCODE_ID_SMC:
83b843c749SSergey Zigachev *type = GFX_FW_TYPE_SMU;
84b843c749SSergey Zigachev break;
85b843c749SSergey Zigachev case AMDGPU_UCODE_ID_UVD:
86b843c749SSergey Zigachev *type = GFX_FW_TYPE_UVD;
87b843c749SSergey Zigachev break;
88b843c749SSergey Zigachev case AMDGPU_UCODE_ID_VCE:
89b843c749SSergey Zigachev *type = GFX_FW_TYPE_VCE;
90b843c749SSergey Zigachev break;
91b843c749SSergey Zigachev case AMDGPU_UCODE_ID_VCN:
92b843c749SSergey Zigachev *type = GFX_FW_TYPE_VCN;
93b843c749SSergey Zigachev break;
94b843c749SSergey Zigachev case AMDGPU_UCODE_ID_MAXIMUM:
95b843c749SSergey Zigachev default:
96b843c749SSergey Zigachev return -EINVAL;
97b843c749SSergey Zigachev }
98b843c749SSergey Zigachev
99b843c749SSergey Zigachev return 0;
100b843c749SSergey Zigachev }
101b843c749SSergey Zigachev
psp_v10_0_init_microcode(struct psp_context * psp)102b843c749SSergey Zigachev static int psp_v10_0_init_microcode(struct psp_context *psp)
103b843c749SSergey Zigachev {
104b843c749SSergey Zigachev struct amdgpu_device *adev = psp->adev;
105b843c749SSergey Zigachev const char *chip_name;
106b843c749SSergey Zigachev char fw_name[30];
107b843c749SSergey Zigachev int err = 0;
108b843c749SSergey Zigachev const struct psp_firmware_header_v1_0 *hdr;
109b843c749SSergey Zigachev
110b843c749SSergey Zigachev DRM_DEBUG("\n");
111b843c749SSergey Zigachev
112b843c749SSergey Zigachev switch (adev->asic_type) {
113b843c749SSergey Zigachev case CHIP_RAVEN:
114b843c749SSergey Zigachev chip_name = "raven";
115b843c749SSergey Zigachev break;
116b843c749SSergey Zigachev default: BUG();
117b843c749SSergey Zigachev }
118b843c749SSergey Zigachev
119*809f3802SSergey Zigachev snprintf(fw_name, sizeof(fw_name), "amdgpufw_%s_asd", chip_name);
120b843c749SSergey Zigachev err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
121b843c749SSergey Zigachev if (err)
122b843c749SSergey Zigachev goto out;
123b843c749SSergey Zigachev
124b843c749SSergey Zigachev err = amdgpu_ucode_validate(adev->psp.asd_fw);
125b843c749SSergey Zigachev if (err)
126b843c749SSergey Zigachev goto out;
127b843c749SSergey Zigachev
128b843c749SSergey Zigachev hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
129b843c749SSergey Zigachev adev->psp.asd_fw_version = le32_to_cpu(hdr->header.ucode_version);
130b843c749SSergey Zigachev adev->psp.asd_feature_version = le32_to_cpu(hdr->ucode_feature_version);
131b843c749SSergey Zigachev adev->psp.asd_ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
132b843c749SSergey Zigachev adev->psp.asd_start_addr = (uint8_t *)hdr +
133b843c749SSergey Zigachev le32_to_cpu(hdr->header.ucode_array_offset_bytes);
134b843c749SSergey Zigachev
135b843c749SSergey Zigachev return 0;
136b843c749SSergey Zigachev out:
137b843c749SSergey Zigachev if (err) {
138b843c749SSergey Zigachev dev_err(adev->dev,
139b843c749SSergey Zigachev "psp v10.0: Failed to load firmware \"%s\"\n",
140b843c749SSergey Zigachev fw_name);
141b843c749SSergey Zigachev release_firmware(adev->psp.asd_fw);
142b843c749SSergey Zigachev adev->psp.asd_fw = NULL;
143b843c749SSergey Zigachev }
144b843c749SSergey Zigachev
145b843c749SSergey Zigachev return err;
146b843c749SSergey Zigachev }
147b843c749SSergey Zigachev
psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info * ucode,struct psp_gfx_cmd_resp * cmd)148b843c749SSergey Zigachev static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
149b843c749SSergey Zigachev struct psp_gfx_cmd_resp *cmd)
150b843c749SSergey Zigachev {
151b843c749SSergey Zigachev int ret;
152b843c749SSergey Zigachev uint64_t fw_mem_mc_addr = ucode->mc_addr;
153b843c749SSergey Zigachev
154b843c749SSergey Zigachev memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
155b843c749SSergey Zigachev
156b843c749SSergey Zigachev cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
157b843c749SSergey Zigachev cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
158b843c749SSergey Zigachev cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
159b843c749SSergey Zigachev cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
160b843c749SSergey Zigachev
161b843c749SSergey Zigachev ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
162b843c749SSergey Zigachev if (ret)
163b843c749SSergey Zigachev DRM_ERROR("Unknown firmware type\n");
164b843c749SSergey Zigachev
165b843c749SSergey Zigachev return ret;
166b843c749SSergey Zigachev }
167b843c749SSergey Zigachev
psp_v10_0_ring_init(struct psp_context * psp,enum psp_ring_type ring_type)168b843c749SSergey Zigachev static int psp_v10_0_ring_init(struct psp_context *psp,
169b843c749SSergey Zigachev enum psp_ring_type ring_type)
170b843c749SSergey Zigachev {
171b843c749SSergey Zigachev int ret = 0;
172b843c749SSergey Zigachev struct psp_ring *ring;
173b843c749SSergey Zigachev struct amdgpu_device *adev = psp->adev;
174b843c749SSergey Zigachev
175b843c749SSergey Zigachev ring = &psp->km_ring;
176b843c749SSergey Zigachev
177b843c749SSergey Zigachev ring->ring_type = ring_type;
178b843c749SSergey Zigachev
179b843c749SSergey Zigachev /* allocate 4k Page of Local Frame Buffer memory for ring */
180b843c749SSergey Zigachev ring->ring_size = 0x1000;
181b843c749SSergey Zigachev ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
182b843c749SSergey Zigachev AMDGPU_GEM_DOMAIN_VRAM,
183b843c749SSergey Zigachev &adev->firmware.rbuf,
18478973132SSergey Zigachev (u64 *)&ring->ring_mem_mc_addr,
185b843c749SSergey Zigachev (void **)&ring->ring_mem);
186b843c749SSergey Zigachev if (ret) {
187b843c749SSergey Zigachev ring->ring_size = 0;
188b843c749SSergey Zigachev return ret;
189b843c749SSergey Zigachev }
190b843c749SSergey Zigachev
191b843c749SSergey Zigachev return 0;
192b843c749SSergey Zigachev }
193b843c749SSergey Zigachev
psp_v10_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)194b843c749SSergey Zigachev static int psp_v10_0_ring_create(struct psp_context *psp,
195b843c749SSergey Zigachev enum psp_ring_type ring_type)
196b843c749SSergey Zigachev {
197b843c749SSergey Zigachev int ret = 0;
198b843c749SSergey Zigachev unsigned int psp_ring_reg = 0;
199b843c749SSergey Zigachev struct psp_ring *ring = &psp->km_ring;
200b843c749SSergey Zigachev struct amdgpu_device *adev = psp->adev;
201b843c749SSergey Zigachev
202b843c749SSergey Zigachev /* Write low address of the ring to C2PMSG_69 */
203b843c749SSergey Zigachev psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
204b843c749SSergey Zigachev WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
205b843c749SSergey Zigachev /* Write high address of the ring to C2PMSG_70 */
206b843c749SSergey Zigachev psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
207b843c749SSergey Zigachev WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
208b843c749SSergey Zigachev /* Write size of ring to C2PMSG_71 */
209b843c749SSergey Zigachev psp_ring_reg = ring->ring_size;
210b843c749SSergey Zigachev WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
211b843c749SSergey Zigachev /* Write the ring initialization command to C2PMSG_64 */
212b843c749SSergey Zigachev psp_ring_reg = ring_type;
213b843c749SSergey Zigachev psp_ring_reg = psp_ring_reg << 16;
214b843c749SSergey Zigachev WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
215b843c749SSergey Zigachev
216b843c749SSergey Zigachev /* There might be handshake issue with hardware which needs delay */
217b843c749SSergey Zigachev mdelay(20);
218b843c749SSergey Zigachev
219b843c749SSergey Zigachev /* Wait for response flag (bit 31) in C2PMSG_64 */
220b843c749SSergey Zigachev ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
221b843c749SSergey Zigachev 0x80000000, 0x8000FFFF, false);
222b843c749SSergey Zigachev
223b843c749SSergey Zigachev return ret;
224b843c749SSergey Zigachev }
225b843c749SSergey Zigachev
psp_v10_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)226b843c749SSergey Zigachev static int psp_v10_0_ring_stop(struct psp_context *psp,
227b843c749SSergey Zigachev enum psp_ring_type ring_type)
228b843c749SSergey Zigachev {
229b843c749SSergey Zigachev int ret = 0;
230b843c749SSergey Zigachev struct psp_ring *ring;
231b843c749SSergey Zigachev unsigned int psp_ring_reg = 0;
232b843c749SSergey Zigachev struct amdgpu_device *adev = psp->adev;
233b843c749SSergey Zigachev
234b843c749SSergey Zigachev ring = &psp->km_ring;
235b843c749SSergey Zigachev
236b843c749SSergey Zigachev /* Write the ring destroy command to C2PMSG_64 */
237b843c749SSergey Zigachev psp_ring_reg = 3 << 16;
238b843c749SSergey Zigachev WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
239b843c749SSergey Zigachev
240b843c749SSergey Zigachev /* There might be handshake issue with hardware which needs delay */
241b843c749SSergey Zigachev mdelay(20);
242b843c749SSergey Zigachev
243b843c749SSergey Zigachev /* Wait for response flag (bit 31) in C2PMSG_64 */
244b843c749SSergey Zigachev ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
245b843c749SSergey Zigachev 0x80000000, 0x80000000, false);
246b843c749SSergey Zigachev
247b843c749SSergey Zigachev return ret;
248b843c749SSergey Zigachev }
249b843c749SSergey Zigachev
psp_v10_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)250b843c749SSergey Zigachev static int psp_v10_0_ring_destroy(struct psp_context *psp,
251b843c749SSergey Zigachev enum psp_ring_type ring_type)
252b843c749SSergey Zigachev {
253b843c749SSergey Zigachev int ret = 0;
254b843c749SSergey Zigachev struct psp_ring *ring = &psp->km_ring;
255b843c749SSergey Zigachev struct amdgpu_device *adev = psp->adev;
256b843c749SSergey Zigachev
257b843c749SSergey Zigachev ret = psp_v10_0_ring_stop(psp, ring_type);
258b843c749SSergey Zigachev if (ret)
259b843c749SSergey Zigachev DRM_ERROR("Fail to stop psp ring\n");
260b843c749SSergey Zigachev
261b843c749SSergey Zigachev amdgpu_bo_free_kernel(&adev->firmware.rbuf,
26278973132SSergey Zigachev (u64 *)&ring->ring_mem_mc_addr,
263b843c749SSergey Zigachev (void **)&ring->ring_mem);
264b843c749SSergey Zigachev
265b843c749SSergey Zigachev return ret;
266b843c749SSergey Zigachev }
267b843c749SSergey Zigachev
psp_v10_0_cmd_submit(struct psp_context * psp,struct amdgpu_firmware_info * ucode,uint64_t cmd_buf_mc_addr,uint64_t fence_mc_addr,int index)268b843c749SSergey Zigachev static int psp_v10_0_cmd_submit(struct psp_context *psp,
269b843c749SSergey Zigachev struct amdgpu_firmware_info *ucode,
270b843c749SSergey Zigachev uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
271b843c749SSergey Zigachev int index)
272b843c749SSergey Zigachev {
273b843c749SSergey Zigachev unsigned int psp_write_ptr_reg = 0;
274b843c749SSergey Zigachev struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
275b843c749SSergey Zigachev struct psp_ring *ring = &psp->km_ring;
276b843c749SSergey Zigachev struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
277b843c749SSergey Zigachev struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
278b843c749SSergey Zigachev ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
279b843c749SSergey Zigachev struct amdgpu_device *adev = psp->adev;
280b843c749SSergey Zigachev uint32_t ring_size_dw = ring->ring_size / 4;
281b843c749SSergey Zigachev uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
282b843c749SSergey Zigachev
283b843c749SSergey Zigachev /* KM (GPCOM) prepare write pointer */
284b843c749SSergey Zigachev psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
285b843c749SSergey Zigachev
286b843c749SSergey Zigachev /* Update KM RB frame pointer to new frame */
287b843c749SSergey Zigachev if ((psp_write_ptr_reg % ring_size_dw) == 0)
288b843c749SSergey Zigachev write_frame = ring_buffer_start;
289b843c749SSergey Zigachev else
290b843c749SSergey Zigachev write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
291b843c749SSergey Zigachev /* Check invalid write_frame ptr address */
292b843c749SSergey Zigachev if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
293b843c749SSergey Zigachev DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
294b843c749SSergey Zigachev ring_buffer_start, ring_buffer_end, write_frame);
295b843c749SSergey Zigachev DRM_ERROR("write_frame is pointing to address out of bounds\n");
296b843c749SSergey Zigachev return -EINVAL;
297b843c749SSergey Zigachev }
298b843c749SSergey Zigachev
299b843c749SSergey Zigachev /* Initialize KM RB frame */
300b843c749SSergey Zigachev memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
301b843c749SSergey Zigachev
302b843c749SSergey Zigachev /* Update KM RB frame */
303b843c749SSergey Zigachev write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
304b843c749SSergey Zigachev write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
305b843c749SSergey Zigachev write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
306b843c749SSergey Zigachev write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
307b843c749SSergey Zigachev write_frame->fence_value = index;
308b843c749SSergey Zigachev
309b843c749SSergey Zigachev /* Update the write Pointer in DWORDs */
310b843c749SSergey Zigachev psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
311b843c749SSergey Zigachev WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
312b843c749SSergey Zigachev
313b843c749SSergey Zigachev return 0;
314b843c749SSergey Zigachev }
315b843c749SSergey Zigachev
316b843c749SSergey Zigachev static int
psp_v10_0_sram_map(struct amdgpu_device * adev,unsigned int * sram_offset,unsigned int * sram_addr_reg_offset,unsigned int * sram_data_reg_offset,enum AMDGPU_UCODE_ID ucode_id)317b843c749SSergey Zigachev psp_v10_0_sram_map(struct amdgpu_device *adev,
318b843c749SSergey Zigachev unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
319b843c749SSergey Zigachev unsigned int *sram_data_reg_offset,
320b843c749SSergey Zigachev enum AMDGPU_UCODE_ID ucode_id)
321b843c749SSergey Zigachev {
322b843c749SSergey Zigachev int ret = 0;
323b843c749SSergey Zigachev
324b843c749SSergey Zigachev switch(ucode_id) {
325b843c749SSergey Zigachev /* TODO: needs to confirm */
326b843c749SSergey Zigachev #if 0
327b843c749SSergey Zigachev case AMDGPU_UCODE_ID_SMC:
328b843c749SSergey Zigachev *sram_offset = 0;
329b843c749SSergey Zigachev *sram_addr_reg_offset = 0;
330b843c749SSergey Zigachev *sram_data_reg_offset = 0;
331b843c749SSergey Zigachev break;
332b843c749SSergey Zigachev #endif
333b843c749SSergey Zigachev
334b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_CE:
335b843c749SSergey Zigachev *sram_offset = 0x0;
336b843c749SSergey Zigachev *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_ADDR);
337b843c749SSergey Zigachev *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_CE_UCODE_DATA);
338b843c749SSergey Zigachev break;
339b843c749SSergey Zigachev
340b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_PFP:
341b843c749SSergey Zigachev *sram_offset = 0x0;
342b843c749SSergey Zigachev *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_ADDR);
343b843c749SSergey Zigachev *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_PFP_UCODE_DATA);
344b843c749SSergey Zigachev break;
345b843c749SSergey Zigachev
346b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_ME:
347b843c749SSergey Zigachev *sram_offset = 0x0;
348b843c749SSergey Zigachev *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_ADDR);
349b843c749SSergey Zigachev *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_ME_UCODE_DATA);
350b843c749SSergey Zigachev break;
351b843c749SSergey Zigachev
352b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_MEC1:
353b843c749SSergey Zigachev *sram_offset = 0x10000;
354b843c749SSergey Zigachev *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_ADDR);
355b843c749SSergey Zigachev *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_MEC_ME1_UCODE_DATA);
356b843c749SSergey Zigachev break;
357b843c749SSergey Zigachev
358b843c749SSergey Zigachev case AMDGPU_UCODE_ID_CP_MEC2:
359b843c749SSergey Zigachev *sram_offset = 0x10000;
360b843c749SSergey Zigachev *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_ADDR);
361b843c749SSergey Zigachev *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_HYP_MEC2_UCODE_DATA);
362b843c749SSergey Zigachev break;
363b843c749SSergey Zigachev
364b843c749SSergey Zigachev case AMDGPU_UCODE_ID_RLC_G:
365b843c749SSergey Zigachev *sram_offset = 0x2000;
366b843c749SSergey Zigachev *sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
367b843c749SSergey Zigachev *sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
368b843c749SSergey Zigachev break;
369b843c749SSergey Zigachev
370b843c749SSergey Zigachev case AMDGPU_UCODE_ID_SDMA0:
371b843c749SSergey Zigachev *sram_offset = 0x0;
372b843c749SSergey Zigachev *sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
373b843c749SSergey Zigachev *sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
374b843c749SSergey Zigachev break;
375b843c749SSergey Zigachev
376b843c749SSergey Zigachev /* TODO: needs to confirm */
377b843c749SSergey Zigachev #if 0
378b843c749SSergey Zigachev case AMDGPU_UCODE_ID_SDMA1:
379b843c749SSergey Zigachev *sram_offset = ;
380b843c749SSergey Zigachev *sram_addr_reg_offset = ;
381b843c749SSergey Zigachev break;
382b843c749SSergey Zigachev
383b843c749SSergey Zigachev case AMDGPU_UCODE_ID_UVD:
384b843c749SSergey Zigachev *sram_offset = ;
385b843c749SSergey Zigachev *sram_addr_reg_offset = ;
386b843c749SSergey Zigachev break;
387b843c749SSergey Zigachev
388b843c749SSergey Zigachev case AMDGPU_UCODE_ID_VCE:
389b843c749SSergey Zigachev *sram_offset = ;
390b843c749SSergey Zigachev *sram_addr_reg_offset = ;
391b843c749SSergey Zigachev break;
392b843c749SSergey Zigachev #endif
393b843c749SSergey Zigachev
394b843c749SSergey Zigachev case AMDGPU_UCODE_ID_MAXIMUM:
395b843c749SSergey Zigachev default:
396b843c749SSergey Zigachev ret = -EINVAL;
397b843c749SSergey Zigachev break;
398b843c749SSergey Zigachev }
399b843c749SSergey Zigachev
400b843c749SSergey Zigachev return ret;
401b843c749SSergey Zigachev }
402b843c749SSergey Zigachev
psp_v10_0_compare_sram_data(struct psp_context * psp,struct amdgpu_firmware_info * ucode,enum AMDGPU_UCODE_ID ucode_type)403b843c749SSergey Zigachev static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
404b843c749SSergey Zigachev struct amdgpu_firmware_info *ucode,
405b843c749SSergey Zigachev enum AMDGPU_UCODE_ID ucode_type)
406b843c749SSergey Zigachev {
407b843c749SSergey Zigachev int err = 0;
408b843c749SSergey Zigachev unsigned int fw_sram_reg_val = 0;
409b843c749SSergey Zigachev unsigned int fw_sram_addr_reg_offset = 0;
410b843c749SSergey Zigachev unsigned int fw_sram_data_reg_offset = 0;
411b843c749SSergey Zigachev unsigned int ucode_size;
412b843c749SSergey Zigachev uint32_t *ucode_mem = NULL;
413b843c749SSergey Zigachev struct amdgpu_device *adev = psp->adev;
414b843c749SSergey Zigachev
415b843c749SSergey Zigachev err = psp_v10_0_sram_map(adev, &fw_sram_reg_val, &fw_sram_addr_reg_offset,
416b843c749SSergey Zigachev &fw_sram_data_reg_offset, ucode_type);
417b843c749SSergey Zigachev if (err)
418b843c749SSergey Zigachev return false;
419b843c749SSergey Zigachev
420b843c749SSergey Zigachev WREG32(fw_sram_addr_reg_offset, fw_sram_reg_val);
421b843c749SSergey Zigachev
422b843c749SSergey Zigachev ucode_size = ucode->ucode_size;
423b843c749SSergey Zigachev ucode_mem = (uint32_t *)ucode->kaddr;
424b843c749SSergey Zigachev while (!ucode_size) {
425b843c749SSergey Zigachev fw_sram_reg_val = RREG32(fw_sram_data_reg_offset);
426b843c749SSergey Zigachev
427b843c749SSergey Zigachev if (*ucode_mem != fw_sram_reg_val)
428b843c749SSergey Zigachev return false;
429b843c749SSergey Zigachev
430b843c749SSergey Zigachev ucode_mem++;
431b843c749SSergey Zigachev /* 4 bytes */
432b843c749SSergey Zigachev ucode_size -= 4;
433b843c749SSergey Zigachev }
434b843c749SSergey Zigachev
435b843c749SSergey Zigachev return true;
436b843c749SSergey Zigachev }
437b843c749SSergey Zigachev
438b843c749SSergey Zigachev
psp_v10_0_mode1_reset(struct psp_context * psp)439b843c749SSergey Zigachev static int psp_v10_0_mode1_reset(struct psp_context *psp)
440b843c749SSergey Zigachev {
441b843c749SSergey Zigachev DRM_INFO("psp mode 1 reset not supported now! \n");
442b843c749SSergey Zigachev return -EINVAL;
443b843c749SSergey Zigachev }
444b843c749SSergey Zigachev
445b843c749SSergey Zigachev static const struct psp_funcs psp_v10_0_funcs = {
446b843c749SSergey Zigachev .init_microcode = psp_v10_0_init_microcode,
447b843c749SSergey Zigachev .prep_cmd_buf = psp_v10_0_prep_cmd_buf,
448b843c749SSergey Zigachev .ring_init = psp_v10_0_ring_init,
449b843c749SSergey Zigachev .ring_create = psp_v10_0_ring_create,
450b843c749SSergey Zigachev .ring_stop = psp_v10_0_ring_stop,
451b843c749SSergey Zigachev .ring_destroy = psp_v10_0_ring_destroy,
452b843c749SSergey Zigachev .cmd_submit = psp_v10_0_cmd_submit,
453b843c749SSergey Zigachev .compare_sram_data = psp_v10_0_compare_sram_data,
454b843c749SSergey Zigachev .mode1_reset = psp_v10_0_mode1_reset,
455b843c749SSergey Zigachev };
456b843c749SSergey Zigachev
psp_v10_0_set_psp_funcs(struct psp_context * psp)457b843c749SSergey Zigachev void psp_v10_0_set_psp_funcs(struct psp_context *psp)
458b843c749SSergey Zigachev {
459b843c749SSergey Zigachev psp->funcs = &psp_v10_0_funcs;
460b843c749SSergey Zigachev }
461