1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef __AMDGPU_VCN_H__ 25*b843c749SSergey Zigachev #define __AMDGPU_VCN_H__ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #define AMDGPU_VCN_STACK_SIZE (200*1024) 28*b843c749SSergey Zigachev #define AMDGPU_VCN_HEAP_SIZE (256*1024) 29*b843c749SSergey Zigachev #define AMDGPU_VCN_SESSION_SIZE (50*1024) 30*b843c749SSergey Zigachev #define AMDGPU_VCN_FIRMWARE_OFFSET 256 31*b843c749SSergey Zigachev #define AMDGPU_VCN_MAX_ENC_RINGS 3 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev #define VCN_DEC_CMD_FENCE 0x00000000 34*b843c749SSergey Zigachev #define VCN_DEC_CMD_TRAP 0x00000001 35*b843c749SSergey Zigachev #define VCN_DEC_CMD_WRITE_REG 0x00000004 36*b843c749SSergey Zigachev #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006 37*b843c749SSergey Zigachev #define VCN_DEC_CMD_PACKET_START 0x0000000a 38*b843c749SSergey Zigachev #define VCN_DEC_CMD_PACKET_END 0x0000000b 39*b843c749SSergey Zigachev 40*b843c749SSergey Zigachev #define VCN_ENC_CMD_NO_OP 0x00000000 41*b843c749SSergey Zigachev #define VCN_ENC_CMD_END 0x00000001 42*b843c749SSergey Zigachev #define VCN_ENC_CMD_IB 0x00000002 43*b843c749SSergey Zigachev #define VCN_ENC_CMD_FENCE 0x00000003 44*b843c749SSergey Zigachev #define VCN_ENC_CMD_TRAP 0x00000004 45*b843c749SSergey Zigachev #define VCN_ENC_CMD_REG_WRITE 0x0000000b 46*b843c749SSergey Zigachev #define VCN_ENC_CMD_REG_WAIT 0x0000000c 47*b843c749SSergey Zigachev 48*b843c749SSergey Zigachev enum engine_status_constants { 49*b843c749SSergey Zigachev UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, 50*b843c749SSergey Zigachev UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON = 0x00000002, 51*b843c749SSergey Zigachev UVD_STATUS__UVD_BUSY = 0x00000004, 52*b843c749SSergey Zigachev GB_ADDR_CONFIG_DEFAULT = 0x26010011, 53*b843c749SSergey Zigachev UVD_STATUS__IDLE = 0x2, 54*b843c749SSergey Zigachev UVD_STATUS__BUSY = 0x5, 55*b843c749SSergey Zigachev UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF = 0x1, 56*b843c749SSergey Zigachev UVD_STATUS__RBC_BUSY = 0x1, 57*b843c749SSergey Zigachev }; 58*b843c749SSergey Zigachev 59*b843c749SSergey Zigachev struct amdgpu_vcn { 60*b843c749SSergey Zigachev struct amdgpu_bo *vcpu_bo; 61*b843c749SSergey Zigachev void *cpu_addr; 62*b843c749SSergey Zigachev uint64_t gpu_addr; 63*b843c749SSergey Zigachev unsigned fw_version; 64*b843c749SSergey Zigachev void *saved_bo; 65*b843c749SSergey Zigachev struct delayed_work idle_work; 66*b843c749SSergey Zigachev const struct firmware *fw; /* VCN firmware */ 67*b843c749SSergey Zigachev struct amdgpu_ring ring_dec; 68*b843c749SSergey Zigachev struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; 69*b843c749SSergey Zigachev struct amdgpu_ring ring_jpeg; 70*b843c749SSergey Zigachev struct amdgpu_irq_src irq; 71*b843c749SSergey Zigachev unsigned num_enc_rings; 72*b843c749SSergey Zigachev }; 73*b843c749SSergey Zigachev 74*b843c749SSergey Zigachev int amdgpu_vcn_sw_init(struct amdgpu_device *adev); 75*b843c749SSergey Zigachev int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); 76*b843c749SSergey Zigachev int amdgpu_vcn_suspend(struct amdgpu_device *adev); 77*b843c749SSergey Zigachev int amdgpu_vcn_resume(struct amdgpu_device *adev); 78*b843c749SSergey Zigachev void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring); 79*b843c749SSergey Zigachev void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring); 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring); 82*b843c749SSergey Zigachev int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout); 83*b843c749SSergey Zigachev 84*b843c749SSergey Zigachev int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring); 85*b843c749SSergey Zigachev int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout); 86*b843c749SSergey Zigachev 87*b843c749SSergey Zigachev int amdgpu_vcn_jpeg_ring_test_ring(struct amdgpu_ring *ring); 88*b843c749SSergey Zigachev int amdgpu_vcn_jpeg_ring_test_ib(struct amdgpu_ring *ring, long timeout); 89*b843c749SSergey Zigachev 90*b843c749SSergey Zigachev #endif 91