1b843c749SSergey Zigachev /* 2b843c749SSergey Zigachev * Copyright 2014 Advanced Micro Devices, Inc. 3b843c749SSergey Zigachev * 4b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10b843c749SSergey Zigachev * 11b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13b843c749SSergey Zigachev * 14b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21b843c749SSergey Zigachev * 22b843c749SSergey Zigachev */ 23b843c749SSergey Zigachev 24b843c749SSergey Zigachev #ifndef __AMDGPU_VCE_H__ 25b843c749SSergey Zigachev #define __AMDGPU_VCE_H__ 26b843c749SSergey Zigachev 27b843c749SSergey Zigachev #define AMDGPU_MAX_VCE_HANDLES 16 28b843c749SSergey Zigachev #define AMDGPU_VCE_FIRMWARE_OFFSET 256 29b843c749SSergey Zigachev 30b843c749SSergey Zigachev #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 31b843c749SSergey Zigachev #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 32b843c749SSergey Zigachev 33b843c749SSergey Zigachev #define AMDGPU_VCE_FW_53_45 ((53 << 24) | (45 << 16)) 34b843c749SSergey Zigachev 35b843c749SSergey Zigachev struct amdgpu_vce { 36b843c749SSergey Zigachev struct amdgpu_bo *vcpu_bo; 37b843c749SSergey Zigachev uint64_t gpu_addr; 38b843c749SSergey Zigachev void *cpu_addr; 39b843c749SSergey Zigachev void *saved_bo; 40b843c749SSergey Zigachev unsigned fw_version; 41b843c749SSergey Zigachev unsigned fb_version; 42b843c749SSergey Zigachev atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 43b843c749SSergey Zigachev struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 44b843c749SSergey Zigachev uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 45b843c749SSergey Zigachev struct delayed_work idle_work; 46*78973132SSergey Zigachev struct lock idle_mutex; 47b843c749SSergey Zigachev const struct firmware *fw; /* VCE firmware */ 48b843c749SSergey Zigachev struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 49b843c749SSergey Zigachev struct amdgpu_irq_src irq; 50b843c749SSergey Zigachev unsigned harvest_config; 51b843c749SSergey Zigachev struct drm_sched_entity entity; 52b843c749SSergey Zigachev uint32_t srbm_soft_reset; 53b843c749SSergey Zigachev unsigned num_rings; 54b843c749SSergey Zigachev }; 55b843c749SSergey Zigachev 56b843c749SSergey Zigachev int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size); 57b843c749SSergey Zigachev int amdgpu_vce_sw_fini(struct amdgpu_device *adev); 58b843c749SSergey Zigachev int amdgpu_vce_entity_init(struct amdgpu_device *adev); 59b843c749SSergey Zigachev int amdgpu_vce_suspend(struct amdgpu_device *adev); 60b843c749SSergey Zigachev int amdgpu_vce_resume(struct amdgpu_device *adev); 61b843c749SSergey Zigachev int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 62b843c749SSergey Zigachev struct dma_fence **fence); 63b843c749SSergey Zigachev int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 64b843c749SSergey Zigachev bool direct, struct dma_fence **fence); 65b843c749SSergey Zigachev void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); 66b843c749SSergey Zigachev int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); 67b843c749SSergey Zigachev int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx); 68b843c749SSergey Zigachev void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib, 69b843c749SSergey Zigachev unsigned vmid, bool ctx_switch); 70*78973132SSergey Zigachev void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr, uint64_t seq, 71b843c749SSergey Zigachev unsigned flags); 72b843c749SSergey Zigachev int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring); 73b843c749SSergey Zigachev int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout); 74b843c749SSergey Zigachev void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring); 75b843c749SSergey Zigachev void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring); 76b843c749SSergey Zigachev unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring); 77b843c749SSergey Zigachev unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring); 78b843c749SSergey Zigachev 79b843c749SSergey Zigachev #endif 80