1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2017 Valve Corporation 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: Andres Rodriguez <andresx7@gmail.com> 23*b843c749SSergey Zigachev */ 24*b843c749SSergey Zigachev 25*b843c749SSergey Zigachev #include <linux/fdtable.h> 26*b843c749SSergey Zigachev #include <linux/pid.h> 27*b843c749SSergey Zigachev #include <drm/amdgpu_drm.h> 28*b843c749SSergey Zigachev #include "amdgpu.h" 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #include "amdgpu_vm.h" 31*b843c749SSergey Zigachev 32*b843c749SSergey Zigachev enum drm_sched_priority amdgpu_to_sched_priority(int amdgpu_priority) 33*b843c749SSergey Zigachev { 34*b843c749SSergey Zigachev switch (amdgpu_priority) { 35*b843c749SSergey Zigachev case AMDGPU_CTX_PRIORITY_VERY_HIGH: 36*b843c749SSergey Zigachev return DRM_SCHED_PRIORITY_HIGH_HW; 37*b843c749SSergey Zigachev case AMDGPU_CTX_PRIORITY_HIGH: 38*b843c749SSergey Zigachev return DRM_SCHED_PRIORITY_HIGH_SW; 39*b843c749SSergey Zigachev case AMDGPU_CTX_PRIORITY_NORMAL: 40*b843c749SSergey Zigachev return DRM_SCHED_PRIORITY_NORMAL; 41*b843c749SSergey Zigachev case AMDGPU_CTX_PRIORITY_LOW: 42*b843c749SSergey Zigachev case AMDGPU_CTX_PRIORITY_VERY_LOW: 43*b843c749SSergey Zigachev return DRM_SCHED_PRIORITY_LOW; 44*b843c749SSergey Zigachev case AMDGPU_CTX_PRIORITY_UNSET: 45*b843c749SSergey Zigachev return DRM_SCHED_PRIORITY_UNSET; 46*b843c749SSergey Zigachev default: 47*b843c749SSergey Zigachev WARN(1, "Invalid context priority %d\n", amdgpu_priority); 48*b843c749SSergey Zigachev return DRM_SCHED_PRIORITY_INVALID; 49*b843c749SSergey Zigachev } 50*b843c749SSergey Zigachev } 51*b843c749SSergey Zigachev 52*b843c749SSergey Zigachev static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, 53*b843c749SSergey Zigachev int fd, 54*b843c749SSergey Zigachev enum drm_sched_priority priority) 55*b843c749SSergey Zigachev { 56*b843c749SSergey Zigachev struct file *filp = fget(fd); 57*b843c749SSergey Zigachev struct drm_file *file; 58*b843c749SSergey Zigachev struct amdgpu_fpriv *fpriv; 59*b843c749SSergey Zigachev struct amdgpu_ctx *ctx; 60*b843c749SSergey Zigachev uint32_t id; 61*b843c749SSergey Zigachev 62*b843c749SSergey Zigachev if (!filp) 63*b843c749SSergey Zigachev return -EINVAL; 64*b843c749SSergey Zigachev 65*b843c749SSergey Zigachev file = filp->private_data; 66*b843c749SSergey Zigachev fpriv = file->driver_priv; 67*b843c749SSergey Zigachev idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) 68*b843c749SSergey Zigachev amdgpu_ctx_priority_override(ctx, priority); 69*b843c749SSergey Zigachev 70*b843c749SSergey Zigachev fput(filp); 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev return 0; 73*b843c749SSergey Zigachev } 74*b843c749SSergey Zigachev 75*b843c749SSergey Zigachev int amdgpu_sched_ioctl(struct drm_device *dev, void *data, 76*b843c749SSergey Zigachev struct drm_file *filp) 77*b843c749SSergey Zigachev { 78*b843c749SSergey Zigachev union drm_amdgpu_sched *args = data; 79*b843c749SSergey Zigachev struct amdgpu_device *adev = dev->dev_private; 80*b843c749SSergey Zigachev enum drm_sched_priority priority; 81*b843c749SSergey Zigachev int r; 82*b843c749SSergey Zigachev 83*b843c749SSergey Zigachev priority = amdgpu_to_sched_priority(args->in.priority); 84*b843c749SSergey Zigachev if (args->in.flags || priority == DRM_SCHED_PRIORITY_INVALID) 85*b843c749SSergey Zigachev return -EINVAL; 86*b843c749SSergey Zigachev 87*b843c749SSergey Zigachev switch (args->in.op) { 88*b843c749SSergey Zigachev case AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE: 89*b843c749SSergey Zigachev r = amdgpu_sched_process_priority_override(adev, 90*b843c749SSergey Zigachev args->in.fd, 91*b843c749SSergey Zigachev priority); 92*b843c749SSergey Zigachev break; 93*b843c749SSergey Zigachev default: 94*b843c749SSergey Zigachev DRM_ERROR("Invalid sched op specified: %d\n", args->in.op); 95*b843c749SSergey Zigachev r = -EINVAL; 96*b843c749SSergey Zigachev break; 97*b843c749SSergey Zigachev } 98*b843c749SSergey Zigachev 99*b843c749SSergey Zigachev return r; 100*b843c749SSergey Zigachev } 101