1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Author: Huang Rui 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev #ifndef __AMDGPU_PSP_H__ 26*b843c749SSergey Zigachev #define __AMDGPU_PSP_H__ 27*b843c749SSergey Zigachev 28*b843c749SSergey Zigachev #include "amdgpu.h" 29*b843c749SSergey Zigachev #include "psp_gfx_if.h" 30*b843c749SSergey Zigachev 31*b843c749SSergey Zigachev #define PSP_FENCE_BUFFER_SIZE 0x1000 32*b843c749SSergey Zigachev #define PSP_CMD_BUFFER_SIZE 0x1000 33*b843c749SSergey Zigachev #define PSP_ASD_SHARED_MEM_SIZE 0x4000 34*b843c749SSergey Zigachev #define PSP_1_MEG 0x100000 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev struct psp_context; 37*b843c749SSergey Zigachev 38*b843c749SSergey Zigachev enum psp_ring_type 39*b843c749SSergey Zigachev { 40*b843c749SSergey Zigachev PSP_RING_TYPE__INVALID = 0, 41*b843c749SSergey Zigachev /* 42*b843c749SSergey Zigachev * These values map to the way the PSP kernel identifies the 43*b843c749SSergey Zigachev * rings. 44*b843c749SSergey Zigachev */ 45*b843c749SSergey Zigachev PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 46*b843c749SSergey Zigachev PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 47*b843c749SSergey Zigachev }; 48*b843c749SSergey Zigachev 49*b843c749SSergey Zigachev struct psp_ring 50*b843c749SSergey Zigachev { 51*b843c749SSergey Zigachev enum psp_ring_type ring_type; 52*b843c749SSergey Zigachev struct psp_gfx_rb_frame *ring_mem; 53*b843c749SSergey Zigachev uint64_t ring_mem_mc_addr; 54*b843c749SSergey Zigachev void *ring_mem_handle; 55*b843c749SSergey Zigachev uint32_t ring_size; 56*b843c749SSergey Zigachev }; 57*b843c749SSergey Zigachev 58*b843c749SSergey Zigachev struct psp_funcs 59*b843c749SSergey Zigachev { 60*b843c749SSergey Zigachev int (*init_microcode)(struct psp_context *psp); 61*b843c749SSergey Zigachev int (*bootloader_load_sysdrv)(struct psp_context *psp); 62*b843c749SSergey Zigachev int (*bootloader_load_sos)(struct psp_context *psp); 63*b843c749SSergey Zigachev int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode, 64*b843c749SSergey Zigachev struct psp_gfx_cmd_resp *cmd); 65*b843c749SSergey Zigachev int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 66*b843c749SSergey Zigachev int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type); 67*b843c749SSergey Zigachev int (*ring_stop)(struct psp_context *psp, 68*b843c749SSergey Zigachev enum psp_ring_type ring_type); 69*b843c749SSergey Zigachev int (*ring_destroy)(struct psp_context *psp, 70*b843c749SSergey Zigachev enum psp_ring_type ring_type); 71*b843c749SSergey Zigachev int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode, 72*b843c749SSergey Zigachev uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index); 73*b843c749SSergey Zigachev bool (*compare_sram_data)(struct psp_context *psp, 74*b843c749SSergey Zigachev struct amdgpu_firmware_info *ucode, 75*b843c749SSergey Zigachev enum AMDGPU_UCODE_ID ucode_type); 76*b843c749SSergey Zigachev bool (*smu_reload_quirk)(struct psp_context *psp); 77*b843c749SSergey Zigachev int (*mode1_reset)(struct psp_context *psp); 78*b843c749SSergey Zigachev }; 79*b843c749SSergey Zigachev 80*b843c749SSergey Zigachev struct psp_context 81*b843c749SSergey Zigachev { 82*b843c749SSergey Zigachev struct amdgpu_device *adev; 83*b843c749SSergey Zigachev struct psp_ring km_ring; 84*b843c749SSergey Zigachev struct psp_gfx_cmd_resp *cmd; 85*b843c749SSergey Zigachev 86*b843c749SSergey Zigachev const struct psp_funcs *funcs; 87*b843c749SSergey Zigachev 88*b843c749SSergey Zigachev /* fence buffer */ 89*b843c749SSergey Zigachev struct amdgpu_bo *fw_pri_bo; 90*b843c749SSergey Zigachev uint64_t fw_pri_mc_addr; 91*b843c749SSergey Zigachev void *fw_pri_buf; 92*b843c749SSergey Zigachev 93*b843c749SSergey Zigachev /* sos firmware */ 94*b843c749SSergey Zigachev const struct firmware *sos_fw; 95*b843c749SSergey Zigachev uint32_t sos_fw_version; 96*b843c749SSergey Zigachev uint32_t sos_feature_version; 97*b843c749SSergey Zigachev uint32_t sys_bin_size; 98*b843c749SSergey Zigachev uint32_t sos_bin_size; 99*b843c749SSergey Zigachev uint8_t *sys_start_addr; 100*b843c749SSergey Zigachev uint8_t *sos_start_addr; 101*b843c749SSergey Zigachev 102*b843c749SSergey Zigachev /* tmr buffer */ 103*b843c749SSergey Zigachev struct amdgpu_bo *tmr_bo; 104*b843c749SSergey Zigachev uint64_t tmr_mc_addr; 105*b843c749SSergey Zigachev void *tmr_buf; 106*b843c749SSergey Zigachev 107*b843c749SSergey Zigachev /* asd firmware and buffer */ 108*b843c749SSergey Zigachev const struct firmware *asd_fw; 109*b843c749SSergey Zigachev uint32_t asd_fw_version; 110*b843c749SSergey Zigachev uint32_t asd_feature_version; 111*b843c749SSergey Zigachev uint32_t asd_ucode_size; 112*b843c749SSergey Zigachev uint8_t *asd_start_addr; 113*b843c749SSergey Zigachev struct amdgpu_bo *asd_shared_bo; 114*b843c749SSergey Zigachev uint64_t asd_shared_mc_addr; 115*b843c749SSergey Zigachev void *asd_shared_buf; 116*b843c749SSergey Zigachev 117*b843c749SSergey Zigachev /* fence buffer */ 118*b843c749SSergey Zigachev struct amdgpu_bo *fence_buf_bo; 119*b843c749SSergey Zigachev uint64_t fence_buf_mc_addr; 120*b843c749SSergey Zigachev void *fence_buf; 121*b843c749SSergey Zigachev 122*b843c749SSergey Zigachev /* cmd buffer */ 123*b843c749SSergey Zigachev struct amdgpu_bo *cmd_buf_bo; 124*b843c749SSergey Zigachev uint64_t cmd_buf_mc_addr; 125*b843c749SSergey Zigachev struct psp_gfx_cmd_resp *cmd_buf_mem; 126*b843c749SSergey Zigachev }; 127*b843c749SSergey Zigachev 128*b843c749SSergey Zigachev struct amdgpu_psp_funcs { 129*b843c749SSergey Zigachev bool (*check_fw_loading_status)(struct amdgpu_device *adev, 130*b843c749SSergey Zigachev enum AMDGPU_UCODE_ID); 131*b843c749SSergey Zigachev }; 132*b843c749SSergey Zigachev 133*b843c749SSergey Zigachev #define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type)) 134*b843c749SSergey Zigachev #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 135*b843c749SSergey Zigachev #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 136*b843c749SSergey Zigachev #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 137*b843c749SSergey Zigachev #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 138*b843c749SSergey Zigachev #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ 139*b843c749SSergey Zigachev (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) 140*b843c749SSergey Zigachev #define psp_compare_sram_data(psp, ucode, type) \ 141*b843c749SSergey Zigachev (psp)->funcs->compare_sram_data((psp), (ucode), (type)) 142*b843c749SSergey Zigachev #define psp_init_microcode(psp) \ 143*b843c749SSergey Zigachev ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 144*b843c749SSergey Zigachev #define psp_bootloader_load_sysdrv(psp) \ 145*b843c749SSergey Zigachev ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 146*b843c749SSergey Zigachev #define psp_bootloader_load_sos(psp) \ 147*b843c749SSergey Zigachev ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 148*b843c749SSergey Zigachev #define psp_smu_reload_quirk(psp) \ 149*b843c749SSergey Zigachev ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 150*b843c749SSergey Zigachev #define psp_mode1_reset(psp) \ 151*b843c749SSergey Zigachev ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 152*b843c749SSergey Zigachev 153*b843c749SSergey Zigachev extern const struct amd_ip_funcs psp_ip_funcs; 154*b843c749SSergey Zigachev 155*b843c749SSergey Zigachev extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 156*b843c749SSergey Zigachev extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 157*b843c749SSergey Zigachev uint32_t field_val, uint32_t mask, bool check_changed); 158*b843c749SSergey Zigachev 159*b843c749SSergey Zigachev extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 160*b843c749SSergey Zigachev 161*b843c749SSergey Zigachev int psp_gpu_reset(struct amdgpu_device *adev); 162*b843c749SSergey Zigachev 163*b843c749SSergey Zigachev #endif 164