1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Rafał Miłecki <zajec5@gmail.com> 23 * Alex Deucher <alexdeucher@gmail.com> 24 */ 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_drv.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_dpm.h" 30 #include "atom.h" 31 #include <linux/power_supply.h> 32 #include <linux/hwmon.h> 33 #include <linux/hwmon-sysfs.h> 34 #include <linux/nospec.h> 35 36 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev); 37 38 static const struct cg_flag_name clocks[] = { 39 {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"}, 40 {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"}, 41 {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"}, 42 {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"}, 43 {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"}, 44 {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"}, 45 {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"}, 46 {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"}, 47 {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"}, 48 {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"}, 49 {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"}, 50 {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"}, 51 {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"}, 52 {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"}, 53 {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"}, 54 {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"}, 55 {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"}, 56 {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"}, 57 {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"}, 58 {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"}, 59 {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"}, 60 {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"}, 61 {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"}, 62 {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"}, 63 {0, NULL}, 64 }; 65 66 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) 67 { 68 if (adev->pm.dpm_enabled) { 69 mutex_lock(&adev->pm.mutex); 70 if (power_supply_is_system_supplied() > 0) 71 adev->pm.ac_power = true; 72 else 73 adev->pm.ac_power = false; 74 if (adev->powerplay.pp_funcs && 75 adev->powerplay.pp_funcs->enable_bapm) 76 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); 77 mutex_unlock(&adev->pm.mutex); 78 } 79 } 80 81 /** 82 * DOC: power_dpm_state 83 * 84 * The power_dpm_state file is a legacy interface and is only provided for 85 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting 86 * certain power related parameters. The file power_dpm_state is used for this. 87 * It accepts the following arguments: 88 * 89 * - battery 90 * 91 * - balanced 92 * 93 * - performance 94 * 95 * battery 96 * 97 * On older GPUs, the vbios provided a special power state for battery 98 * operation. Selecting battery switched to this state. This is no 99 * longer provided on newer GPUs so the option does nothing in that case. 100 * 101 * balanced 102 * 103 * On older GPUs, the vbios provided a special power state for balanced 104 * operation. Selecting balanced switched to this state. This is no 105 * longer provided on newer GPUs so the option does nothing in that case. 106 * 107 * performance 108 * 109 * On older GPUs, the vbios provided a special power state for performance 110 * operation. Selecting performance switched to this state. This is no 111 * longer provided on newer GPUs so the option does nothing in that case. 112 * 113 */ 114 115 static ssize_t amdgpu_get_dpm_state(struct device *dev, 116 struct device_attribute *attr, 117 char *buf) 118 { 119 struct drm_device *ddev = dev_get_drvdata(dev); 120 struct amdgpu_device *adev = ddev->dev_private; 121 enum amd_pm_state_type pm; 122 123 if (adev->powerplay.pp_funcs->get_current_power_state) 124 pm = amdgpu_dpm_get_current_power_state(adev); 125 else 126 pm = adev->pm.dpm.user_state; 127 128 return snprintf(buf, PAGE_SIZE, "%s\n", 129 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 130 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 131 } 132 133 static ssize_t amdgpu_set_dpm_state(struct device *dev, 134 struct device_attribute *attr, 135 const char *buf, 136 size_t count) 137 { 138 struct drm_device *ddev = dev_get_drvdata(dev); 139 struct amdgpu_device *adev = ddev->dev_private; 140 enum amd_pm_state_type state; 141 142 if (strncmp("battery", buf, strlen("battery")) == 0) 143 state = POWER_STATE_TYPE_BATTERY; 144 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 145 state = POWER_STATE_TYPE_BALANCED; 146 else if (strncmp("performance", buf, strlen("performance")) == 0) 147 state = POWER_STATE_TYPE_PERFORMANCE; 148 else { 149 count = -EINVAL; 150 goto fail; 151 } 152 153 if (adev->powerplay.pp_funcs->dispatch_tasks) { 154 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state); 155 } else { 156 mutex_lock(&adev->pm.mutex); 157 adev->pm.dpm.user_state = state; 158 mutex_unlock(&adev->pm.mutex); 159 160 /* Can't set dpm state when the card is off */ 161 if (!(adev->flags & AMD_IS_PX) || 162 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 163 amdgpu_pm_compute_clocks(adev); 164 } 165 fail: 166 return count; 167 } 168 169 170 /** 171 * DOC: power_dpm_force_performance_level 172 * 173 * The amdgpu driver provides a sysfs API for adjusting certain power 174 * related parameters. The file power_dpm_force_performance_level is 175 * used for this. It accepts the following arguments: 176 * 177 * - auto 178 * 179 * - low 180 * 181 * - high 182 * 183 * - manual 184 * 185 * - profile_standard 186 * 187 * - profile_min_sclk 188 * 189 * - profile_min_mclk 190 * 191 * - profile_peak 192 * 193 * auto 194 * 195 * When auto is selected, the driver will attempt to dynamically select 196 * the optimal power profile for current conditions in the driver. 197 * 198 * low 199 * 200 * When low is selected, the clocks are forced to the lowest power state. 201 * 202 * high 203 * 204 * When high is selected, the clocks are forced to the highest power state. 205 * 206 * manual 207 * 208 * When manual is selected, the user can manually adjust which power states 209 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk, 210 * and pp_dpm_pcie files and adjust the power state transition heuristics 211 * via the pp_power_profile_mode sysfs file. 212 * 213 * profile_standard 214 * profile_min_sclk 215 * profile_min_mclk 216 * profile_peak 217 * 218 * When the profiling modes are selected, clock and power gating are 219 * disabled and the clocks are set for different profiling cases. This 220 * mode is recommended for profiling specific work loads where you do 221 * not want clock or power gating for clock fluctuation to interfere 222 * with your results. profile_standard sets the clocks to a fixed clock 223 * level which varies from asic to asic. profile_min_sclk forces the sclk 224 * to the lowest level. profile_min_mclk forces the mclk to the lowest level. 225 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels. 226 * 227 */ 228 229 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev, 230 struct device_attribute *attr, 231 char *buf) 232 { 233 struct drm_device *ddev = dev_get_drvdata(dev); 234 struct amdgpu_device *adev = ddev->dev_private; 235 enum amd_dpm_forced_level level = 0xff; 236 237 if ((adev->flags & AMD_IS_PX) && 238 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 239 return snprintf(buf, PAGE_SIZE, "off\n"); 240 241 if (adev->powerplay.pp_funcs->get_performance_level) 242 level = amdgpu_dpm_get_performance_level(adev); 243 else 244 level = adev->pm.dpm.forced_level; 245 246 return snprintf(buf, PAGE_SIZE, "%s\n", 247 (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" : 248 (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" : 249 (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" : 250 (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" : 251 (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" : 252 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" : 253 (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" : 254 (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" : 255 "unknown"); 256 } 257 258 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev, 259 struct device_attribute *attr, 260 const char *buf, 261 size_t count) 262 { 263 struct drm_device *ddev = dev_get_drvdata(dev); 264 struct amdgpu_device *adev = ddev->dev_private; 265 enum amd_dpm_forced_level level; 266 enum amd_dpm_forced_level current_level = 0xff; 267 int ret = 0; 268 269 /* Can't force performance level when the card is off */ 270 if ((adev->flags & AMD_IS_PX) && 271 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 272 return -EINVAL; 273 274 if (adev->powerplay.pp_funcs->get_performance_level) 275 current_level = amdgpu_dpm_get_performance_level(adev); 276 277 if (strncmp("low", buf, strlen("low")) == 0) { 278 level = AMD_DPM_FORCED_LEVEL_LOW; 279 } else if (strncmp("high", buf, strlen("high")) == 0) { 280 level = AMD_DPM_FORCED_LEVEL_HIGH; 281 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 282 level = AMD_DPM_FORCED_LEVEL_AUTO; 283 } else if (strncmp("manual", buf, strlen("manual")) == 0) { 284 level = AMD_DPM_FORCED_LEVEL_MANUAL; 285 } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) { 286 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT; 287 } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) { 288 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD; 289 } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) { 290 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK; 291 } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) { 292 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK; 293 } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) { 294 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK; 295 } else { 296 count = -EINVAL; 297 goto fail; 298 } 299 300 if (current_level == level) 301 return count; 302 303 if (adev->powerplay.pp_funcs->force_performance_level) { 304 mutex_lock(&adev->pm.mutex); 305 if (adev->pm.dpm.thermal_active) { 306 count = -EINVAL; 307 mutex_unlock(&adev->pm.mutex); 308 goto fail; 309 } 310 ret = amdgpu_dpm_force_performance_level(adev, level); 311 if (ret) 312 count = -EINVAL; 313 else 314 adev->pm.dpm.forced_level = level; 315 mutex_unlock(&adev->pm.mutex); 316 } 317 318 fail: 319 return count; 320 } 321 322 static ssize_t amdgpu_get_pp_num_states(struct device *dev, 323 struct device_attribute *attr, 324 char *buf) 325 { 326 struct drm_device *ddev = dev_get_drvdata(dev); 327 struct amdgpu_device *adev = ddev->dev_private; 328 struct pp_states_info data; 329 int i, buf_len; 330 331 if (adev->powerplay.pp_funcs->get_pp_num_states) 332 amdgpu_dpm_get_pp_num_states(adev, &data); 333 334 buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums); 335 for (i = 0; i < data.nums; i++) 336 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i, 337 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : 338 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : 339 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : 340 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); 341 342 return buf_len; 343 } 344 345 static ssize_t amdgpu_get_pp_cur_state(struct device *dev, 346 struct device_attribute *attr, 347 char *buf) 348 { 349 struct drm_device *ddev = dev_get_drvdata(dev); 350 struct amdgpu_device *adev = ddev->dev_private; 351 struct pp_states_info data; 352 enum amd_pm_state_type pm = 0; 353 int i = 0; 354 355 if (adev->powerplay.pp_funcs->get_current_power_state 356 && adev->powerplay.pp_funcs->get_pp_num_states) { 357 pm = amdgpu_dpm_get_current_power_state(adev); 358 amdgpu_dpm_get_pp_num_states(adev, &data); 359 360 for (i = 0; i < data.nums; i++) { 361 if (pm == data.states[i]) 362 break; 363 } 364 365 if (i == data.nums) 366 i = -EINVAL; 367 } 368 369 return snprintf(buf, PAGE_SIZE, "%d\n", i); 370 } 371 372 static ssize_t amdgpu_get_pp_force_state(struct device *dev, 373 struct device_attribute *attr, 374 char *buf) 375 { 376 struct drm_device *ddev = dev_get_drvdata(dev); 377 struct amdgpu_device *adev = ddev->dev_private; 378 379 if (adev->pp_force_state_enabled) 380 return amdgpu_get_pp_cur_state(dev, attr, buf); 381 else 382 return snprintf(buf, PAGE_SIZE, "\n"); 383 } 384 385 static ssize_t amdgpu_set_pp_force_state(struct device *dev, 386 struct device_attribute *attr, 387 const char *buf, 388 size_t count) 389 { 390 struct drm_device *ddev = dev_get_drvdata(dev); 391 struct amdgpu_device *adev = ddev->dev_private; 392 enum amd_pm_state_type state = 0; 393 unsigned long idx; 394 int ret; 395 396 if (strlen(buf) == 1) 397 adev->pp_force_state_enabled = false; 398 else if (adev->powerplay.pp_funcs->dispatch_tasks && 399 adev->powerplay.pp_funcs->get_pp_num_states) { 400 struct pp_states_info data; 401 402 ret = kstrtoul(buf, 0, &idx); 403 if (ret || idx >= ARRAY_SIZE(data.states)) { 404 count = -EINVAL; 405 goto fail; 406 } 407 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); 408 409 amdgpu_dpm_get_pp_num_states(adev, &data); 410 state = data.states[idx]; 411 /* only set user selected power states */ 412 if (state != POWER_STATE_TYPE_INTERNAL_BOOT && 413 state != POWER_STATE_TYPE_DEFAULT) { 414 amdgpu_dpm_dispatch_task(adev, 415 AMD_PP_TASK_ENABLE_USER_STATE, &state); 416 adev->pp_force_state_enabled = true; 417 } 418 } 419 fail: 420 return count; 421 } 422 423 /** 424 * DOC: pp_table 425 * 426 * The amdgpu driver provides a sysfs API for uploading new powerplay 427 * tables. The file pp_table is used for this. Reading the file 428 * will dump the current power play table. Writing to the file 429 * will attempt to upload a new powerplay table and re-initialize 430 * powerplay using that new table. 431 * 432 */ 433 434 static ssize_t amdgpu_get_pp_table(struct device *dev, 435 struct device_attribute *attr, 436 char *buf) 437 { 438 struct drm_device *ddev = dev_get_drvdata(dev); 439 struct amdgpu_device *adev = ddev->dev_private; 440 char *table = NULL; 441 int size; 442 443 if (adev->powerplay.pp_funcs->get_pp_table) 444 size = amdgpu_dpm_get_pp_table(adev, &table); 445 else 446 return 0; 447 448 if (size >= PAGE_SIZE) 449 size = PAGE_SIZE - 1; 450 451 memcpy(buf, table, size); 452 453 return size; 454 } 455 456 static ssize_t amdgpu_set_pp_table(struct device *dev, 457 struct device_attribute *attr, 458 const char *buf, 459 size_t count) 460 { 461 struct drm_device *ddev = dev_get_drvdata(dev); 462 struct amdgpu_device *adev = ddev->dev_private; 463 464 if (adev->powerplay.pp_funcs->set_pp_table) 465 amdgpu_dpm_set_pp_table(adev, buf, count); 466 467 return count; 468 } 469 470 /** 471 * DOC: pp_od_clk_voltage 472 * 473 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages 474 * in each power level within a power state. The pp_od_clk_voltage is used for 475 * this. 476 * 477 * Reading the file will display: 478 * 479 * - a list of engine clock levels and voltages labeled OD_SCLK 480 * 481 * - a list of memory clock levels and voltages labeled OD_MCLK 482 * 483 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE 484 * 485 * To manually adjust these settings, first select manual using 486 * power_dpm_force_performance_level. Enter a new value for each 487 * level by writing a string that contains "s/m level clock voltage" to 488 * the file. E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz 489 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at 490 * 810 mV. When you have edited all of the states as needed, write 491 * "c" (commit) to the file to commit your changes. If you want to reset to the 492 * default power levels, write "r" (reset) to the file to reset them. 493 * 494 */ 495 496 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev, 497 struct device_attribute *attr, 498 const char *buf, 499 size_t count) 500 { 501 struct drm_device *ddev = dev_get_drvdata(dev); 502 struct amdgpu_device *adev = ddev->dev_private; 503 int ret; 504 uint32_t parameter_size = 0; 505 long parameter[64]; 506 char buf_cpy[128]; 507 char *tmp_str; 508 char *sub_str; 509 const char delimiter[3] = {' ', '\n', '\0'}; 510 uint32_t type; 511 512 if (count > 127) 513 return -EINVAL; 514 515 if (*buf == 's') 516 type = PP_OD_EDIT_SCLK_VDDC_TABLE; 517 else if (*buf == 'm') 518 type = PP_OD_EDIT_MCLK_VDDC_TABLE; 519 else if(*buf == 'r') 520 type = PP_OD_RESTORE_DEFAULT_TABLE; 521 else if (*buf == 'c') 522 type = PP_OD_COMMIT_DPM_TABLE; 523 else 524 return -EINVAL; 525 526 memcpy(buf_cpy, buf, count+1); 527 528 tmp_str = buf_cpy; 529 530 while (isspace(*++tmp_str)); 531 532 while (tmp_str[0]) { 533 sub_str = strsep(&tmp_str, delimiter); 534 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 535 if (ret) 536 return -EINVAL; 537 parameter_size++; 538 539 while (isspace(*tmp_str)) 540 tmp_str++; 541 } 542 543 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) 544 ret = amdgpu_dpm_odn_edit_dpm_table(adev, type, 545 parameter, parameter_size); 546 547 if (ret) 548 return -EINVAL; 549 550 if (type == PP_OD_COMMIT_DPM_TABLE) { 551 if (adev->powerplay.pp_funcs->dispatch_tasks) { 552 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 553 return count; 554 } else { 555 return -EINVAL; 556 } 557 } 558 559 return count; 560 } 561 562 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 563 struct device_attribute *attr, 564 char *buf) 565 { 566 struct drm_device *ddev = dev_get_drvdata(dev); 567 struct amdgpu_device *adev = ddev->dev_private; 568 uint32_t size = 0; 569 570 if (adev->powerplay.pp_funcs->print_clock_levels) { 571 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf); 572 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size); 573 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size); 574 return size; 575 } else { 576 return snprintf(buf, PAGE_SIZE, "\n"); 577 } 578 579 } 580 581 /** 582 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie 583 * 584 * The amdgpu driver provides a sysfs API for adjusting what power levels 585 * are enabled for a given power state. The files pp_dpm_sclk, pp_dpm_mclk, 586 * and pp_dpm_pcie are used for this. 587 * 588 * Reading back the files will show you the available power levels within 589 * the power state and the clock information for those levels. 590 * 591 * To manually adjust these states, first select manual using 592 * power_dpm_force_performance_level. 593 * Secondly,Enter a new value for each level by inputing a string that 594 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie" 595 * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6. 596 */ 597 598 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev, 599 struct device_attribute *attr, 600 char *buf) 601 { 602 struct drm_device *ddev = dev_get_drvdata(dev); 603 struct amdgpu_device *adev = ddev->dev_private; 604 605 if (adev->powerplay.pp_funcs->print_clock_levels) 606 return amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf); 607 else 608 return snprintf(buf, PAGE_SIZE, "\n"); 609 } 610 611 /* 612 * Worst case: 32 bits individually specified, in octal at 12 characters 613 * per line (+1 for \n). 614 */ 615 #define AMDGPU_MASK_BUF_MAX (32 * 13) 616 617 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask) 618 { 619 int ret; 620 unsigned long level; 621 char *sub_str = NULL; 622 char *tmp; 623 char buf_cpy[AMDGPU_MASK_BUF_MAX + 1]; 624 const char delimiter[3] = {' ', '\n', '\0'}; 625 size_t bytes; 626 627 *mask = 0; 628 629 bytes = min(count, sizeof(buf_cpy) - 1); 630 memcpy(buf_cpy, buf, bytes); 631 buf_cpy[bytes] = '\0'; 632 tmp = buf_cpy; 633 while (tmp[0]) { 634 sub_str = strsep(&tmp, delimiter); 635 if (strlen(sub_str)) { 636 ret = kstrtoul(sub_str, 0, &level); 637 if (ret || level > 31) 638 return -EINVAL; 639 *mask |= 1 << level; 640 } else 641 break; 642 } 643 644 return 0; 645 } 646 647 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 648 struct device_attribute *attr, 649 const char *buf, 650 size_t count) 651 { 652 struct drm_device *ddev = dev_get_drvdata(dev); 653 struct amdgpu_device *adev = ddev->dev_private; 654 int ret; 655 uint32_t mask = 0; 656 657 ret = amdgpu_read_mask(buf, count, &mask); 658 if (ret) 659 return ret; 660 661 if (adev->powerplay.pp_funcs->force_clock_level) 662 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask); 663 664 return count; 665 } 666 667 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev, 668 struct device_attribute *attr, 669 char *buf) 670 { 671 struct drm_device *ddev = dev_get_drvdata(dev); 672 struct amdgpu_device *adev = ddev->dev_private; 673 674 if (adev->powerplay.pp_funcs->print_clock_levels) 675 return amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf); 676 else 677 return snprintf(buf, PAGE_SIZE, "\n"); 678 } 679 680 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 681 struct device_attribute *attr, 682 const char *buf, 683 size_t count) 684 { 685 struct drm_device *ddev = dev_get_drvdata(dev); 686 struct amdgpu_device *adev = ddev->dev_private; 687 int ret; 688 uint32_t mask = 0; 689 690 ret = amdgpu_read_mask(buf, count, &mask); 691 if (ret) 692 return ret; 693 694 if (adev->powerplay.pp_funcs->force_clock_level) 695 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask); 696 697 return count; 698 } 699 700 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev, 701 struct device_attribute *attr, 702 char *buf) 703 { 704 struct drm_device *ddev = dev_get_drvdata(dev); 705 struct amdgpu_device *adev = ddev->dev_private; 706 707 if (adev->powerplay.pp_funcs->print_clock_levels) 708 return amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf); 709 else 710 return snprintf(buf, PAGE_SIZE, "\n"); 711 } 712 713 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 714 struct device_attribute *attr, 715 const char *buf, 716 size_t count) 717 { 718 struct drm_device *ddev = dev_get_drvdata(dev); 719 struct amdgpu_device *adev = ddev->dev_private; 720 int ret; 721 uint32_t mask = 0; 722 723 ret = amdgpu_read_mask(buf, count, &mask); 724 if (ret) 725 return ret; 726 727 if (adev->powerplay.pp_funcs->force_clock_level) 728 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask); 729 730 return count; 731 } 732 733 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev, 734 struct device_attribute *attr, 735 char *buf) 736 { 737 struct drm_device *ddev = dev_get_drvdata(dev); 738 struct amdgpu_device *adev = ddev->dev_private; 739 uint32_t value = 0; 740 741 if (adev->powerplay.pp_funcs->get_sclk_od) 742 value = amdgpu_dpm_get_sclk_od(adev); 743 744 return snprintf(buf, PAGE_SIZE, "%d\n", value); 745 } 746 747 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev, 748 struct device_attribute *attr, 749 const char *buf, 750 size_t count) 751 { 752 struct drm_device *ddev = dev_get_drvdata(dev); 753 struct amdgpu_device *adev = ddev->dev_private; 754 int ret; 755 long int value; 756 757 ret = kstrtol(buf, 0, &value); 758 759 if (ret) { 760 count = -EINVAL; 761 goto fail; 762 } 763 if (adev->powerplay.pp_funcs->set_sclk_od) 764 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value); 765 766 if (adev->powerplay.pp_funcs->dispatch_tasks) { 767 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 768 } else { 769 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 770 amdgpu_pm_compute_clocks(adev); 771 } 772 773 fail: 774 return count; 775 } 776 777 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev, 778 struct device_attribute *attr, 779 char *buf) 780 { 781 struct drm_device *ddev = dev_get_drvdata(dev); 782 struct amdgpu_device *adev = ddev->dev_private; 783 uint32_t value = 0; 784 785 if (adev->powerplay.pp_funcs->get_mclk_od) 786 value = amdgpu_dpm_get_mclk_od(adev); 787 788 return snprintf(buf, PAGE_SIZE, "%d\n", value); 789 } 790 791 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev, 792 struct device_attribute *attr, 793 const char *buf, 794 size_t count) 795 { 796 struct drm_device *ddev = dev_get_drvdata(dev); 797 struct amdgpu_device *adev = ddev->dev_private; 798 int ret; 799 long int value; 800 801 ret = kstrtol(buf, 0, &value); 802 803 if (ret) { 804 count = -EINVAL; 805 goto fail; 806 } 807 if (adev->powerplay.pp_funcs->set_mclk_od) 808 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value); 809 810 if (adev->powerplay.pp_funcs->dispatch_tasks) { 811 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL); 812 } else { 813 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; 814 amdgpu_pm_compute_clocks(adev); 815 } 816 817 fail: 818 return count; 819 } 820 821 /** 822 * DOC: pp_power_profile_mode 823 * 824 * The amdgpu driver provides a sysfs API for adjusting the heuristics 825 * related to switching between power levels in a power state. The file 826 * pp_power_profile_mode is used for this. 827 * 828 * Reading this file outputs a list of all of the predefined power profiles 829 * and the relevant heuristics settings for that profile. 830 * 831 * To select a profile or create a custom profile, first select manual using 832 * power_dpm_force_performance_level. Writing the number of a predefined 833 * profile to pp_power_profile_mode will enable those heuristics. To 834 * create a custom set of heuristics, write a string of numbers to the file 835 * starting with the number of the custom profile along with a setting 836 * for each heuristic parameter. Due to differences across asic families 837 * the heuristic parameters vary from family to family. 838 * 839 */ 840 841 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev, 842 struct device_attribute *attr, 843 char *buf) 844 { 845 struct drm_device *ddev = dev_get_drvdata(dev); 846 struct amdgpu_device *adev = ddev->dev_private; 847 848 if (adev->powerplay.pp_funcs->get_power_profile_mode) 849 return amdgpu_dpm_get_power_profile_mode(adev, buf); 850 851 return snprintf(buf, PAGE_SIZE, "\n"); 852 } 853 854 855 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev, 856 struct device_attribute *attr, 857 const char *buf, 858 size_t count) 859 { 860 int ret = 0xff; 861 struct drm_device *ddev = dev_get_drvdata(dev); 862 struct amdgpu_device *adev = ddev->dev_private; 863 uint32_t parameter_size = 0; 864 long parameter[64]; 865 char *sub_str, buf_cpy[128]; 866 char *tmp_str; 867 uint32_t i = 0; 868 char tmp[2]; 869 long int profile_mode = 0; 870 const char delimiter[3] = {' ', '\n', '\0'}; 871 872 tmp[0] = *(buf); 873 tmp[1] = '\0'; 874 ret = kstrtol(tmp, 0, &profile_mode); 875 if (ret) 876 goto fail; 877 878 if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) { 879 if (count < 2 || count > 127) 880 return -EINVAL; 881 while (isspace(*++buf)) 882 i++; 883 memcpy(buf_cpy, buf, count-i); 884 tmp_str = buf_cpy; 885 while (tmp_str[0]) { 886 sub_str = strsep(&tmp_str, delimiter); 887 ret = kstrtol(sub_str, 0, ¶meter[parameter_size]); 888 if (ret) { 889 count = -EINVAL; 890 goto fail; 891 } 892 parameter_size++; 893 while (isspace(*tmp_str)) 894 tmp_str++; 895 } 896 } 897 parameter[parameter_size] = profile_mode; 898 if (adev->powerplay.pp_funcs->set_power_profile_mode) 899 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size); 900 901 if (!ret) 902 return count; 903 fail: 904 return -EINVAL; 905 } 906 907 /** 908 * DOC: busy_percent 909 * 910 * The amdgpu driver provides a sysfs API for reading how busy the GPU 911 * is as a percentage. The file gpu_busy_percent is used for this. 912 * The SMU firmware computes a percentage of load based on the 913 * aggregate activity level in the IP cores. 914 */ 915 static ssize_t amdgpu_get_busy_percent(struct device *dev, 916 struct device_attribute *attr, 917 char *buf) 918 { 919 struct drm_device *ddev = dev_get_drvdata(dev); 920 struct amdgpu_device *adev = ddev->dev_private; 921 int r, value, size = sizeof(value); 922 923 /* sanity check PP is enabled */ 924 if (!(adev->powerplay.pp_funcs && 925 adev->powerplay.pp_funcs->read_sensor)) 926 return -EINVAL; 927 928 /* read the IP busy sensor */ 929 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, 930 (void *)&value, &size); 931 if (r) 932 return r; 933 934 return snprintf(buf, PAGE_SIZE, "%d\n", value); 935 } 936 937 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state); 938 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 939 amdgpu_get_dpm_forced_performance_level, 940 amdgpu_set_dpm_forced_performance_level); 941 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL); 942 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL); 943 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR, 944 amdgpu_get_pp_force_state, 945 amdgpu_set_pp_force_state); 946 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR, 947 amdgpu_get_pp_table, 948 amdgpu_set_pp_table); 949 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR, 950 amdgpu_get_pp_dpm_sclk, 951 amdgpu_set_pp_dpm_sclk); 952 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR, 953 amdgpu_get_pp_dpm_mclk, 954 amdgpu_set_pp_dpm_mclk); 955 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR, 956 amdgpu_get_pp_dpm_pcie, 957 amdgpu_set_pp_dpm_pcie); 958 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR, 959 amdgpu_get_pp_sclk_od, 960 amdgpu_set_pp_sclk_od); 961 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR, 962 amdgpu_get_pp_mclk_od, 963 amdgpu_set_pp_mclk_od); 964 static DEVICE_ATTR(pp_power_profile_mode, S_IRUGO | S_IWUSR, 965 amdgpu_get_pp_power_profile_mode, 966 amdgpu_set_pp_power_profile_mode); 967 static DEVICE_ATTR(pp_od_clk_voltage, S_IRUGO | S_IWUSR, 968 amdgpu_get_pp_od_clk_voltage, 969 amdgpu_set_pp_od_clk_voltage); 970 static DEVICE_ATTR(gpu_busy_percent, S_IRUGO, 971 amdgpu_get_busy_percent, NULL); 972 973 static ssize_t amdgpu_hwmon_show_temp(struct device *dev, 974 struct device_attribute *attr, 975 char *buf) 976 { 977 struct amdgpu_device *adev = dev_get_drvdata(dev); 978 struct drm_device *ddev = adev->ddev; 979 int r, temp, size = sizeof(temp); 980 981 /* Can't get temperature when the card is off */ 982 if ((adev->flags & AMD_IS_PX) && 983 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 984 return -EINVAL; 985 986 /* sanity check PP is enabled */ 987 if (!(adev->powerplay.pp_funcs && 988 adev->powerplay.pp_funcs->read_sensor)) 989 return -EINVAL; 990 991 /* get the temperature */ 992 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, 993 (void *)&temp, &size); 994 if (r) 995 return r; 996 997 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 998 } 999 1000 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev, 1001 struct device_attribute *attr, 1002 char *buf) 1003 { 1004 struct amdgpu_device *adev = dev_get_drvdata(dev); 1005 int hyst = to_sensor_dev_attr(attr)->index; 1006 int temp; 1007 1008 if (hyst) 1009 temp = adev->pm.dpm.thermal.min_temp; 1010 else 1011 temp = adev->pm.dpm.thermal.max_temp; 1012 1013 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 1014 } 1015 1016 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev, 1017 struct device_attribute *attr, 1018 char *buf) 1019 { 1020 struct amdgpu_device *adev = dev_get_drvdata(dev); 1021 u32 pwm_mode = 0; 1022 1023 if (!adev->powerplay.pp_funcs->get_fan_control_mode) 1024 return -EINVAL; 1025 1026 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev); 1027 1028 return sprintf(buf, "%i\n", pwm_mode); 1029 } 1030 1031 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev, 1032 struct device_attribute *attr, 1033 const char *buf, 1034 size_t count) 1035 { 1036 struct amdgpu_device *adev = dev_get_drvdata(dev); 1037 int err; 1038 int value; 1039 1040 /* Can't adjust fan when the card is off */ 1041 if ((adev->flags & AMD_IS_PX) && 1042 (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 1043 return -EINVAL; 1044 1045 if (!adev->powerplay.pp_funcs->set_fan_control_mode) 1046 return -EINVAL; 1047 1048 err = kstrtoint(buf, 10, &value); 1049 if (err) 1050 return err; 1051 1052 amdgpu_dpm_set_fan_control_mode(adev, value); 1053 1054 return count; 1055 } 1056 1057 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev, 1058 struct device_attribute *attr, 1059 char *buf) 1060 { 1061 return sprintf(buf, "%i\n", 0); 1062 } 1063 1064 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev, 1065 struct device_attribute *attr, 1066 char *buf) 1067 { 1068 return sprintf(buf, "%i\n", 255); 1069 } 1070 1071 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev, 1072 struct device_attribute *attr, 1073 const char *buf, size_t count) 1074 { 1075 struct amdgpu_device *adev = dev_get_drvdata(dev); 1076 int err; 1077 u32 value; 1078 1079 /* Can't adjust fan when the card is off */ 1080 if ((adev->flags & AMD_IS_PX) && 1081 (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 1082 return -EINVAL; 1083 1084 err = kstrtou32(buf, 10, &value); 1085 if (err) 1086 return err; 1087 1088 value = (value * 100) / 255; 1089 1090 if (adev->powerplay.pp_funcs->set_fan_speed_percent) { 1091 err = amdgpu_dpm_set_fan_speed_percent(adev, value); 1092 if (err) 1093 return err; 1094 } 1095 1096 return count; 1097 } 1098 1099 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev, 1100 struct device_attribute *attr, 1101 char *buf) 1102 { 1103 struct amdgpu_device *adev = dev_get_drvdata(dev); 1104 int err; 1105 u32 speed = 0; 1106 1107 /* Can't adjust fan when the card is off */ 1108 if ((adev->flags & AMD_IS_PX) && 1109 (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 1110 return -EINVAL; 1111 1112 if (adev->powerplay.pp_funcs->get_fan_speed_percent) { 1113 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed); 1114 if (err) 1115 return err; 1116 } 1117 1118 speed = (speed * 255) / 100; 1119 1120 return sprintf(buf, "%i\n", speed); 1121 } 1122 1123 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev, 1124 struct device_attribute *attr, 1125 char *buf) 1126 { 1127 struct amdgpu_device *adev = dev_get_drvdata(dev); 1128 int err; 1129 u32 speed = 0; 1130 1131 /* Can't adjust fan when the card is off */ 1132 if ((adev->flags & AMD_IS_PX) && 1133 (adev->ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 1134 return -EINVAL; 1135 1136 if (adev->powerplay.pp_funcs->get_fan_speed_rpm) { 1137 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed); 1138 if (err) 1139 return err; 1140 } 1141 1142 return sprintf(buf, "%i\n", speed); 1143 } 1144 1145 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev, 1146 struct device_attribute *attr, 1147 char *buf) 1148 { 1149 struct amdgpu_device *adev = dev_get_drvdata(dev); 1150 struct drm_device *ddev = adev->ddev; 1151 u32 vddgfx; 1152 int r, size = sizeof(vddgfx); 1153 1154 /* Can't get voltage when the card is off */ 1155 if ((adev->flags & AMD_IS_PX) && 1156 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 1157 return -EINVAL; 1158 1159 /* sanity check PP is enabled */ 1160 if (!(adev->powerplay.pp_funcs && 1161 adev->powerplay.pp_funcs->read_sensor)) 1162 return -EINVAL; 1163 1164 /* get the voltage */ 1165 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, 1166 (void *)&vddgfx, &size); 1167 if (r) 1168 return r; 1169 1170 return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx); 1171 } 1172 1173 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev, 1174 struct device_attribute *attr, 1175 char *buf) 1176 { 1177 return snprintf(buf, PAGE_SIZE, "vddgfx\n"); 1178 } 1179 1180 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev, 1181 struct device_attribute *attr, 1182 char *buf) 1183 { 1184 struct amdgpu_device *adev = dev_get_drvdata(dev); 1185 struct drm_device *ddev = adev->ddev; 1186 u32 vddnb; 1187 int r, size = sizeof(vddnb); 1188 1189 /* only APUs have vddnb */ 1190 if (!(adev->flags & AMD_IS_APU)) 1191 return -EINVAL; 1192 1193 /* Can't get voltage when the card is off */ 1194 if ((adev->flags & AMD_IS_PX) && 1195 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 1196 return -EINVAL; 1197 1198 /* sanity check PP is enabled */ 1199 if (!(adev->powerplay.pp_funcs && 1200 adev->powerplay.pp_funcs->read_sensor)) 1201 return -EINVAL; 1202 1203 /* get the voltage */ 1204 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, 1205 (void *)&vddnb, &size); 1206 if (r) 1207 return r; 1208 1209 return snprintf(buf, PAGE_SIZE, "%d\n", vddnb); 1210 } 1211 1212 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev, 1213 struct device_attribute *attr, 1214 char *buf) 1215 { 1216 return snprintf(buf, PAGE_SIZE, "vddnb\n"); 1217 } 1218 1219 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev, 1220 struct device_attribute *attr, 1221 char *buf) 1222 { 1223 struct amdgpu_device *adev = dev_get_drvdata(dev); 1224 struct drm_device *ddev = adev->ddev; 1225 u32 query = 0; 1226 int r, size = sizeof(u32); 1227 unsigned uw; 1228 1229 /* Can't get power when the card is off */ 1230 if ((adev->flags & AMD_IS_PX) && 1231 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 1232 return -EINVAL; 1233 1234 /* sanity check PP is enabled */ 1235 if (!(adev->powerplay.pp_funcs && 1236 adev->powerplay.pp_funcs->read_sensor)) 1237 return -EINVAL; 1238 1239 /* get the voltage */ 1240 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, 1241 (void *)&query, &size); 1242 if (r) 1243 return r; 1244 1245 /* convert to microwatts */ 1246 uw = (query >> 8) * 1000000 + (query & 0xff) * 1000; 1247 1248 return snprintf(buf, PAGE_SIZE, "%u\n", uw); 1249 } 1250 1251 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev, 1252 struct device_attribute *attr, 1253 char *buf) 1254 { 1255 return sprintf(buf, "%i\n", 0); 1256 } 1257 1258 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev, 1259 struct device_attribute *attr, 1260 char *buf) 1261 { 1262 struct amdgpu_device *adev = dev_get_drvdata(dev); 1263 uint32_t limit = 0; 1264 1265 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { 1266 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true); 1267 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 1268 } else { 1269 return snprintf(buf, PAGE_SIZE, "\n"); 1270 } 1271 } 1272 1273 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev, 1274 struct device_attribute *attr, 1275 char *buf) 1276 { 1277 struct amdgpu_device *adev = dev_get_drvdata(dev); 1278 uint32_t limit = 0; 1279 1280 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) { 1281 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false); 1282 return snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000); 1283 } else { 1284 return snprintf(buf, PAGE_SIZE, "\n"); 1285 } 1286 } 1287 1288 1289 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev, 1290 struct device_attribute *attr, 1291 const char *buf, 1292 size_t count) 1293 { 1294 struct amdgpu_device *adev = dev_get_drvdata(dev); 1295 int err; 1296 u32 value; 1297 1298 err = kstrtou32(buf, 10, &value); 1299 if (err) 1300 return err; 1301 1302 value = value / 1000000; /* convert to Watt */ 1303 if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit) { 1304 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value); 1305 if (err) 1306 return err; 1307 } else { 1308 return -EINVAL; 1309 } 1310 1311 return count; 1312 } 1313 1314 1315 /** 1316 * DOC: hwmon 1317 * 1318 * The amdgpu driver exposes the following sensor interfaces: 1319 * 1320 * - GPU temperature (via the on-die sensor) 1321 * 1322 * - GPU voltage 1323 * 1324 * - Northbridge voltage (APUs only) 1325 * 1326 * - GPU power 1327 * 1328 * - GPU fan 1329 * 1330 * hwmon interfaces for GPU temperature: 1331 * 1332 * - temp1_input: the on die GPU temperature in millidegrees Celsius 1333 * 1334 * - temp1_crit: temperature critical max value in millidegrees Celsius 1335 * 1336 * - temp1_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius 1337 * 1338 * hwmon interfaces for GPU voltage: 1339 * 1340 * - in0_input: the voltage on the GPU in millivolts 1341 * 1342 * - in1_input: the voltage on the Northbridge in millivolts 1343 * 1344 * hwmon interfaces for GPU power: 1345 * 1346 * - power1_average: average power used by the GPU in microWatts 1347 * 1348 * - power1_cap_min: minimum cap supported in microWatts 1349 * 1350 * - power1_cap_max: maximum cap supported in microWatts 1351 * 1352 * - power1_cap: selected power cap in microWatts 1353 * 1354 * hwmon interfaces for GPU fan: 1355 * 1356 * - pwm1: pulse width modulation fan level (0-255) 1357 * 1358 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control) 1359 * 1360 * - pwm1_min: pulse width modulation fan control minimum level (0) 1361 * 1362 * - pwm1_max: pulse width modulation fan control maximum level (255) 1363 * 1364 * - fan1_input: fan speed in RPM 1365 * 1366 * You can use hwmon tools like sensors to view this information on your system. 1367 * 1368 */ 1369 1370 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0); 1371 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0); 1372 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1); 1373 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0); 1374 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0); 1375 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0); 1376 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0); 1377 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0); 1378 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0); 1379 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0); 1380 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0); 1381 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0); 1382 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0); 1383 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0); 1384 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0); 1385 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0); 1386 1387 static struct attribute *hwmon_attributes[] = { 1388 &sensor_dev_attr_temp1_input.dev_attr.attr, 1389 &sensor_dev_attr_temp1_crit.dev_attr.attr, 1390 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 1391 &sensor_dev_attr_pwm1.dev_attr.attr, 1392 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 1393 &sensor_dev_attr_pwm1_min.dev_attr.attr, 1394 &sensor_dev_attr_pwm1_max.dev_attr.attr, 1395 &sensor_dev_attr_fan1_input.dev_attr.attr, 1396 &sensor_dev_attr_in0_input.dev_attr.attr, 1397 &sensor_dev_attr_in0_label.dev_attr.attr, 1398 &sensor_dev_attr_in1_input.dev_attr.attr, 1399 &sensor_dev_attr_in1_label.dev_attr.attr, 1400 &sensor_dev_attr_power1_average.dev_attr.attr, 1401 &sensor_dev_attr_power1_cap_max.dev_attr.attr, 1402 &sensor_dev_attr_power1_cap_min.dev_attr.attr, 1403 &sensor_dev_attr_power1_cap.dev_attr.attr, 1404 NULL 1405 }; 1406 1407 static umode_t hwmon_attributes_visible(struct kobject *kobj, 1408 struct attribute *attr, int index) 1409 { 1410 struct device *dev = kobj_to_dev(kobj); 1411 struct amdgpu_device *adev = dev_get_drvdata(dev); 1412 umode_t effective_mode = attr->mode; 1413 1414 1415 /* Skip fan attributes if fan is not present */ 1416 if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 1417 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 1418 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 1419 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 1420 attr == &sensor_dev_attr_fan1_input.dev_attr.attr)) 1421 return 0; 1422 1423 /* Skip limit attributes if DPM is not enabled */ 1424 if (!adev->pm.dpm_enabled && 1425 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 1426 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 1427 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 1428 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 1429 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 1430 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 1431 return 0; 1432 1433 /* mask fan attributes if we have no bindings for this asic to expose */ 1434 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent && 1435 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 1436 (!adev->powerplay.pp_funcs->get_fan_control_mode && 1437 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 1438 effective_mode &= ~S_IRUGO; 1439 1440 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && 1441 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 1442 (!adev->powerplay.pp_funcs->set_fan_control_mode && 1443 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 1444 effective_mode &= ~S_IWUSR; 1445 1446 if ((adev->flags & AMD_IS_APU) && 1447 (attr == &sensor_dev_attr_power1_average.dev_attr.attr || 1448 attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr || 1449 attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr|| 1450 attr == &sensor_dev_attr_power1_cap.dev_attr.attr)) 1451 return 0; 1452 1453 /* hide max/min values if we can't both query and manage the fan */ 1454 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent && 1455 !adev->powerplay.pp_funcs->get_fan_speed_percent) && 1456 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 1457 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 1458 return 0; 1459 1460 /* only APUs have vddnb */ 1461 if (!(adev->flags & AMD_IS_APU) && 1462 (attr == &sensor_dev_attr_in1_input.dev_attr.attr || 1463 attr == &sensor_dev_attr_in1_label.dev_attr.attr)) 1464 return 0; 1465 1466 return effective_mode; 1467 } 1468 1469 static const struct attribute_group hwmon_attrgroup = { 1470 .attrs = hwmon_attributes, 1471 .is_visible = hwmon_attributes_visible, 1472 }; 1473 1474 static const struct attribute_group *hwmon_groups[] = { 1475 &hwmon_attrgroup, 1476 NULL 1477 }; 1478 1479 void amdgpu_dpm_thermal_work_handler(struct work_struct *work) 1480 { 1481 struct amdgpu_device *adev = 1482 container_of(work, struct amdgpu_device, 1483 pm.dpm.thermal.work); 1484 /* switch to the thermal state */ 1485 enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 1486 int temp, size = sizeof(temp); 1487 1488 if (!adev->pm.dpm_enabled) 1489 return; 1490 1491 if (adev->powerplay.pp_funcs && 1492 adev->powerplay.pp_funcs->read_sensor && 1493 !amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, 1494 (void *)&temp, &size)) { 1495 if (temp < adev->pm.dpm.thermal.min_temp) 1496 /* switch back the user state */ 1497 dpm_state = adev->pm.dpm.user_state; 1498 } else { 1499 if (adev->pm.dpm.thermal.high_to_low) 1500 /* switch back the user state */ 1501 dpm_state = adev->pm.dpm.user_state; 1502 } 1503 mutex_lock(&adev->pm.mutex); 1504 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 1505 adev->pm.dpm.thermal_active = true; 1506 else 1507 adev->pm.dpm.thermal_active = false; 1508 adev->pm.dpm.state = dpm_state; 1509 mutex_unlock(&adev->pm.mutex); 1510 1511 amdgpu_pm_compute_clocks(adev); 1512 } 1513 1514 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev, 1515 enum amd_pm_state_type dpm_state) 1516 { 1517 int i; 1518 struct amdgpu_ps *ps; 1519 u32 ui_class; 1520 bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ? 1521 true : false; 1522 1523 /* check if the vblank period is too short to adjust the mclk */ 1524 if (single_display && adev->powerplay.pp_funcs->vblank_too_short) { 1525 if (amdgpu_dpm_vblank_too_short(adev)) 1526 single_display = false; 1527 } 1528 1529 /* certain older asics have a separare 3D performance state, 1530 * so try that first if the user selected performance 1531 */ 1532 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 1533 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 1534 /* balanced states don't exist at the moment */ 1535 if (dpm_state == POWER_STATE_TYPE_BALANCED) 1536 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1537 1538 restart_search: 1539 /* Pick the best power state based on current conditions */ 1540 for (i = 0; i < adev->pm.dpm.num_ps; i++) { 1541 ps = &adev->pm.dpm.ps[i]; 1542 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 1543 switch (dpm_state) { 1544 /* user states */ 1545 case POWER_STATE_TYPE_BATTERY: 1546 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 1547 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 1548 if (single_display) 1549 return ps; 1550 } else 1551 return ps; 1552 } 1553 break; 1554 case POWER_STATE_TYPE_BALANCED: 1555 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 1556 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 1557 if (single_display) 1558 return ps; 1559 } else 1560 return ps; 1561 } 1562 break; 1563 case POWER_STATE_TYPE_PERFORMANCE: 1564 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 1565 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 1566 if (single_display) 1567 return ps; 1568 } else 1569 return ps; 1570 } 1571 break; 1572 /* internal states */ 1573 case POWER_STATE_TYPE_INTERNAL_UVD: 1574 if (adev->pm.dpm.uvd_ps) 1575 return adev->pm.dpm.uvd_ps; 1576 else 1577 break; 1578 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 1579 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 1580 return ps; 1581 break; 1582 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 1583 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 1584 return ps; 1585 break; 1586 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 1587 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 1588 return ps; 1589 break; 1590 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 1591 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 1592 return ps; 1593 break; 1594 case POWER_STATE_TYPE_INTERNAL_BOOT: 1595 return adev->pm.dpm.boot_ps; 1596 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1597 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 1598 return ps; 1599 break; 1600 case POWER_STATE_TYPE_INTERNAL_ACPI: 1601 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 1602 return ps; 1603 break; 1604 case POWER_STATE_TYPE_INTERNAL_ULV: 1605 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 1606 return ps; 1607 break; 1608 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1609 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 1610 return ps; 1611 break; 1612 default: 1613 break; 1614 } 1615 } 1616 /* use a fallback state if we didn't match */ 1617 switch (dpm_state) { 1618 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 1619 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1620 goto restart_search; 1621 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 1622 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 1623 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 1624 if (adev->pm.dpm.uvd_ps) { 1625 return adev->pm.dpm.uvd_ps; 1626 } else { 1627 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1628 goto restart_search; 1629 } 1630 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1631 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 1632 goto restart_search; 1633 case POWER_STATE_TYPE_INTERNAL_ACPI: 1634 dpm_state = POWER_STATE_TYPE_BATTERY; 1635 goto restart_search; 1636 case POWER_STATE_TYPE_BATTERY: 1637 case POWER_STATE_TYPE_BALANCED: 1638 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1639 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1640 goto restart_search; 1641 default: 1642 break; 1643 } 1644 1645 return NULL; 1646 } 1647 1648 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev) 1649 { 1650 struct amdgpu_ps *ps; 1651 enum amd_pm_state_type dpm_state; 1652 int ret; 1653 bool equal = false; 1654 1655 /* if dpm init failed */ 1656 if (!adev->pm.dpm_enabled) 1657 return; 1658 1659 if (adev->pm.dpm.user_state != adev->pm.dpm.state) { 1660 /* add other state override checks here */ 1661 if ((!adev->pm.dpm.thermal_active) && 1662 (!adev->pm.dpm.uvd_active)) 1663 adev->pm.dpm.state = adev->pm.dpm.user_state; 1664 } 1665 dpm_state = adev->pm.dpm.state; 1666 1667 ps = amdgpu_dpm_pick_power_state(adev, dpm_state); 1668 if (ps) 1669 adev->pm.dpm.requested_ps = ps; 1670 else 1671 return; 1672 1673 if (amdgpu_dpm == 1 && adev->powerplay.pp_funcs->print_power_state) { 1674 printk("switching from power state:\n"); 1675 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); 1676 printk("switching to power state:\n"); 1677 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); 1678 } 1679 1680 /* update whether vce is active */ 1681 ps->vce_active = adev->pm.dpm.vce_active; 1682 if (adev->powerplay.pp_funcs->display_configuration_changed) 1683 amdgpu_dpm_display_configuration_changed(adev); 1684 1685 ret = amdgpu_dpm_pre_set_power_state(adev); 1686 if (ret) 1687 return; 1688 1689 if (adev->powerplay.pp_funcs->check_state_equal) { 1690 if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)) 1691 equal = false; 1692 } 1693 1694 if (equal) 1695 return; 1696 1697 amdgpu_dpm_set_power_state(adev); 1698 amdgpu_dpm_post_set_power_state(adev); 1699 1700 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; 1701 adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count; 1702 1703 if (adev->powerplay.pp_funcs->force_performance_level) { 1704 if (adev->pm.dpm.thermal_active) { 1705 enum amd_dpm_forced_level level = adev->pm.dpm.forced_level; 1706 /* force low perf level for thermal */ 1707 amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW); 1708 /* save the user's level */ 1709 adev->pm.dpm.forced_level = level; 1710 } else { 1711 /* otherwise, user selected level */ 1712 amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level); 1713 } 1714 } 1715 } 1716 1717 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) 1718 { 1719 if (adev->powerplay.pp_funcs->set_powergating_by_smu) { 1720 /* enable/disable UVD */ 1721 mutex_lock(&adev->pm.mutex); 1722 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); 1723 mutex_unlock(&adev->pm.mutex); 1724 } else { 1725 if (enable) { 1726 mutex_lock(&adev->pm.mutex); 1727 adev->pm.dpm.uvd_active = true; 1728 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; 1729 mutex_unlock(&adev->pm.mutex); 1730 } else { 1731 mutex_lock(&adev->pm.mutex); 1732 adev->pm.dpm.uvd_active = false; 1733 mutex_unlock(&adev->pm.mutex); 1734 } 1735 amdgpu_pm_compute_clocks(adev); 1736 } 1737 } 1738 1739 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) 1740 { 1741 if (adev->powerplay.pp_funcs->set_powergating_by_smu) { 1742 /* enable/disable VCE */ 1743 mutex_lock(&adev->pm.mutex); 1744 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); 1745 mutex_unlock(&adev->pm.mutex); 1746 } else { 1747 if (enable) { 1748 mutex_lock(&adev->pm.mutex); 1749 adev->pm.dpm.vce_active = true; 1750 /* XXX select vce level based on ring/task */ 1751 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; 1752 mutex_unlock(&adev->pm.mutex); 1753 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1754 AMD_CG_STATE_UNGATE); 1755 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1756 AMD_PG_STATE_UNGATE); 1757 amdgpu_pm_compute_clocks(adev); 1758 } else { 1759 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1760 AMD_PG_STATE_GATE); 1761 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE, 1762 AMD_CG_STATE_GATE); 1763 mutex_lock(&adev->pm.mutex); 1764 adev->pm.dpm.vce_active = false; 1765 mutex_unlock(&adev->pm.mutex); 1766 amdgpu_pm_compute_clocks(adev); 1767 } 1768 1769 } 1770 } 1771 1772 void amdgpu_pm_print_power_states(struct amdgpu_device *adev) 1773 { 1774 int i; 1775 1776 if (adev->powerplay.pp_funcs->print_power_state == NULL) 1777 return; 1778 1779 for (i = 0; i < adev->pm.dpm.num_ps; i++) 1780 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); 1781 1782 } 1783 1784 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) 1785 { 1786 int ret; 1787 1788 if (adev->pm.sysfs_initialized) 1789 return 0; 1790 1791 if (adev->pm.dpm_enabled == 0) 1792 return 0; 1793 1794 adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev, 1795 DRIVER_NAME, adev, 1796 hwmon_groups); 1797 if (IS_ERR(adev->pm.int_hwmon_dev)) { 1798 ret = PTR_ERR(adev->pm.int_hwmon_dev); 1799 dev_err(adev->dev, 1800 "Unable to register hwmon device: %d\n", ret); 1801 return ret; 1802 } 1803 1804 ret = device_create_file(adev->dev, &dev_attr_power_dpm_state); 1805 if (ret) { 1806 DRM_ERROR("failed to create device file for dpm state\n"); 1807 return ret; 1808 } 1809 ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level); 1810 if (ret) { 1811 DRM_ERROR("failed to create device file for dpm state\n"); 1812 return ret; 1813 } 1814 1815 1816 ret = device_create_file(adev->dev, &dev_attr_pp_num_states); 1817 if (ret) { 1818 DRM_ERROR("failed to create device file pp_num_states\n"); 1819 return ret; 1820 } 1821 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state); 1822 if (ret) { 1823 DRM_ERROR("failed to create device file pp_cur_state\n"); 1824 return ret; 1825 } 1826 ret = device_create_file(adev->dev, &dev_attr_pp_force_state); 1827 if (ret) { 1828 DRM_ERROR("failed to create device file pp_force_state\n"); 1829 return ret; 1830 } 1831 ret = device_create_file(adev->dev, &dev_attr_pp_table); 1832 if (ret) { 1833 DRM_ERROR("failed to create device file pp_table\n"); 1834 return ret; 1835 } 1836 1837 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk); 1838 if (ret) { 1839 DRM_ERROR("failed to create device file pp_dpm_sclk\n"); 1840 return ret; 1841 } 1842 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk); 1843 if (ret) { 1844 DRM_ERROR("failed to create device file pp_dpm_mclk\n"); 1845 return ret; 1846 } 1847 ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie); 1848 if (ret) { 1849 DRM_ERROR("failed to create device file pp_dpm_pcie\n"); 1850 return ret; 1851 } 1852 ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od); 1853 if (ret) { 1854 DRM_ERROR("failed to create device file pp_sclk_od\n"); 1855 return ret; 1856 } 1857 ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od); 1858 if (ret) { 1859 DRM_ERROR("failed to create device file pp_mclk_od\n"); 1860 return ret; 1861 } 1862 ret = device_create_file(adev->dev, 1863 &dev_attr_pp_power_profile_mode); 1864 if (ret) { 1865 DRM_ERROR("failed to create device file " 1866 "pp_power_profile_mode\n"); 1867 return ret; 1868 } 1869 ret = device_create_file(adev->dev, 1870 &dev_attr_pp_od_clk_voltage); 1871 if (ret) { 1872 DRM_ERROR("failed to create device file " 1873 "pp_od_clk_voltage\n"); 1874 return ret; 1875 } 1876 ret = device_create_file(adev->dev, 1877 &dev_attr_gpu_busy_percent); 1878 if (ret) { 1879 DRM_ERROR("failed to create device file " 1880 "gpu_busy_level\n"); 1881 return ret; 1882 } 1883 ret = amdgpu_debugfs_pm_init(adev); 1884 if (ret) { 1885 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1886 return ret; 1887 } 1888 1889 adev->pm.sysfs_initialized = true; 1890 1891 return 0; 1892 } 1893 1894 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) 1895 { 1896 if (adev->pm.dpm_enabled == 0) 1897 return; 1898 1899 if (adev->pm.int_hwmon_dev) 1900 hwmon_device_unregister(adev->pm.int_hwmon_dev); 1901 device_remove_file(adev->dev, &dev_attr_power_dpm_state); 1902 device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level); 1903 1904 device_remove_file(adev->dev, &dev_attr_pp_num_states); 1905 device_remove_file(adev->dev, &dev_attr_pp_cur_state); 1906 device_remove_file(adev->dev, &dev_attr_pp_force_state); 1907 device_remove_file(adev->dev, &dev_attr_pp_table); 1908 1909 device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk); 1910 device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk); 1911 device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie); 1912 device_remove_file(adev->dev, &dev_attr_pp_sclk_od); 1913 device_remove_file(adev->dev, &dev_attr_pp_mclk_od); 1914 device_remove_file(adev->dev, 1915 &dev_attr_pp_power_profile_mode); 1916 device_remove_file(adev->dev, 1917 &dev_attr_pp_od_clk_voltage); 1918 device_remove_file(adev->dev, &dev_attr_gpu_busy_percent); 1919 } 1920 1921 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev) 1922 { 1923 int i = 0; 1924 1925 if (!adev->pm.dpm_enabled) 1926 return; 1927 1928 if (adev->mode_info.num_crtc) 1929 amdgpu_display_bandwidth_update(adev); 1930 1931 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1932 struct amdgpu_ring *ring = adev->rings[i]; 1933 if (ring && ring->ready) 1934 amdgpu_fence_wait_empty(ring); 1935 } 1936 1937 if (adev->powerplay.pp_funcs->dispatch_tasks) { 1938 if (!amdgpu_device_has_dc_support(adev)) { 1939 mutex_lock(&adev->pm.mutex); 1940 amdgpu_dpm_get_active_displays(adev); 1941 adev->pm.pm_display_cfg.num_display = adev->pm.dpm.new_active_crtc_count; 1942 adev->pm.pm_display_cfg.vrefresh = amdgpu_dpm_get_vrefresh(adev); 1943 adev->pm.pm_display_cfg.min_vblank_time = amdgpu_dpm_get_vblank_time(adev); 1944 /* we have issues with mclk switching with refresh rates over 120 hz on the non-DC code. */ 1945 if (adev->pm.pm_display_cfg.vrefresh > 120) 1946 adev->pm.pm_display_cfg.min_vblank_time = 0; 1947 if (adev->powerplay.pp_funcs->display_configuration_change) 1948 adev->powerplay.pp_funcs->display_configuration_change( 1949 adev->powerplay.pp_handle, 1950 &adev->pm.pm_display_cfg); 1951 mutex_unlock(&adev->pm.mutex); 1952 } 1953 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, NULL); 1954 } else { 1955 mutex_lock(&adev->pm.mutex); 1956 amdgpu_dpm_get_active_displays(adev); 1957 amdgpu_dpm_change_power_state_locked(adev); 1958 mutex_unlock(&adev->pm.mutex); 1959 } 1960 } 1961 1962 /* 1963 * Debugfs info 1964 */ 1965 #if defined(CONFIG_DEBUG_FS) 1966 1967 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev) 1968 { 1969 uint32_t value; 1970 uint32_t query = 0; 1971 int size; 1972 1973 /* sanity check PP is enabled */ 1974 if (!(adev->powerplay.pp_funcs && 1975 adev->powerplay.pp_funcs->read_sensor)) 1976 return -EINVAL; 1977 1978 /* GPU Clocks */ 1979 size = sizeof(value); 1980 seq_printf(m, "GFX Clocks and Power:\n"); 1981 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size)) 1982 seq_printf(m, "\t%u MHz (MCLK)\n", value/100); 1983 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size)) 1984 seq_printf(m, "\t%u MHz (SCLK)\n", value/100); 1985 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size)) 1986 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100); 1987 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size)) 1988 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100); 1989 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size)) 1990 seq_printf(m, "\t%u mV (VDDGFX)\n", value); 1991 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size)) 1992 seq_printf(m, "\t%u mV (VDDNB)\n", value); 1993 size = sizeof(uint32_t); 1994 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) 1995 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff); 1996 size = sizeof(value); 1997 seq_printf(m, "\n"); 1998 1999 /* GPU Temp */ 2000 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size)) 2001 seq_printf(m, "GPU Temperature: %u C\n", value/1000); 2002 2003 /* GPU Load */ 2004 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size)) 2005 seq_printf(m, "GPU Load: %u %%\n", value); 2006 seq_printf(m, "\n"); 2007 2008 /* UVD clocks */ 2009 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) { 2010 if (!value) { 2011 seq_printf(m, "UVD: Disabled\n"); 2012 } else { 2013 seq_printf(m, "UVD: Enabled\n"); 2014 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size)) 2015 seq_printf(m, "\t%u MHz (DCLK)\n", value/100); 2016 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size)) 2017 seq_printf(m, "\t%u MHz (VCLK)\n", value/100); 2018 } 2019 } 2020 seq_printf(m, "\n"); 2021 2022 /* VCE clocks */ 2023 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) { 2024 if (!value) { 2025 seq_printf(m, "VCE: Disabled\n"); 2026 } else { 2027 seq_printf(m, "VCE: Enabled\n"); 2028 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size)) 2029 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100); 2030 } 2031 } 2032 2033 return 0; 2034 } 2035 2036 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags) 2037 { 2038 int i; 2039 2040 for (i = 0; clocks[i].flag; i++) 2041 seq_printf(m, "\t%s: %s\n", clocks[i].name, 2042 (flags & clocks[i].flag) ? "On" : "Off"); 2043 } 2044 2045 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data) 2046 { 2047 struct drm_info_node *node = (struct drm_info_node *) m->private; 2048 struct drm_device *dev = node->minor->dev; 2049 struct amdgpu_device *adev = dev->dev_private; 2050 struct drm_device *ddev = adev->ddev; 2051 u32 flags = 0; 2052 2053 amdgpu_device_ip_get_clockgating_state(adev, &flags); 2054 seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags); 2055 amdgpu_parse_cg_state(m, flags); 2056 seq_printf(m, "\n"); 2057 2058 if (!adev->pm.dpm_enabled) { 2059 seq_printf(m, "dpm not enabled\n"); 2060 return 0; 2061 } 2062 if ((adev->flags & AMD_IS_PX) && 2063 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 2064 seq_printf(m, "PX asic powered off\n"); 2065 } else if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) { 2066 mutex_lock(&adev->pm.mutex); 2067 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level) 2068 adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m); 2069 else 2070 seq_printf(m, "Debugfs support not implemented for this asic\n"); 2071 mutex_unlock(&adev->pm.mutex); 2072 } else { 2073 return amdgpu_debugfs_pm_info_pp(m, adev); 2074 } 2075 2076 return 0; 2077 } 2078 2079 static const struct drm_info_list amdgpu_pm_info_list[] = { 2080 {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL}, 2081 }; 2082 #endif 2083 2084 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev) 2085 { 2086 #if defined(CONFIG_DEBUG_FS) 2087 return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list)); 2088 #else 2089 return 0; 2090 #endif 2091 } 2092