1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2018 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev #ifndef __AMDGPU_JOB_H__ 24*b843c749SSergey Zigachev #define __AMDGPU_JOB_H__ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev /* bit set means command submit involves a preamble IB */ 27*b843c749SSergey Zigachev #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) 28*b843c749SSergey Zigachev /* bit set means preamble IB is first presented in belonging context */ 29*b843c749SSergey Zigachev #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) 30*b843c749SSergey Zigachev /* bit set means context switch occured */ 31*b843c749SSergey Zigachev #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) 32*b843c749SSergey Zigachev 33*b843c749SSergey Zigachev #define to_amdgpu_job(sched_job) \ 34*b843c749SSergey Zigachev container_of((sched_job), struct amdgpu_job, base) 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev struct amdgpu_fence; 37*b843c749SSergey Zigachev 38*b843c749SSergey Zigachev struct amdgpu_job { 39*b843c749SSergey Zigachev struct drm_sched_job base; 40*b843c749SSergey Zigachev struct amdgpu_vm *vm; 41*b843c749SSergey Zigachev struct amdgpu_sync sync; 42*b843c749SSergey Zigachev struct amdgpu_sync sched_sync; 43*b843c749SSergey Zigachev struct amdgpu_ib *ibs; 44*b843c749SSergey Zigachev struct dma_fence *fence; /* the hw fence */ 45*b843c749SSergey Zigachev uint32_t preamble_status; 46*b843c749SSergey Zigachev uint32_t num_ibs; 47*b843c749SSergey Zigachev void *owner; 48*b843c749SSergey Zigachev bool vm_needs_flush; 49*b843c749SSergey Zigachev uint64_t vm_pd_addr; 50*b843c749SSergey Zigachev unsigned vmid; 51*b843c749SSergey Zigachev unsigned pasid; 52*b843c749SSergey Zigachev uint32_t gds_base, gds_size; 53*b843c749SSergey Zigachev uint32_t gws_base, gws_size; 54*b843c749SSergey Zigachev uint32_t oa_base, oa_size; 55*b843c749SSergey Zigachev uint32_t vram_lost_counter; 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev /* user fence handling */ 58*b843c749SSergey Zigachev uint64_t uf_addr; 59*b843c749SSergey Zigachev uint64_t uf_sequence; 60*b843c749SSergey Zigachev 61*b843c749SSergey Zigachev }; 62*b843c749SSergey Zigachev 63*b843c749SSergey Zigachev int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 64*b843c749SSergey Zigachev struct amdgpu_job **job, struct amdgpu_vm *vm); 65*b843c749SSergey Zigachev int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 66*b843c749SSergey Zigachev struct amdgpu_job **job); 67*b843c749SSergey Zigachev 68*b843c749SSergey Zigachev void amdgpu_job_free_resources(struct amdgpu_job *job); 69*b843c749SSergey Zigachev void amdgpu_job_free(struct amdgpu_job *job); 70*b843c749SSergey Zigachev int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity, 71*b843c749SSergey Zigachev void *owner, struct dma_fence **f); 72*b843c749SSergey Zigachev int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring, 73*b843c749SSergey Zigachev struct dma_fence **fence); 74*b843c749SSergey Zigachev #endif 75