1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2014 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef __AMDGPU_IH_H__ 25*b843c749SSergey Zigachev #define __AMDGPU_IH_H__ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include <linux/chash.h> 28*b843c749SSergey Zigachev #include "soc15_ih_clientid.h" 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev struct amdgpu_device; 31*b843c749SSergey Zigachev 32*b843c749SSergey Zigachev #define AMDGPU_IH_CLIENTID_LEGACY 0 33*b843c749SSergey Zigachev #define AMDGPU_IH_CLIENTID_MAX SOC15_IH_CLIENTID_MAX 34*b843c749SSergey Zigachev 35*b843c749SSergey Zigachev #define AMDGPU_PAGEFAULT_HASH_BITS 8 36*b843c749SSergey Zigachev struct amdgpu_retryfault_hashtable { 37*b843c749SSergey Zigachev DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0); 38*b843c749SSergey Zigachev spinlock_t lock; 39*b843c749SSergey Zigachev int count; 40*b843c749SSergey Zigachev }; 41*b843c749SSergey Zigachev 42*b843c749SSergey Zigachev /* 43*b843c749SSergey Zigachev * R6xx+ IH ring 44*b843c749SSergey Zigachev */ 45*b843c749SSergey Zigachev struct amdgpu_ih_ring { 46*b843c749SSergey Zigachev struct amdgpu_bo *ring_obj; 47*b843c749SSergey Zigachev volatile uint32_t *ring; 48*b843c749SSergey Zigachev unsigned rptr; 49*b843c749SSergey Zigachev unsigned ring_size; 50*b843c749SSergey Zigachev uint64_t gpu_addr; 51*b843c749SSergey Zigachev uint32_t ptr_mask; 52*b843c749SSergey Zigachev atomic_t lock; 53*b843c749SSergey Zigachev bool enabled; 54*b843c749SSergey Zigachev unsigned wptr_offs; 55*b843c749SSergey Zigachev unsigned rptr_offs; 56*b843c749SSergey Zigachev u32 doorbell_index; 57*b843c749SSergey Zigachev bool use_doorbell; 58*b843c749SSergey Zigachev bool use_bus_addr; 59*b843c749SSergey Zigachev dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */ 60*b843c749SSergey Zigachev struct amdgpu_retryfault_hashtable *faults; 61*b843c749SSergey Zigachev }; 62*b843c749SSergey Zigachev 63*b843c749SSergey Zigachev #define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4 64*b843c749SSergey Zigachev 65*b843c749SSergey Zigachev struct amdgpu_iv_entry { 66*b843c749SSergey Zigachev unsigned client_id; 67*b843c749SSergey Zigachev unsigned src_id; 68*b843c749SSergey Zigachev unsigned ring_id; 69*b843c749SSergey Zigachev unsigned vmid; 70*b843c749SSergey Zigachev unsigned vmid_src; 71*b843c749SSergey Zigachev uint64_t timestamp; 72*b843c749SSergey Zigachev unsigned timestamp_src; 73*b843c749SSergey Zigachev unsigned pasid; 74*b843c749SSergey Zigachev unsigned pasid_src; 75*b843c749SSergey Zigachev unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW]; 76*b843c749SSergey Zigachev const uint32_t *iv_entry; 77*b843c749SSergey Zigachev }; 78*b843c749SSergey Zigachev 79*b843c749SSergey Zigachev int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size, 80*b843c749SSergey Zigachev bool use_bus_addr); 81*b843c749SSergey Zigachev void amdgpu_ih_ring_fini(struct amdgpu_device *adev); 82*b843c749SSergey Zigachev int amdgpu_ih_process(struct amdgpu_device *adev); 83*b843c749SSergey Zigachev int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key); 84*b843c749SSergey Zigachev void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key); 85*b843c749SSergey Zigachev 86*b843c749SSergey Zigachev #endif 87