1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2014 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev */
23*b843c749SSergey Zigachev
24*b843c749SSergey Zigachev #ifndef __AMDGPU_GFX_H__
25*b843c749SSergey Zigachev #define __AMDGPU_GFX_H__
26*b843c749SSergey Zigachev
27*b843c749SSergey Zigachev int amdgpu_gfx_scratch_get(struct amdgpu_device *adev, uint32_t *reg);
28*b843c749SSergey Zigachev void amdgpu_gfx_scratch_free(struct amdgpu_device *adev, uint32_t reg);
29*b843c749SSergey Zigachev
30*b843c749SSergey Zigachev void amdgpu_gfx_parse_disable_cu(unsigned *mask, unsigned max_se,
31*b843c749SSergey Zigachev unsigned max_sh);
32*b843c749SSergey Zigachev
33*b843c749SSergey Zigachev void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev);
34*b843c749SSergey Zigachev
35*b843c749SSergey Zigachev int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
36*b843c749SSergey Zigachev struct amdgpu_ring *ring,
37*b843c749SSergey Zigachev struct amdgpu_irq_src *irq);
38*b843c749SSergey Zigachev
39*b843c749SSergey Zigachev void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring,
40*b843c749SSergey Zigachev struct amdgpu_irq_src *irq);
41*b843c749SSergey Zigachev
42*b843c749SSergey Zigachev void amdgpu_gfx_kiq_fini(struct amdgpu_device *adev);
43*b843c749SSergey Zigachev int amdgpu_gfx_kiq_init(struct amdgpu_device *adev,
44*b843c749SSergey Zigachev unsigned hpd_size);
45*b843c749SSergey Zigachev
46*b843c749SSergey Zigachev int amdgpu_gfx_compute_mqd_sw_init(struct amdgpu_device *adev,
47*b843c749SSergey Zigachev unsigned mqd_size);
48*b843c749SSergey Zigachev void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev);
49*b843c749SSergey Zigachev
50*b843c749SSergey Zigachev /**
51*b843c749SSergey Zigachev * amdgpu_gfx_create_bitmask - create a bitmask
52*b843c749SSergey Zigachev *
53*b843c749SSergey Zigachev * @bit_width: length of the mask
54*b843c749SSergey Zigachev *
55*b843c749SSergey Zigachev * create a variable length bit mask.
56*b843c749SSergey Zigachev * Returns the bitmask.
57*b843c749SSergey Zigachev */
amdgpu_gfx_create_bitmask(u32 bit_width)58*b843c749SSergey Zigachev static inline u32 amdgpu_gfx_create_bitmask(u32 bit_width)
59*b843c749SSergey Zigachev {
60*b843c749SSergey Zigachev return (u32)((1ULL << bit_width) - 1);
61*b843c749SSergey Zigachev }
62*b843c749SSergey Zigachev
amdgpu_gfx_queue_to_bit(struct amdgpu_device * adev,int mec,int pipe,int queue)63*b843c749SSergey Zigachev static inline int amdgpu_gfx_queue_to_bit(struct amdgpu_device *adev,
64*b843c749SSergey Zigachev int mec, int pipe, int queue)
65*b843c749SSergey Zigachev {
66*b843c749SSergey Zigachev int bit = 0;
67*b843c749SSergey Zigachev
68*b843c749SSergey Zigachev bit += mec * adev->gfx.mec.num_pipe_per_mec
69*b843c749SSergey Zigachev * adev->gfx.mec.num_queue_per_pipe;
70*b843c749SSergey Zigachev bit += pipe * adev->gfx.mec.num_queue_per_pipe;
71*b843c749SSergey Zigachev bit += queue;
72*b843c749SSergey Zigachev
73*b843c749SSergey Zigachev return bit;
74*b843c749SSergey Zigachev }
75*b843c749SSergey Zigachev
amdgpu_gfx_bit_to_queue(struct amdgpu_device * adev,int bit,int * mec,int * pipe,int * queue)76*b843c749SSergey Zigachev static inline void amdgpu_gfx_bit_to_queue(struct amdgpu_device *adev, int bit,
77*b843c749SSergey Zigachev int *mec, int *pipe, int *queue)
78*b843c749SSergey Zigachev {
79*b843c749SSergey Zigachev *queue = bit % adev->gfx.mec.num_queue_per_pipe;
80*b843c749SSergey Zigachev *pipe = (bit / adev->gfx.mec.num_queue_per_pipe)
81*b843c749SSergey Zigachev % adev->gfx.mec.num_pipe_per_mec;
82*b843c749SSergey Zigachev *mec = (bit / adev->gfx.mec.num_queue_per_pipe)
83*b843c749SSergey Zigachev / adev->gfx.mec.num_pipe_per_mec;
84*b843c749SSergey Zigachev
85*b843c749SSergey Zigachev }
amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device * adev,int mec,int pipe,int queue)86*b843c749SSergey Zigachev static inline bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
87*b843c749SSergey Zigachev int mec, int pipe, int queue)
88*b843c749SSergey Zigachev {
89*b843c749SSergey Zigachev return test_bit(amdgpu_gfx_queue_to_bit(adev, mec, pipe, queue),
90*b843c749SSergey Zigachev adev->gfx.mec.queue_bitmap);
91*b843c749SSergey Zigachev }
92*b843c749SSergey Zigachev
93*b843c749SSergey Zigachev #endif
94